1/* SPDX-License-Identifier: GPL-2.0-only */ 2/* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. 3 */ 4 5#ifndef _DPU_HWIO_H 6#define _DPU_HWIO_H 7 8#include "dpu_hw_util.h" 9 10/** 11 * MDP TOP block Register and bit fields and defines 12 */ 13#define DISP_INTF_SEL 0x004 14#define INTR_EN 0x010 15#define INTR_STATUS 0x014 16#define INTR_CLEAR 0x018 17#define INTR2_EN 0x008 18#define INTR2_STATUS 0x00c 19#define INTR2_CLEAR 0x02c 20#define HIST_INTR_EN 0x01c 21#define HIST_INTR_STATUS 0x020 22#define HIST_INTR_CLEAR 0x024 23#define INTF_INTR_EN 0x1C0 24#define INTF_INTR_STATUS 0x1C4 25#define INTF_INTR_CLEAR 0x1C8 26#define SPLIT_DISPLAY_EN 0x2F4 27#define SPLIT_DISPLAY_UPPER_PIPE_CTRL 0x2F8 28#define DSPP_IGC_COLOR0_RAM_LUTN 0x300 29#define DSPP_IGC_COLOR1_RAM_LUTN 0x304 30#define DSPP_IGC_COLOR2_RAM_LUTN 0x308 31#define HW_EVENTS_CTL 0x37C 32#define CLK_CTRL3 0x3A8 33#define CLK_STATUS3 0x3AC 34#define CLK_CTRL4 0x3B0 35#define CLK_STATUS4 0x3B4 36#define CLK_CTRL5 0x3B8 37#define CLK_STATUS5 0x3BC 38#define CLK_CTRL7 0x3D0 39#define CLK_STATUS7 0x3D4 40#define SPLIT_DISPLAY_LOWER_PIPE_CTRL 0x3F0 41#define SPLIT_DISPLAY_TE_LINE_INTERVAL 0x3F4 42#define INTF_SW_RESET_MASK 0x3FC 43#define HDMI_DP_CORE_SELECT 0x408 44#define MDP_OUT_CTL_0 0x410 45#define MDP_VSYNC_SEL 0x414 46#define DCE_SEL 0x450 47 48#endif /*_DPU_HWIO_H */ 49