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6#ifndef __DSI_PHY_H__
7#define __DSI_PHY_H__
8
9#include <linux/clk-provider.h>
10#include <linux/delay.h>
11#include <linux/regulator/consumer.h>
12
13#include "dsi.h"
14
15#define dsi_phy_read(offset) msm_readl((offset))
16#define dsi_phy_write(offset, data) msm_writel((data), (offset))
17#define dsi_phy_write_udelay(offset, data, delay_us) { msm_writel((data), (offset)); udelay(delay_us); }
18#define dsi_phy_write_ndelay(offset, data, delay_ns) { msm_writel((data), (offset)); ndelay(delay_ns); }
19
20struct msm_dsi_phy_ops {
21 int (*pll_init)(struct msm_dsi_phy *phy);
22 int (*enable)(struct msm_dsi_phy *phy,
23 struct msm_dsi_phy_clk_request *clk_req);
24 void (*disable)(struct msm_dsi_phy *phy);
25 void (*save_pll_state)(struct msm_dsi_phy *phy);
26 int (*restore_pll_state)(struct msm_dsi_phy *phy);
27 bool (*set_continuous_clock)(struct msm_dsi_phy *phy, bool enable);
28 int (*parse_dt_properties)(struct msm_dsi_phy *phy);
29};
30
31struct msm_dsi_phy_cfg {
32 struct dsi_reg_config reg_cfg;
33 struct msm_dsi_phy_ops ops;
34
35 unsigned long min_pll_rate;
36 unsigned long max_pll_rate;
37
38 const resource_size_t io_start[DSI_MAX];
39 const int num_dsi_phy;
40 const int quirks;
41 bool has_phy_regulator;
42 bool has_phy_lane;
43};
44
45extern const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_cfgs;
46extern const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_famb_cfgs;
47extern const struct msm_dsi_phy_cfg dsi_phy_28nm_lp_cfgs;
48extern const struct msm_dsi_phy_cfg dsi_phy_20nm_cfgs;
49extern const struct msm_dsi_phy_cfg dsi_phy_28nm_8960_cfgs;
50extern const struct msm_dsi_phy_cfg dsi_phy_14nm_cfgs;
51extern const struct msm_dsi_phy_cfg dsi_phy_14nm_660_cfgs;
52extern const struct msm_dsi_phy_cfg dsi_phy_14nm_8953_cfgs;
53extern const struct msm_dsi_phy_cfg dsi_phy_10nm_cfgs;
54extern const struct msm_dsi_phy_cfg dsi_phy_10nm_8998_cfgs;
55extern const struct msm_dsi_phy_cfg dsi_phy_7nm_cfgs;
56extern const struct msm_dsi_phy_cfg dsi_phy_7nm_8150_cfgs;
57extern const struct msm_dsi_phy_cfg dsi_phy_7nm_7280_cfgs;
58
59struct msm_dsi_dphy_timing {
60 u32 clk_zero;
61 u32 clk_trail;
62 u32 clk_prepare;
63 u32 hs_exit;
64 u32 hs_zero;
65 u32 hs_prepare;
66 u32 hs_trail;
67 u32 hs_rqst;
68 u32 ta_go;
69 u32 ta_sure;
70 u32 ta_get;
71
72 struct msm_dsi_phy_shared_timings shared_timings;
73
74
75 u32 hs_rqst_ckln;
76 u32 hs_prep_dly;
77 u32 hs_prep_dly_ckln;
78 u8 hs_halfbyte_en;
79 u8 hs_halfbyte_en_ckln;
80};
81
82#define DSI_BYTE_PLL_CLK 0
83#define DSI_PIXEL_PLL_CLK 1
84#define NUM_PROVIDED_CLKS 2
85
86#define DSI_LANE_MAX 5
87
88struct msm_dsi_phy {
89 struct platform_device *pdev;
90 void __iomem *base;
91 void __iomem *pll_base;
92 void __iomem *reg_base;
93 void __iomem *lane_base;
94 phys_addr_t base_size;
95 phys_addr_t pll_size;
96 phys_addr_t reg_size;
97 phys_addr_t lane_size;
98 int id;
99
100 struct clk *ahb_clk;
101 struct regulator_bulk_data supplies[DSI_DEV_REGULATOR_MAX];
102
103 struct msm_dsi_dphy_timing timing;
104 const struct msm_dsi_phy_cfg *cfg;
105 void *tuning_cfg;
106
107 enum msm_dsi_phy_usecase usecase;
108 bool regulator_ldo_mode;
109 bool cphy_mode;
110
111 struct clk_hw *vco_hw;
112 bool pll_on;
113
114 struct clk_hw_onecell_data *provided_clocks;
115
116 bool state_saved;
117};
118
119
120
121
122int msm_dsi_dphy_timing_calc(struct msm_dsi_dphy_timing *timing,
123 struct msm_dsi_phy_clk_request *clk_req);
124int msm_dsi_dphy_timing_calc_v2(struct msm_dsi_dphy_timing *timing,
125 struct msm_dsi_phy_clk_request *clk_req);
126int msm_dsi_dphy_timing_calc_v3(struct msm_dsi_dphy_timing *timing,
127 struct msm_dsi_phy_clk_request *clk_req);
128int msm_dsi_dphy_timing_calc_v4(struct msm_dsi_dphy_timing *timing,
129 struct msm_dsi_phy_clk_request *clk_req);
130int msm_dsi_cphy_timing_calc_v4(struct msm_dsi_dphy_timing *timing,
131 struct msm_dsi_phy_clk_request *clk_req);
132
133#endif
134
