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9#include <linux/clk.h>
10#include <linux/iopoll.h>
11#include <linux/math64.h>
12#include <linux/mfd/syscon.h>
13#include <linux/module.h>
14#include <linux/of_device.h>
15#include <linux/phy/phy.h>
16#include <linux/pm_runtime.h>
17#include <linux/regmap.h>
18
19#include <video/mipi_display.h>
20
21#include <drm/bridge/dw_mipi_dsi.h>
22#include <drm/drm_mipi_dsi.h>
23#include <drm/drm_of.h>
24#include <drm/drm_simple_kms_helper.h>
25
26#include "rockchip_drm_drv.h"
27#include "rockchip_drm_vop.h"
28
29#define DSI_PHY_RSTZ 0xa0
30#define PHY_DISFORCEPLL 0
31#define PHY_ENFORCEPLL BIT(3)
32#define PHY_DISABLECLK 0
33#define PHY_ENABLECLK BIT(2)
34#define PHY_RSTZ 0
35#define PHY_UNRSTZ BIT(1)
36#define PHY_SHUTDOWNZ 0
37#define PHY_UNSHUTDOWNZ BIT(0)
38
39#define DSI_PHY_IF_CFG 0xa4
40#define N_LANES(n) ((((n) - 1) & 0x3) << 0)
41#define PHY_STOP_WAIT_TIME(cycle) (((cycle) & 0xff) << 8)
42
43#define DSI_PHY_STATUS 0xb0
44#define LOCK BIT(0)
45#define STOP_STATE_CLK_LANE BIT(2)
46
47#define DSI_PHY_TST_CTRL0 0xb4
48#define PHY_TESTCLK BIT(1)
49#define PHY_UNTESTCLK 0
50#define PHY_TESTCLR BIT(0)
51#define PHY_UNTESTCLR 0
52
53#define DSI_PHY_TST_CTRL1 0xb8
54#define PHY_TESTEN BIT(16)
55#define PHY_UNTESTEN 0
56#define PHY_TESTDOUT(n) (((n) & 0xff) << 8)
57#define PHY_TESTDIN(n) (((n) & 0xff) << 0)
58
59#define DSI_INT_ST0 0xbc
60#define DSI_INT_ST1 0xc0
61#define DSI_INT_MSK0 0xc4
62#define DSI_INT_MSK1 0xc8
63
64#define PHY_STATUS_TIMEOUT_US 10000
65#define CMD_PKT_STATUS_TIMEOUT_US 20000
66
67#define BYPASS_VCO_RANGE BIT(7)
68#define VCO_RANGE_CON_SEL(val) (((val) & 0x7) << 3)
69#define VCO_IN_CAP_CON_DEFAULT (0x0 << 1)
70#define VCO_IN_CAP_CON_LOW (0x1 << 1)
71#define VCO_IN_CAP_CON_HIGH (0x2 << 1)
72#define REF_BIAS_CUR_SEL BIT(0)
73
74#define CP_CURRENT_3UA 0x1
75#define CP_CURRENT_4_5UA 0x2
76#define CP_CURRENT_7_5UA 0x6
77#define CP_CURRENT_6UA 0x9
78#define CP_CURRENT_12UA 0xb
79#define CP_CURRENT_SEL(val) ((val) & 0xf)
80#define CP_PROGRAM_EN BIT(7)
81
82#define LPF_RESISTORS_15_5KOHM 0x1
83#define LPF_RESISTORS_13KOHM 0x2
84#define LPF_RESISTORS_11_5KOHM 0x4
85#define LPF_RESISTORS_10_5KOHM 0x8
86#define LPF_RESISTORS_8KOHM 0x10
87#define LPF_PROGRAM_EN BIT(6)
88#define LPF_RESISTORS_SEL(val) ((val) & 0x3f)
89
90#define HSFREQRANGE_SEL(val) (((val) & 0x3f) << 1)
91
92#define INPUT_DIVIDER(val) (((val) - 1) & 0x7f)
93#define LOW_PROGRAM_EN 0
94#define HIGH_PROGRAM_EN BIT(7)
95#define LOOP_DIV_LOW_SEL(val) (((val) - 1) & 0x1f)
96#define LOOP_DIV_HIGH_SEL(val) ((((val) - 1) >> 5) & 0xf)
97#define PLL_LOOP_DIV_EN BIT(5)
98#define PLL_INPUT_DIV_EN BIT(4)
99
100#define POWER_CONTROL BIT(6)
101#define INTERNAL_REG_CURRENT BIT(3)
102#define BIAS_BLOCK_ON BIT(2)
103#define BANDGAP_ON BIT(0)
104
105#define TER_RESISTOR_HIGH BIT(7)
106#define TER_RESISTOR_LOW 0
107#define LEVEL_SHIFTERS_ON BIT(6)
108#define TER_CAL_DONE BIT(5)
109#define SETRD_MAX (0x7 << 2)
110#define POWER_MANAGE BIT(1)
111#define TER_RESISTORS_ON BIT(0)
112
113#define BIASEXTR_SEL(val) ((val) & 0x7)
114#define BANDGAP_SEL(val) ((val) & 0x7)
115#define TLP_PROGRAM_EN BIT(7)
116#define THS_PRE_PROGRAM_EN BIT(7)
117#define THS_ZERO_PROGRAM_EN BIT(6)
118
119#define PLL_BIAS_CUR_SEL_CAP_VCO_CONTROL 0x10
120#define PLL_CP_CONTROL_PLL_LOCK_BYPASS 0x11
121#define PLL_LPF_AND_CP_CONTROL 0x12
122#define PLL_INPUT_DIVIDER_RATIO 0x17
123#define PLL_LOOP_DIVIDER_RATIO 0x18
124#define PLL_INPUT_AND_LOOP_DIVIDER_RATIOS_CONTROL 0x19
125#define BANDGAP_AND_BIAS_CONTROL 0x20
126#define TERMINATION_RESISTER_CONTROL 0x21
127#define AFE_BIAS_BANDGAP_ANALOG_PROGRAMMABILITY 0x22
128#define HS_RX_CONTROL_OF_LANE_CLK 0x34
129#define HS_RX_CONTROL_OF_LANE_0 0x44
130#define HS_RX_CONTROL_OF_LANE_1 0x54
131#define HS_TX_CLOCK_LANE_REQUEST_STATE_TIME_CONTROL 0x60
132#define HS_TX_CLOCK_LANE_PREPARE_STATE_TIME_CONTROL 0x61
133#define HS_TX_CLOCK_LANE_HS_ZERO_STATE_TIME_CONTROL 0x62
134#define HS_TX_CLOCK_LANE_TRAIL_STATE_TIME_CONTROL 0x63
135#define HS_TX_CLOCK_LANE_EXIT_STATE_TIME_CONTROL 0x64
136#define HS_TX_CLOCK_LANE_POST_TIME_CONTROL 0x65
137#define HS_TX_DATA_LANE_REQUEST_STATE_TIME_CONTROL 0x70
138#define HS_TX_DATA_LANE_PREPARE_STATE_TIME_CONTROL 0x71
139#define HS_TX_DATA_LANE_HS_ZERO_STATE_TIME_CONTROL 0x72
140#define HS_TX_DATA_LANE_TRAIL_STATE_TIME_CONTROL 0x73
141#define HS_TX_DATA_LANE_EXIT_STATE_TIME_CONTROL 0x74
142#define HS_RX_DATA_LANE_THS_SETTLE_CONTROL 0x75
143#define HS_RX_CONTROL_OF_LANE_2 0x84
144#define HS_RX_CONTROL_OF_LANE_3 0x94
145
146#define DW_MIPI_NEEDS_PHY_CFG_CLK BIT(0)
147#define DW_MIPI_NEEDS_GRF_CLK BIT(1)
148
149#define PX30_GRF_PD_VO_CON1 0x0438
150#define PX30_DSI_FORCETXSTOPMODE (0xf << 7)
151#define PX30_DSI_FORCERXMODE BIT(6)
152#define PX30_DSI_TURNDISABLE BIT(5)
153#define PX30_DSI_LCDC_SEL BIT(0)
154
155#define RK3288_GRF_SOC_CON6 0x025c
156#define RK3288_DSI0_LCDC_SEL BIT(6)
157#define RK3288_DSI1_LCDC_SEL BIT(9)
158
159#define RK3399_GRF_SOC_CON20 0x6250
160#define RK3399_DSI0_LCDC_SEL BIT(0)
161#define RK3399_DSI1_LCDC_SEL BIT(4)
162
163#define RK3399_GRF_SOC_CON22 0x6258
164#define RK3399_DSI0_TURNREQUEST (0xf << 12)
165#define RK3399_DSI0_TURNDISABLE (0xf << 8)
166#define RK3399_DSI0_FORCETXSTOPMODE (0xf << 4)
167#define RK3399_DSI0_FORCERXMODE (0xf << 0)
168
169#define RK3399_GRF_SOC_CON23 0x625c
170#define RK3399_DSI1_TURNDISABLE (0xf << 12)
171#define RK3399_DSI1_FORCETXSTOPMODE (0xf << 8)
172#define RK3399_DSI1_FORCERXMODE (0xf << 4)
173#define RK3399_DSI1_ENABLE (0xf << 0)
174
175#define RK3399_GRF_SOC_CON24 0x6260
176#define RK3399_TXRX_MASTERSLAVEZ BIT(7)
177#define RK3399_TXRX_ENABLECLK BIT(6)
178#define RK3399_TXRX_BASEDIR BIT(5)
179#define RK3399_TXRX_SRC_SEL_ISP0 BIT(4)
180#define RK3399_TXRX_TURNREQUEST GENMASK(3, 0)
181
182#define HIWORD_UPDATE(val, mask) (val | (mask) << 16)
183
184enum {
185 DW_DSI_USAGE_IDLE,
186 DW_DSI_USAGE_DSI,
187 DW_DSI_USAGE_PHY,
188};
189
190enum {
191 BANDGAP_97_07,
192 BANDGAP_98_05,
193 BANDGAP_99_02,
194 BANDGAP_100_00,
195 BANDGAP_93_17,
196 BANDGAP_94_15,
197 BANDGAP_95_12,
198 BANDGAP_96_10,
199};
200
201enum {
202 BIASEXTR_87_1,
203 BIASEXTR_91_5,
204 BIASEXTR_95_9,
205 BIASEXTR_100,
206 BIASEXTR_105_94,
207 BIASEXTR_111_88,
208 BIASEXTR_118_8,
209 BIASEXTR_127_7,
210};
211
212struct rockchip_dw_dsi_chip_data {
213 u32 reg;
214
215 u32 lcdsel_grf_reg;
216 u32 lcdsel_big;
217 u32 lcdsel_lit;
218
219 u32 enable_grf_reg;
220 u32 enable;
221
222 u32 lanecfg1_grf_reg;
223 u32 lanecfg1;
224 u32 lanecfg2_grf_reg;
225 u32 lanecfg2;
226
227 int (*dphy_rx_init)(struct phy *phy);
228 int (*dphy_rx_power_on)(struct phy *phy);
229 int (*dphy_rx_power_off)(struct phy *phy);
230
231 unsigned int flags;
232 unsigned int max_data_lanes;
233};
234
235struct dw_mipi_dsi_rockchip {
236 struct device *dev;
237 struct rockchip_encoder encoder;
238 void __iomem *base;
239
240 struct regmap *grf_regmap;
241 struct clk *pclk;
242 struct clk *pllref_clk;
243 struct clk *grf_clk;
244 struct clk *phy_cfg_clk;
245
246
247 bool is_slave;
248 struct dw_mipi_dsi_rockchip *slave;
249
250
251 struct phy *phy;
252 union phy_configure_opts phy_opts;
253
254
255 unsigned int usage_mode;
256 struct mutex usage_mutex;
257 struct phy *dphy;
258 struct phy_configure_opts_mipi_dphy dphy_config;
259
260 unsigned int lane_mbps;
261 u16 input_div;
262 u16 feedback_div;
263 u32 format;
264
265 struct dw_mipi_dsi *dmd;
266 const struct rockchip_dw_dsi_chip_data *cdata;
267 struct dw_mipi_dsi_plat_data pdata;
268
269 bool dsi_bound;
270};
271
272static struct dw_mipi_dsi_rockchip *to_dsi(struct drm_encoder *encoder)
273{
274 struct rockchip_encoder *rkencoder = to_rockchip_encoder(encoder);
275
276 return container_of(rkencoder, struct dw_mipi_dsi_rockchip, encoder);
277}
278
279struct dphy_pll_parameter_map {
280 unsigned int max_mbps;
281 u8 hsfreqrange;
282 u8 icpctrl;
283 u8 lpfctrl;
284};
285
286
287static const struct dphy_pll_parameter_map dppa_map[] = {
288 { 89, 0x00, CP_CURRENT_3UA, LPF_RESISTORS_13KOHM },
289 { 99, 0x10, CP_CURRENT_3UA, LPF_RESISTORS_13KOHM },
290 { 109, 0x20, CP_CURRENT_3UA, LPF_RESISTORS_13KOHM },
291 { 129, 0x01, CP_CURRENT_3UA, LPF_RESISTORS_15_5KOHM },
292 { 139, 0x11, CP_CURRENT_3UA, LPF_RESISTORS_15_5KOHM },
293 { 149, 0x21, CP_CURRENT_3UA, LPF_RESISTORS_15_5KOHM },
294 { 169, 0x02, CP_CURRENT_6UA, LPF_RESISTORS_13KOHM },
295 { 179, 0x12, CP_CURRENT_6UA, LPF_RESISTORS_13KOHM },
296 { 199, 0x22, CP_CURRENT_6UA, LPF_RESISTORS_13KOHM },
297 { 219, 0x03, CP_CURRENT_4_5UA, LPF_RESISTORS_13KOHM },
298 { 239, 0x13, CP_CURRENT_4_5UA, LPF_RESISTORS_13KOHM },
299 { 249, 0x23, CP_CURRENT_4_5UA, LPF_RESISTORS_13KOHM },
300 { 269, 0x04, CP_CURRENT_6UA, LPF_RESISTORS_11_5KOHM },
301 { 299, 0x14, CP_CURRENT_6UA, LPF_RESISTORS_11_5KOHM },
302 { 329, 0x05, CP_CURRENT_3UA, LPF_RESISTORS_15_5KOHM },
303 { 359, 0x15, CP_CURRENT_3UA, LPF_RESISTORS_15_5KOHM },
304 { 399, 0x25, CP_CURRENT_3UA, LPF_RESISTORS_15_5KOHM },
305 { 449, 0x06, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM },
306 { 499, 0x16, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM },
307 { 549, 0x07, CP_CURRENT_7_5UA, LPF_RESISTORS_10_5KOHM },
308 { 599, 0x17, CP_CURRENT_7_5UA, LPF_RESISTORS_10_5KOHM },
309 { 649, 0x08, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM },
310 { 699, 0x18, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM },
311 { 749, 0x09, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM },
312 { 799, 0x19, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM },
313 { 849, 0x29, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM },
314 { 899, 0x39, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM },
315 { 949, 0x0a, CP_CURRENT_12UA, LPF_RESISTORS_8KOHM },
316 { 999, 0x1a, CP_CURRENT_12UA, LPF_RESISTORS_8KOHM },
317 {1049, 0x2a, CP_CURRENT_12UA, LPF_RESISTORS_8KOHM },
318 {1099, 0x3a, CP_CURRENT_12UA, LPF_RESISTORS_8KOHM },
319 {1149, 0x0b, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM },
320 {1199, 0x1b, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM },
321 {1249, 0x2b, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM },
322 {1299, 0x3b, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM },
323 {1349, 0x0c, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM },
324 {1399, 0x1c, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM },
325 {1449, 0x2c, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM },
326 {1500, 0x3c, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM }
327};
328
329static int max_mbps_to_parameter(unsigned int max_mbps)
330{
331 int i;
332
333 for (i = 0; i < ARRAY_SIZE(dppa_map); i++)
334 if (dppa_map[i].max_mbps >= max_mbps)
335 return i;
336
337 return -EINVAL;
338}
339
340static inline void dsi_write(struct dw_mipi_dsi_rockchip *dsi, u32 reg, u32 val)
341{
342 writel(val, dsi->base + reg);
343}
344
345static inline u32 dsi_read(struct dw_mipi_dsi_rockchip *dsi, u32 reg)
346{
347 return readl(dsi->base + reg);
348}
349
350static inline void dsi_update_bits(struct dw_mipi_dsi_rockchip *dsi, u32 reg,
351 u32 mask, u32 val)
352{
353 dsi_write(dsi, reg, (dsi_read(dsi, reg) & ~mask) | val);
354}
355
356static void dw_mipi_dsi_phy_write(struct dw_mipi_dsi_rockchip *dsi,
357 u8 test_code,
358 u8 test_data)
359{
360
361
362
363
364
365 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_UNTESTCLR);
366
367 dsi_write(dsi, DSI_PHY_TST_CTRL1, PHY_TESTEN | PHY_TESTDOUT(0) |
368 PHY_TESTDIN(test_code));
369
370 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLK | PHY_UNTESTCLR);
371
372 dsi_write(dsi, DSI_PHY_TST_CTRL1, PHY_UNTESTEN | PHY_TESTDOUT(0) |
373 PHY_TESTDIN(test_data));
374
375 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_UNTESTCLR);
376}
377
378
379
380
381static inline unsigned int ns2bc(struct dw_mipi_dsi_rockchip *dsi, int ns)
382{
383 return DIV_ROUND_UP(ns * dsi->lane_mbps / 8, 1000);
384}
385
386
387
388
389static inline unsigned int ns2ui(struct dw_mipi_dsi_rockchip *dsi, int ns)
390{
391 return DIV_ROUND_UP(ns * dsi->lane_mbps, 1000);
392}
393
394static int dw_mipi_dsi_phy_init(void *priv_data)
395{
396 struct dw_mipi_dsi_rockchip *dsi = priv_data;
397 int ret, i, vco;
398
399 if (dsi->phy)
400 return 0;
401
402
403
404
405
406
407
408
409
410
411
412
413
414 vco = (dsi->lane_mbps < 200) ? 0 : (dsi->lane_mbps + 100) / 200;
415
416 i = max_mbps_to_parameter(dsi->lane_mbps);
417 if (i < 0) {
418 DRM_DEV_ERROR(dsi->dev,
419 "failed to get parameter for %dmbps clock\n",
420 dsi->lane_mbps);
421 return i;
422 }
423
424 ret = clk_prepare_enable(dsi->phy_cfg_clk);
425 if (ret) {
426 DRM_DEV_ERROR(dsi->dev, "Failed to enable phy_cfg_clk\n");
427 return ret;
428 }
429
430 dw_mipi_dsi_phy_write(dsi, PLL_BIAS_CUR_SEL_CAP_VCO_CONTROL,
431 BYPASS_VCO_RANGE |
432 VCO_RANGE_CON_SEL(vco) |
433 VCO_IN_CAP_CON_LOW |
434 REF_BIAS_CUR_SEL);
435
436 dw_mipi_dsi_phy_write(dsi, PLL_CP_CONTROL_PLL_LOCK_BYPASS,
437 CP_CURRENT_SEL(dppa_map[i].icpctrl));
438 dw_mipi_dsi_phy_write(dsi, PLL_LPF_AND_CP_CONTROL,
439 CP_PROGRAM_EN | LPF_PROGRAM_EN |
440 LPF_RESISTORS_SEL(dppa_map[i].lpfctrl));
441
442 dw_mipi_dsi_phy_write(dsi, HS_RX_CONTROL_OF_LANE_0,
443 HSFREQRANGE_SEL(dppa_map[i].hsfreqrange));
444
445 dw_mipi_dsi_phy_write(dsi, PLL_INPUT_DIVIDER_RATIO,
446 INPUT_DIVIDER(dsi->input_div));
447 dw_mipi_dsi_phy_write(dsi, PLL_LOOP_DIVIDER_RATIO,
448 LOOP_DIV_LOW_SEL(dsi->feedback_div) |
449 LOW_PROGRAM_EN);
450
451
452
453
454
455
456 dw_mipi_dsi_phy_write(dsi, PLL_INPUT_AND_LOOP_DIVIDER_RATIOS_CONTROL,
457 PLL_LOOP_DIV_EN | PLL_INPUT_DIV_EN);
458 dw_mipi_dsi_phy_write(dsi, PLL_LOOP_DIVIDER_RATIO,
459 LOOP_DIV_HIGH_SEL(dsi->feedback_div) |
460 HIGH_PROGRAM_EN);
461 dw_mipi_dsi_phy_write(dsi, PLL_INPUT_AND_LOOP_DIVIDER_RATIOS_CONTROL,
462 PLL_LOOP_DIV_EN | PLL_INPUT_DIV_EN);
463
464 dw_mipi_dsi_phy_write(dsi, AFE_BIAS_BANDGAP_ANALOG_PROGRAMMABILITY,
465 LOW_PROGRAM_EN | BIASEXTR_SEL(BIASEXTR_127_7));
466 dw_mipi_dsi_phy_write(dsi, AFE_BIAS_BANDGAP_ANALOG_PROGRAMMABILITY,
467 HIGH_PROGRAM_EN | BANDGAP_SEL(BANDGAP_96_10));
468
469 dw_mipi_dsi_phy_write(dsi, BANDGAP_AND_BIAS_CONTROL,
470 POWER_CONTROL | INTERNAL_REG_CURRENT |
471 BIAS_BLOCK_ON | BANDGAP_ON);
472
473 dw_mipi_dsi_phy_write(dsi, TERMINATION_RESISTER_CONTROL,
474 TER_RESISTOR_LOW | TER_CAL_DONE |
475 SETRD_MAX | TER_RESISTORS_ON);
476 dw_mipi_dsi_phy_write(dsi, TERMINATION_RESISTER_CONTROL,
477 TER_RESISTOR_HIGH | LEVEL_SHIFTERS_ON |
478 SETRD_MAX | POWER_MANAGE |
479 TER_RESISTORS_ON);
480
481 dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_REQUEST_STATE_TIME_CONTROL,
482 TLP_PROGRAM_EN | ns2bc(dsi, 500));
483 dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_PREPARE_STATE_TIME_CONTROL,
484 THS_PRE_PROGRAM_EN | ns2ui(dsi, 40));
485 dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_HS_ZERO_STATE_TIME_CONTROL,
486 THS_ZERO_PROGRAM_EN | ns2bc(dsi, 300));
487 dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_TRAIL_STATE_TIME_CONTROL,
488 THS_PRE_PROGRAM_EN | ns2ui(dsi, 100));
489 dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_EXIT_STATE_TIME_CONTROL,
490 BIT(5) | ns2bc(dsi, 100));
491 dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_POST_TIME_CONTROL,
492 BIT(5) | (ns2bc(dsi, 60) + 7));
493
494 dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_REQUEST_STATE_TIME_CONTROL,
495 TLP_PROGRAM_EN | ns2bc(dsi, 500));
496 dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_PREPARE_STATE_TIME_CONTROL,
497 THS_PRE_PROGRAM_EN | (ns2ui(dsi, 50) + 20));
498 dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_HS_ZERO_STATE_TIME_CONTROL,
499 THS_ZERO_PROGRAM_EN | (ns2bc(dsi, 140) + 2));
500 dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_TRAIL_STATE_TIME_CONTROL,
501 THS_PRE_PROGRAM_EN | (ns2ui(dsi, 60) + 8));
502 dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_EXIT_STATE_TIME_CONTROL,
503 BIT(5) | ns2bc(dsi, 100));
504
505 clk_disable_unprepare(dsi->phy_cfg_clk);
506
507 return ret;
508}
509
510static void dw_mipi_dsi_phy_power_on(void *priv_data)
511{
512 struct dw_mipi_dsi_rockchip *dsi = priv_data;
513 int ret;
514
515 ret = phy_set_mode(dsi->phy, PHY_MODE_MIPI_DPHY);
516 if (ret) {
517 DRM_DEV_ERROR(dsi->dev, "failed to set phy mode: %d\n", ret);
518 return;
519 }
520
521 phy_configure(dsi->phy, &dsi->phy_opts);
522 phy_power_on(dsi->phy);
523}
524
525static void dw_mipi_dsi_phy_power_off(void *priv_data)
526{
527 struct dw_mipi_dsi_rockchip *dsi = priv_data;
528
529 phy_power_off(dsi->phy);
530}
531
532static int
533dw_mipi_dsi_get_lane_mbps(void *priv_data, const struct drm_display_mode *mode,
534 unsigned long mode_flags, u32 lanes, u32 format,
535 unsigned int *lane_mbps)
536{
537 struct dw_mipi_dsi_rockchip *dsi = priv_data;
538 int bpp;
539 unsigned long mpclk, tmp;
540 unsigned int target_mbps = 1000;
541 unsigned int max_mbps = dppa_map[ARRAY_SIZE(dppa_map) - 1].max_mbps;
542 unsigned long best_freq = 0;
543 unsigned long fvco_min, fvco_max, fin, fout;
544 unsigned int min_prediv, max_prediv;
545 unsigned int _prediv, best_prediv;
546 unsigned long _fbdiv, best_fbdiv;
547 unsigned long min_delta = ULONG_MAX;
548
549 dsi->format = format;
550 bpp = mipi_dsi_pixel_format_to_bpp(dsi->format);
551 if (bpp < 0) {
552 DRM_DEV_ERROR(dsi->dev,
553 "failed to get bpp for pixel format %d\n",
554 dsi->format);
555 return bpp;
556 }
557
558 mpclk = DIV_ROUND_UP(mode->clock, MSEC_PER_SEC);
559 if (mpclk) {
560
561 tmp = mpclk * (bpp / lanes) * 10 / 8;
562 if (tmp < max_mbps)
563 target_mbps = tmp;
564 else
565 DRM_DEV_ERROR(dsi->dev,
566 "DPHY clock frequency is out of range\n");
567 }
568
569
570 if (dsi->phy) {
571 phy_mipi_dphy_get_default_config(mode->clock * 1000 * 10 / 8,
572 bpp, lanes,
573 &dsi->phy_opts.mipi_dphy);
574 dsi->lane_mbps = target_mbps;
575 *lane_mbps = dsi->lane_mbps;
576
577 return 0;
578 }
579
580 fin = clk_get_rate(dsi->pllref_clk);
581 fout = target_mbps * USEC_PER_SEC;
582
583
584 min_prediv = DIV_ROUND_UP(fin, 40 * USEC_PER_SEC);
585 max_prediv = fin / (5 * USEC_PER_SEC);
586
587
588 fvco_min = 80 * USEC_PER_SEC;
589 fvco_max = 1500 * USEC_PER_SEC;
590
591 for (_prediv = min_prediv; _prediv <= max_prediv; _prediv++) {
592 u64 tmp;
593 u32 delta;
594
595 tmp = (u64)fout * _prediv;
596 do_div(tmp, fin);
597 _fbdiv = tmp;
598
599
600
601
602
603 if (_fbdiv < 6 || _fbdiv > 512)
604 continue;
605
606 _fbdiv += _fbdiv % 2;
607
608 tmp = (u64)_fbdiv * fin;
609 do_div(tmp, _prediv);
610 if (tmp < fvco_min || tmp > fvco_max)
611 continue;
612
613 delta = abs(fout - tmp);
614 if (delta < min_delta) {
615 best_prediv = _prediv;
616 best_fbdiv = _fbdiv;
617 min_delta = delta;
618 best_freq = tmp;
619 }
620 }
621
622 if (best_freq) {
623 dsi->lane_mbps = DIV_ROUND_UP(best_freq, USEC_PER_SEC);
624 *lane_mbps = dsi->lane_mbps;
625 dsi->input_div = best_prediv;
626 dsi->feedback_div = best_fbdiv;
627 } else {
628 DRM_DEV_ERROR(dsi->dev, "Can not find best_freq for DPHY\n");
629 return -EINVAL;
630 }
631
632 return 0;
633}
634
635struct hstt {
636 unsigned int maxfreq;
637 struct dw_mipi_dsi_dphy_timing timing;
638};
639
640#define HSTT(_maxfreq, _c_lp2hs, _c_hs2lp, _d_lp2hs, _d_hs2lp) \
641{ \
642 .maxfreq = _maxfreq, \
643 .timing = { \
644 .clk_lp2hs = _c_lp2hs, \
645 .clk_hs2lp = _c_hs2lp, \
646 .data_lp2hs = _d_lp2hs, \
647 .data_hs2lp = _d_hs2lp, \
648 } \
649}
650
651
652static struct hstt hstt_table[] = {
653 HSTT( 90, 32, 20, 26, 13),
654 HSTT( 100, 35, 23, 28, 14),
655 HSTT( 110, 32, 22, 26, 13),
656 HSTT( 130, 31, 20, 27, 13),
657 HSTT( 140, 33, 22, 26, 14),
658 HSTT( 150, 33, 21, 26, 14),
659 HSTT( 170, 32, 20, 27, 13),
660 HSTT( 180, 36, 23, 30, 15),
661 HSTT( 200, 40, 22, 33, 15),
662 HSTT( 220, 40, 22, 33, 15),
663 HSTT( 240, 44, 24, 36, 16),
664 HSTT( 250, 48, 24, 38, 17),
665 HSTT( 270, 48, 24, 38, 17),
666 HSTT( 300, 50, 27, 41, 18),
667 HSTT( 330, 56, 28, 45, 18),
668 HSTT( 360, 59, 28, 48, 19),
669 HSTT( 400, 61, 30, 50, 20),
670 HSTT( 450, 67, 31, 55, 21),
671 HSTT( 500, 73, 31, 59, 22),
672 HSTT( 550, 79, 36, 63, 24),
673 HSTT( 600, 83, 37, 68, 25),
674 HSTT( 650, 90, 38, 73, 27),
675 HSTT( 700, 95, 40, 77, 28),
676 HSTT( 750, 102, 40, 84, 28),
677 HSTT( 800, 106, 42, 87, 30),
678 HSTT( 850, 113, 44, 93, 31),
679 HSTT( 900, 118, 47, 98, 32),
680 HSTT( 950, 124, 47, 102, 34),
681 HSTT(1000, 130, 49, 107, 35),
682 HSTT(1050, 135, 51, 111, 37),
683 HSTT(1100, 139, 51, 114, 38),
684 HSTT(1150, 146, 54, 120, 40),
685 HSTT(1200, 153, 57, 125, 41),
686 HSTT(1250, 158, 58, 130, 42),
687 HSTT(1300, 163, 58, 135, 44),
688 HSTT(1350, 168, 60, 140, 45),
689 HSTT(1400, 172, 64, 144, 47),
690 HSTT(1450, 176, 65, 148, 48),
691 HSTT(1500, 181, 66, 153, 50)
692};
693
694static int
695dw_mipi_dsi_phy_get_timing(void *priv_data, unsigned int lane_mbps,
696 struct dw_mipi_dsi_dphy_timing *timing)
697{
698 int i;
699
700 for (i = 0; i < ARRAY_SIZE(hstt_table); i++)
701 if (lane_mbps < hstt_table[i].maxfreq)
702 break;
703
704 if (i == ARRAY_SIZE(hstt_table))
705 i--;
706
707 *timing = hstt_table[i].timing;
708
709 return 0;
710}
711
712static const struct dw_mipi_dsi_phy_ops dw_mipi_dsi_rockchip_phy_ops = {
713 .init = dw_mipi_dsi_phy_init,
714 .power_on = dw_mipi_dsi_phy_power_on,
715 .power_off = dw_mipi_dsi_phy_power_off,
716 .get_lane_mbps = dw_mipi_dsi_get_lane_mbps,
717 .get_timing = dw_mipi_dsi_phy_get_timing,
718};
719
720static void dw_mipi_dsi_rockchip_config(struct dw_mipi_dsi_rockchip *dsi)
721{
722 if (dsi->cdata->lanecfg1_grf_reg)
723 regmap_write(dsi->grf_regmap, dsi->cdata->lanecfg1_grf_reg,
724 dsi->cdata->lanecfg1);
725
726 if (dsi->cdata->lanecfg2_grf_reg)
727 regmap_write(dsi->grf_regmap, dsi->cdata->lanecfg2_grf_reg,
728 dsi->cdata->lanecfg2);
729
730 if (dsi->cdata->enable_grf_reg)
731 regmap_write(dsi->grf_regmap, dsi->cdata->enable_grf_reg,
732 dsi->cdata->enable);
733}
734
735static void dw_mipi_dsi_rockchip_set_lcdsel(struct dw_mipi_dsi_rockchip *dsi,
736 int mux)
737{
738 regmap_write(dsi->grf_regmap, dsi->cdata->lcdsel_grf_reg,
739 mux ? dsi->cdata->lcdsel_lit : dsi->cdata->lcdsel_big);
740}
741
742static int
743dw_mipi_dsi_encoder_atomic_check(struct drm_encoder *encoder,
744 struct drm_crtc_state *crtc_state,
745 struct drm_connector_state *conn_state)
746{
747 struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
748 struct dw_mipi_dsi_rockchip *dsi = to_dsi(encoder);
749
750 switch (dsi->format) {
751 case MIPI_DSI_FMT_RGB888:
752 s->output_mode = ROCKCHIP_OUT_MODE_P888;
753 break;
754 case MIPI_DSI_FMT_RGB666:
755 s->output_mode = ROCKCHIP_OUT_MODE_P666;
756 break;
757 case MIPI_DSI_FMT_RGB565:
758 s->output_mode = ROCKCHIP_OUT_MODE_P565;
759 break;
760 default:
761 WARN_ON(1);
762 return -EINVAL;
763 }
764
765 s->output_type = DRM_MODE_CONNECTOR_DSI;
766 if (dsi->slave)
767 s->output_flags = ROCKCHIP_OUTPUT_DSI_DUAL;
768
769 return 0;
770}
771
772static void dw_mipi_dsi_encoder_enable(struct drm_encoder *encoder)
773{
774 struct dw_mipi_dsi_rockchip *dsi = to_dsi(encoder);
775 int ret, mux;
776
777 mux = drm_of_encoder_active_endpoint_id(dsi->dev->of_node,
778 &dsi->encoder.encoder);
779 if (mux < 0)
780 return;
781
782
783
784
785
786
787 ret = clk_prepare_enable(dsi->grf_clk);
788 if (ret) {
789 DRM_DEV_ERROR(dsi->dev, "Failed to enable grf_clk: %d\n", ret);
790 return;
791 }
792
793 dw_mipi_dsi_rockchip_set_lcdsel(dsi, mux);
794 if (dsi->slave)
795 dw_mipi_dsi_rockchip_set_lcdsel(dsi->slave, mux);
796
797 clk_disable_unprepare(dsi->grf_clk);
798}
799
800static const struct drm_encoder_helper_funcs
801dw_mipi_dsi_encoder_helper_funcs = {
802 .atomic_check = dw_mipi_dsi_encoder_atomic_check,
803 .enable = dw_mipi_dsi_encoder_enable,
804};
805
806static int rockchip_dsi_drm_create_encoder(struct dw_mipi_dsi_rockchip *dsi,
807 struct drm_device *drm_dev)
808{
809 struct drm_encoder *encoder = &dsi->encoder.encoder;
810 int ret;
811
812 encoder->possible_crtcs = drm_of_find_possible_crtcs(drm_dev,
813 dsi->dev->of_node);
814
815 ret = drm_simple_encoder_init(drm_dev, encoder, DRM_MODE_ENCODER_DSI);
816 if (ret) {
817 DRM_ERROR("Failed to initialize encoder with drm\n");
818 return ret;
819 }
820
821 drm_encoder_helper_add(encoder, &dw_mipi_dsi_encoder_helper_funcs);
822
823 return 0;
824}
825
826static struct device
827*dw_mipi_dsi_rockchip_find_second(struct dw_mipi_dsi_rockchip *dsi)
828{
829 const struct of_device_id *match;
830 struct device_node *node = NULL, *local;
831
832 match = of_match_device(dsi->dev->driver->of_match_table, dsi->dev);
833
834 local = of_graph_get_remote_node(dsi->dev->of_node, 1, 0);
835 if (!local)
836 return NULL;
837
838 while ((node = of_find_compatible_node(node, NULL,
839 match->compatible))) {
840 struct device_node *remote;
841
842
843 if (node == dsi->dev->of_node)
844 continue;
845
846 remote = of_graph_get_remote_node(node, 1, 0);
847 if (!remote)
848 continue;
849
850
851 if (remote == local) {
852 struct dw_mipi_dsi_rockchip *dsi2;
853 struct platform_device *pdev;
854
855 pdev = of_find_device_by_node(node);
856
857
858
859
860
861
862 of_node_put(remote);
863 of_node_put(node);
864 of_node_put(local);
865
866 if (!pdev)
867 return ERR_PTR(-EPROBE_DEFER);
868
869 dsi2 = platform_get_drvdata(pdev);
870 if (!dsi2) {
871 platform_device_put(pdev);
872 return ERR_PTR(-EPROBE_DEFER);
873 }
874
875 return &pdev->dev;
876 }
877
878 of_node_put(remote);
879 }
880
881 of_node_put(local);
882
883 return NULL;
884}
885
886static int dw_mipi_dsi_rockchip_bind(struct device *dev,
887 struct device *master,
888 void *data)
889{
890 struct dw_mipi_dsi_rockchip *dsi = dev_get_drvdata(dev);
891 struct drm_device *drm_dev = data;
892 struct device *second;
893 bool master1, master2;
894 int ret;
895
896 second = dw_mipi_dsi_rockchip_find_second(dsi);
897 if (IS_ERR(second))
898 return PTR_ERR(second);
899
900 if (second) {
901 master1 = of_property_read_bool(dsi->dev->of_node,
902 "clock-master");
903 master2 = of_property_read_bool(second->of_node,
904 "clock-master");
905
906 if (master1 && master2) {
907 DRM_DEV_ERROR(dsi->dev, "only one clock-master allowed\n");
908 return -EINVAL;
909 }
910
911 if (!master1 && !master2) {
912 DRM_DEV_ERROR(dsi->dev, "no clock-master defined\n");
913 return -EINVAL;
914 }
915
916
917 if (!master1) {
918 dsi->is_slave = true;
919 return 0;
920 }
921
922 dsi->slave = dev_get_drvdata(second);
923 if (!dsi->slave) {
924 DRM_DEV_ERROR(dev, "could not get slaves data\n");
925 return -ENODEV;
926 }
927
928 dsi->slave->is_slave = true;
929 dw_mipi_dsi_set_slave(dsi->dmd, dsi->slave->dmd);
930 put_device(second);
931 }
932
933 pm_runtime_get_sync(dsi->dev);
934 if (dsi->slave)
935 pm_runtime_get_sync(dsi->slave->dev);
936
937 ret = clk_prepare_enable(dsi->pllref_clk);
938 if (ret) {
939 DRM_DEV_ERROR(dev, "Failed to enable pllref_clk: %d\n", ret);
940 goto out_pm_runtime;
941 }
942
943
944
945
946
947
948
949 ret = clk_prepare_enable(dsi->grf_clk);
950 if (ret) {
951 DRM_DEV_ERROR(dsi->dev, "Failed to enable grf_clk: %d\n", ret);
952 goto out_pll_clk;
953 }
954
955 dw_mipi_dsi_rockchip_config(dsi);
956 if (dsi->slave)
957 dw_mipi_dsi_rockchip_config(dsi->slave);
958
959 clk_disable_unprepare(dsi->grf_clk);
960
961 ret = rockchip_dsi_drm_create_encoder(dsi, drm_dev);
962 if (ret) {
963 DRM_DEV_ERROR(dev, "Failed to create drm encoder\n");
964 goto out_pll_clk;
965 }
966
967 ret = dw_mipi_dsi_bind(dsi->dmd, &dsi->encoder.encoder);
968 if (ret) {
969 DRM_DEV_ERROR(dev, "Failed to bind: %d\n", ret);
970 goto out_pll_clk;
971 }
972
973 dsi->dsi_bound = true;
974
975 return 0;
976
977out_pll_clk:
978 clk_disable_unprepare(dsi->pllref_clk);
979out_pm_runtime:
980 pm_runtime_put(dsi->dev);
981 if (dsi->slave)
982 pm_runtime_put(dsi->slave->dev);
983
984 return ret;
985}
986
987static void dw_mipi_dsi_rockchip_unbind(struct device *dev,
988 struct device *master,
989 void *data)
990{
991 struct dw_mipi_dsi_rockchip *dsi = dev_get_drvdata(dev);
992
993 if (dsi->is_slave)
994 return;
995
996 dsi->dsi_bound = false;
997
998 dw_mipi_dsi_unbind(dsi->dmd);
999
1000 clk_disable_unprepare(dsi->pllref_clk);
1001
1002 pm_runtime_put(dsi->dev);
1003 if (dsi->slave)
1004 pm_runtime_put(dsi->slave->dev);
1005}
1006
1007static const struct component_ops dw_mipi_dsi_rockchip_ops = {
1008 .bind = dw_mipi_dsi_rockchip_bind,
1009 .unbind = dw_mipi_dsi_rockchip_unbind,
1010};
1011
1012static int dw_mipi_dsi_rockchip_host_attach(void *priv_data,
1013 struct mipi_dsi_device *device)
1014{
1015 struct dw_mipi_dsi_rockchip *dsi = priv_data;
1016 struct device *second;
1017 int ret;
1018
1019 mutex_lock(&dsi->usage_mutex);
1020
1021 if (dsi->usage_mode != DW_DSI_USAGE_IDLE) {
1022 DRM_DEV_ERROR(dsi->dev, "dsi controller already in use\n");
1023 mutex_unlock(&dsi->usage_mutex);
1024 return -EBUSY;
1025 }
1026
1027 dsi->usage_mode = DW_DSI_USAGE_DSI;
1028 mutex_unlock(&dsi->usage_mutex);
1029
1030 ret = component_add(dsi->dev, &dw_mipi_dsi_rockchip_ops);
1031 if (ret) {
1032 DRM_DEV_ERROR(dsi->dev, "Failed to register component: %d\n",
1033 ret);
1034 return ret;
1035 }
1036
1037 second = dw_mipi_dsi_rockchip_find_second(dsi);
1038 if (IS_ERR(second))
1039 return PTR_ERR(second);
1040 if (second) {
1041 ret = component_add(second, &dw_mipi_dsi_rockchip_ops);
1042 if (ret) {
1043 DRM_DEV_ERROR(second,
1044 "Failed to register component: %d\n",
1045 ret);
1046 return ret;
1047 }
1048 }
1049
1050 return 0;
1051}
1052
1053static int dw_mipi_dsi_rockchip_host_detach(void *priv_data,
1054 struct mipi_dsi_device *device)
1055{
1056 struct dw_mipi_dsi_rockchip *dsi = priv_data;
1057 struct device *second;
1058
1059 second = dw_mipi_dsi_rockchip_find_second(dsi);
1060 if (second && !IS_ERR(second))
1061 component_del(second, &dw_mipi_dsi_rockchip_ops);
1062
1063 component_del(dsi->dev, &dw_mipi_dsi_rockchip_ops);
1064
1065 mutex_lock(&dsi->usage_mutex);
1066 dsi->usage_mode = DW_DSI_USAGE_IDLE;
1067 mutex_unlock(&dsi->usage_mutex);
1068
1069 return 0;
1070}
1071
1072static const struct dw_mipi_dsi_host_ops dw_mipi_dsi_rockchip_host_ops = {
1073 .attach = dw_mipi_dsi_rockchip_host_attach,
1074 .detach = dw_mipi_dsi_rockchip_host_detach,
1075};
1076
1077static int dw_mipi_dsi_rockchip_dphy_bind(struct device *dev,
1078 struct device *master,
1079 void *data)
1080{
1081
1082
1083
1084
1085
1086
1087 return 0;
1088}
1089
1090static void dw_mipi_dsi_rockchip_dphy_unbind(struct device *dev,
1091 struct device *master,
1092 void *data)
1093{
1094
1095}
1096
1097static const struct component_ops dw_mipi_dsi_rockchip_dphy_ops = {
1098 .bind = dw_mipi_dsi_rockchip_dphy_bind,
1099 .unbind = dw_mipi_dsi_rockchip_dphy_unbind,
1100};
1101
1102static int dw_mipi_dsi_dphy_init(struct phy *phy)
1103{
1104 struct dw_mipi_dsi_rockchip *dsi = phy_get_drvdata(phy);
1105 int ret;
1106
1107 mutex_lock(&dsi->usage_mutex);
1108
1109 if (dsi->usage_mode != DW_DSI_USAGE_IDLE) {
1110 DRM_DEV_ERROR(dsi->dev, "dsi controller already in use\n");
1111 mutex_unlock(&dsi->usage_mutex);
1112 return -EBUSY;
1113 }
1114
1115 dsi->usage_mode = DW_DSI_USAGE_PHY;
1116 mutex_unlock(&dsi->usage_mutex);
1117
1118 ret = component_add(dsi->dev, &dw_mipi_dsi_rockchip_dphy_ops);
1119 if (ret < 0)
1120 goto err_graph;
1121
1122 if (dsi->cdata->dphy_rx_init) {
1123 ret = clk_prepare_enable(dsi->pclk);
1124 if (ret < 0)
1125 goto err_init;
1126
1127 ret = clk_prepare_enable(dsi->grf_clk);
1128 if (ret) {
1129 clk_disable_unprepare(dsi->pclk);
1130 goto err_init;
1131 }
1132
1133 ret = dsi->cdata->dphy_rx_init(phy);
1134 clk_disable_unprepare(dsi->grf_clk);
1135 clk_disable_unprepare(dsi->pclk);
1136 if (ret < 0)
1137 goto err_init;
1138 }
1139
1140 return 0;
1141
1142err_init:
1143 component_del(dsi->dev, &dw_mipi_dsi_rockchip_dphy_ops);
1144err_graph:
1145 mutex_lock(&dsi->usage_mutex);
1146 dsi->usage_mode = DW_DSI_USAGE_IDLE;
1147 mutex_unlock(&dsi->usage_mutex);
1148
1149 return ret;
1150}
1151
1152static int dw_mipi_dsi_dphy_exit(struct phy *phy)
1153{
1154 struct dw_mipi_dsi_rockchip *dsi = phy_get_drvdata(phy);
1155
1156 component_del(dsi->dev, &dw_mipi_dsi_rockchip_dphy_ops);
1157
1158 mutex_lock(&dsi->usage_mutex);
1159 dsi->usage_mode = DW_DSI_USAGE_IDLE;
1160 mutex_unlock(&dsi->usage_mutex);
1161
1162 return 0;
1163}
1164
1165static int dw_mipi_dsi_dphy_configure(struct phy *phy, union phy_configure_opts *opts)
1166{
1167 struct phy_configure_opts_mipi_dphy *config = &opts->mipi_dphy;
1168 struct dw_mipi_dsi_rockchip *dsi = phy_get_drvdata(phy);
1169 int ret;
1170
1171 ret = phy_mipi_dphy_config_validate(&opts->mipi_dphy);
1172 if (ret)
1173 return ret;
1174
1175 dsi->dphy_config = *config;
1176 dsi->lane_mbps = div_u64(config->hs_clk_rate, 1000 * 1000 * 1);
1177
1178 return 0;
1179}
1180
1181static int dw_mipi_dsi_dphy_power_on(struct phy *phy)
1182{
1183 struct dw_mipi_dsi_rockchip *dsi = phy_get_drvdata(phy);
1184 int i, ret;
1185
1186 DRM_DEV_DEBUG(dsi->dev, "lanes %d - data_rate_mbps %u\n",
1187 dsi->dphy_config.lanes, dsi->lane_mbps);
1188
1189 i = max_mbps_to_parameter(dsi->lane_mbps);
1190 if (i < 0) {
1191 DRM_DEV_ERROR(dsi->dev, "failed to get parameter for %dmbps clock\n",
1192 dsi->lane_mbps);
1193 return i;
1194 }
1195
1196 ret = pm_runtime_get_sync(dsi->dev);
1197 if (ret < 0) {
1198 DRM_DEV_ERROR(dsi->dev, "failed to enable device: %d\n", ret);
1199 return ret;
1200 }
1201
1202 ret = clk_prepare_enable(dsi->pclk);
1203 if (ret) {
1204 DRM_DEV_ERROR(dsi->dev, "Failed to enable pclk: %d\n", ret);
1205 goto err_pclk;
1206 }
1207
1208 ret = clk_prepare_enable(dsi->grf_clk);
1209 if (ret) {
1210 DRM_DEV_ERROR(dsi->dev, "Failed to enable grf_clk: %d\n", ret);
1211 goto err_grf_clk;
1212 }
1213
1214 ret = clk_prepare_enable(dsi->phy_cfg_clk);
1215 if (ret) {
1216 DRM_DEV_ERROR(dsi->dev, "Failed to enable phy_cfg_clk: %d\n", ret);
1217 goto err_phy_cfg_clk;
1218 }
1219
1220
1221 if (dsi->cdata->dphy_rx_power_on) {
1222 ret = dsi->cdata->dphy_rx_power_on(phy);
1223 if (ret < 0) {
1224 DRM_DEV_ERROR(dsi->dev, "hardware-specific phy bringup failed: %d\n", ret);
1225 goto err_pwr_on;
1226 }
1227 }
1228
1229
1230
1231
1232
1233 dw_mipi_dsi_phy_write(dsi, HS_RX_CONTROL_OF_LANE_CLK, 0);
1234 dw_mipi_dsi_phy_write(dsi, HS_RX_CONTROL_OF_LANE_0,
1235 HSFREQRANGE_SEL(dppa_map[i].hsfreqrange));
1236 dw_mipi_dsi_phy_write(dsi, HS_RX_CONTROL_OF_LANE_1, 0);
1237 dw_mipi_dsi_phy_write(dsi, HS_RX_CONTROL_OF_LANE_2, 0);
1238 dw_mipi_dsi_phy_write(dsi, HS_RX_CONTROL_OF_LANE_3, 0);
1239
1240
1241 dw_mipi_dsi_phy_write(dsi, 0x0, 0);
1242
1243 clk_disable_unprepare(dsi->phy_cfg_clk);
1244 clk_disable_unprepare(dsi->grf_clk);
1245
1246 return ret;
1247
1248err_pwr_on:
1249 clk_disable_unprepare(dsi->phy_cfg_clk);
1250err_phy_cfg_clk:
1251 clk_disable_unprepare(dsi->grf_clk);
1252err_grf_clk:
1253 clk_disable_unprepare(dsi->pclk);
1254err_pclk:
1255 pm_runtime_put(dsi->dev);
1256 return ret;
1257}
1258
1259static int dw_mipi_dsi_dphy_power_off(struct phy *phy)
1260{
1261 struct dw_mipi_dsi_rockchip *dsi = phy_get_drvdata(phy);
1262 int ret;
1263
1264 ret = clk_prepare_enable(dsi->grf_clk);
1265 if (ret) {
1266 DRM_DEV_ERROR(dsi->dev, "Failed to enable grf_clk: %d\n", ret);
1267 return ret;
1268 }
1269
1270 if (dsi->cdata->dphy_rx_power_off) {
1271 ret = dsi->cdata->dphy_rx_power_off(phy);
1272 if (ret < 0)
1273 DRM_DEV_ERROR(dsi->dev, "hardware-specific phy shutdown failed: %d\n", ret);
1274 }
1275
1276 clk_disable_unprepare(dsi->grf_clk);
1277 clk_disable_unprepare(dsi->pclk);
1278
1279 pm_runtime_put(dsi->dev);
1280
1281 return ret;
1282}
1283
1284static const struct phy_ops dw_mipi_dsi_dphy_ops = {
1285 .configure = dw_mipi_dsi_dphy_configure,
1286 .power_on = dw_mipi_dsi_dphy_power_on,
1287 .power_off = dw_mipi_dsi_dphy_power_off,
1288 .init = dw_mipi_dsi_dphy_init,
1289 .exit = dw_mipi_dsi_dphy_exit,
1290};
1291
1292static int __maybe_unused dw_mipi_dsi_rockchip_resume(struct device *dev)
1293{
1294 struct dw_mipi_dsi_rockchip *dsi = dev_get_drvdata(dev);
1295 int ret;
1296
1297
1298
1299
1300
1301 if (dsi->dsi_bound) {
1302 ret = clk_prepare_enable(dsi->grf_clk);
1303 if (ret) {
1304 DRM_DEV_ERROR(dsi->dev, "Failed to enable grf_clk: %d\n", ret);
1305 return ret;
1306 }
1307
1308 dw_mipi_dsi_rockchip_config(dsi);
1309 if (dsi->slave)
1310 dw_mipi_dsi_rockchip_config(dsi->slave);
1311
1312 clk_disable_unprepare(dsi->grf_clk);
1313 }
1314
1315 return 0;
1316}
1317
1318static const struct dev_pm_ops dw_mipi_dsi_rockchip_pm_ops = {
1319 SET_LATE_SYSTEM_SLEEP_PM_OPS(NULL, dw_mipi_dsi_rockchip_resume)
1320};
1321
1322static int dw_mipi_dsi_rockchip_probe(struct platform_device *pdev)
1323{
1324 struct device *dev = &pdev->dev;
1325 struct device_node *np = dev->of_node;
1326 struct dw_mipi_dsi_rockchip *dsi;
1327 struct phy_provider *phy_provider;
1328 struct resource *res;
1329 const struct rockchip_dw_dsi_chip_data *cdata =
1330 of_device_get_match_data(dev);
1331 int ret, i;
1332
1333 dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL);
1334 if (!dsi)
1335 return -ENOMEM;
1336
1337 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1338 dsi->base = devm_ioremap_resource(dev, res);
1339 if (IS_ERR(dsi->base)) {
1340 DRM_DEV_ERROR(dev, "Unable to get dsi registers\n");
1341 return PTR_ERR(dsi->base);
1342 }
1343
1344 i = 0;
1345 while (cdata[i].reg) {
1346 if (cdata[i].reg == res->start) {
1347 dsi->cdata = &cdata[i];
1348 break;
1349 }
1350
1351 i++;
1352 }
1353
1354 if (!dsi->cdata) {
1355 DRM_DEV_ERROR(dev, "no dsi-config for %s node\n", np->name);
1356 return -EINVAL;
1357 }
1358
1359
1360 dsi->phy = devm_phy_optional_get(dev, "dphy");
1361 if (IS_ERR(dsi->phy)) {
1362 ret = PTR_ERR(dsi->phy);
1363 DRM_DEV_ERROR(dev, "failed to get mipi dphy: %d\n", ret);
1364 return ret;
1365 }
1366
1367 dsi->pclk = devm_clk_get(dev, "pclk");
1368 if (IS_ERR(dsi->pclk)) {
1369 ret = PTR_ERR(dsi->pclk);
1370 DRM_DEV_ERROR(dev, "Unable to get pclk: %d\n", ret);
1371 return ret;
1372 }
1373
1374 dsi->pllref_clk = devm_clk_get(dev, "ref");
1375 if (IS_ERR(dsi->pllref_clk)) {
1376 if (dsi->phy) {
1377
1378
1379
1380
1381 dsi->pllref_clk = NULL;
1382 } else {
1383 ret = PTR_ERR(dsi->pllref_clk);
1384 DRM_DEV_ERROR(dev,
1385 "Unable to get pll reference clock: %d\n",
1386 ret);
1387 return ret;
1388 }
1389 }
1390
1391 if (dsi->cdata->flags & DW_MIPI_NEEDS_PHY_CFG_CLK) {
1392 dsi->phy_cfg_clk = devm_clk_get(dev, "phy_cfg");
1393 if (IS_ERR(dsi->phy_cfg_clk)) {
1394 ret = PTR_ERR(dsi->phy_cfg_clk);
1395 DRM_DEV_ERROR(dev,
1396 "Unable to get phy_cfg_clk: %d\n", ret);
1397 return ret;
1398 }
1399 }
1400
1401 if (dsi->cdata->flags & DW_MIPI_NEEDS_GRF_CLK) {
1402 dsi->grf_clk = devm_clk_get(dev, "grf");
1403 if (IS_ERR(dsi->grf_clk)) {
1404 ret = PTR_ERR(dsi->grf_clk);
1405 DRM_DEV_ERROR(dev, "Unable to get grf_clk: %d\n", ret);
1406 return ret;
1407 }
1408 }
1409
1410 dsi->grf_regmap = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
1411 if (IS_ERR(dsi->grf_regmap)) {
1412 DRM_DEV_ERROR(dev, "Unable to get rockchip,grf\n");
1413 return PTR_ERR(dsi->grf_regmap);
1414 }
1415
1416 dsi->dev = dev;
1417 dsi->pdata.base = dsi->base;
1418 dsi->pdata.max_data_lanes = dsi->cdata->max_data_lanes;
1419 dsi->pdata.phy_ops = &dw_mipi_dsi_rockchip_phy_ops;
1420 dsi->pdata.host_ops = &dw_mipi_dsi_rockchip_host_ops;
1421 dsi->pdata.priv_data = dsi;
1422 platform_set_drvdata(pdev, dsi);
1423
1424 mutex_init(&dsi->usage_mutex);
1425
1426 dsi->dphy = devm_phy_create(dev, NULL, &dw_mipi_dsi_dphy_ops);
1427 if (IS_ERR(dsi->dphy)) {
1428 DRM_DEV_ERROR(&pdev->dev, "failed to create PHY\n");
1429 return PTR_ERR(dsi->dphy);
1430 }
1431
1432 phy_set_drvdata(dsi->dphy, dsi);
1433 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
1434 if (IS_ERR(phy_provider))
1435 return PTR_ERR(phy_provider);
1436
1437 dsi->dmd = dw_mipi_dsi_probe(pdev, &dsi->pdata);
1438 if (IS_ERR(dsi->dmd)) {
1439 ret = PTR_ERR(dsi->dmd);
1440 if (ret != -EPROBE_DEFER)
1441 DRM_DEV_ERROR(dev,
1442 "Failed to probe dw_mipi_dsi: %d\n", ret);
1443 return ret;
1444 }
1445
1446 return 0;
1447}
1448
1449static int dw_mipi_dsi_rockchip_remove(struct platform_device *pdev)
1450{
1451 struct dw_mipi_dsi_rockchip *dsi = platform_get_drvdata(pdev);
1452
1453 dw_mipi_dsi_remove(dsi->dmd);
1454
1455 return 0;
1456}
1457
1458static const struct rockchip_dw_dsi_chip_data px30_chip_data[] = {
1459 {
1460 .reg = 0xff450000,
1461 .lcdsel_grf_reg = PX30_GRF_PD_VO_CON1,
1462 .lcdsel_big = HIWORD_UPDATE(0, PX30_DSI_LCDC_SEL),
1463 .lcdsel_lit = HIWORD_UPDATE(PX30_DSI_LCDC_SEL,
1464 PX30_DSI_LCDC_SEL),
1465
1466 .lanecfg1_grf_reg = PX30_GRF_PD_VO_CON1,
1467 .lanecfg1 = HIWORD_UPDATE(0, PX30_DSI_TURNDISABLE |
1468 PX30_DSI_FORCERXMODE |
1469 PX30_DSI_FORCETXSTOPMODE),
1470
1471 .max_data_lanes = 4,
1472 },
1473 { }
1474};
1475
1476static const struct rockchip_dw_dsi_chip_data rk3288_chip_data[] = {
1477 {
1478 .reg = 0xff960000,
1479 .lcdsel_grf_reg = RK3288_GRF_SOC_CON6,
1480 .lcdsel_big = HIWORD_UPDATE(0, RK3288_DSI0_LCDC_SEL),
1481 .lcdsel_lit = HIWORD_UPDATE(RK3288_DSI0_LCDC_SEL, RK3288_DSI0_LCDC_SEL),
1482
1483 .max_data_lanes = 4,
1484 },
1485 {
1486 .reg = 0xff964000,
1487 .lcdsel_grf_reg = RK3288_GRF_SOC_CON6,
1488 .lcdsel_big = HIWORD_UPDATE(0, RK3288_DSI1_LCDC_SEL),
1489 .lcdsel_lit = HIWORD_UPDATE(RK3288_DSI1_LCDC_SEL, RK3288_DSI1_LCDC_SEL),
1490
1491 .max_data_lanes = 4,
1492 },
1493 { }
1494};
1495
1496static int rk3399_dphy_tx1rx1_init(struct phy *phy)
1497{
1498 struct dw_mipi_dsi_rockchip *dsi = phy_get_drvdata(phy);
1499
1500
1501
1502
1503
1504 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON24,
1505 HIWORD_UPDATE(0, RK3399_TXRX_SRC_SEL_ISP0));
1506 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON24,
1507 HIWORD_UPDATE(0, RK3399_TXRX_MASTERSLAVEZ));
1508 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON24,
1509 HIWORD_UPDATE(0, RK3399_TXRX_BASEDIR));
1510 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON23,
1511 HIWORD_UPDATE(0, RK3399_DSI1_ENABLE));
1512
1513 return 0;
1514}
1515
1516static int rk3399_dphy_tx1rx1_power_on(struct phy *phy)
1517{
1518 struct dw_mipi_dsi_rockchip *dsi = phy_get_drvdata(phy);
1519
1520
1521 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_TESTCLR);
1522 usleep_range(100, 150);
1523
1524 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON24,
1525 HIWORD_UPDATE(0, RK3399_TXRX_MASTERSLAVEZ));
1526 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON24,
1527 HIWORD_UPDATE(RK3399_TXRX_BASEDIR, RK3399_TXRX_BASEDIR));
1528
1529 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON23,
1530 HIWORD_UPDATE(0, RK3399_DSI1_FORCERXMODE));
1531 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON23,
1532 HIWORD_UPDATE(0, RK3399_DSI1_FORCETXSTOPMODE));
1533
1534
1535 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON24,
1536 HIWORD_UPDATE(0, RK3399_TXRX_TURNREQUEST));
1537 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON23,
1538 HIWORD_UPDATE(RK3399_DSI1_TURNDISABLE,
1539 RK3399_DSI1_TURNDISABLE));
1540 usleep_range(100, 150);
1541
1542 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_UNTESTCLR);
1543 usleep_range(100, 150);
1544
1545
1546 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON23,
1547 HIWORD_UPDATE(GENMASK(dsi->dphy_config.lanes - 1, 0),
1548 RK3399_DSI1_ENABLE));
1549
1550 usleep_range(100, 150);
1551
1552 return 0;
1553}
1554
1555static int rk3399_dphy_tx1rx1_power_off(struct phy *phy)
1556{
1557 struct dw_mipi_dsi_rockchip *dsi = phy_get_drvdata(phy);
1558
1559 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON23,
1560 HIWORD_UPDATE(0, RK3399_DSI1_ENABLE));
1561
1562 return 0;
1563}
1564
1565static const struct rockchip_dw_dsi_chip_data rk3399_chip_data[] = {
1566 {
1567 .reg = 0xff960000,
1568 .lcdsel_grf_reg = RK3399_GRF_SOC_CON20,
1569 .lcdsel_big = HIWORD_UPDATE(0, RK3399_DSI0_LCDC_SEL),
1570 .lcdsel_lit = HIWORD_UPDATE(RK3399_DSI0_LCDC_SEL,
1571 RK3399_DSI0_LCDC_SEL),
1572
1573 .lanecfg1_grf_reg = RK3399_GRF_SOC_CON22,
1574 .lanecfg1 = HIWORD_UPDATE(0, RK3399_DSI0_TURNREQUEST |
1575 RK3399_DSI0_TURNDISABLE |
1576 RK3399_DSI0_FORCETXSTOPMODE |
1577 RK3399_DSI0_FORCERXMODE),
1578
1579 .flags = DW_MIPI_NEEDS_PHY_CFG_CLK | DW_MIPI_NEEDS_GRF_CLK,
1580 .max_data_lanes = 4,
1581 },
1582 {
1583 .reg = 0xff968000,
1584 .lcdsel_grf_reg = RK3399_GRF_SOC_CON20,
1585 .lcdsel_big = HIWORD_UPDATE(0, RK3399_DSI1_LCDC_SEL),
1586 .lcdsel_lit = HIWORD_UPDATE(RK3399_DSI1_LCDC_SEL,
1587 RK3399_DSI1_LCDC_SEL),
1588
1589 .lanecfg1_grf_reg = RK3399_GRF_SOC_CON23,
1590 .lanecfg1 = HIWORD_UPDATE(0, RK3399_DSI1_TURNDISABLE |
1591 RK3399_DSI1_FORCETXSTOPMODE |
1592 RK3399_DSI1_FORCERXMODE |
1593 RK3399_DSI1_ENABLE),
1594
1595 .lanecfg2_grf_reg = RK3399_GRF_SOC_CON24,
1596 .lanecfg2 = HIWORD_UPDATE(RK3399_TXRX_MASTERSLAVEZ |
1597 RK3399_TXRX_ENABLECLK,
1598 RK3399_TXRX_MASTERSLAVEZ |
1599 RK3399_TXRX_ENABLECLK |
1600 RK3399_TXRX_BASEDIR),
1601
1602 .enable_grf_reg = RK3399_GRF_SOC_CON23,
1603 .enable = HIWORD_UPDATE(RK3399_DSI1_ENABLE, RK3399_DSI1_ENABLE),
1604
1605 .flags = DW_MIPI_NEEDS_PHY_CFG_CLK | DW_MIPI_NEEDS_GRF_CLK,
1606 .max_data_lanes = 4,
1607
1608 .dphy_rx_init = rk3399_dphy_tx1rx1_init,
1609 .dphy_rx_power_on = rk3399_dphy_tx1rx1_power_on,
1610 .dphy_rx_power_off = rk3399_dphy_tx1rx1_power_off,
1611 },
1612 { }
1613};
1614
1615static const struct of_device_id dw_mipi_dsi_rockchip_dt_ids[] = {
1616 {
1617 .compatible = "rockchip,px30-mipi-dsi",
1618 .data = &px30_chip_data,
1619 }, {
1620 .compatible = "rockchip,rk3288-mipi-dsi",
1621 .data = &rk3288_chip_data,
1622 }, {
1623 .compatible = "rockchip,rk3399-mipi-dsi",
1624 .data = &rk3399_chip_data,
1625 },
1626 { }
1627};
1628MODULE_DEVICE_TABLE(of, dw_mipi_dsi_rockchip_dt_ids);
1629
1630struct platform_driver dw_mipi_dsi_rockchip_driver = {
1631 .probe = dw_mipi_dsi_rockchip_probe,
1632 .remove = dw_mipi_dsi_rockchip_remove,
1633 .driver = {
1634 .of_match_table = dw_mipi_dsi_rockchip_dt_ids,
1635 .pm = &dw_mipi_dsi_rockchip_pm_ops,
1636 .name = "dw-mipi-dsi-rockchip",
1637 },
1638};
1639
