1
2
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5
6#include <linux/module.h>
7#include <linux/slab.h>
8#include <linux/i2c.h>
9#include <linux/err.h>
10#include <linux/delay.h>
11#include <linux/sysfs.h>
12#include <linux/jiffies.h>
13#include <linux/irq.h>
14#include <linux/interrupt.h>
15#include <linux/iio/iio.h>
16#include <linux/acpi.h>
17#include <linux/platform_device.h>
18#include <linux/regulator/consumer.h>
19#include <linux/pm.h>
20#include <linux/pm_runtime.h>
21#include "inv_mpu_iio.h"
22#include "inv_mpu_magn.h"
23
24
25
26
27
28static const int gyro_scale_6050[] = {133090, 266181, 532362, 1064724};
29
30
31
32
33
34static const int accel_scale[] = {598, 1196, 2392, 4785};
35
36static const struct inv_mpu6050_reg_map reg_set_icm20602 = {
37 .sample_rate_div = INV_MPU6050_REG_SAMPLE_RATE_DIV,
38 .lpf = INV_MPU6050_REG_CONFIG,
39 .accel_lpf = INV_MPU6500_REG_ACCEL_CONFIG_2,
40 .user_ctrl = INV_MPU6050_REG_USER_CTRL,
41 .fifo_en = INV_MPU6050_REG_FIFO_EN,
42 .gyro_config = INV_MPU6050_REG_GYRO_CONFIG,
43 .accl_config = INV_MPU6050_REG_ACCEL_CONFIG,
44 .fifo_count_h = INV_MPU6050_REG_FIFO_COUNT_H,
45 .fifo_r_w = INV_MPU6050_REG_FIFO_R_W,
46 .raw_gyro = INV_MPU6050_REG_RAW_GYRO,
47 .raw_accl = INV_MPU6050_REG_RAW_ACCEL,
48 .temperature = INV_MPU6050_REG_TEMPERATURE,
49 .int_enable = INV_MPU6050_REG_INT_ENABLE,
50 .int_status = INV_MPU6050_REG_INT_STATUS,
51 .pwr_mgmt_1 = INV_MPU6050_REG_PWR_MGMT_1,
52 .pwr_mgmt_2 = INV_MPU6050_REG_PWR_MGMT_2,
53 .int_pin_cfg = INV_MPU6050_REG_INT_PIN_CFG,
54 .accl_offset = INV_MPU6500_REG_ACCEL_OFFSET,
55 .gyro_offset = INV_MPU6050_REG_GYRO_OFFSET,
56 .i2c_if = INV_ICM20602_REG_I2C_IF,
57};
58
59static const struct inv_mpu6050_reg_map reg_set_6500 = {
60 .sample_rate_div = INV_MPU6050_REG_SAMPLE_RATE_DIV,
61 .lpf = INV_MPU6050_REG_CONFIG,
62 .accel_lpf = INV_MPU6500_REG_ACCEL_CONFIG_2,
63 .user_ctrl = INV_MPU6050_REG_USER_CTRL,
64 .fifo_en = INV_MPU6050_REG_FIFO_EN,
65 .gyro_config = INV_MPU6050_REG_GYRO_CONFIG,
66 .accl_config = INV_MPU6050_REG_ACCEL_CONFIG,
67 .fifo_count_h = INV_MPU6050_REG_FIFO_COUNT_H,
68 .fifo_r_w = INV_MPU6050_REG_FIFO_R_W,
69 .raw_gyro = INV_MPU6050_REG_RAW_GYRO,
70 .raw_accl = INV_MPU6050_REG_RAW_ACCEL,
71 .temperature = INV_MPU6050_REG_TEMPERATURE,
72 .int_enable = INV_MPU6050_REG_INT_ENABLE,
73 .int_status = INV_MPU6050_REG_INT_STATUS,
74 .pwr_mgmt_1 = INV_MPU6050_REG_PWR_MGMT_1,
75 .pwr_mgmt_2 = INV_MPU6050_REG_PWR_MGMT_2,
76 .int_pin_cfg = INV_MPU6050_REG_INT_PIN_CFG,
77 .accl_offset = INV_MPU6500_REG_ACCEL_OFFSET,
78 .gyro_offset = INV_MPU6050_REG_GYRO_OFFSET,
79 .i2c_if = 0,
80};
81
82static const struct inv_mpu6050_reg_map reg_set_6050 = {
83 .sample_rate_div = INV_MPU6050_REG_SAMPLE_RATE_DIV,
84 .lpf = INV_MPU6050_REG_CONFIG,
85 .user_ctrl = INV_MPU6050_REG_USER_CTRL,
86 .fifo_en = INV_MPU6050_REG_FIFO_EN,
87 .gyro_config = INV_MPU6050_REG_GYRO_CONFIG,
88 .accl_config = INV_MPU6050_REG_ACCEL_CONFIG,
89 .fifo_count_h = INV_MPU6050_REG_FIFO_COUNT_H,
90 .fifo_r_w = INV_MPU6050_REG_FIFO_R_W,
91 .raw_gyro = INV_MPU6050_REG_RAW_GYRO,
92 .raw_accl = INV_MPU6050_REG_RAW_ACCEL,
93 .temperature = INV_MPU6050_REG_TEMPERATURE,
94 .int_enable = INV_MPU6050_REG_INT_ENABLE,
95 .pwr_mgmt_1 = INV_MPU6050_REG_PWR_MGMT_1,
96 .pwr_mgmt_2 = INV_MPU6050_REG_PWR_MGMT_2,
97 .int_pin_cfg = INV_MPU6050_REG_INT_PIN_CFG,
98 .accl_offset = INV_MPU6050_REG_ACCEL_OFFSET,
99 .gyro_offset = INV_MPU6050_REG_GYRO_OFFSET,
100 .i2c_if = 0,
101};
102
103static const struct inv_mpu6050_chip_config chip_config_6050 = {
104 .clk = INV_CLK_INTERNAL,
105 .fsr = INV_MPU6050_FSR_2000DPS,
106 .lpf = INV_MPU6050_FILTER_20HZ,
107 .divider = INV_MPU6050_FIFO_RATE_TO_DIVIDER(50),
108 .gyro_en = true,
109 .accl_en = true,
110 .temp_en = true,
111 .magn_en = false,
112 .gyro_fifo_enable = false,
113 .accl_fifo_enable = false,
114 .temp_fifo_enable = false,
115 .magn_fifo_enable = false,
116 .accl_fs = INV_MPU6050_FS_02G,
117 .user_ctrl = 0,
118};
119
120static const struct inv_mpu6050_chip_config chip_config_6500 = {
121 .clk = INV_CLK_PLL,
122 .fsr = INV_MPU6050_FSR_2000DPS,
123 .lpf = INV_MPU6050_FILTER_20HZ,
124 .divider = INV_MPU6050_FIFO_RATE_TO_DIVIDER(50),
125 .gyro_en = true,
126 .accl_en = true,
127 .temp_en = true,
128 .magn_en = false,
129 .gyro_fifo_enable = false,
130 .accl_fifo_enable = false,
131 .temp_fifo_enable = false,
132 .magn_fifo_enable = false,
133 .accl_fs = INV_MPU6050_FS_02G,
134 .user_ctrl = 0,
135};
136
137
138static const struct inv_mpu6050_hw hw_info[] = {
139 {
140 .whoami = INV_MPU6050_WHOAMI_VALUE,
141 .name = "MPU6050",
142 .reg = ®_set_6050,
143 .config = &chip_config_6050,
144 .fifo_size = 1024,
145 .temp = {INV_MPU6050_TEMP_OFFSET, INV_MPU6050_TEMP_SCALE},
146 .startup_time = {INV_MPU6050_GYRO_STARTUP_TIME, INV_MPU6050_ACCEL_STARTUP_TIME},
147 },
148 {
149 .whoami = INV_MPU6500_WHOAMI_VALUE,
150 .name = "MPU6500",
151 .reg = ®_set_6500,
152 .config = &chip_config_6500,
153 .fifo_size = 512,
154 .temp = {INV_MPU6500_TEMP_OFFSET, INV_MPU6500_TEMP_SCALE},
155 .startup_time = {INV_MPU6500_GYRO_STARTUP_TIME, INV_MPU6500_ACCEL_STARTUP_TIME},
156 },
157 {
158 .whoami = INV_MPU6515_WHOAMI_VALUE,
159 .name = "MPU6515",
160 .reg = ®_set_6500,
161 .config = &chip_config_6500,
162 .fifo_size = 512,
163 .temp = {INV_MPU6500_TEMP_OFFSET, INV_MPU6500_TEMP_SCALE},
164 .startup_time = {INV_MPU6500_GYRO_STARTUP_TIME, INV_MPU6500_ACCEL_STARTUP_TIME},
165 },
166 {
167 .whoami = INV_MPU6880_WHOAMI_VALUE,
168 .name = "MPU6880",
169 .reg = ®_set_6500,
170 .config = &chip_config_6500,
171 .fifo_size = 4096,
172 .temp = {INV_MPU6500_TEMP_OFFSET, INV_MPU6500_TEMP_SCALE},
173 .startup_time = {INV_MPU6500_GYRO_STARTUP_TIME, INV_MPU6500_ACCEL_STARTUP_TIME},
174 },
175 {
176 .whoami = INV_MPU6000_WHOAMI_VALUE,
177 .name = "MPU6000",
178 .reg = ®_set_6050,
179 .config = &chip_config_6050,
180 .fifo_size = 1024,
181 .temp = {INV_MPU6050_TEMP_OFFSET, INV_MPU6050_TEMP_SCALE},
182 .startup_time = {INV_MPU6050_GYRO_STARTUP_TIME, INV_MPU6050_ACCEL_STARTUP_TIME},
183 },
184 {
185 .whoami = INV_MPU9150_WHOAMI_VALUE,
186 .name = "MPU9150",
187 .reg = ®_set_6050,
188 .config = &chip_config_6050,
189 .fifo_size = 1024,
190 .temp = {INV_MPU6050_TEMP_OFFSET, INV_MPU6050_TEMP_SCALE},
191 .startup_time = {INV_MPU6050_GYRO_STARTUP_TIME, INV_MPU6050_ACCEL_STARTUP_TIME},
192 },
193 {
194 .whoami = INV_MPU9250_WHOAMI_VALUE,
195 .name = "MPU9250",
196 .reg = ®_set_6500,
197 .config = &chip_config_6500,
198 .fifo_size = 512,
199 .temp = {INV_MPU6500_TEMP_OFFSET, INV_MPU6500_TEMP_SCALE},
200 .startup_time = {INV_MPU6500_GYRO_STARTUP_TIME, INV_MPU6500_ACCEL_STARTUP_TIME},
201 },
202 {
203 .whoami = INV_MPU9255_WHOAMI_VALUE,
204 .name = "MPU9255",
205 .reg = ®_set_6500,
206 .config = &chip_config_6500,
207 .fifo_size = 512,
208 .temp = {INV_MPU6500_TEMP_OFFSET, INV_MPU6500_TEMP_SCALE},
209 .startup_time = {INV_MPU6500_GYRO_STARTUP_TIME, INV_MPU6500_ACCEL_STARTUP_TIME},
210 },
211 {
212 .whoami = INV_ICM20608_WHOAMI_VALUE,
213 .name = "ICM20608",
214 .reg = ®_set_6500,
215 .config = &chip_config_6500,
216 .fifo_size = 512,
217 .temp = {INV_ICM20608_TEMP_OFFSET, INV_ICM20608_TEMP_SCALE},
218 .startup_time = {INV_MPU6500_GYRO_STARTUP_TIME, INV_MPU6500_ACCEL_STARTUP_TIME},
219 },
220 {
221 .whoami = INV_ICM20608D_WHOAMI_VALUE,
222 .name = "ICM20608D",
223 .reg = ®_set_6500,
224 .config = &chip_config_6500,
225 .fifo_size = 512,
226 .temp = {INV_ICM20608_TEMP_OFFSET, INV_ICM20608_TEMP_SCALE},
227 .startup_time = {INV_MPU6500_GYRO_STARTUP_TIME, INV_MPU6500_ACCEL_STARTUP_TIME},
228 },
229 {
230 .whoami = INV_ICM20609_WHOAMI_VALUE,
231 .name = "ICM20609",
232 .reg = ®_set_6500,
233 .config = &chip_config_6500,
234 .fifo_size = 4 * 1024,
235 .temp = {INV_ICM20608_TEMP_OFFSET, INV_ICM20608_TEMP_SCALE},
236 .startup_time = {INV_MPU6500_GYRO_STARTUP_TIME, INV_MPU6500_ACCEL_STARTUP_TIME},
237 },
238 {
239 .whoami = INV_ICM20689_WHOAMI_VALUE,
240 .name = "ICM20689",
241 .reg = ®_set_6500,
242 .config = &chip_config_6500,
243 .fifo_size = 4 * 1024,
244 .temp = {INV_ICM20608_TEMP_OFFSET, INV_ICM20608_TEMP_SCALE},
245 .startup_time = {INV_MPU6500_GYRO_STARTUP_TIME, INV_MPU6500_ACCEL_STARTUP_TIME},
246 },
247 {
248 .whoami = INV_ICM20602_WHOAMI_VALUE,
249 .name = "ICM20602",
250 .reg = ®_set_icm20602,
251 .config = &chip_config_6500,
252 .fifo_size = 1008,
253 .temp = {INV_ICM20608_TEMP_OFFSET, INV_ICM20608_TEMP_SCALE},
254 .startup_time = {INV_ICM20602_GYRO_STARTUP_TIME, INV_ICM20602_ACCEL_STARTUP_TIME},
255 },
256 {
257 .whoami = INV_ICM20690_WHOAMI_VALUE,
258 .name = "ICM20690",
259 .reg = ®_set_6500,
260 .config = &chip_config_6500,
261 .fifo_size = 1024,
262 .temp = {INV_ICM20608_TEMP_OFFSET, INV_ICM20608_TEMP_SCALE},
263 .startup_time = {INV_ICM20690_GYRO_STARTUP_TIME, INV_ICM20690_ACCEL_STARTUP_TIME},
264 },
265 {
266 .whoami = INV_IAM20680_WHOAMI_VALUE,
267 .name = "IAM20680",
268 .reg = ®_set_6500,
269 .config = &chip_config_6500,
270 .fifo_size = 512,
271 .temp = {INV_ICM20608_TEMP_OFFSET, INV_ICM20608_TEMP_SCALE},
272 .startup_time = {INV_MPU6500_GYRO_STARTUP_TIME, INV_MPU6500_ACCEL_STARTUP_TIME},
273 },
274};
275
276static int inv_mpu6050_pwr_mgmt_1_write(struct inv_mpu6050_state *st, bool sleep,
277 int clock, int temp_dis)
278{
279 u8 val;
280
281 if (clock < 0)
282 clock = st->chip_config.clk;
283 if (temp_dis < 0)
284 temp_dis = !st->chip_config.temp_en;
285
286 val = clock & INV_MPU6050_BIT_CLK_MASK;
287 if (temp_dis)
288 val |= INV_MPU6050_BIT_TEMP_DIS;
289 if (sleep)
290 val |= INV_MPU6050_BIT_SLEEP;
291
292 dev_dbg(regmap_get_device(st->map), "pwr_mgmt_1: 0x%x\n", val);
293 return regmap_write(st->map, st->reg->pwr_mgmt_1, val);
294}
295
296static int inv_mpu6050_clock_switch(struct inv_mpu6050_state *st,
297 unsigned int clock)
298{
299 int ret;
300
301 switch (st->chip_type) {
302 case INV_MPU6050:
303 case INV_MPU6000:
304 case INV_MPU9150:
305
306 ret = inv_mpu6050_pwr_mgmt_1_write(st, false, clock, -1);
307 if (ret)
308 return ret;
309 st->chip_config.clk = clock;
310 break;
311 default:
312
313 break;
314 }
315
316 return 0;
317}
318
319int inv_mpu6050_switch_engine(struct inv_mpu6050_state *st, bool en,
320 unsigned int mask)
321{
322 unsigned int sleep;
323 u8 pwr_mgmt2, user_ctrl;
324 int ret;
325
326
327 if (mask & INV_MPU6050_SENSOR_ACCL && en == st->chip_config.accl_en)
328 mask &= ~INV_MPU6050_SENSOR_ACCL;
329 if (mask & INV_MPU6050_SENSOR_GYRO && en == st->chip_config.gyro_en)
330 mask &= ~INV_MPU6050_SENSOR_GYRO;
331 if (mask & INV_MPU6050_SENSOR_TEMP && en == st->chip_config.temp_en)
332 mask &= ~INV_MPU6050_SENSOR_TEMP;
333 if (mask & INV_MPU6050_SENSOR_MAGN && en == st->chip_config.magn_en)
334 mask &= ~INV_MPU6050_SENSOR_MAGN;
335 if (mask == 0)
336 return 0;
337
338
339 if (mask & INV_MPU6050_SENSOR_TEMP) {
340 ret = inv_mpu6050_pwr_mgmt_1_write(st, false, -1, !en);
341 if (ret)
342 return ret;
343 st->chip_config.temp_en = en;
344 }
345
346
347 if (mask & INV_MPU6050_SENSOR_MAGN) {
348 user_ctrl = st->chip_config.user_ctrl;
349 if (en)
350 user_ctrl |= INV_MPU6050_BIT_I2C_MST_EN;
351 else
352 user_ctrl &= ~INV_MPU6050_BIT_I2C_MST_EN;
353 ret = regmap_write(st->map, st->reg->user_ctrl, user_ctrl);
354 if (ret)
355 return ret;
356 st->chip_config.user_ctrl = user_ctrl;
357 st->chip_config.magn_en = en;
358 }
359
360
361 if (mask & (INV_MPU6050_SENSOR_ACCL | INV_MPU6050_SENSOR_GYRO)) {
362
363 pwr_mgmt2 = 0;
364 if (!st->chip_config.accl_en)
365 pwr_mgmt2 |= INV_MPU6050_BIT_PWR_ACCL_STBY;
366 if (!st->chip_config.gyro_en)
367 pwr_mgmt2 |= INV_MPU6050_BIT_PWR_GYRO_STBY;
368
369
370 if (mask & INV_MPU6050_SENSOR_ACCL) {
371 if (en)
372 pwr_mgmt2 &= ~INV_MPU6050_BIT_PWR_ACCL_STBY;
373 else
374 pwr_mgmt2 |= INV_MPU6050_BIT_PWR_ACCL_STBY;
375 }
376 if (mask & INV_MPU6050_SENSOR_GYRO) {
377 if (en)
378 pwr_mgmt2 &= ~INV_MPU6050_BIT_PWR_GYRO_STBY;
379 else
380 pwr_mgmt2 |= INV_MPU6050_BIT_PWR_GYRO_STBY;
381 }
382
383
384 if (mask & INV_MPU6050_SENSOR_GYRO && !en) {
385 ret = inv_mpu6050_clock_switch(st, INV_CLK_INTERNAL);
386 if (ret)
387 return ret;
388 }
389
390
391 dev_dbg(regmap_get_device(st->map), "pwr_mgmt_2: 0x%x\n",
392 pwr_mgmt2);
393 ret = regmap_write(st->map, st->reg->pwr_mgmt_2, pwr_mgmt2);
394 if (ret)
395 return ret;
396 if (mask & INV_MPU6050_SENSOR_ACCL)
397 st->chip_config.accl_en = en;
398 if (mask & INV_MPU6050_SENSOR_GYRO)
399 st->chip_config.gyro_en = en;
400
401
402 sleep = 0;
403 if (en) {
404 if (mask & INV_MPU6050_SENSOR_ACCL) {
405 if (sleep < st->hw->startup_time.accel)
406 sleep = st->hw->startup_time.accel;
407 }
408 if (mask & INV_MPU6050_SENSOR_GYRO) {
409 if (sleep < st->hw->startup_time.gyro)
410 sleep = st->hw->startup_time.gyro;
411 }
412 } else {
413 if (mask & INV_MPU6050_SENSOR_GYRO) {
414 if (sleep < INV_MPU6050_GYRO_DOWN_TIME)
415 sleep = INV_MPU6050_GYRO_DOWN_TIME;
416 }
417 }
418 if (sleep)
419 msleep(sleep);
420
421
422 if (mask & INV_MPU6050_SENSOR_GYRO && en) {
423 ret = inv_mpu6050_clock_switch(st, INV_CLK_PLL);
424 if (ret)
425 return ret;
426 }
427 }
428
429 return 0;
430}
431
432static int inv_mpu6050_set_power_itg(struct inv_mpu6050_state *st,
433 bool power_on)
434{
435 int result;
436
437 result = inv_mpu6050_pwr_mgmt_1_write(st, !power_on, -1, -1);
438 if (result)
439 return result;
440
441 if (power_on)
442 usleep_range(INV_MPU6050_REG_UP_TIME_MIN,
443 INV_MPU6050_REG_UP_TIME_MAX);
444
445 return 0;
446}
447
448static int inv_mpu6050_set_gyro_fsr(struct inv_mpu6050_state *st,
449 enum inv_mpu6050_fsr_e val)
450{
451 unsigned int gyro_shift;
452 u8 data;
453
454 switch (st->chip_type) {
455 case INV_ICM20690:
456 gyro_shift = INV_ICM20690_GYRO_CONFIG_FSR_SHIFT;
457 break;
458 default:
459 gyro_shift = INV_MPU6050_GYRO_CONFIG_FSR_SHIFT;
460 break;
461 }
462
463 data = val << gyro_shift;
464 return regmap_write(st->map, st->reg->gyro_config, data);
465}
466
467
468
469
470
471
472
473static int inv_mpu6050_set_lpf_regs(struct inv_mpu6050_state *st,
474 enum inv_mpu6050_filter_e val)
475{
476 int result;
477
478 result = regmap_write(st->map, st->reg->lpf, val);
479 if (result)
480 return result;
481
482
483 switch (st->chip_type) {
484 case INV_MPU6050:
485 case INV_MPU6000:
486 case INV_MPU9150:
487
488 return 0;
489 case INV_ICM20689:
490 case INV_ICM20690:
491
492 val |= INV_ICM20689_BITS_FIFO_SIZE_MAX;
493 break;
494 default:
495 break;
496 }
497
498 return regmap_write(st->map, st->reg->accel_lpf, val);
499}
500
501
502
503
504
505
506
507
508
509
510static int inv_mpu6050_init_config(struct iio_dev *indio_dev)
511{
512 int result;
513 u8 d;
514 struct inv_mpu6050_state *st = iio_priv(indio_dev);
515
516 result = inv_mpu6050_set_gyro_fsr(st, st->chip_config.fsr);
517 if (result)
518 return result;
519
520 result = inv_mpu6050_set_lpf_regs(st, st->chip_config.lpf);
521 if (result)
522 return result;
523
524 d = st->chip_config.divider;
525 result = regmap_write(st->map, st->reg->sample_rate_div, d);
526 if (result)
527 return result;
528
529 d = (st->chip_config.accl_fs << INV_MPU6050_ACCL_CONFIG_FSR_SHIFT);
530 result = regmap_write(st->map, st->reg->accl_config, d);
531 if (result)
532 return result;
533
534 result = regmap_write(st->map, st->reg->int_pin_cfg, st->irq_mask);
535 if (result)
536 return result;
537
538
539
540
541
542
543 st->chip_period = NSEC_PER_MSEC;
544
545
546 result = inv_mpu_magn_probe(st);
547 if (result)
548 return result;
549
550 return 0;
551}
552
553static int inv_mpu6050_sensor_set(struct inv_mpu6050_state *st, int reg,
554 int axis, int val)
555{
556 int ind, result;
557 __be16 d = cpu_to_be16(val);
558
559 ind = (axis - IIO_MOD_X) * 2;
560 result = regmap_bulk_write(st->map, reg + ind, &d, sizeof(d));
561 if (result)
562 return -EINVAL;
563
564 return 0;
565}
566
567static int inv_mpu6050_sensor_show(struct inv_mpu6050_state *st, int reg,
568 int axis, int *val)
569{
570 int ind, result;
571 __be16 d;
572
573 ind = (axis - IIO_MOD_X) * 2;
574 result = regmap_bulk_read(st->map, reg + ind, &d, sizeof(d));
575 if (result)
576 return -EINVAL;
577 *val = (short)be16_to_cpup(&d);
578
579 return IIO_VAL_INT;
580}
581
582static int inv_mpu6050_read_channel_data(struct iio_dev *indio_dev,
583 struct iio_chan_spec const *chan,
584 int *val)
585{
586 struct inv_mpu6050_state *st = iio_priv(indio_dev);
587 struct device *pdev = regmap_get_device(st->map);
588 unsigned int freq_hz, period_us, min_sleep_us, max_sleep_us;
589 int result;
590 int ret;
591
592
593 freq_hz = INV_MPU6050_DIVIDER_TO_FIFO_RATE(st->chip_config.divider);
594 period_us = 1000000 / freq_hz;
595
596 result = pm_runtime_resume_and_get(pdev);
597 if (result)
598 return result;
599
600 switch (chan->type) {
601 case IIO_ANGL_VEL:
602 if (!st->chip_config.gyro_en) {
603 result = inv_mpu6050_switch_engine(st, true,
604 INV_MPU6050_SENSOR_GYRO);
605 if (result)
606 goto error_power_off;
607
608 min_sleep_us = 2 * period_us;
609 max_sleep_us = 2 * (period_us + period_us / 2);
610 usleep_range(min_sleep_us, max_sleep_us);
611 }
612 ret = inv_mpu6050_sensor_show(st, st->reg->raw_gyro,
613 chan->channel2, val);
614 break;
615 case IIO_ACCEL:
616 if (!st->chip_config.accl_en) {
617 result = inv_mpu6050_switch_engine(st, true,
618 INV_MPU6050_SENSOR_ACCL);
619 if (result)
620 goto error_power_off;
621
622 min_sleep_us = period_us;
623 max_sleep_us = period_us + period_us / 2;
624 usleep_range(min_sleep_us, max_sleep_us);
625 }
626 ret = inv_mpu6050_sensor_show(st, st->reg->raw_accl,
627 chan->channel2, val);
628 break;
629 case IIO_TEMP:
630
631 if (!st->chip_config.accl_en && !st->chip_config.gyro_en) {
632 result = -EBUSY;
633 goto error_power_off;
634 }
635 if (!st->chip_config.temp_en) {
636 result = inv_mpu6050_switch_engine(st, true,
637 INV_MPU6050_SENSOR_TEMP);
638 if (result)
639 goto error_power_off;
640
641 min_sleep_us = period_us;
642 max_sleep_us = period_us + period_us / 2;
643 usleep_range(min_sleep_us, max_sleep_us);
644 }
645 ret = inv_mpu6050_sensor_show(st, st->reg->temperature,
646 IIO_MOD_X, val);
647 break;
648 case IIO_MAGN:
649 if (!st->chip_config.magn_en) {
650 result = inv_mpu6050_switch_engine(st, true,
651 INV_MPU6050_SENSOR_MAGN);
652 if (result)
653 goto error_power_off;
654
655 if (freq_hz > INV_MPU_MAGN_FREQ_HZ_MAX) {
656 freq_hz = INV_MPU_MAGN_FREQ_HZ_MAX;
657 period_us = 1000000 / freq_hz;
658 }
659
660 min_sleep_us = 2 * period_us;
661 max_sleep_us = 2 * (period_us + period_us / 2);
662 usleep_range(min_sleep_us, max_sleep_us);
663 }
664 ret = inv_mpu_magn_read(st, chan->channel2, val);
665 break;
666 default:
667 ret = -EINVAL;
668 break;
669 }
670
671 pm_runtime_mark_last_busy(pdev);
672 pm_runtime_put_autosuspend(pdev);
673
674 return ret;
675
676error_power_off:
677 pm_runtime_put_autosuspend(pdev);
678 return result;
679}
680
681static int
682inv_mpu6050_read_raw(struct iio_dev *indio_dev,
683 struct iio_chan_spec const *chan,
684 int *val, int *val2, long mask)
685{
686 struct inv_mpu6050_state *st = iio_priv(indio_dev);
687 int ret = 0;
688
689 switch (mask) {
690 case IIO_CHAN_INFO_RAW:
691 ret = iio_device_claim_direct_mode(indio_dev);
692 if (ret)
693 return ret;
694 mutex_lock(&st->lock);
695 ret = inv_mpu6050_read_channel_data(indio_dev, chan, val);
696 mutex_unlock(&st->lock);
697 iio_device_release_direct_mode(indio_dev);
698 return ret;
699 case IIO_CHAN_INFO_SCALE:
700 switch (chan->type) {
701 case IIO_ANGL_VEL:
702 mutex_lock(&st->lock);
703 *val = 0;
704 *val2 = gyro_scale_6050[st->chip_config.fsr];
705 mutex_unlock(&st->lock);
706
707 return IIO_VAL_INT_PLUS_NANO;
708 case IIO_ACCEL:
709 mutex_lock(&st->lock);
710 *val = 0;
711 *val2 = accel_scale[st->chip_config.accl_fs];
712 mutex_unlock(&st->lock);
713
714 return IIO_VAL_INT_PLUS_MICRO;
715 case IIO_TEMP:
716 *val = st->hw->temp.scale / 1000000;
717 *val2 = st->hw->temp.scale % 1000000;
718 return IIO_VAL_INT_PLUS_MICRO;
719 case IIO_MAGN:
720 return inv_mpu_magn_get_scale(st, chan, val, val2);
721 default:
722 return -EINVAL;
723 }
724 case IIO_CHAN_INFO_OFFSET:
725 switch (chan->type) {
726 case IIO_TEMP:
727 *val = st->hw->temp.offset;
728 return IIO_VAL_INT;
729 default:
730 return -EINVAL;
731 }
732 case IIO_CHAN_INFO_CALIBBIAS:
733 switch (chan->type) {
734 case IIO_ANGL_VEL:
735 mutex_lock(&st->lock);
736 ret = inv_mpu6050_sensor_show(st, st->reg->gyro_offset,
737 chan->channel2, val);
738 mutex_unlock(&st->lock);
739 return IIO_VAL_INT;
740 case IIO_ACCEL:
741 mutex_lock(&st->lock);
742 ret = inv_mpu6050_sensor_show(st, st->reg->accl_offset,
743 chan->channel2, val);
744 mutex_unlock(&st->lock);
745 return IIO_VAL_INT;
746
747 default:
748 return -EINVAL;
749 }
750 default:
751 return -EINVAL;
752 }
753}
754
755static int inv_mpu6050_write_gyro_scale(struct inv_mpu6050_state *st, int val,
756 int val2)
757{
758 int result, i;
759
760 if (val != 0)
761 return -EINVAL;
762
763 for (i = 0; i < ARRAY_SIZE(gyro_scale_6050); ++i) {
764 if (gyro_scale_6050[i] == val2) {
765 result = inv_mpu6050_set_gyro_fsr(st, i);
766 if (result)
767 return result;
768
769 st->chip_config.fsr = i;
770 return 0;
771 }
772 }
773
774 return -EINVAL;
775}
776
777static int inv_write_raw_get_fmt(struct iio_dev *indio_dev,
778 struct iio_chan_spec const *chan, long mask)
779{
780 switch (mask) {
781 case IIO_CHAN_INFO_SCALE:
782 switch (chan->type) {
783 case IIO_ANGL_VEL:
784 return IIO_VAL_INT_PLUS_NANO;
785 default:
786 return IIO_VAL_INT_PLUS_MICRO;
787 }
788 default:
789 return IIO_VAL_INT_PLUS_MICRO;
790 }
791
792 return -EINVAL;
793}
794
795static int inv_mpu6050_write_accel_scale(struct inv_mpu6050_state *st, int val,
796 int val2)
797{
798 int result, i;
799 u8 d;
800
801 if (val != 0)
802 return -EINVAL;
803
804 for (i = 0; i < ARRAY_SIZE(accel_scale); ++i) {
805 if (accel_scale[i] == val2) {
806 d = (i << INV_MPU6050_ACCL_CONFIG_FSR_SHIFT);
807 result = regmap_write(st->map, st->reg->accl_config, d);
808 if (result)
809 return result;
810
811 st->chip_config.accl_fs = i;
812 return 0;
813 }
814 }
815
816 return -EINVAL;
817}
818
819static int inv_mpu6050_write_raw(struct iio_dev *indio_dev,
820 struct iio_chan_spec const *chan,
821 int val, int val2, long mask)
822{
823 struct inv_mpu6050_state *st = iio_priv(indio_dev);
824 struct device *pdev = regmap_get_device(st->map);
825 int result;
826
827
828
829
830
831 result = iio_device_claim_direct_mode(indio_dev);
832 if (result)
833 return result;
834
835 mutex_lock(&st->lock);
836 result = pm_runtime_resume_and_get(pdev);
837 if (result)
838 goto error_write_raw_unlock;
839
840 switch (mask) {
841 case IIO_CHAN_INFO_SCALE:
842 switch (chan->type) {
843 case IIO_ANGL_VEL:
844 result = inv_mpu6050_write_gyro_scale(st, val, val2);
845 break;
846 case IIO_ACCEL:
847 result = inv_mpu6050_write_accel_scale(st, val, val2);
848 break;
849 default:
850 result = -EINVAL;
851 break;
852 }
853 break;
854 case IIO_CHAN_INFO_CALIBBIAS:
855 switch (chan->type) {
856 case IIO_ANGL_VEL:
857 result = inv_mpu6050_sensor_set(st,
858 st->reg->gyro_offset,
859 chan->channel2, val);
860 break;
861 case IIO_ACCEL:
862 result = inv_mpu6050_sensor_set(st,
863 st->reg->accl_offset,
864 chan->channel2, val);
865 break;
866 default:
867 result = -EINVAL;
868 break;
869 }
870 break;
871 default:
872 result = -EINVAL;
873 break;
874 }
875
876 pm_runtime_mark_last_busy(pdev);
877 pm_runtime_put_autosuspend(pdev);
878error_write_raw_unlock:
879 mutex_unlock(&st->lock);
880 iio_device_release_direct_mode(indio_dev);
881
882 return result;
883}
884
885
886
887
888
889
890
891
892
893
894
895
896static int inv_mpu6050_set_lpf(struct inv_mpu6050_state *st, int rate)
897{
898 static const int hz[] = {400, 200, 90, 40, 20, 10};
899 static const int d[] = {
900 INV_MPU6050_FILTER_200HZ, INV_MPU6050_FILTER_100HZ,
901 INV_MPU6050_FILTER_45HZ, INV_MPU6050_FILTER_20HZ,
902 INV_MPU6050_FILTER_10HZ, INV_MPU6050_FILTER_5HZ
903 };
904 int i, result;
905 u8 data;
906
907 data = INV_MPU6050_FILTER_5HZ;
908 for (i = 0; i < ARRAY_SIZE(hz); ++i) {
909 if (rate >= hz[i]) {
910 data = d[i];
911 break;
912 }
913 }
914 result = inv_mpu6050_set_lpf_regs(st, data);
915 if (result)
916 return result;
917 st->chip_config.lpf = data;
918
919 return 0;
920}
921
922
923
924
925static ssize_t
926inv_mpu6050_fifo_rate_store(struct device *dev, struct device_attribute *attr,
927 const char *buf, size_t count)
928{
929 int fifo_rate;
930 u8 d;
931 int result;
932 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
933 struct inv_mpu6050_state *st = iio_priv(indio_dev);
934 struct device *pdev = regmap_get_device(st->map);
935
936 if (kstrtoint(buf, 10, &fifo_rate))
937 return -EINVAL;
938 if (fifo_rate < INV_MPU6050_MIN_FIFO_RATE ||
939 fifo_rate > INV_MPU6050_MAX_FIFO_RATE)
940 return -EINVAL;
941
942
943 d = INV_MPU6050_FIFO_RATE_TO_DIVIDER(fifo_rate);
944
945 fifo_rate = INV_MPU6050_DIVIDER_TO_FIFO_RATE(d);
946
947 mutex_lock(&st->lock);
948 if (d == st->chip_config.divider) {
949 result = 0;
950 goto fifo_rate_fail_unlock;
951 }
952 result = pm_runtime_resume_and_get(pdev);
953 if (result)
954 goto fifo_rate_fail_unlock;
955
956 result = regmap_write(st->map, st->reg->sample_rate_div, d);
957 if (result)
958 goto fifo_rate_fail_power_off;
959 st->chip_config.divider = d;
960
961 result = inv_mpu6050_set_lpf(st, fifo_rate);
962 if (result)
963 goto fifo_rate_fail_power_off;
964
965
966 result = inv_mpu_magn_set_rate(st, fifo_rate);
967 if (result)
968 goto fifo_rate_fail_power_off;
969
970 pm_runtime_mark_last_busy(pdev);
971fifo_rate_fail_power_off:
972 pm_runtime_put_autosuspend(pdev);
973fifo_rate_fail_unlock:
974 mutex_unlock(&st->lock);
975 if (result)
976 return result;
977
978 return count;
979}
980
981
982
983
984static ssize_t
985inv_fifo_rate_show(struct device *dev, struct device_attribute *attr,
986 char *buf)
987{
988 struct inv_mpu6050_state *st = iio_priv(dev_to_iio_dev(dev));
989 unsigned fifo_rate;
990
991 mutex_lock(&st->lock);
992 fifo_rate = INV_MPU6050_DIVIDER_TO_FIFO_RATE(st->chip_config.divider);
993 mutex_unlock(&st->lock);
994
995 return scnprintf(buf, PAGE_SIZE, "%u\n", fifo_rate);
996}
997
998
999
1000
1001
1002
1003
1004
1005
1006static ssize_t inv_attr_show(struct device *dev, struct device_attribute *attr,
1007 char *buf)
1008{
1009 struct inv_mpu6050_state *st = iio_priv(dev_to_iio_dev(dev));
1010 struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
1011 s8 *m;
1012
1013 switch (this_attr->address) {
1014
1015
1016
1017
1018 case ATTR_GYRO_MATRIX:
1019 case ATTR_ACCL_MATRIX:
1020 m = st->plat_data.orientation;
1021
1022 return scnprintf(buf, PAGE_SIZE,
1023 "%d, %d, %d; %d, %d, %d; %d, %d, %d\n",
1024 m[0], m[1], m[2], m[3], m[4], m[5], m[6], m[7], m[8]);
1025 default:
1026 return -EINVAL;
1027 }
1028}
1029
1030
1031
1032
1033
1034
1035
1036
1037
1038
1039static int inv_mpu6050_validate_trigger(struct iio_dev *indio_dev,
1040 struct iio_trigger *trig)
1041{
1042 struct inv_mpu6050_state *st = iio_priv(indio_dev);
1043
1044 if (st->trig != trig)
1045 return -EINVAL;
1046
1047 return 0;
1048}
1049
1050static const struct iio_mount_matrix *
1051inv_get_mount_matrix(const struct iio_dev *indio_dev,
1052 const struct iio_chan_spec *chan)
1053{
1054 struct inv_mpu6050_state *data = iio_priv(indio_dev);
1055 const struct iio_mount_matrix *matrix;
1056
1057 if (chan->type == IIO_MAGN)
1058 matrix = &data->magn_orient;
1059 else
1060 matrix = &data->orientation;
1061
1062 return matrix;
1063}
1064
1065static const struct iio_chan_spec_ext_info inv_ext_info[] = {
1066 IIO_MOUNT_MATRIX(IIO_SHARED_BY_TYPE, inv_get_mount_matrix),
1067 { }
1068};
1069
1070#define INV_MPU6050_CHAN(_type, _channel2, _index) \
1071 { \
1072 .type = _type, \
1073 .modified = 1, \
1074 .channel2 = _channel2, \
1075 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
1076 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
1077 BIT(IIO_CHAN_INFO_CALIBBIAS), \
1078 .scan_index = _index, \
1079 .scan_type = { \
1080 .sign = 's', \
1081 .realbits = 16, \
1082 .storagebits = 16, \
1083 .shift = 0, \
1084 .endianness = IIO_BE, \
1085 }, \
1086 .ext_info = inv_ext_info, \
1087 }
1088
1089#define INV_MPU6050_TEMP_CHAN(_index) \
1090 { \
1091 .type = IIO_TEMP, \
1092 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) \
1093 | BIT(IIO_CHAN_INFO_OFFSET) \
1094 | BIT(IIO_CHAN_INFO_SCALE), \
1095 .scan_index = _index, \
1096 .scan_type = { \
1097 .sign = 's', \
1098 .realbits = 16, \
1099 .storagebits = 16, \
1100 .shift = 0, \
1101 .endianness = IIO_BE, \
1102 }, \
1103 }
1104
1105static const struct iio_chan_spec inv_mpu_channels[] = {
1106 IIO_CHAN_SOFT_TIMESTAMP(INV_MPU6050_SCAN_TIMESTAMP),
1107
1108 INV_MPU6050_TEMP_CHAN(INV_MPU6050_SCAN_TEMP),
1109
1110 INV_MPU6050_CHAN(IIO_ANGL_VEL, IIO_MOD_X, INV_MPU6050_SCAN_GYRO_X),
1111 INV_MPU6050_CHAN(IIO_ANGL_VEL, IIO_MOD_Y, INV_MPU6050_SCAN_GYRO_Y),
1112 INV_MPU6050_CHAN(IIO_ANGL_VEL, IIO_MOD_Z, INV_MPU6050_SCAN_GYRO_Z),
1113
1114 INV_MPU6050_CHAN(IIO_ACCEL, IIO_MOD_X, INV_MPU6050_SCAN_ACCL_X),
1115 INV_MPU6050_CHAN(IIO_ACCEL, IIO_MOD_Y, INV_MPU6050_SCAN_ACCL_Y),
1116 INV_MPU6050_CHAN(IIO_ACCEL, IIO_MOD_Z, INV_MPU6050_SCAN_ACCL_Z),
1117};
1118
1119#define INV_MPU6050_SCAN_MASK_3AXIS_ACCEL \
1120 (BIT(INV_MPU6050_SCAN_ACCL_X) \
1121 | BIT(INV_MPU6050_SCAN_ACCL_Y) \
1122 | BIT(INV_MPU6050_SCAN_ACCL_Z))
1123
1124#define INV_MPU6050_SCAN_MASK_3AXIS_GYRO \
1125 (BIT(INV_MPU6050_SCAN_GYRO_X) \
1126 | BIT(INV_MPU6050_SCAN_GYRO_Y) \
1127 | BIT(INV_MPU6050_SCAN_GYRO_Z))
1128
1129#define INV_MPU6050_SCAN_MASK_TEMP (BIT(INV_MPU6050_SCAN_TEMP))
1130
1131static const unsigned long inv_mpu_scan_masks[] = {
1132
1133 INV_MPU6050_SCAN_MASK_3AXIS_ACCEL,
1134 INV_MPU6050_SCAN_MASK_3AXIS_ACCEL | INV_MPU6050_SCAN_MASK_TEMP,
1135
1136 INV_MPU6050_SCAN_MASK_3AXIS_GYRO,
1137 INV_MPU6050_SCAN_MASK_3AXIS_GYRO | INV_MPU6050_SCAN_MASK_TEMP,
1138
1139 INV_MPU6050_SCAN_MASK_3AXIS_ACCEL | INV_MPU6050_SCAN_MASK_3AXIS_GYRO,
1140 INV_MPU6050_SCAN_MASK_3AXIS_ACCEL | INV_MPU6050_SCAN_MASK_3AXIS_GYRO
1141 | INV_MPU6050_SCAN_MASK_TEMP,
1142 0,
1143};
1144
1145#define INV_MPU9X50_MAGN_CHAN(_chan2, _bits, _index) \
1146 { \
1147 .type = IIO_MAGN, \
1148 .modified = 1, \
1149 .channel2 = _chan2, \
1150 .info_mask_separate = BIT(IIO_CHAN_INFO_SCALE) | \
1151 BIT(IIO_CHAN_INFO_RAW), \
1152 .scan_index = _index, \
1153 .scan_type = { \
1154 .sign = 's', \
1155 .realbits = _bits, \
1156 .storagebits = 16, \
1157 .shift = 0, \
1158 .endianness = IIO_BE, \
1159 }, \
1160 .ext_info = inv_ext_info, \
1161 }
1162
1163static const struct iio_chan_spec inv_mpu9150_channels[] = {
1164 IIO_CHAN_SOFT_TIMESTAMP(INV_MPU9X50_SCAN_TIMESTAMP),
1165
1166 INV_MPU6050_TEMP_CHAN(INV_MPU6050_SCAN_TEMP),
1167
1168 INV_MPU6050_CHAN(IIO_ANGL_VEL, IIO_MOD_X, INV_MPU6050_SCAN_GYRO_X),
1169 INV_MPU6050_CHAN(IIO_ANGL_VEL, IIO_MOD_Y, INV_MPU6050_SCAN_GYRO_Y),
1170 INV_MPU6050_CHAN(IIO_ANGL_VEL, IIO_MOD_Z, INV_MPU6050_SCAN_GYRO_Z),
1171
1172 INV_MPU6050_CHAN(IIO_ACCEL, IIO_MOD_X, INV_MPU6050_SCAN_ACCL_X),
1173 INV_MPU6050_CHAN(IIO_ACCEL, IIO_MOD_Y, INV_MPU6050_SCAN_ACCL_Y),
1174 INV_MPU6050_CHAN(IIO_ACCEL, IIO_MOD_Z, INV_MPU6050_SCAN_ACCL_Z),
1175
1176
1177 INV_MPU9X50_MAGN_CHAN(IIO_MOD_X, 13, INV_MPU9X50_SCAN_MAGN_X),
1178 INV_MPU9X50_MAGN_CHAN(IIO_MOD_Y, 13, INV_MPU9X50_SCAN_MAGN_Y),
1179 INV_MPU9X50_MAGN_CHAN(IIO_MOD_Z, 13, INV_MPU9X50_SCAN_MAGN_Z),
1180};
1181
1182static const struct iio_chan_spec inv_mpu9250_channels[] = {
1183 IIO_CHAN_SOFT_TIMESTAMP(INV_MPU9X50_SCAN_TIMESTAMP),
1184
1185 INV_MPU6050_TEMP_CHAN(INV_MPU6050_SCAN_TEMP),
1186
1187 INV_MPU6050_CHAN(IIO_ANGL_VEL, IIO_MOD_X, INV_MPU6050_SCAN_GYRO_X),
1188 INV_MPU6050_CHAN(IIO_ANGL_VEL, IIO_MOD_Y, INV_MPU6050_SCAN_GYRO_Y),
1189 INV_MPU6050_CHAN(IIO_ANGL_VEL, IIO_MOD_Z, INV_MPU6050_SCAN_GYRO_Z),
1190
1191 INV_MPU6050_CHAN(IIO_ACCEL, IIO_MOD_X, INV_MPU6050_SCAN_ACCL_X),
1192 INV_MPU6050_CHAN(IIO_ACCEL, IIO_MOD_Y, INV_MPU6050_SCAN_ACCL_Y),
1193 INV_MPU6050_CHAN(IIO_ACCEL, IIO_MOD_Z, INV_MPU6050_SCAN_ACCL_Z),
1194
1195
1196 INV_MPU9X50_MAGN_CHAN(IIO_MOD_X, 16, INV_MPU9X50_SCAN_MAGN_X),
1197 INV_MPU9X50_MAGN_CHAN(IIO_MOD_Y, 16, INV_MPU9X50_SCAN_MAGN_Y),
1198 INV_MPU9X50_MAGN_CHAN(IIO_MOD_Z, 16, INV_MPU9X50_SCAN_MAGN_Z),
1199};
1200
1201#define INV_MPU9X50_SCAN_MASK_3AXIS_MAGN \
1202 (BIT(INV_MPU9X50_SCAN_MAGN_X) \
1203 | BIT(INV_MPU9X50_SCAN_MAGN_Y) \
1204 | BIT(INV_MPU9X50_SCAN_MAGN_Z))
1205
1206static const unsigned long inv_mpu9x50_scan_masks[] = {
1207
1208 INV_MPU6050_SCAN_MASK_3AXIS_ACCEL,
1209 INV_MPU6050_SCAN_MASK_3AXIS_ACCEL | INV_MPU6050_SCAN_MASK_TEMP,
1210
1211 INV_MPU6050_SCAN_MASK_3AXIS_GYRO,
1212 INV_MPU6050_SCAN_MASK_3AXIS_GYRO | INV_MPU6050_SCAN_MASK_TEMP,
1213
1214 INV_MPU9X50_SCAN_MASK_3AXIS_MAGN,
1215 INV_MPU9X50_SCAN_MASK_3AXIS_MAGN | INV_MPU6050_SCAN_MASK_TEMP,
1216
1217 INV_MPU6050_SCAN_MASK_3AXIS_ACCEL | INV_MPU6050_SCAN_MASK_3AXIS_GYRO,
1218 INV_MPU6050_SCAN_MASK_3AXIS_ACCEL | INV_MPU6050_SCAN_MASK_3AXIS_GYRO
1219 | INV_MPU6050_SCAN_MASK_TEMP,
1220
1221 INV_MPU6050_SCAN_MASK_3AXIS_ACCEL | INV_MPU9X50_SCAN_MASK_3AXIS_MAGN,
1222 INV_MPU6050_SCAN_MASK_3AXIS_ACCEL | INV_MPU9X50_SCAN_MASK_3AXIS_MAGN
1223 | INV_MPU6050_SCAN_MASK_TEMP,
1224
1225 INV_MPU6050_SCAN_MASK_3AXIS_GYRO | INV_MPU9X50_SCAN_MASK_3AXIS_MAGN,
1226 INV_MPU6050_SCAN_MASK_3AXIS_GYRO | INV_MPU9X50_SCAN_MASK_3AXIS_MAGN
1227 | INV_MPU6050_SCAN_MASK_TEMP,
1228
1229 INV_MPU6050_SCAN_MASK_3AXIS_ACCEL | INV_MPU6050_SCAN_MASK_3AXIS_GYRO
1230 | INV_MPU9X50_SCAN_MASK_3AXIS_MAGN,
1231 INV_MPU6050_SCAN_MASK_3AXIS_ACCEL | INV_MPU6050_SCAN_MASK_3AXIS_GYRO
1232 | INV_MPU9X50_SCAN_MASK_3AXIS_MAGN
1233 | INV_MPU6050_SCAN_MASK_TEMP,
1234 0,
1235};
1236
1237static const unsigned long inv_icm20602_scan_masks[] = {
1238
1239 INV_MPU6050_SCAN_MASK_3AXIS_ACCEL | INV_MPU6050_SCAN_MASK_TEMP,
1240
1241 INV_MPU6050_SCAN_MASK_3AXIS_GYRO | INV_MPU6050_SCAN_MASK_TEMP,
1242
1243 INV_MPU6050_SCAN_MASK_3AXIS_ACCEL | INV_MPU6050_SCAN_MASK_3AXIS_GYRO
1244 | INV_MPU6050_SCAN_MASK_TEMP,
1245 0,
1246};
1247
1248
1249
1250
1251
1252
1253
1254
1255
1256static IIO_CONST_ATTR_SAMP_FREQ_AVAIL("10 20 50 100 200 500");
1257static IIO_CONST_ATTR(in_anglvel_scale_available,
1258 "0.000133090 0.000266181 0.000532362 0.001064724");
1259static IIO_CONST_ATTR(in_accel_scale_available,
1260 "0.000598 0.001196 0.002392 0.004785");
1261static IIO_DEV_ATTR_SAMP_FREQ(S_IRUGO | S_IWUSR, inv_fifo_rate_show,
1262 inv_mpu6050_fifo_rate_store);
1263
1264
1265static IIO_DEVICE_ATTR(in_gyro_matrix, S_IRUGO, inv_attr_show, NULL,
1266 ATTR_GYRO_MATRIX);
1267static IIO_DEVICE_ATTR(in_accel_matrix, S_IRUGO, inv_attr_show, NULL,
1268 ATTR_ACCL_MATRIX);
1269
1270static struct attribute *inv_attributes[] = {
1271 &iio_dev_attr_in_gyro_matrix.dev_attr.attr,
1272 &iio_dev_attr_in_accel_matrix.dev_attr.attr,
1273 &iio_dev_attr_sampling_frequency.dev_attr.attr,
1274 &iio_const_attr_sampling_frequency_available.dev_attr.attr,
1275 &iio_const_attr_in_accel_scale_available.dev_attr.attr,
1276 &iio_const_attr_in_anglvel_scale_available.dev_attr.attr,
1277 NULL,
1278};
1279
1280static const struct attribute_group inv_attribute_group = {
1281 .attrs = inv_attributes
1282};
1283
1284static int inv_mpu6050_reg_access(struct iio_dev *indio_dev,
1285 unsigned int reg,
1286 unsigned int writeval,
1287 unsigned int *readval)
1288{
1289 struct inv_mpu6050_state *st = iio_priv(indio_dev);
1290 int ret;
1291
1292 mutex_lock(&st->lock);
1293 if (readval)
1294 ret = regmap_read(st->map, reg, readval);
1295 else
1296 ret = regmap_write(st->map, reg, writeval);
1297 mutex_unlock(&st->lock);
1298
1299 return ret;
1300}
1301
1302static const struct iio_info mpu_info = {
1303 .read_raw = &inv_mpu6050_read_raw,
1304 .write_raw = &inv_mpu6050_write_raw,
1305 .write_raw_get_fmt = &inv_write_raw_get_fmt,
1306 .attrs = &inv_attribute_group,
1307 .validate_trigger = inv_mpu6050_validate_trigger,
1308 .debugfs_reg_access = &inv_mpu6050_reg_access,
1309};
1310
1311
1312
1313
1314static int inv_check_and_setup_chip(struct inv_mpu6050_state *st)
1315{
1316 int result;
1317 unsigned int regval, mask;
1318 int i;
1319
1320 st->hw = &hw_info[st->chip_type];
1321 st->reg = hw_info[st->chip_type].reg;
1322 memcpy(&st->chip_config, hw_info[st->chip_type].config,
1323 sizeof(st->chip_config));
1324
1325
1326 result = regmap_read(st->map, INV_MPU6050_REG_WHOAMI, ®val);
1327 if (result)
1328 return result;
1329 if (regval != st->hw->whoami) {
1330
1331 for (i = 0; i < INV_NUM_PARTS; ++i) {
1332 if (regval == hw_info[i].whoami) {
1333 dev_warn(regmap_get_device(st->map),
1334 "whoami mismatch got 0x%02x (%s) expected 0x%02x (%s)\n",
1335 regval, hw_info[i].name,
1336 st->hw->whoami, st->hw->name);
1337 break;
1338 }
1339 }
1340 if (i >= INV_NUM_PARTS) {
1341 dev_err(regmap_get_device(st->map),
1342 "invalid whoami 0x%02x expected 0x%02x (%s)\n",
1343 regval, st->hw->whoami, st->hw->name);
1344 return -ENODEV;
1345 }
1346 }
1347
1348
1349 result = regmap_write(st->map, st->reg->pwr_mgmt_1,
1350 INV_MPU6050_BIT_H_RESET);
1351 if (result)
1352 return result;
1353 msleep(INV_MPU6050_POWER_UP_TIME);
1354 switch (st->chip_type) {
1355 case INV_MPU6000:
1356 case INV_MPU6500:
1357 case INV_MPU6515:
1358 case INV_MPU6880:
1359 case INV_MPU9250:
1360 case INV_MPU9255:
1361
1362 regval = INV_MPU6050_BIT_TEMP_RST | INV_MPU6050_BIT_ACCEL_RST |
1363 INV_MPU6050_BIT_GYRO_RST;
1364 result = regmap_write(st->map, INV_MPU6050_REG_SIGNAL_PATH_RESET,
1365 regval);
1366 if (result)
1367 return result;
1368 msleep(INV_MPU6050_POWER_UP_TIME);
1369 break;
1370 default:
1371 break;
1372 }
1373
1374
1375
1376
1377
1378
1379
1380 result = inv_mpu6050_set_power_itg(st, true);
1381 if (result)
1382 return result;
1383 mask = INV_MPU6050_SENSOR_ACCL | INV_MPU6050_SENSOR_GYRO |
1384 INV_MPU6050_SENSOR_TEMP | INV_MPU6050_SENSOR_MAGN;
1385 result = inv_mpu6050_switch_engine(st, false, mask);
1386 if (result)
1387 goto error_power_off;
1388
1389 return 0;
1390
1391error_power_off:
1392 inv_mpu6050_set_power_itg(st, false);
1393 return result;
1394}
1395
1396static int inv_mpu_core_enable_regulator_vddio(struct inv_mpu6050_state *st)
1397{
1398 int result;
1399
1400 result = regulator_enable(st->vddio_supply);
1401 if (result) {
1402 dev_err(regmap_get_device(st->map),
1403 "Failed to enable vddio regulator: %d\n", result);
1404 } else {
1405
1406 usleep_range(3000, 5000);
1407 }
1408
1409 return result;
1410}
1411
1412static int inv_mpu_core_disable_regulator_vddio(struct inv_mpu6050_state *st)
1413{
1414 int result;
1415
1416 result = regulator_disable(st->vddio_supply);
1417 if (result)
1418 dev_err(regmap_get_device(st->map),
1419 "Failed to disable vddio regulator: %d\n", result);
1420
1421 return result;
1422}
1423
1424static void inv_mpu_core_disable_regulator_action(void *_data)
1425{
1426 struct inv_mpu6050_state *st = _data;
1427 int result;
1428
1429 result = regulator_disable(st->vdd_supply);
1430 if (result)
1431 dev_err(regmap_get_device(st->map),
1432 "Failed to disable vdd regulator: %d\n", result);
1433
1434 inv_mpu_core_disable_regulator_vddio(st);
1435}
1436
1437static void inv_mpu_pm_disable(void *data)
1438{
1439 struct device *dev = data;
1440
1441 pm_runtime_disable(dev);
1442}
1443
1444int inv_mpu_core_probe(struct regmap *regmap, int irq, const char *name,
1445 int (*inv_mpu_bus_setup)(struct iio_dev *), int chip_type)
1446{
1447 struct inv_mpu6050_state *st;
1448 struct iio_dev *indio_dev;
1449 struct inv_mpu6050_platform_data *pdata;
1450 struct device *dev = regmap_get_device(regmap);
1451 int result;
1452 struct irq_data *desc;
1453 int irq_type;
1454
1455 indio_dev = devm_iio_device_alloc(dev, sizeof(*st));
1456 if (!indio_dev)
1457 return -ENOMEM;
1458
1459 BUILD_BUG_ON(ARRAY_SIZE(hw_info) != INV_NUM_PARTS);
1460 if (chip_type < 0 || chip_type >= INV_NUM_PARTS) {
1461 dev_err(dev, "Bad invensense chip_type=%d name=%s\n",
1462 chip_type, name);
1463 return -ENODEV;
1464 }
1465 st = iio_priv(indio_dev);
1466 mutex_init(&st->lock);
1467 st->chip_type = chip_type;
1468 st->irq = irq;
1469 st->map = regmap;
1470
1471 pdata = dev_get_platdata(dev);
1472 if (!pdata) {
1473 result = iio_read_mount_matrix(dev, &st->orientation);
1474 if (result) {
1475 dev_err(dev, "Failed to retrieve mounting matrix %d\n",
1476 result);
1477 return result;
1478 }
1479 } else {
1480 st->plat_data = *pdata;
1481 }
1482
1483 if (irq > 0) {
1484 desc = irq_get_irq_data(irq);
1485 if (!desc) {
1486 dev_err(dev, "Could not find IRQ %d\n", irq);
1487 return -EINVAL;
1488 }
1489
1490 irq_type = irqd_get_trigger_type(desc);
1491 if (!irq_type)
1492 irq_type = IRQF_TRIGGER_RISING;
1493 } else {
1494
1495 irq_type = IRQF_TRIGGER_RISING;
1496 }
1497
1498 if (irq_type & IRQF_TRIGGER_RISING)
1499 st->irq_mask = INV_MPU6050_ACTIVE_HIGH;
1500 else if (irq_type == IRQF_TRIGGER_FALLING)
1501 st->irq_mask = INV_MPU6050_ACTIVE_LOW;
1502 else if (irq_type == IRQF_TRIGGER_HIGH)
1503 st->irq_mask = INV_MPU6050_ACTIVE_HIGH |
1504 INV_MPU6050_LATCH_INT_EN;
1505 else if (irq_type == IRQF_TRIGGER_LOW)
1506 st->irq_mask = INV_MPU6050_ACTIVE_LOW |
1507 INV_MPU6050_LATCH_INT_EN;
1508 else {
1509 dev_err(dev, "Invalid interrupt type 0x%x specified\n",
1510 irq_type);
1511 return -EINVAL;
1512 }
1513
1514 st->vdd_supply = devm_regulator_get(dev, "vdd");
1515 if (IS_ERR(st->vdd_supply))
1516 return dev_err_probe(dev, PTR_ERR(st->vdd_supply),
1517 "Failed to get vdd regulator\n");
1518
1519 st->vddio_supply = devm_regulator_get(dev, "vddio");
1520 if (IS_ERR(st->vddio_supply))
1521 return dev_err_probe(dev, PTR_ERR(st->vddio_supply),
1522 "Failed to get vddio regulator\n");
1523
1524 result = regulator_enable(st->vdd_supply);
1525 if (result) {
1526 dev_err(dev, "Failed to enable vdd regulator: %d\n", result);
1527 return result;
1528 }
1529 msleep(INV_MPU6050_POWER_UP_TIME);
1530
1531 result = inv_mpu_core_enable_regulator_vddio(st);
1532 if (result) {
1533 regulator_disable(st->vdd_supply);
1534 return result;
1535 }
1536
1537 result = devm_add_action_or_reset(dev, inv_mpu_core_disable_regulator_action,
1538 st);
1539 if (result) {
1540 dev_err(dev, "Failed to setup regulator cleanup action %d\n",
1541 result);
1542 return result;
1543 }
1544
1545
1546 result = inv_mpu_magn_set_orient(st);
1547 if (result)
1548 return result;
1549
1550
1551 result = inv_check_and_setup_chip(st);
1552 if (result)
1553 return result;
1554
1555 result = inv_mpu6050_init_config(indio_dev);
1556 if (result) {
1557 dev_err(dev, "Could not initialize device.\n");
1558 goto error_power_off;
1559 }
1560
1561 dev_set_drvdata(dev, indio_dev);
1562
1563 if (name)
1564 indio_dev->name = name;
1565 else
1566 indio_dev->name = dev_name(dev);
1567
1568
1569 if (inv_mpu_bus_setup) {
1570 result = inv_mpu_bus_setup(indio_dev);
1571 if (result)
1572 goto error_power_off;
1573 }
1574
1575
1576 result = pm_runtime_set_active(dev);
1577 if (result)
1578 goto error_power_off;
1579 pm_runtime_get_noresume(dev);
1580 pm_runtime_enable(dev);
1581 pm_runtime_set_autosuspend_delay(dev, INV_MPU6050_SUSPEND_DELAY_MS);
1582 pm_runtime_use_autosuspend(dev);
1583 pm_runtime_put(dev);
1584 result = devm_add_action_or_reset(dev, inv_mpu_pm_disable, dev);
1585 if (result)
1586 return result;
1587
1588 switch (chip_type) {
1589 case INV_MPU9150:
1590 indio_dev->channels = inv_mpu9150_channels;
1591 indio_dev->num_channels = ARRAY_SIZE(inv_mpu9150_channels);
1592 indio_dev->available_scan_masks = inv_mpu9x50_scan_masks;
1593 break;
1594 case INV_MPU9250:
1595 case INV_MPU9255:
1596 indio_dev->channels = inv_mpu9250_channels;
1597 indio_dev->num_channels = ARRAY_SIZE(inv_mpu9250_channels);
1598 indio_dev->available_scan_masks = inv_mpu9x50_scan_masks;
1599 break;
1600 case INV_ICM20602:
1601 indio_dev->channels = inv_mpu_channels;
1602 indio_dev->num_channels = ARRAY_SIZE(inv_mpu_channels);
1603 indio_dev->available_scan_masks = inv_icm20602_scan_masks;
1604 break;
1605 default:
1606 indio_dev->channels = inv_mpu_channels;
1607 indio_dev->num_channels = ARRAY_SIZE(inv_mpu_channels);
1608 indio_dev->available_scan_masks = inv_mpu_scan_masks;
1609 break;
1610 }
1611
1612
1613
1614
1615 if (st->magn_disabled) {
1616 indio_dev->channels = inv_mpu_channels;
1617 indio_dev->num_channels = ARRAY_SIZE(inv_mpu_channels);
1618 indio_dev->available_scan_masks = inv_mpu_scan_masks;
1619 }
1620
1621 indio_dev->info = &mpu_info;
1622
1623 if (irq > 0) {
1624
1625
1626
1627
1628 result = devm_iio_triggered_buffer_setup(dev, indio_dev,
1629 iio_pollfunc_store_time,
1630 inv_mpu6050_read_fifo,
1631 NULL);
1632 if (result) {
1633 dev_err(dev, "configure buffer fail %d\n", result);
1634 return result;
1635 }
1636
1637 result = inv_mpu6050_probe_trigger(indio_dev, irq_type);
1638 if (result) {
1639 dev_err(dev, "trigger probe fail %d\n", result);
1640 return result;
1641 }
1642 }
1643
1644 result = devm_iio_device_register(dev, indio_dev);
1645 if (result) {
1646 dev_err(dev, "IIO register fail %d\n", result);
1647 return result;
1648 }
1649
1650 return 0;
1651
1652error_power_off:
1653 inv_mpu6050_set_power_itg(st, false);
1654 return result;
1655}
1656EXPORT_SYMBOL_GPL(inv_mpu_core_probe);
1657
1658static int __maybe_unused inv_mpu_resume(struct device *dev)
1659{
1660 struct iio_dev *indio_dev = dev_get_drvdata(dev);
1661 struct inv_mpu6050_state *st = iio_priv(indio_dev);
1662 int result;
1663
1664 mutex_lock(&st->lock);
1665 result = inv_mpu_core_enable_regulator_vddio(st);
1666 if (result)
1667 goto out_unlock;
1668
1669 result = inv_mpu6050_set_power_itg(st, true);
1670 if (result)
1671 goto out_unlock;
1672
1673 pm_runtime_disable(dev);
1674 pm_runtime_set_active(dev);
1675 pm_runtime_enable(dev);
1676
1677 result = inv_mpu6050_switch_engine(st, true, st->suspended_sensors);
1678 if (result)
1679 goto out_unlock;
1680
1681 if (iio_buffer_enabled(indio_dev))
1682 result = inv_mpu6050_prepare_fifo(st, true);
1683
1684out_unlock:
1685 mutex_unlock(&st->lock);
1686
1687 return result;
1688}
1689
1690static int __maybe_unused inv_mpu_suspend(struct device *dev)
1691{
1692 struct iio_dev *indio_dev = dev_get_drvdata(dev);
1693 struct inv_mpu6050_state *st = iio_priv(indio_dev);
1694 int result;
1695
1696 mutex_lock(&st->lock);
1697
1698 st->suspended_sensors = 0;
1699 if (pm_runtime_suspended(dev)) {
1700 result = 0;
1701 goto out_unlock;
1702 }
1703
1704 if (iio_buffer_enabled(indio_dev)) {
1705 result = inv_mpu6050_prepare_fifo(st, false);
1706 if (result)
1707 goto out_unlock;
1708 }
1709
1710 if (st->chip_config.accl_en)
1711 st->suspended_sensors |= INV_MPU6050_SENSOR_ACCL;
1712 if (st->chip_config.gyro_en)
1713 st->suspended_sensors |= INV_MPU6050_SENSOR_GYRO;
1714 if (st->chip_config.temp_en)
1715 st->suspended_sensors |= INV_MPU6050_SENSOR_TEMP;
1716 if (st->chip_config.magn_en)
1717 st->suspended_sensors |= INV_MPU6050_SENSOR_MAGN;
1718 result = inv_mpu6050_switch_engine(st, false, st->suspended_sensors);
1719 if (result)
1720 goto out_unlock;
1721
1722 result = inv_mpu6050_set_power_itg(st, false);
1723 if (result)
1724 goto out_unlock;
1725
1726 inv_mpu_core_disable_regulator_vddio(st);
1727out_unlock:
1728 mutex_unlock(&st->lock);
1729
1730 return result;
1731}
1732
1733static int __maybe_unused inv_mpu_runtime_suspend(struct device *dev)
1734{
1735 struct inv_mpu6050_state *st = iio_priv(dev_get_drvdata(dev));
1736 unsigned int sensors;
1737 int ret;
1738
1739 mutex_lock(&st->lock);
1740
1741 sensors = INV_MPU6050_SENSOR_ACCL | INV_MPU6050_SENSOR_GYRO |
1742 INV_MPU6050_SENSOR_TEMP | INV_MPU6050_SENSOR_MAGN;
1743 ret = inv_mpu6050_switch_engine(st, false, sensors);
1744 if (ret)
1745 goto out_unlock;
1746
1747 ret = inv_mpu6050_set_power_itg(st, false);
1748 if (ret)
1749 goto out_unlock;
1750
1751 inv_mpu_core_disable_regulator_vddio(st);
1752
1753out_unlock:
1754 mutex_unlock(&st->lock);
1755 return ret;
1756}
1757
1758static int __maybe_unused inv_mpu_runtime_resume(struct device *dev)
1759{
1760 struct inv_mpu6050_state *st = iio_priv(dev_get_drvdata(dev));
1761 int ret;
1762
1763 ret = inv_mpu_core_enable_regulator_vddio(st);
1764 if (ret)
1765 return ret;
1766
1767 return inv_mpu6050_set_power_itg(st, true);
1768}
1769
1770const struct dev_pm_ops inv_mpu_pmops = {
1771 SET_SYSTEM_SLEEP_PM_OPS(inv_mpu_suspend, inv_mpu_resume)
1772 SET_RUNTIME_PM_OPS(inv_mpu_runtime_suspend, inv_mpu_runtime_resume, NULL)
1773};
1774EXPORT_SYMBOL_GPL(inv_mpu_pmops);
1775
1776MODULE_AUTHOR("Invensense Corporation");
1777MODULE_DESCRIPTION("Invensense device MPU6050 driver");
1778MODULE_LICENSE("GPL");
1779
