1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39#define dev_fmt(fmt) "QPLIB: " fmt
40
41#include <linux/interrupt.h>
42#include <linux/spinlock.h>
43#include <linux/pci.h>
44#include <linux/prefetch.h>
45#include <linux/delay.h>
46
47#include "roce_hsi.h"
48#include "qplib_res.h"
49#include "qplib_rcfw.h"
50#include "qplib_sp.h"
51#include "qplib_fp.h"
52
53static void bnxt_qplib_service_creq(struct tasklet_struct *t);
54
55
56static int __wait_for_resp(struct bnxt_qplib_rcfw *rcfw, u16 cookie)
57{
58 struct bnxt_qplib_cmdq_ctx *cmdq;
59 u16 cbit;
60 int rc;
61
62 cmdq = &rcfw->cmdq;
63 cbit = cookie % rcfw->cmdq_depth;
64 rc = wait_event_timeout(cmdq->waitq,
65 !test_bit(cbit, cmdq->cmdq_bitmap),
66 msecs_to_jiffies(RCFW_CMD_WAIT_TIME_MS));
67 return rc ? 0 : -ETIMEDOUT;
68};
69
70static int __block_for_resp(struct bnxt_qplib_rcfw *rcfw, u16 cookie)
71{
72 u32 count = RCFW_BLOCKED_CMD_WAIT_COUNT;
73 struct bnxt_qplib_cmdq_ctx *cmdq;
74 u16 cbit;
75
76 cmdq = &rcfw->cmdq;
77 cbit = cookie % rcfw->cmdq_depth;
78 if (!test_bit(cbit, cmdq->cmdq_bitmap))
79 goto done;
80 do {
81 udelay(1);
82 bnxt_qplib_service_creq(&rcfw->creq.creq_tasklet);
83 } while (test_bit(cbit, cmdq->cmdq_bitmap) && --count);
84done:
85 return count ? 0 : -ETIMEDOUT;
86};
87
88static int __send_message(struct bnxt_qplib_rcfw *rcfw, struct cmdq_base *req,
89 struct creq_base *resp, void *sb, u8 is_block)
90{
91 struct bnxt_qplib_cmdq_ctx *cmdq = &rcfw->cmdq;
92 struct bnxt_qplib_hwq *hwq = &cmdq->hwq;
93 struct bnxt_qplib_crsqe *crsqe;
94 struct bnxt_qplib_cmdqe *cmdqe;
95 u32 sw_prod, cmdq_prod;
96 struct pci_dev *pdev;
97 unsigned long flags;
98 u32 size, opcode;
99 u16 cookie, cbit;
100 u8 *preq;
101
102 pdev = rcfw->pdev;
103
104 opcode = req->opcode;
105 if (!test_bit(FIRMWARE_INITIALIZED_FLAG, &cmdq->flags) &&
106 (opcode != CMDQ_BASE_OPCODE_QUERY_FUNC &&
107 opcode != CMDQ_BASE_OPCODE_INITIALIZE_FW &&
108 opcode != CMDQ_BASE_OPCODE_QUERY_VERSION)) {
109 dev_err(&pdev->dev,
110 "RCFW not initialized, reject opcode 0x%x\n", opcode);
111 return -EINVAL;
112 }
113
114 if (test_bit(FIRMWARE_INITIALIZED_FLAG, &cmdq->flags) &&
115 opcode == CMDQ_BASE_OPCODE_INITIALIZE_FW) {
116 dev_err(&pdev->dev, "RCFW already initialized!\n");
117 return -EINVAL;
118 }
119
120 if (test_bit(FIRMWARE_TIMED_OUT, &cmdq->flags))
121 return -ETIMEDOUT;
122
123
124
125
126 spin_lock_irqsave(&hwq->lock, flags);
127 if (req->cmd_size >= HWQ_FREE_SLOTS(hwq)) {
128 dev_err(&pdev->dev, "RCFW: CMDQ is full!\n");
129 spin_unlock_irqrestore(&hwq->lock, flags);
130 return -EAGAIN;
131 }
132
133
134 cookie = cmdq->seq_num & RCFW_MAX_COOKIE_VALUE;
135 cbit = cookie % rcfw->cmdq_depth;
136 if (is_block)
137 cookie |= RCFW_CMD_IS_BLOCKING;
138
139 set_bit(cbit, cmdq->cmdq_bitmap);
140 req->cookie = cpu_to_le16(cookie);
141 crsqe = &rcfw->crsqe_tbl[cbit];
142 if (crsqe->resp) {
143 spin_unlock_irqrestore(&hwq->lock, flags);
144 return -EBUSY;
145 }
146
147 size = req->cmd_size;
148
149
150
151 bnxt_qplib_set_cmd_slots(req);
152
153 memset(resp, 0, sizeof(*resp));
154 crsqe->resp = (struct creq_qp_event *)resp;
155 crsqe->resp->cookie = req->cookie;
156 crsqe->req_size = req->cmd_size;
157 if (req->resp_size && sb) {
158 struct bnxt_qplib_rcfw_sbuf *sbuf = sb;
159
160 req->resp_addr = cpu_to_le64(sbuf->dma_addr);
161 req->resp_size = (sbuf->size + BNXT_QPLIB_CMDQE_UNITS - 1) /
162 BNXT_QPLIB_CMDQE_UNITS;
163 }
164
165 preq = (u8 *)req;
166 do {
167
168 sw_prod = HWQ_CMP(hwq->prod, hwq);
169 cmdqe = bnxt_qplib_get_qe(hwq, sw_prod, NULL);
170 if (!cmdqe) {
171 dev_err(&pdev->dev,
172 "RCFW request failed with no cmdqe!\n");
173 goto done;
174 }
175
176 memset(cmdqe, 0, sizeof(*cmdqe));
177 memcpy(cmdqe, preq, min_t(u32, size, sizeof(*cmdqe)));
178 preq += min_t(u32, size, sizeof(*cmdqe));
179 size -= min_t(u32, size, sizeof(*cmdqe));
180 hwq->prod++;
181 } while (size > 0);
182 cmdq->seq_num++;
183
184 cmdq_prod = hwq->prod;
185 if (test_bit(FIRMWARE_FIRST_FLAG, &cmdq->flags)) {
186
187
188
189
190
191 cmdq_prod |= BIT(FIRMWARE_FIRST_FLAG);
192 clear_bit(FIRMWARE_FIRST_FLAG, &cmdq->flags);
193 }
194
195
196 wmb();
197 writel(cmdq_prod, cmdq->cmdq_mbox.prod);
198 writel(RCFW_CMDQ_TRIG_VAL, cmdq->cmdq_mbox.db);
199done:
200 spin_unlock_irqrestore(&hwq->lock, flags);
201
202 return 0;
203}
204
205int bnxt_qplib_rcfw_send_message(struct bnxt_qplib_rcfw *rcfw,
206 struct cmdq_base *req,
207 struct creq_base *resp,
208 void *sb, u8 is_block)
209{
210 struct creq_qp_event *evnt = (struct creq_qp_event *)resp;
211 u16 cookie;
212 u8 opcode, retry_cnt = 0xFF;
213 int rc = 0;
214
215
216 if (test_bit(ERR_DEVICE_DETACHED, &rcfw->cmdq.flags))
217 return 0;
218
219 do {
220 opcode = req->opcode;
221 rc = __send_message(rcfw, req, resp, sb, is_block);
222 cookie = le16_to_cpu(req->cookie) & RCFW_MAX_COOKIE_VALUE;
223 if (!rc)
224 break;
225
226 if (!retry_cnt || (rc != -EAGAIN && rc != -EBUSY)) {
227
228 dev_err(&rcfw->pdev->dev, "cmdq[%#x]=%#x send failed\n",
229 cookie, opcode);
230 return rc;
231 }
232 is_block ? mdelay(1) : usleep_range(500, 1000);
233
234 } while (retry_cnt--);
235
236 if (is_block)
237 rc = __block_for_resp(rcfw, cookie);
238 else
239 rc = __wait_for_resp(rcfw, cookie);
240 if (rc) {
241
242 dev_err(&rcfw->pdev->dev, "cmdq[%#x]=%#x timedout (%d)msec\n",
243 cookie, opcode, RCFW_CMD_WAIT_TIME_MS);
244 set_bit(FIRMWARE_TIMED_OUT, &rcfw->cmdq.flags);
245 return rc;
246 }
247
248 if (evnt->status) {
249
250 dev_err(&rcfw->pdev->dev, "cmdq[%#x]=%#x status %#x\n",
251 cookie, opcode, evnt->status);
252 rc = -EFAULT;
253 }
254
255 return rc;
256}
257
258static int bnxt_qplib_process_func_event(struct bnxt_qplib_rcfw *rcfw,
259 struct creq_func_event *func_event)
260{
261 int rc;
262
263 switch (func_event->event) {
264 case CREQ_FUNC_EVENT_EVENT_TX_WQE_ERROR:
265 break;
266 case CREQ_FUNC_EVENT_EVENT_TX_DATA_ERROR:
267 break;
268 case CREQ_FUNC_EVENT_EVENT_RX_WQE_ERROR:
269 break;
270 case CREQ_FUNC_EVENT_EVENT_RX_DATA_ERROR:
271 break;
272 case CREQ_FUNC_EVENT_EVENT_CQ_ERROR:
273 break;
274 case CREQ_FUNC_EVENT_EVENT_TQM_ERROR:
275 break;
276 case CREQ_FUNC_EVENT_EVENT_CFCQ_ERROR:
277 break;
278 case CREQ_FUNC_EVENT_EVENT_CFCS_ERROR:
279
280
281
282 break;
283 case CREQ_FUNC_EVENT_EVENT_CFCC_ERROR:
284 break;
285 case CREQ_FUNC_EVENT_EVENT_CFCM_ERROR:
286 break;
287 case CREQ_FUNC_EVENT_EVENT_TIM_ERROR:
288 break;
289 case CREQ_FUNC_EVENT_EVENT_VF_COMM_REQUEST:
290 break;
291 case CREQ_FUNC_EVENT_EVENT_RESOURCE_EXHAUSTED:
292 break;
293 default:
294 return -EINVAL;
295 }
296
297 rc = rcfw->creq.aeq_handler(rcfw, (void *)func_event, NULL);
298 return rc;
299}
300
301static int bnxt_qplib_process_qp_event(struct bnxt_qplib_rcfw *rcfw,
302 struct creq_qp_event *qp_event)
303{
304 struct creq_qp_error_notification *err_event;
305 struct bnxt_qplib_hwq *hwq = &rcfw->cmdq.hwq;
306 struct bnxt_qplib_crsqe *crsqe;
307 struct bnxt_qplib_qp *qp;
308 u16 cbit, blocked = 0;
309 struct pci_dev *pdev;
310 unsigned long flags;
311 __le16 mcookie;
312 u16 cookie;
313 int rc = 0;
314 u32 qp_id, tbl_indx;
315
316 pdev = rcfw->pdev;
317 switch (qp_event->event) {
318 case CREQ_QP_EVENT_EVENT_QP_ERROR_NOTIFICATION:
319 err_event = (struct creq_qp_error_notification *)qp_event;
320 qp_id = le32_to_cpu(err_event->xid);
321 tbl_indx = map_qp_id_to_tbl_indx(qp_id, rcfw);
322 qp = rcfw->qp_tbl[tbl_indx].qp_handle;
323 dev_dbg(&pdev->dev, "Received QP error notification\n");
324 dev_dbg(&pdev->dev,
325 "qpid 0x%x, req_err=0x%x, resp_err=0x%x\n",
326 qp_id, err_event->req_err_state_reason,
327 err_event->res_err_state_reason);
328 if (!qp)
329 break;
330 bnxt_qplib_mark_qp_error(qp);
331 rc = rcfw->creq.aeq_handler(rcfw, qp_event, qp);
332 break;
333 default:
334
335
336
337
338
339
340
341
342
343 spin_lock_irqsave_nested(&hwq->lock, flags,
344 SINGLE_DEPTH_NESTING);
345 cookie = le16_to_cpu(qp_event->cookie);
346 mcookie = qp_event->cookie;
347 blocked = cookie & RCFW_CMD_IS_BLOCKING;
348 cookie &= RCFW_MAX_COOKIE_VALUE;
349 cbit = cookie % rcfw->cmdq_depth;
350 crsqe = &rcfw->crsqe_tbl[cbit];
351 if (crsqe->resp &&
352 crsqe->resp->cookie == mcookie) {
353 memcpy(crsqe->resp, qp_event, sizeof(*qp_event));
354 crsqe->resp = NULL;
355 } else {
356 if (crsqe->resp && crsqe->resp->cookie)
357 dev_err(&pdev->dev,
358 "CMD %s cookie sent=%#x, recd=%#x\n",
359 crsqe->resp ? "mismatch" : "collision",
360 crsqe->resp ? crsqe->resp->cookie : 0,
361 mcookie);
362 }
363 if (!test_and_clear_bit(cbit, rcfw->cmdq.cmdq_bitmap))
364 dev_warn(&pdev->dev,
365 "CMD bit %d was not requested\n", cbit);
366 hwq->cons += crsqe->req_size;
367 crsqe->req_size = 0;
368
369 if (!blocked)
370 wake_up(&rcfw->cmdq.waitq);
371 spin_unlock_irqrestore(&hwq->lock, flags);
372 }
373 return rc;
374}
375
376
377static void bnxt_qplib_service_creq(struct tasklet_struct *t)
378{
379 struct bnxt_qplib_rcfw *rcfw = from_tasklet(rcfw, t, creq.creq_tasklet);
380 struct bnxt_qplib_creq_ctx *creq = &rcfw->creq;
381 u32 type, budget = CREQ_ENTRY_POLL_BUDGET;
382 struct bnxt_qplib_hwq *hwq = &creq->hwq;
383 struct creq_base *creqe;
384 u32 sw_cons, raw_cons;
385 unsigned long flags;
386
387
388 spin_lock_irqsave(&hwq->lock, flags);
389 raw_cons = hwq->cons;
390 while (budget > 0) {
391 sw_cons = HWQ_CMP(raw_cons, hwq);
392 creqe = bnxt_qplib_get_qe(hwq, sw_cons, NULL);
393 if (!CREQ_CMP_VALID(creqe, raw_cons, hwq->max_elements))
394 break;
395
396
397
398 dma_rmb();
399
400 type = creqe->type & CREQ_BASE_TYPE_MASK;
401 switch (type) {
402 case CREQ_BASE_TYPE_QP_EVENT:
403 bnxt_qplib_process_qp_event
404 (rcfw, (struct creq_qp_event *)creqe);
405 creq->stats.creq_qp_event_processed++;
406 break;
407 case CREQ_BASE_TYPE_FUNC_EVENT:
408 if (!bnxt_qplib_process_func_event
409 (rcfw, (struct creq_func_event *)creqe))
410 creq->stats.creq_func_event_processed++;
411 else
412 dev_warn(&rcfw->pdev->dev,
413 "aeqe:%#x Not handled\n", type);
414 break;
415 default:
416 if (type != ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT)
417 dev_warn(&rcfw->pdev->dev,
418 "creqe with event 0x%x not handled\n",
419 type);
420 break;
421 }
422 raw_cons++;
423 budget--;
424 }
425
426 if (hwq->cons != raw_cons) {
427 hwq->cons = raw_cons;
428 bnxt_qplib_ring_nq_db(&creq->creq_db.dbinfo,
429 rcfw->res->cctx, true);
430 }
431 spin_unlock_irqrestore(&hwq->lock, flags);
432}
433
434static irqreturn_t bnxt_qplib_creq_irq(int irq, void *dev_instance)
435{
436 struct bnxt_qplib_rcfw *rcfw = dev_instance;
437 struct bnxt_qplib_creq_ctx *creq;
438 struct bnxt_qplib_hwq *hwq;
439 u32 sw_cons;
440
441 creq = &rcfw->creq;
442 hwq = &creq->hwq;
443
444 sw_cons = HWQ_CMP(hwq->cons, hwq);
445 prefetch(bnxt_qplib_get_qe(hwq, sw_cons, NULL));
446
447 tasklet_schedule(&creq->creq_tasklet);
448
449 return IRQ_HANDLED;
450}
451
452
453int bnxt_qplib_deinit_rcfw(struct bnxt_qplib_rcfw *rcfw)
454{
455 struct cmdq_deinitialize_fw req;
456 struct creq_deinitialize_fw_resp resp;
457 u16 cmd_flags = 0;
458 int rc;
459
460 RCFW_CMD_PREP(req, DEINITIALIZE_FW, cmd_flags);
461 rc = bnxt_qplib_rcfw_send_message(rcfw, (void *)&req, (void *)&resp,
462 NULL, 0);
463 if (rc)
464 return rc;
465
466 clear_bit(FIRMWARE_INITIALIZED_FLAG, &rcfw->cmdq.flags);
467 return 0;
468}
469
470int bnxt_qplib_init_rcfw(struct bnxt_qplib_rcfw *rcfw,
471 struct bnxt_qplib_ctx *ctx, int is_virtfn)
472{
473 struct creq_initialize_fw_resp resp;
474 struct cmdq_initialize_fw req;
475 u16 cmd_flags = 0;
476 u8 pgsz, lvl;
477 int rc;
478
479 RCFW_CMD_PREP(req, INITIALIZE_FW, cmd_flags);
480
481
482
483 req.log2_dbr_pg_size = cpu_to_le16(PAGE_SHIFT -
484 RCFW_DBR_BASE_PAGE_SHIFT);
485
486
487
488
489
490
491
492 if (is_virtfn)
493 goto skip_ctx_setup;
494 if (bnxt_qplib_is_chip_gen_p5(rcfw->res->cctx))
495 goto config_vf_res;
496
497 lvl = ctx->qpc_tbl.level;
498 pgsz = bnxt_qplib_base_pg_size(&ctx->qpc_tbl);
499 req.qpc_pg_size_qpc_lvl = (pgsz << CMDQ_INITIALIZE_FW_QPC_PG_SIZE_SFT) |
500 lvl;
501 lvl = ctx->mrw_tbl.level;
502 pgsz = bnxt_qplib_base_pg_size(&ctx->mrw_tbl);
503 req.mrw_pg_size_mrw_lvl = (pgsz << CMDQ_INITIALIZE_FW_QPC_PG_SIZE_SFT) |
504 lvl;
505 lvl = ctx->srqc_tbl.level;
506 pgsz = bnxt_qplib_base_pg_size(&ctx->srqc_tbl);
507 req.srq_pg_size_srq_lvl = (pgsz << CMDQ_INITIALIZE_FW_QPC_PG_SIZE_SFT) |
508 lvl;
509 lvl = ctx->cq_tbl.level;
510 pgsz = bnxt_qplib_base_pg_size(&ctx->cq_tbl);
511 req.cq_pg_size_cq_lvl = (pgsz << CMDQ_INITIALIZE_FW_QPC_PG_SIZE_SFT) |
512 lvl;
513 lvl = ctx->tim_tbl.level;
514 pgsz = bnxt_qplib_base_pg_size(&ctx->tim_tbl);
515 req.tim_pg_size_tim_lvl = (pgsz << CMDQ_INITIALIZE_FW_QPC_PG_SIZE_SFT) |
516 lvl;
517 lvl = ctx->tqm_ctx.pde.level;
518 pgsz = bnxt_qplib_base_pg_size(&ctx->tqm_ctx.pde);
519 req.tqm_pg_size_tqm_lvl = (pgsz << CMDQ_INITIALIZE_FW_QPC_PG_SIZE_SFT) |
520 lvl;
521 req.qpc_page_dir =
522 cpu_to_le64(ctx->qpc_tbl.pbl[PBL_LVL_0].pg_map_arr[0]);
523 req.mrw_page_dir =
524 cpu_to_le64(ctx->mrw_tbl.pbl[PBL_LVL_0].pg_map_arr[0]);
525 req.srq_page_dir =
526 cpu_to_le64(ctx->srqc_tbl.pbl[PBL_LVL_0].pg_map_arr[0]);
527 req.cq_page_dir =
528 cpu_to_le64(ctx->cq_tbl.pbl[PBL_LVL_0].pg_map_arr[0]);
529 req.tim_page_dir =
530 cpu_to_le64(ctx->tim_tbl.pbl[PBL_LVL_0].pg_map_arr[0]);
531 req.tqm_page_dir =
532 cpu_to_le64(ctx->tqm_ctx.pde.pbl[PBL_LVL_0].pg_map_arr[0]);
533
534 req.number_of_qp = cpu_to_le32(ctx->qpc_tbl.max_elements);
535 req.number_of_mrw = cpu_to_le32(ctx->mrw_tbl.max_elements);
536 req.number_of_srq = cpu_to_le32(ctx->srqc_tbl.max_elements);
537 req.number_of_cq = cpu_to_le32(ctx->cq_tbl.max_elements);
538
539config_vf_res:
540 req.max_qp_per_vf = cpu_to_le32(ctx->vf_res.max_qp_per_vf);
541 req.max_mrw_per_vf = cpu_to_le32(ctx->vf_res.max_mrw_per_vf);
542 req.max_srq_per_vf = cpu_to_le32(ctx->vf_res.max_srq_per_vf);
543 req.max_cq_per_vf = cpu_to_le32(ctx->vf_res.max_cq_per_vf);
544 req.max_gid_per_vf = cpu_to_le32(ctx->vf_res.max_gid_per_vf);
545
546skip_ctx_setup:
547 req.stat_ctx_id = cpu_to_le32(ctx->stats.fw_id);
548 rc = bnxt_qplib_rcfw_send_message(rcfw, (void *)&req, (void *)&resp,
549 NULL, 0);
550 if (rc)
551 return rc;
552 set_bit(FIRMWARE_INITIALIZED_FLAG, &rcfw->cmdq.flags);
553 return 0;
554}
555
556void bnxt_qplib_free_rcfw_channel(struct bnxt_qplib_rcfw *rcfw)
557{
558 bitmap_free(rcfw->cmdq.cmdq_bitmap);
559 kfree(rcfw->qp_tbl);
560 kfree(rcfw->crsqe_tbl);
561 bnxt_qplib_free_hwq(rcfw->res, &rcfw->cmdq.hwq);
562 bnxt_qplib_free_hwq(rcfw->res, &rcfw->creq.hwq);
563 rcfw->pdev = NULL;
564}
565
566int bnxt_qplib_alloc_rcfw_channel(struct bnxt_qplib_res *res,
567 struct bnxt_qplib_rcfw *rcfw,
568 struct bnxt_qplib_ctx *ctx,
569 int qp_tbl_sz)
570{
571 struct bnxt_qplib_hwq_attr hwq_attr = {};
572 struct bnxt_qplib_sg_info sginfo = {};
573 struct bnxt_qplib_cmdq_ctx *cmdq;
574 struct bnxt_qplib_creq_ctx *creq;
575
576 rcfw->pdev = res->pdev;
577 cmdq = &rcfw->cmdq;
578 creq = &rcfw->creq;
579 rcfw->res = res;
580
581 sginfo.pgsize = PAGE_SIZE;
582 sginfo.pgshft = PAGE_SHIFT;
583
584 hwq_attr.sginfo = &sginfo;
585 hwq_attr.res = rcfw->res;
586 hwq_attr.depth = BNXT_QPLIB_CREQE_MAX_CNT;
587 hwq_attr.stride = BNXT_QPLIB_CREQE_UNITS;
588 hwq_attr.type = bnxt_qplib_get_hwq_type(res);
589
590 if (bnxt_qplib_alloc_init_hwq(&creq->hwq, &hwq_attr)) {
591 dev_err(&rcfw->pdev->dev,
592 "HW channel CREQ allocation failed\n");
593 goto fail;
594 }
595 if (ctx->hwrm_intf_ver < HWRM_VERSION_RCFW_CMDQ_DEPTH_CHECK)
596 rcfw->cmdq_depth = BNXT_QPLIB_CMDQE_MAX_CNT_256;
597 else
598 rcfw->cmdq_depth = BNXT_QPLIB_CMDQE_MAX_CNT_8192;
599
600 sginfo.pgsize = bnxt_qplib_cmdqe_page_size(rcfw->cmdq_depth);
601 hwq_attr.depth = rcfw->cmdq_depth;
602 hwq_attr.stride = BNXT_QPLIB_CMDQE_UNITS;
603 hwq_attr.type = HWQ_TYPE_CTX;
604 if (bnxt_qplib_alloc_init_hwq(&cmdq->hwq, &hwq_attr)) {
605 dev_err(&rcfw->pdev->dev,
606 "HW channel CMDQ allocation failed\n");
607 goto fail;
608 }
609
610 rcfw->crsqe_tbl = kcalloc(cmdq->hwq.max_elements,
611 sizeof(*rcfw->crsqe_tbl), GFP_KERNEL);
612 if (!rcfw->crsqe_tbl)
613 goto fail;
614
615 cmdq->cmdq_bitmap = bitmap_zalloc(rcfw->cmdq_depth, GFP_KERNEL);
616 if (!cmdq->cmdq_bitmap)
617 goto fail;
618
619
620 rcfw->qp_tbl_size = qp_tbl_sz + 1;
621 rcfw->qp_tbl = kcalloc(rcfw->qp_tbl_size, sizeof(struct bnxt_qplib_qp_node),
622 GFP_KERNEL);
623 if (!rcfw->qp_tbl)
624 goto fail;
625
626 return 0;
627
628fail:
629 bnxt_qplib_free_rcfw_channel(rcfw);
630 return -ENOMEM;
631}
632
633void bnxt_qplib_rcfw_stop_irq(struct bnxt_qplib_rcfw *rcfw, bool kill)
634{
635 struct bnxt_qplib_creq_ctx *creq;
636
637 creq = &rcfw->creq;
638 tasklet_disable(&creq->creq_tasklet);
639
640 bnxt_qplib_ring_nq_db(&creq->creq_db.dbinfo, rcfw->res->cctx, false);
641
642 synchronize_irq(creq->msix_vec);
643 if (kill)
644 tasklet_kill(&creq->creq_tasklet);
645
646 if (creq->requested) {
647 free_irq(creq->msix_vec, rcfw);
648 creq->requested = false;
649 }
650}
651
652void bnxt_qplib_disable_rcfw_channel(struct bnxt_qplib_rcfw *rcfw)
653{
654 struct bnxt_qplib_creq_ctx *creq;
655 struct bnxt_qplib_cmdq_ctx *cmdq;
656 unsigned long indx;
657
658 creq = &rcfw->creq;
659 cmdq = &rcfw->cmdq;
660
661 bnxt_qplib_rcfw_stop_irq(rcfw, true);
662
663 iounmap(cmdq->cmdq_mbox.reg.bar_reg);
664 iounmap(creq->creq_db.reg.bar_reg);
665
666 indx = find_first_bit(cmdq->cmdq_bitmap, rcfw->cmdq_depth);
667 if (indx != rcfw->cmdq_depth)
668 dev_err(&rcfw->pdev->dev,
669 "disabling RCFW with pending cmd-bit %lx\n", indx);
670
671 cmdq->cmdq_mbox.reg.bar_reg = NULL;
672 creq->creq_db.reg.bar_reg = NULL;
673 creq->aeq_handler = NULL;
674 creq->msix_vec = 0;
675}
676
677int bnxt_qplib_rcfw_start_irq(struct bnxt_qplib_rcfw *rcfw, int msix_vector,
678 bool need_init)
679{
680 struct bnxt_qplib_creq_ctx *creq;
681 int rc;
682
683 creq = &rcfw->creq;
684
685 if (creq->requested)
686 return -EFAULT;
687
688 creq->msix_vec = msix_vector;
689 if (need_init)
690 tasklet_setup(&creq->creq_tasklet, bnxt_qplib_service_creq);
691 else
692 tasklet_enable(&creq->creq_tasklet);
693 rc = request_irq(creq->msix_vec, bnxt_qplib_creq_irq, 0,
694 "bnxt_qplib_creq", rcfw);
695 if (rc)
696 return rc;
697 creq->requested = true;
698
699 bnxt_qplib_ring_nq_db(&creq->creq_db.dbinfo, rcfw->res->cctx, true);
700
701 return 0;
702}
703
704static int bnxt_qplib_map_cmdq_mbox(struct bnxt_qplib_rcfw *rcfw, bool is_vf)
705{
706 struct bnxt_qplib_cmdq_mbox *mbox;
707 resource_size_t bar_reg;
708 struct pci_dev *pdev;
709 u16 prod_offt;
710 int rc = 0;
711
712 pdev = rcfw->pdev;
713 mbox = &rcfw->cmdq.cmdq_mbox;
714
715 mbox->reg.bar_id = RCFW_COMM_PCI_BAR_REGION;
716 mbox->reg.len = RCFW_COMM_SIZE;
717 mbox->reg.bar_base = pci_resource_start(pdev, mbox->reg.bar_id);
718 if (!mbox->reg.bar_base) {
719 dev_err(&pdev->dev,
720 "QPLIB: CMDQ BAR region %d resc start is 0!\n",
721 mbox->reg.bar_id);
722 return -ENOMEM;
723 }
724
725 bar_reg = mbox->reg.bar_base + RCFW_COMM_BASE_OFFSET;
726 mbox->reg.len = RCFW_COMM_SIZE;
727 mbox->reg.bar_reg = ioremap(bar_reg, mbox->reg.len);
728 if (!mbox->reg.bar_reg) {
729 dev_err(&pdev->dev,
730 "QPLIB: CMDQ BAR region %d mapping failed\n",
731 mbox->reg.bar_id);
732 return -ENOMEM;
733 }
734
735 prod_offt = is_vf ? RCFW_VF_COMM_PROD_OFFSET :
736 RCFW_PF_COMM_PROD_OFFSET;
737 mbox->prod = (void __iomem *)(mbox->reg.bar_reg + prod_offt);
738 mbox->db = (void __iomem *)(mbox->reg.bar_reg + RCFW_COMM_TRIG_OFFSET);
739 return rc;
740}
741
742static int bnxt_qplib_map_creq_db(struct bnxt_qplib_rcfw *rcfw, u32 reg_offt)
743{
744 struct bnxt_qplib_creq_db *creq_db;
745 resource_size_t bar_reg;
746 struct pci_dev *pdev;
747
748 pdev = rcfw->pdev;
749 creq_db = &rcfw->creq.creq_db;
750
751 creq_db->reg.bar_id = RCFW_COMM_CONS_PCI_BAR_REGION;
752 creq_db->reg.bar_base = pci_resource_start(pdev, creq_db->reg.bar_id);
753 if (!creq_db->reg.bar_id)
754 dev_err(&pdev->dev,
755 "QPLIB: CREQ BAR region %d resc start is 0!",
756 creq_db->reg.bar_id);
757
758 bar_reg = creq_db->reg.bar_base + reg_offt;
759
760 creq_db->reg.len = 8;
761 creq_db->reg.bar_reg = ioremap(bar_reg, creq_db->reg.len);
762 if (!creq_db->reg.bar_reg) {
763 dev_err(&pdev->dev,
764 "QPLIB: CREQ BAR region %d mapping failed",
765 creq_db->reg.bar_id);
766 return -ENOMEM;
767 }
768 creq_db->dbinfo.db = creq_db->reg.bar_reg;
769 creq_db->dbinfo.hwq = &rcfw->creq.hwq;
770 creq_db->dbinfo.xid = rcfw->creq.ring_id;
771 return 0;
772}
773
774static void bnxt_qplib_start_rcfw(struct bnxt_qplib_rcfw *rcfw)
775{
776 struct bnxt_qplib_cmdq_ctx *cmdq;
777 struct bnxt_qplib_creq_ctx *creq;
778 struct bnxt_qplib_cmdq_mbox *mbox;
779 struct cmdq_init init = {0};
780
781 cmdq = &rcfw->cmdq;
782 creq = &rcfw->creq;
783 mbox = &cmdq->cmdq_mbox;
784
785 init.cmdq_pbl = cpu_to_le64(cmdq->hwq.pbl[PBL_LVL_0].pg_map_arr[0]);
786 init.cmdq_size_cmdq_lvl =
787 cpu_to_le16(((rcfw->cmdq_depth <<
788 CMDQ_INIT_CMDQ_SIZE_SFT) &
789 CMDQ_INIT_CMDQ_SIZE_MASK) |
790 ((cmdq->hwq.level <<
791 CMDQ_INIT_CMDQ_LVL_SFT) &
792 CMDQ_INIT_CMDQ_LVL_MASK));
793 init.creq_ring_id = cpu_to_le16(creq->ring_id);
794
795 __iowrite32_copy(mbox->reg.bar_reg, &init, sizeof(init) / 4);
796}
797
798int bnxt_qplib_enable_rcfw_channel(struct bnxt_qplib_rcfw *rcfw,
799 int msix_vector,
800 int cp_bar_reg_off, int virt_fn,
801 aeq_handler_t aeq_handler)
802{
803 struct bnxt_qplib_cmdq_ctx *cmdq;
804 struct bnxt_qplib_creq_ctx *creq;
805 int rc;
806
807 cmdq = &rcfw->cmdq;
808 creq = &rcfw->creq;
809
810
811
812 cmdq->seq_num = 0;
813 set_bit(FIRMWARE_FIRST_FLAG, &cmdq->flags);
814 init_waitqueue_head(&cmdq->waitq);
815
816 creq->stats.creq_qp_event_processed = 0;
817 creq->stats.creq_func_event_processed = 0;
818 creq->aeq_handler = aeq_handler;
819
820 rc = bnxt_qplib_map_cmdq_mbox(rcfw, virt_fn);
821 if (rc)
822 return rc;
823
824 rc = bnxt_qplib_map_creq_db(rcfw, cp_bar_reg_off);
825 if (rc)
826 return rc;
827
828 rc = bnxt_qplib_rcfw_start_irq(rcfw, msix_vector, true);
829 if (rc) {
830 dev_err(&rcfw->pdev->dev,
831 "Failed to request IRQ for CREQ rc = 0x%x\n", rc);
832 bnxt_qplib_disable_rcfw_channel(rcfw);
833 return rc;
834 }
835
836 bnxt_qplib_start_rcfw(rcfw);
837
838 return 0;
839}
840
841struct bnxt_qplib_rcfw_sbuf *bnxt_qplib_rcfw_alloc_sbuf(
842 struct bnxt_qplib_rcfw *rcfw,
843 u32 size)
844{
845 struct bnxt_qplib_rcfw_sbuf *sbuf;
846
847 sbuf = kzalloc(sizeof(*sbuf), GFP_KERNEL);
848 if (!sbuf)
849 return NULL;
850
851 sbuf->size = size;
852 sbuf->sb = dma_alloc_coherent(&rcfw->pdev->dev, sbuf->size,
853 &sbuf->dma_addr, GFP_KERNEL);
854 if (!sbuf->sb)
855 goto bail;
856
857 return sbuf;
858bail:
859 kfree(sbuf);
860 return NULL;
861}
862
863void bnxt_qplib_rcfw_free_sbuf(struct bnxt_qplib_rcfw *rcfw,
864 struct bnxt_qplib_rcfw_sbuf *sbuf)
865{
866 if (sbuf->sb)
867 dma_free_coherent(&rcfw->pdev->dev, sbuf->size,
868 sbuf->sb, sbuf->dma_addr);
869 kfree(sbuf);
870}
871
