1
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3
4
5
6#include <linux/io.h>
7#include <rdma/rdma_vt.h>
8#include <rdma/rdmavt_qp.h>
9
10#include "hfi.h"
11#include "qp.h"
12#include "rc.h"
13#include "verbs_txreq.h"
14#include "trace.h"
15
16struct rvt_ack_entry *find_prev_entry(struct rvt_qp *qp, u32 psn, u8 *prev,
17 u8 *prev_ack, bool *scheduled)
18 __must_hold(&qp->s_lock)
19{
20 struct rvt_ack_entry *e = NULL;
21 u8 i, p;
22 bool s = true;
23
24 for (i = qp->r_head_ack_queue; ; i = p) {
25 if (i == qp->s_tail_ack_queue)
26 s = false;
27 if (i)
28 p = i - 1;
29 else
30 p = rvt_size_atomic(ib_to_rvt(qp->ibqp.device));
31 if (p == qp->r_head_ack_queue) {
32 e = NULL;
33 break;
34 }
35 e = &qp->s_ack_queue[p];
36 if (!e->opcode) {
37 e = NULL;
38 break;
39 }
40 if (cmp_psn(psn, e->psn) >= 0) {
41 if (p == qp->s_tail_ack_queue &&
42 cmp_psn(psn, e->lpsn) <= 0)
43 s = false;
44 break;
45 }
46 }
47 if (prev)
48 *prev = p;
49 if (prev_ack)
50 *prev_ack = i;
51 if (scheduled)
52 *scheduled = s;
53 return e;
54}
55
56
57
58
59
60
61
62
63
64
65
66
67static int make_rc_ack(struct hfi1_ibdev *dev, struct rvt_qp *qp,
68 struct ib_other_headers *ohdr,
69 struct hfi1_pkt_state *ps)
70{
71 struct rvt_ack_entry *e;
72 u32 hwords, hdrlen;
73 u32 len = 0;
74 u32 bth0 = 0, bth2 = 0;
75 u32 bth1 = qp->remote_qpn | (HFI1_CAP_IS_KSET(OPFN) << IB_BTHE_E_SHIFT);
76 int middle = 0;
77 u32 pmtu = qp->pmtu;
78 struct hfi1_qp_priv *qpriv = qp->priv;
79 bool last_pkt;
80 u32 delta;
81 u8 next = qp->s_tail_ack_queue;
82 struct tid_rdma_request *req;
83
84 trace_hfi1_rsp_make_rc_ack(qp, 0);
85 lockdep_assert_held(&qp->s_lock);
86
87 if (!(ib_rvt_state_ops[qp->state] & RVT_PROCESS_RECV_OK))
88 goto bail;
89
90 if (qpriv->hdr_type == HFI1_PKT_TYPE_9B)
91
92 hwords = 5;
93 else
94
95 hwords = 7;
96
97 switch (qp->s_ack_state) {
98 case OP(RDMA_READ_RESPONSE_LAST):
99 case OP(RDMA_READ_RESPONSE_ONLY):
100 e = &qp->s_ack_queue[qp->s_tail_ack_queue];
101 release_rdma_sge_mr(e);
102 fallthrough;
103 case OP(ATOMIC_ACKNOWLEDGE):
104
105
106
107
108
109 if (++next > rvt_size_atomic(&dev->rdi))
110 next = 0;
111
112
113
114
115 e = &qp->s_ack_queue[qp->s_tail_ack_queue];
116 if (e->opcode != TID_OP(WRITE_REQ) &&
117 qp->s_acked_ack_queue == qp->s_tail_ack_queue)
118 qp->s_acked_ack_queue = next;
119 qp->s_tail_ack_queue = next;
120 trace_hfi1_rsp_make_rc_ack(qp, e->psn);
121 fallthrough;
122 case OP(SEND_ONLY):
123 case OP(ACKNOWLEDGE):
124
125 if (qp->r_head_ack_queue == qp->s_tail_ack_queue) {
126 if (qp->s_flags & RVT_S_ACK_PENDING)
127 goto normal;
128 goto bail;
129 }
130
131 e = &qp->s_ack_queue[qp->s_tail_ack_queue];
132
133 if ((qpriv->s_flags & HFI1_R_TID_WAIT_INTERLCK) ||
134 hfi1_tid_rdma_ack_interlock(qp, e)) {
135 iowait_set_flag(&qpriv->s_iowait, IOWAIT_PENDING_IB);
136 goto bail;
137 }
138 if (e->opcode == OP(RDMA_READ_REQUEST)) {
139
140
141
142
143
144
145 len = e->rdma_sge.sge_length;
146 if (len && !e->rdma_sge.mr) {
147 if (qp->s_acked_ack_queue ==
148 qp->s_tail_ack_queue)
149 qp->s_acked_ack_queue =
150 qp->r_head_ack_queue;
151 qp->s_tail_ack_queue = qp->r_head_ack_queue;
152 goto bail;
153 }
154
155 ps->s_txreq->mr = e->rdma_sge.mr;
156 if (ps->s_txreq->mr)
157 rvt_get_mr(ps->s_txreq->mr);
158 qp->s_ack_rdma_sge.sge = e->rdma_sge;
159 qp->s_ack_rdma_sge.num_sge = 1;
160 ps->s_txreq->ss = &qp->s_ack_rdma_sge;
161 if (len > pmtu) {
162 len = pmtu;
163 qp->s_ack_state = OP(RDMA_READ_RESPONSE_FIRST);
164 } else {
165 qp->s_ack_state = OP(RDMA_READ_RESPONSE_ONLY);
166 e->sent = 1;
167 }
168 ohdr->u.aeth = rvt_compute_aeth(qp);
169 hwords++;
170 qp->s_ack_rdma_psn = e->psn;
171 bth2 = mask_psn(qp->s_ack_rdma_psn++);
172 } else if (e->opcode == TID_OP(WRITE_REQ)) {
173
174
175
176
177
178
179
180 req = ack_to_tid_req(e);
181 if (req->state == TID_REQUEST_RESEND ||
182 req->state == TID_REQUEST_INIT_RESEND)
183 goto bail;
184 qp->s_ack_state = TID_OP(WRITE_RESP);
185 qp->s_ack_rdma_psn = mask_psn(e->psn + req->cur_seg);
186 goto write_resp;
187 } else if (e->opcode == TID_OP(READ_REQ)) {
188
189
190
191
192
193
194 len = e->rdma_sge.sge_length;
195 if (len && !e->rdma_sge.mr) {
196 if (qp->s_acked_ack_queue ==
197 qp->s_tail_ack_queue)
198 qp->s_acked_ack_queue =
199 qp->r_head_ack_queue;
200 qp->s_tail_ack_queue = qp->r_head_ack_queue;
201 goto bail;
202 }
203
204 ps->s_txreq->mr = e->rdma_sge.mr;
205 if (ps->s_txreq->mr)
206 rvt_get_mr(ps->s_txreq->mr);
207 qp->s_ack_rdma_sge.sge = e->rdma_sge;
208 qp->s_ack_rdma_sge.num_sge = 1;
209 qp->s_ack_state = TID_OP(READ_RESP);
210 goto read_resp;
211 } else {
212
213 ps->s_txreq->ss = NULL;
214 len = 0;
215 qp->s_ack_state = OP(ATOMIC_ACKNOWLEDGE);
216 ohdr->u.at.aeth = rvt_compute_aeth(qp);
217 ib_u64_put(e->atomic_data, &ohdr->u.at.atomic_ack_eth);
218 hwords += sizeof(ohdr->u.at) / sizeof(u32);
219 bth2 = mask_psn(e->psn);
220 e->sent = 1;
221 }
222 trace_hfi1_tid_write_rsp_make_rc_ack(qp);
223 bth0 = qp->s_ack_state << 24;
224 break;
225
226 case OP(RDMA_READ_RESPONSE_FIRST):
227 qp->s_ack_state = OP(RDMA_READ_RESPONSE_MIDDLE);
228 fallthrough;
229 case OP(RDMA_READ_RESPONSE_MIDDLE):
230 ps->s_txreq->ss = &qp->s_ack_rdma_sge;
231 ps->s_txreq->mr = qp->s_ack_rdma_sge.sge.mr;
232 if (ps->s_txreq->mr)
233 rvt_get_mr(ps->s_txreq->mr);
234 len = qp->s_ack_rdma_sge.sge.sge_length;
235 if (len > pmtu) {
236 len = pmtu;
237 middle = HFI1_CAP_IS_KSET(SDMA_AHG);
238 } else {
239 ohdr->u.aeth = rvt_compute_aeth(qp);
240 hwords++;
241 qp->s_ack_state = OP(RDMA_READ_RESPONSE_LAST);
242 e = &qp->s_ack_queue[qp->s_tail_ack_queue];
243 e->sent = 1;
244 }
245 bth0 = qp->s_ack_state << 24;
246 bth2 = mask_psn(qp->s_ack_rdma_psn++);
247 break;
248
249 case TID_OP(WRITE_RESP):
250write_resp:
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270 e = &qp->s_ack_queue[qp->s_tail_ack_queue];
271 req = ack_to_tid_req(e);
272
273
274
275
276
277
278 if (qpriv->rnr_nak_state == TID_RNR_NAK_SEND &&
279 qp->s_tail_ack_queue == qpriv->r_tid_alloc &&
280 req->cur_seg == req->alloc_seg) {
281 qpriv->rnr_nak_state = TID_RNR_NAK_SENT;
282 goto normal_no_state;
283 }
284
285 bth2 = mask_psn(qp->s_ack_rdma_psn);
286 hdrlen = hfi1_build_tid_rdma_write_resp(qp, e, ohdr, &bth1,
287 bth2, &len,
288 &ps->s_txreq->ss);
289 if (!hdrlen)
290 return 0;
291
292 hwords += hdrlen;
293 bth0 = qp->s_ack_state << 24;
294 qp->s_ack_rdma_psn++;
295 trace_hfi1_tid_req_make_rc_ack_write(qp, 0, e->opcode, e->psn,
296 e->lpsn, req);
297 if (req->cur_seg != req->total_segs)
298 break;
299
300 e->sent = 1;
301
302 qp->s_ack_state = OP(ATOMIC_ACKNOWLEDGE);
303 break;
304
305 case TID_OP(READ_RESP):
306read_resp:
307 e = &qp->s_ack_queue[qp->s_tail_ack_queue];
308 ps->s_txreq->ss = &qp->s_ack_rdma_sge;
309 delta = hfi1_build_tid_rdma_read_resp(qp, e, ohdr, &bth0,
310 &bth1, &bth2, &len,
311 &last_pkt);
312 if (delta == 0)
313 goto error_qp;
314 hwords += delta;
315 if (last_pkt) {
316 e->sent = 1;
317
318
319
320
321 qp->s_ack_state = OP(RDMA_READ_RESPONSE_LAST);
322 }
323 break;
324 case TID_OP(READ_REQ):
325 goto bail;
326
327 default:
328normal:
329
330
331
332
333
334
335 qp->s_ack_state = OP(SEND_ONLY);
336normal_no_state:
337 if (qp->s_nak_state)
338 ohdr->u.aeth =
339 cpu_to_be32((qp->r_msn & IB_MSN_MASK) |
340 (qp->s_nak_state <<
341 IB_AETH_CREDIT_SHIFT));
342 else
343 ohdr->u.aeth = rvt_compute_aeth(qp);
344 hwords++;
345 len = 0;
346 bth0 = OP(ACKNOWLEDGE) << 24;
347 bth2 = mask_psn(qp->s_ack_psn);
348 qp->s_flags &= ~RVT_S_ACK_PENDING;
349 ps->s_txreq->txreq.flags |= SDMA_TXREQ_F_VIP;
350 ps->s_txreq->ss = NULL;
351 }
352 qp->s_rdma_ack_cnt++;
353 ps->s_txreq->sde = qpriv->s_sde;
354 ps->s_txreq->s_cur_size = len;
355 ps->s_txreq->hdr_dwords = hwords;
356 hfi1_make_ruc_header(qp, ohdr, bth0, bth1, bth2, middle, ps);
357 return 1;
358error_qp:
359 spin_unlock_irqrestore(&qp->s_lock, ps->flags);
360 spin_lock_irqsave(&qp->r_lock, ps->flags);
361 spin_lock(&qp->s_lock);
362 rvt_error_qp(qp, IB_WC_WR_FLUSH_ERR);
363 spin_unlock(&qp->s_lock);
364 spin_unlock_irqrestore(&qp->r_lock, ps->flags);
365 spin_lock_irqsave(&qp->s_lock, ps->flags);
366bail:
367 qp->s_ack_state = OP(ACKNOWLEDGE);
368
369
370
371
372 smp_wmb();
373 qp->s_flags &= ~(RVT_S_RESP_PENDING
374 | RVT_S_ACK_PENDING
375 | HFI1_S_AHG_VALID);
376 return 0;
377}
378
379
380
381
382
383
384
385
386
387
388int hfi1_make_rc_req(struct rvt_qp *qp, struct hfi1_pkt_state *ps)
389{
390 struct hfi1_qp_priv *priv = qp->priv;
391 struct hfi1_ibdev *dev = to_idev(qp->ibqp.device);
392 struct ib_other_headers *ohdr;
393 struct rvt_sge_state *ss = NULL;
394 struct rvt_swqe *wqe;
395 struct hfi1_swqe_priv *wpriv;
396 struct tid_rdma_request *req = NULL;
397
398 u32 hwords = 5;
399 u32 len = 0;
400 u32 bth0 = 0, bth2 = 0;
401 u32 bth1 = qp->remote_qpn | (HFI1_CAP_IS_KSET(OPFN) << IB_BTHE_E_SHIFT);
402 u32 pmtu = qp->pmtu;
403 char newreq;
404 int middle = 0;
405 int delta;
406 struct tid_rdma_flow *flow = NULL;
407 struct tid_rdma_params *remote;
408
409 trace_hfi1_sender_make_rc_req(qp);
410 lockdep_assert_held(&qp->s_lock);
411 ps->s_txreq = get_txreq(ps->dev, qp);
412 if (!ps->s_txreq)
413 goto bail_no_tx;
414
415 if (priv->hdr_type == HFI1_PKT_TYPE_9B) {
416
417 hwords = 5;
418 if (rdma_ah_get_ah_flags(&qp->remote_ah_attr) & IB_AH_GRH)
419 ohdr = &ps->s_txreq->phdr.hdr.ibh.u.l.oth;
420 else
421 ohdr = &ps->s_txreq->phdr.hdr.ibh.u.oth;
422 } else {
423
424 hwords = 7;
425 if ((rdma_ah_get_ah_flags(&qp->remote_ah_attr) & IB_AH_GRH) &&
426 (hfi1_check_mcast(rdma_ah_get_dlid(&qp->remote_ah_attr))))
427 ohdr = &ps->s_txreq->phdr.hdr.opah.u.l.oth;
428 else
429 ohdr = &ps->s_txreq->phdr.hdr.opah.u.oth;
430 }
431
432
433 if ((qp->s_flags & RVT_S_RESP_PENDING) &&
434 make_rc_ack(dev, qp, ohdr, ps))
435 return 1;
436
437 if (!(ib_rvt_state_ops[qp->state] & RVT_PROCESS_SEND_OK)) {
438 if (!(ib_rvt_state_ops[qp->state] & RVT_FLUSH_SEND))
439 goto bail;
440
441 if (qp->s_last == READ_ONCE(qp->s_head))
442 goto bail;
443
444 if (iowait_sdma_pending(&priv->s_iowait)) {
445 qp->s_flags |= RVT_S_WAIT_DMA;
446 goto bail;
447 }
448 clear_ahg(qp);
449 wqe = rvt_get_swqe_ptr(qp, qp->s_last);
450 hfi1_trdma_send_complete(qp, wqe, qp->s_last != qp->s_acked ?
451 IB_WC_SUCCESS : IB_WC_WR_FLUSH_ERR);
452
453 goto done_free_tx;
454 }
455
456 if (qp->s_flags & (RVT_S_WAIT_RNR | RVT_S_WAIT_ACK | HFI1_S_WAIT_HALT))
457 goto bail;
458
459 if (cmp_psn(qp->s_psn, qp->s_sending_hpsn) <= 0) {
460 if (cmp_psn(qp->s_sending_psn, qp->s_sending_hpsn) <= 0) {
461 qp->s_flags |= RVT_S_WAIT_PSN;
462 goto bail;
463 }
464 qp->s_sending_psn = qp->s_psn;
465 qp->s_sending_hpsn = qp->s_psn - 1;
466 }
467
468
469 wqe = rvt_get_swqe_ptr(qp, qp->s_cur);
470check_s_state:
471 switch (qp->s_state) {
472 default:
473 if (!(ib_rvt_state_ops[qp->state] & RVT_PROCESS_NEXT_SEND_OK))
474 goto bail;
475
476
477
478
479
480
481
482 newreq = 0;
483 if (qp->s_cur == qp->s_tail) {
484
485 if (qp->s_tail == READ_ONCE(qp->s_head)) {
486 clear_ahg(qp);
487 goto bail;
488 }
489
490
491
492
493
494
495 if ((wqe->wr.send_flags & IB_SEND_FENCE) &&
496 qp->s_num_rd_atomic &&
497 (wqe->wr.opcode != IB_WR_TID_RDMA_READ ||
498 priv->pending_tid_r_segs < qp->s_num_rd_atomic)) {
499 qp->s_flags |= RVT_S_WAIT_FENCE;
500 goto bail;
501 }
502
503
504
505
506 if (wqe->wr.opcode == IB_WR_REG_MR ||
507 wqe->wr.opcode == IB_WR_LOCAL_INV) {
508 int local_ops = 0;
509 int err = 0;
510
511 if (qp->s_last != qp->s_cur)
512 goto bail;
513 if (++qp->s_cur == qp->s_size)
514 qp->s_cur = 0;
515 if (++qp->s_tail == qp->s_size)
516 qp->s_tail = 0;
517 if (!(wqe->wr.send_flags &
518 RVT_SEND_COMPLETION_ONLY)) {
519 err = rvt_invalidate_rkey(
520 qp,
521 wqe->wr.ex.invalidate_rkey);
522 local_ops = 1;
523 }
524 rvt_send_complete(qp, wqe,
525 err ? IB_WC_LOC_PROT_ERR
526 : IB_WC_SUCCESS);
527 if (local_ops)
528 atomic_dec(&qp->local_ops_pending);
529 goto done_free_tx;
530 }
531
532 newreq = 1;
533 qp->s_psn = wqe->psn;
534 }
535
536
537
538
539
540 len = wqe->length;
541 ss = &qp->s_sge;
542 bth2 = mask_psn(qp->s_psn);
543
544
545
546
547
548 if ((priv->s_flags & HFI1_S_TID_WAIT_INTERLCK) ||
549 hfi1_tid_rdma_wqe_interlock(qp, wqe))
550 goto bail;
551
552 switch (wqe->wr.opcode) {
553 case IB_WR_SEND:
554 case IB_WR_SEND_WITH_IMM:
555 case IB_WR_SEND_WITH_INV:
556
557 if (!rvt_rc_credit_avail(qp, wqe))
558 goto bail;
559 if (len > pmtu) {
560 qp->s_state = OP(SEND_FIRST);
561 len = pmtu;
562 break;
563 }
564 if (wqe->wr.opcode == IB_WR_SEND) {
565 qp->s_state = OP(SEND_ONLY);
566 } else if (wqe->wr.opcode == IB_WR_SEND_WITH_IMM) {
567 qp->s_state = OP(SEND_ONLY_WITH_IMMEDIATE);
568
569 ohdr->u.imm_data = wqe->wr.ex.imm_data;
570 hwords += 1;
571 } else {
572 qp->s_state = OP(SEND_ONLY_WITH_INVALIDATE);
573
574 ohdr->u.ieth = cpu_to_be32(
575 wqe->wr.ex.invalidate_rkey);
576 hwords += 1;
577 }
578 if (wqe->wr.send_flags & IB_SEND_SOLICITED)
579 bth0 |= IB_BTH_SOLICITED;
580 bth2 |= IB_BTH_REQ_ACK;
581 if (++qp->s_cur == qp->s_size)
582 qp->s_cur = 0;
583 break;
584
585 case IB_WR_RDMA_WRITE:
586 if (newreq && !(qp->s_flags & RVT_S_UNLIMITED_CREDIT))
587 qp->s_lsn++;
588 goto no_flow_control;
589 case IB_WR_RDMA_WRITE_WITH_IMM:
590
591 if (!rvt_rc_credit_avail(qp, wqe))
592 goto bail;
593no_flow_control:
594 put_ib_reth_vaddr(
595 wqe->rdma_wr.remote_addr,
596 &ohdr->u.rc.reth);
597 ohdr->u.rc.reth.rkey =
598 cpu_to_be32(wqe->rdma_wr.rkey);
599 ohdr->u.rc.reth.length = cpu_to_be32(len);
600 hwords += sizeof(struct ib_reth) / sizeof(u32);
601 if (len > pmtu) {
602 qp->s_state = OP(RDMA_WRITE_FIRST);
603 len = pmtu;
604 break;
605 }
606 if (wqe->wr.opcode == IB_WR_RDMA_WRITE) {
607 qp->s_state = OP(RDMA_WRITE_ONLY);
608 } else {
609 qp->s_state =
610 OP(RDMA_WRITE_ONLY_WITH_IMMEDIATE);
611
612 ohdr->u.rc.imm_data = wqe->wr.ex.imm_data;
613 hwords += 1;
614 if (wqe->wr.send_flags & IB_SEND_SOLICITED)
615 bth0 |= IB_BTH_SOLICITED;
616 }
617 bth2 |= IB_BTH_REQ_ACK;
618 if (++qp->s_cur == qp->s_size)
619 qp->s_cur = 0;
620 break;
621
622 case IB_WR_TID_RDMA_WRITE:
623 if (newreq) {
624
625
626
627 if (atomic_read(&priv->n_tid_requests) >=
628 HFI1_TID_RDMA_WRITE_CNT)
629 goto bail;
630
631 if (!(qp->s_flags & RVT_S_UNLIMITED_CREDIT))
632 qp->s_lsn++;
633 }
634
635 hwords += hfi1_build_tid_rdma_write_req(qp, wqe, ohdr,
636 &bth1, &bth2,
637 &len);
638 ss = NULL;
639 if (priv->s_tid_cur == HFI1_QP_WQE_INVALID) {
640 priv->s_tid_cur = qp->s_cur;
641 if (priv->s_tid_tail == HFI1_QP_WQE_INVALID) {
642 priv->s_tid_tail = qp->s_cur;
643 priv->s_state = TID_OP(WRITE_RESP);
644 }
645 } else if (priv->s_tid_cur == priv->s_tid_head) {
646 struct rvt_swqe *__w;
647 struct tid_rdma_request *__r;
648
649 __w = rvt_get_swqe_ptr(qp, priv->s_tid_cur);
650 __r = wqe_to_tid_req(__w);
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672 if (__w->wr.opcode != IB_WR_TID_RDMA_WRITE ||
673 __r->state == TID_REQUEST_INACTIVE ||
674 __r->state == TID_REQUEST_COMPLETE ||
675 ((__r->state == TID_REQUEST_ACTIVE ||
676 __r->state == TID_REQUEST_SYNC) &&
677 __r->comp_seg == __r->total_segs)) {
678 if (priv->s_tid_tail ==
679 priv->s_tid_cur &&
680 priv->s_state ==
681 TID_OP(WRITE_DATA_LAST)) {
682 priv->s_tid_tail = qp->s_cur;
683 priv->s_state =
684 TID_OP(WRITE_RESP);
685 }
686 priv->s_tid_cur = qp->s_cur;
687 }
688
689
690
691
692
693
694
695
696
697
698 if (priv->s_tid_tail == qp->s_cur &&
699 priv->s_state == TID_OP(WRITE_DATA_LAST))
700 priv->s_state = TID_OP(WRITE_RESP);
701 }
702 req = wqe_to_tid_req(wqe);
703 if (newreq) {
704 priv->s_tid_head = qp->s_cur;
705 priv->pending_tid_w_resp += req->total_segs;
706 atomic_inc(&priv->n_tid_requests);
707 atomic_dec(&priv->n_requests);
708 } else {
709 req->state = TID_REQUEST_RESEND;
710 req->comp_seg = delta_psn(bth2, wqe->psn);
711
712
713
714
715 req->setup_head = req->clear_tail;
716 priv->pending_tid_w_resp +=
717 delta_psn(wqe->lpsn, bth2) + 1;
718 }
719
720 trace_hfi1_tid_write_sender_make_req(qp, newreq);
721 trace_hfi1_tid_req_make_req_write(qp, newreq,
722 wqe->wr.opcode,
723 wqe->psn, wqe->lpsn,
724 req);
725 if (++qp->s_cur == qp->s_size)
726 qp->s_cur = 0;
727 break;
728
729 case IB_WR_RDMA_READ:
730
731
732
733
734 if (qp->s_num_rd_atomic >=
735 qp->s_max_rd_atomic) {
736 qp->s_flags |= RVT_S_WAIT_RDMAR;
737 goto bail;
738 }
739 qp->s_num_rd_atomic++;
740 if (newreq && !(qp->s_flags & RVT_S_UNLIMITED_CREDIT))
741 qp->s_lsn++;
742 put_ib_reth_vaddr(
743 wqe->rdma_wr.remote_addr,
744 &ohdr->u.rc.reth);
745 ohdr->u.rc.reth.rkey =
746 cpu_to_be32(wqe->rdma_wr.rkey);
747 ohdr->u.rc.reth.length = cpu_to_be32(len);
748 qp->s_state = OP(RDMA_READ_REQUEST);
749 hwords += sizeof(ohdr->u.rc.reth) / sizeof(u32);
750 ss = NULL;
751 len = 0;
752 bth2 |= IB_BTH_REQ_ACK;
753 if (++qp->s_cur == qp->s_size)
754 qp->s_cur = 0;
755 break;
756
757 case IB_WR_TID_RDMA_READ:
758 trace_hfi1_tid_read_sender_make_req(qp, newreq);
759 wpriv = wqe->priv;
760 req = wqe_to_tid_req(wqe);
761 trace_hfi1_tid_req_make_req_read(qp, newreq,
762 wqe->wr.opcode,
763 wqe->psn, wqe->lpsn,
764 req);
765 delta = cmp_psn(qp->s_psn, wqe->psn);
766
767
768
769
770
771
772
773
774
775
776
777 if (qp->s_num_rd_atomic >= qp->s_max_rd_atomic) {
778 qp->s_flags |= RVT_S_WAIT_RDMAR;
779 goto bail;
780 }
781 if (newreq) {
782 struct tid_rdma_flow *flow =
783 &req->flows[req->setup_head];
784
785
786
787
788
789
790
791 if (!flow->npagesets) {
792 qp->s_sge.sge = wqe->sg_list[0];
793 qp->s_sge.sg_list = wqe->sg_list + 1;
794 qp->s_sge.num_sge = wqe->wr.num_sge;
795 qp->s_sge.total_len = wqe->length;
796 qp->s_len = wqe->length;
797 req->isge = 0;
798 req->clear_tail = req->setup_head;
799 req->flow_idx = req->setup_head;
800 req->state = TID_REQUEST_ACTIVE;
801 }
802 } else if (delta == 0) {
803
804 req->cur_seg = 0;
805 req->comp_seg = 0;
806 req->ack_pending = 0;
807 req->flow_idx = req->clear_tail;
808 req->state = TID_REQUEST_RESEND;
809 }
810 req->s_next_psn = qp->s_psn;
811
812 len = min_t(u32, req->seg_len,
813 wqe->length - req->seg_len * req->cur_seg);
814 delta = hfi1_build_tid_rdma_read_req(qp, wqe, ohdr,
815 &bth1, &bth2,
816 &len);
817 if (delta <= 0) {
818
819 goto bail;
820 }
821 if (newreq && !(qp->s_flags & RVT_S_UNLIMITED_CREDIT))
822 qp->s_lsn++;
823 hwords += delta;
824 ss = &wpriv->ss;
825
826 if (req->cur_seg >= req->total_segs &&
827 ++qp->s_cur == qp->s_size)
828 qp->s_cur = 0;
829 break;
830
831 case IB_WR_ATOMIC_CMP_AND_SWP:
832 case IB_WR_ATOMIC_FETCH_AND_ADD:
833
834
835
836
837 if (qp->s_num_rd_atomic >=
838 qp->s_max_rd_atomic) {
839 qp->s_flags |= RVT_S_WAIT_RDMAR;
840 goto bail;
841 }
842 qp->s_num_rd_atomic++;
843 fallthrough;
844 case IB_WR_OPFN:
845 if (newreq && !(qp->s_flags & RVT_S_UNLIMITED_CREDIT))
846 qp->s_lsn++;
847 if (wqe->wr.opcode == IB_WR_ATOMIC_CMP_AND_SWP ||
848 wqe->wr.opcode == IB_WR_OPFN) {
849 qp->s_state = OP(COMPARE_SWAP);
850 put_ib_ateth_swap(wqe->atomic_wr.swap,
851 &ohdr->u.atomic_eth);
852 put_ib_ateth_compare(wqe->atomic_wr.compare_add,
853 &ohdr->u.atomic_eth);
854 } else {
855 qp->s_state = OP(FETCH_ADD);
856 put_ib_ateth_swap(wqe->atomic_wr.compare_add,
857 &ohdr->u.atomic_eth);
858 put_ib_ateth_compare(0, &ohdr->u.atomic_eth);
859 }
860 put_ib_ateth_vaddr(wqe->atomic_wr.remote_addr,
861 &ohdr->u.atomic_eth);
862 ohdr->u.atomic_eth.rkey = cpu_to_be32(
863 wqe->atomic_wr.rkey);
864 hwords += sizeof(struct ib_atomic_eth) / sizeof(u32);
865 ss = NULL;
866 len = 0;
867 bth2 |= IB_BTH_REQ_ACK;
868 if (++qp->s_cur == qp->s_size)
869 qp->s_cur = 0;
870 break;
871
872 default:
873 goto bail;
874 }
875 if (wqe->wr.opcode != IB_WR_TID_RDMA_READ) {
876 qp->s_sge.sge = wqe->sg_list[0];
877 qp->s_sge.sg_list = wqe->sg_list + 1;
878 qp->s_sge.num_sge = wqe->wr.num_sge;
879 qp->s_sge.total_len = wqe->length;
880 qp->s_len = wqe->length;
881 }
882 if (newreq) {
883 qp->s_tail++;
884 if (qp->s_tail >= qp->s_size)
885 qp->s_tail = 0;
886 }
887 if (wqe->wr.opcode == IB_WR_RDMA_READ ||
888 wqe->wr.opcode == IB_WR_TID_RDMA_WRITE)
889 qp->s_psn = wqe->lpsn + 1;
890 else if (wqe->wr.opcode == IB_WR_TID_RDMA_READ)
891 qp->s_psn = req->s_next_psn;
892 else
893 qp->s_psn++;
894 break;
895
896 case OP(RDMA_READ_RESPONSE_FIRST):
897
898
899
900
901
902
903
904
905
906 qp->s_len = restart_sge(&qp->s_sge, wqe, qp->s_psn, pmtu);
907 fallthrough;
908 case OP(SEND_FIRST):
909 qp->s_state = OP(SEND_MIDDLE);
910 fallthrough;
911 case OP(SEND_MIDDLE):
912 bth2 = mask_psn(qp->s_psn++);
913 ss = &qp->s_sge;
914 len = qp->s_len;
915 if (len > pmtu) {
916 len = pmtu;
917 middle = HFI1_CAP_IS_KSET(SDMA_AHG);
918 break;
919 }
920 if (wqe->wr.opcode == IB_WR_SEND) {
921 qp->s_state = OP(SEND_LAST);
922 } else if (wqe->wr.opcode == IB_WR_SEND_WITH_IMM) {
923 qp->s_state = OP(SEND_LAST_WITH_IMMEDIATE);
924
925 ohdr->u.imm_data = wqe->wr.ex.imm_data;
926 hwords += 1;
927 } else {
928 qp->s_state = OP(SEND_LAST_WITH_INVALIDATE);
929
930 ohdr->u.ieth = cpu_to_be32(wqe->wr.ex.invalidate_rkey);
931 hwords += 1;
932 }
933 if (wqe->wr.send_flags & IB_SEND_SOLICITED)
934 bth0 |= IB_BTH_SOLICITED;
935 bth2 |= IB_BTH_REQ_ACK;
936 qp->s_cur++;
937 if (qp->s_cur >= qp->s_size)
938 qp->s_cur = 0;
939 break;
940
941 case OP(RDMA_READ_RESPONSE_LAST):
942
943
944
945
946
947
948
949
950
951 qp->s_len = restart_sge(&qp->s_sge, wqe, qp->s_psn, pmtu);
952 fallthrough;
953 case OP(RDMA_WRITE_FIRST):
954 qp->s_state = OP(RDMA_WRITE_MIDDLE);
955 fallthrough;
956 case OP(RDMA_WRITE_MIDDLE):
957 bth2 = mask_psn(qp->s_psn++);
958 ss = &qp->s_sge;
959 len = qp->s_len;
960 if (len > pmtu) {
961 len = pmtu;
962 middle = HFI1_CAP_IS_KSET(SDMA_AHG);
963 break;
964 }
965 if (wqe->wr.opcode == IB_WR_RDMA_WRITE) {
966 qp->s_state = OP(RDMA_WRITE_LAST);
967 } else {
968 qp->s_state = OP(RDMA_WRITE_LAST_WITH_IMMEDIATE);
969
970 ohdr->u.imm_data = wqe->wr.ex.imm_data;
971 hwords += 1;
972 if (wqe->wr.send_flags & IB_SEND_SOLICITED)
973 bth0 |= IB_BTH_SOLICITED;
974 }
975 bth2 |= IB_BTH_REQ_ACK;
976 qp->s_cur++;
977 if (qp->s_cur >= qp->s_size)
978 qp->s_cur = 0;
979 break;
980
981 case OP(RDMA_READ_RESPONSE_MIDDLE):
982
983
984
985
986
987
988
989
990
991 len = (delta_psn(qp->s_psn, wqe->psn)) * pmtu;
992 put_ib_reth_vaddr(
993 wqe->rdma_wr.remote_addr + len,
994 &ohdr->u.rc.reth);
995 ohdr->u.rc.reth.rkey =
996 cpu_to_be32(wqe->rdma_wr.rkey);
997 ohdr->u.rc.reth.length = cpu_to_be32(wqe->length - len);
998 qp->s_state = OP(RDMA_READ_REQUEST);
999 hwords += sizeof(ohdr->u.rc.reth) / sizeof(u32);
1000 bth2 = mask_psn(qp->s_psn) | IB_BTH_REQ_ACK;
1001 qp->s_psn = wqe->lpsn + 1;
1002 ss = NULL;
1003 len = 0;
1004 qp->s_cur++;
1005 if (qp->s_cur == qp->s_size)
1006 qp->s_cur = 0;
1007 break;
1008
1009 case TID_OP(WRITE_RESP):
1010
1011
1012
1013
1014
1015 req = wqe_to_tid_req(wqe);
1016 req->state = TID_REQUEST_RESEND;
1017 rcu_read_lock();
1018 remote = rcu_dereference(priv->tid_rdma.remote);
1019 req->comp_seg = delta_psn(qp->s_psn, wqe->psn);
1020 len = wqe->length - (req->comp_seg * remote->max_len);
1021 rcu_read_unlock();
1022
1023 bth2 = mask_psn(qp->s_psn);
1024 hwords += hfi1_build_tid_rdma_write_req(qp, wqe, ohdr, &bth1,
1025 &bth2, &len);
1026 qp->s_psn = wqe->lpsn + 1;
1027 ss = NULL;
1028 qp->s_state = TID_OP(WRITE_REQ);
1029 priv->pending_tid_w_resp += delta_psn(wqe->lpsn, bth2) + 1;
1030 priv->s_tid_cur = qp->s_cur;
1031 if (++qp->s_cur == qp->s_size)
1032 qp->s_cur = 0;
1033 trace_hfi1_tid_req_make_req_write(qp, 0, wqe->wr.opcode,
1034 wqe->psn, wqe->lpsn, req);
1035 break;
1036
1037 case TID_OP(READ_RESP):
1038 if (wqe->wr.opcode != IB_WR_TID_RDMA_READ)
1039 goto bail;
1040
1041 req = wqe_to_tid_req(wqe);
1042 wpriv = wqe->priv;
1043
1044
1045
1046
1047
1048 req->cur_seg = delta_psn(qp->s_psn, wqe->psn) / priv->pkts_ps;
1049
1050
1051
1052
1053
1054
1055
1056 req->state = TID_REQUEST_RESEND;
1057 hfi1_tid_rdma_restart_req(qp, wqe, &bth2);
1058 if (req->state != TID_REQUEST_ACTIVE) {
1059
1060
1061
1062
1063 hfi1_kern_exp_rcv_clear_all(req);
1064 hfi1_kern_clear_hw_flow(priv->rcd, qp);
1065
1066 hfi1_trdma_send_complete(qp, wqe, IB_WC_LOC_QP_OP_ERR);
1067 goto bail;
1068 }
1069 req->state = TID_REQUEST_RESEND;
1070 len = min_t(u32, req->seg_len,
1071 wqe->length - req->seg_len * req->cur_seg);
1072 flow = &req->flows[req->flow_idx];
1073 len -= flow->sent;
1074 req->s_next_psn = flow->flow_state.ib_lpsn + 1;
1075 delta = hfi1_build_tid_rdma_read_packet(wqe, ohdr, &bth1,
1076 &bth2, &len);
1077 if (delta <= 0) {
1078
1079 goto bail;
1080 }
1081 hwords += delta;
1082 ss = &wpriv->ss;
1083
1084 if (req->cur_seg >= req->total_segs &&
1085 ++qp->s_cur == qp->s_size)
1086 qp->s_cur = 0;
1087 qp->s_psn = req->s_next_psn;
1088 trace_hfi1_tid_req_make_req_read(qp, 0, wqe->wr.opcode,
1089 wqe->psn, wqe->lpsn, req);
1090 break;
1091 case TID_OP(READ_REQ):
1092 req = wqe_to_tid_req(wqe);
1093 delta = cmp_psn(qp->s_psn, wqe->psn);
1094
1095
1096
1097
1098
1099 if (wqe->wr.opcode != IB_WR_TID_RDMA_READ || delta == 0 ||
1100 qp->s_cur == qp->s_tail) {
1101 qp->s_state = OP(RDMA_READ_REQUEST);
1102 if (delta == 0 || qp->s_cur == qp->s_tail)
1103 goto check_s_state;
1104 else
1105 goto bail;
1106 }
1107
1108
1109 if (qp->s_num_rd_atomic >= qp->s_max_rd_atomic) {
1110 qp->s_flags |= RVT_S_WAIT_RDMAR;
1111 goto bail;
1112 }
1113
1114 wpriv = wqe->priv;
1115
1116 len = min_t(u32, req->seg_len,
1117 wqe->length - req->seg_len * req->cur_seg);
1118 delta = hfi1_build_tid_rdma_read_req(qp, wqe, ohdr, &bth1,
1119 &bth2, &len);
1120 if (delta <= 0) {
1121
1122 goto bail;
1123 }
1124 hwords += delta;
1125 ss = &wpriv->ss;
1126
1127 if (req->cur_seg >= req->total_segs &&
1128 ++qp->s_cur == qp->s_size)
1129 qp->s_cur = 0;
1130 qp->s_psn = req->s_next_psn;
1131 trace_hfi1_tid_req_make_req_read(qp, 0, wqe->wr.opcode,
1132 wqe->psn, wqe->lpsn, req);
1133 break;
1134 }
1135 qp->s_sending_hpsn = bth2;
1136 delta = delta_psn(bth2, wqe->psn);
1137 if (delta && delta % HFI1_PSN_CREDIT == 0 &&
1138 wqe->wr.opcode != IB_WR_TID_RDMA_WRITE)
1139 bth2 |= IB_BTH_REQ_ACK;
1140 if (qp->s_flags & RVT_S_SEND_ONE) {
1141 qp->s_flags &= ~RVT_S_SEND_ONE;
1142 qp->s_flags |= RVT_S_WAIT_ACK;
1143 bth2 |= IB_BTH_REQ_ACK;
1144 }
1145 qp->s_len -= len;
1146 ps->s_txreq->hdr_dwords = hwords;
1147 ps->s_txreq->sde = priv->s_sde;
1148 ps->s_txreq->ss = ss;
1149 ps->s_txreq->s_cur_size = len;
1150 hfi1_make_ruc_header(
1151 qp,
1152 ohdr,
1153 bth0 | (qp->s_state << 24),
1154 bth1,
1155 bth2,
1156 middle,
1157 ps);
1158 return 1;
1159
1160done_free_tx:
1161 hfi1_put_txreq(ps->s_txreq);
1162 ps->s_txreq = NULL;
1163 return 1;
1164
1165bail:
1166 hfi1_put_txreq(ps->s_txreq);
1167
1168bail_no_tx:
1169 ps->s_txreq = NULL;
1170 qp->s_flags &= ~RVT_S_BUSY;
1171
1172
1173
1174
1175
1176 iowait_set_flag(&priv->s_iowait, IOWAIT_PENDING_IB);
1177 return 0;
1178}
1179
1180static inline void hfi1_make_bth_aeth(struct rvt_qp *qp,
1181 struct ib_other_headers *ohdr,
1182 u32 bth0, u32 bth1)
1183{
1184 if (qp->r_nak_state)
1185 ohdr->u.aeth = cpu_to_be32((qp->r_msn & IB_MSN_MASK) |
1186 (qp->r_nak_state <<
1187 IB_AETH_CREDIT_SHIFT));
1188 else
1189 ohdr->u.aeth = rvt_compute_aeth(qp);
1190
1191 ohdr->bth[0] = cpu_to_be32(bth0);
1192 ohdr->bth[1] = cpu_to_be32(bth1 | qp->remote_qpn);
1193 ohdr->bth[2] = cpu_to_be32(mask_psn(qp->r_ack_psn));
1194}
1195
1196static inline void hfi1_queue_rc_ack(struct hfi1_packet *packet, bool is_fecn)
1197{
1198 struct rvt_qp *qp = packet->qp;
1199 struct hfi1_ibport *ibp;
1200 unsigned long flags;
1201
1202 spin_lock_irqsave(&qp->s_lock, flags);
1203 if (!(ib_rvt_state_ops[qp->state] & RVT_PROCESS_RECV_OK))
1204 goto unlock;
1205 ibp = rcd_to_iport(packet->rcd);
1206 this_cpu_inc(*ibp->rvp.rc_qacks);
1207 qp->s_flags |= RVT_S_ACK_PENDING | RVT_S_RESP_PENDING;
1208 qp->s_nak_state = qp->r_nak_state;
1209 qp->s_ack_psn = qp->r_ack_psn;
1210 if (is_fecn)
1211 qp->s_flags |= RVT_S_ECN;
1212
1213
1214 hfi1_schedule_send(qp);
1215unlock:
1216 spin_unlock_irqrestore(&qp->s_lock, flags);
1217}
1218
1219static inline void hfi1_make_rc_ack_9B(struct hfi1_packet *packet,
1220 struct hfi1_opa_header *opa_hdr,
1221 u8 sc5, bool is_fecn,
1222 u64 *pbc_flags, u32 *hwords,
1223 u32 *nwords)
1224{
1225 struct rvt_qp *qp = packet->qp;
1226 struct hfi1_ibport *ibp = rcd_to_iport(packet->rcd);
1227 struct hfi1_pportdata *ppd = ppd_from_ibp(ibp);
1228 struct ib_header *hdr = &opa_hdr->ibh;
1229 struct ib_other_headers *ohdr;
1230 u16 lrh0 = HFI1_LRH_BTH;
1231 u16 pkey;
1232 u32 bth0, bth1;
1233
1234 opa_hdr->hdr_type = HFI1_PKT_TYPE_9B;
1235 ohdr = &hdr->u.oth;
1236
1237 *hwords = 6;
1238
1239 if (unlikely(rdma_ah_get_ah_flags(&qp->remote_ah_attr) & IB_AH_GRH)) {
1240 *hwords += hfi1_make_grh(ibp, &hdr->u.l.grh,
1241 rdma_ah_read_grh(&qp->remote_ah_attr),
1242 *hwords - 2, SIZE_OF_CRC);
1243 ohdr = &hdr->u.l.oth;
1244 lrh0 = HFI1_LRH_GRH;
1245 }
1246
1247 *pbc_flags |= ((!!(sc5 & 0x10)) << PBC_DC_INFO_SHIFT);
1248
1249
1250 pkey = hfi1_get_pkey(ibp, qp->s_pkey_index);
1251
1252 lrh0 |= (sc5 & IB_SC_MASK) << IB_SC_SHIFT |
1253 (rdma_ah_get_sl(&qp->remote_ah_attr) & IB_SL_MASK) <<
1254 IB_SL_SHIFT;
1255
1256 hfi1_make_ib_hdr(hdr, lrh0, *hwords + SIZE_OF_CRC,
1257 opa_get_lid(rdma_ah_get_dlid(&qp->remote_ah_attr), 9B),
1258 ppd->lid | rdma_ah_get_path_bits(&qp->remote_ah_attr));
1259
1260 bth0 = pkey | (OP(ACKNOWLEDGE) << 24);
1261 if (qp->s_mig_state == IB_MIG_MIGRATED)
1262 bth0 |= IB_BTH_MIG_REQ;
1263 bth1 = (!!is_fecn) << IB_BECN_SHIFT;
1264
1265
1266
1267
1268 bth1 |= HFI1_CAP_IS_KSET(OPFN) << IB_BTHE_E_SHIFT;
1269 hfi1_make_bth_aeth(qp, ohdr, bth0, bth1);
1270}
1271
1272static inline void hfi1_make_rc_ack_16B(struct hfi1_packet *packet,
1273 struct hfi1_opa_header *opa_hdr,
1274 u8 sc5, bool is_fecn,
1275 u64 *pbc_flags, u32 *hwords,
1276 u32 *nwords)
1277{
1278 struct rvt_qp *qp = packet->qp;
1279 struct hfi1_ibport *ibp = rcd_to_iport(packet->rcd);
1280 struct hfi1_pportdata *ppd = ppd_from_ibp(ibp);
1281 struct hfi1_16b_header *hdr = &opa_hdr->opah;
1282 struct ib_other_headers *ohdr;
1283 u32 bth0, bth1 = 0;
1284 u16 len, pkey;
1285 bool becn = is_fecn;
1286 u8 l4 = OPA_16B_L4_IB_LOCAL;
1287 u8 extra_bytes;
1288
1289 opa_hdr->hdr_type = HFI1_PKT_TYPE_16B;
1290 ohdr = &hdr->u.oth;
1291
1292 *hwords = 8;
1293 extra_bytes = hfi1_get_16b_padding(*hwords << 2, 0);
1294 *nwords = SIZE_OF_CRC + ((extra_bytes + SIZE_OF_LT) >> 2);
1295
1296 if (unlikely(rdma_ah_get_ah_flags(&qp->remote_ah_attr) & IB_AH_GRH) &&
1297 hfi1_check_mcast(rdma_ah_get_dlid(&qp->remote_ah_attr))) {
1298 *hwords += hfi1_make_grh(ibp, &hdr->u.l.grh,
1299 rdma_ah_read_grh(&qp->remote_ah_attr),
1300 *hwords - 4, *nwords);
1301 ohdr = &hdr->u.l.oth;
1302 l4 = OPA_16B_L4_IB_GLOBAL;
1303 }
1304 *pbc_flags |= PBC_PACKET_BYPASS | PBC_INSERT_BYPASS_ICRC;
1305
1306
1307 pkey = hfi1_get_pkey(ibp, qp->s_pkey_index);
1308
1309
1310 len = (*hwords + *nwords) >> 1;
1311
1312 hfi1_make_16b_hdr(hdr, ppd->lid |
1313 (rdma_ah_get_path_bits(&qp->remote_ah_attr) &
1314 ((1 << ppd->lmc) - 1)),
1315 opa_get_lid(rdma_ah_get_dlid(&qp->remote_ah_attr),
1316 16B), len, pkey, becn, 0, l4, sc5);
1317
1318 bth0 = pkey | (OP(ACKNOWLEDGE) << 24);
1319 bth0 |= extra_bytes << 20;
1320 if (qp->s_mig_state == IB_MIG_MIGRATED)
1321 bth1 = OPA_BTH_MIG_REQ;
1322 hfi1_make_bth_aeth(qp, ohdr, bth0, bth1);
1323}
1324
1325typedef void (*hfi1_make_rc_ack)(struct hfi1_packet *packet,
1326 struct hfi1_opa_header *opa_hdr,
1327 u8 sc5, bool is_fecn,
1328 u64 *pbc_flags, u32 *hwords,
1329 u32 *nwords);
1330
1331
1332static const hfi1_make_rc_ack hfi1_make_rc_ack_tbl[2] = {
1333 [HFI1_PKT_TYPE_9B] = &hfi1_make_rc_ack_9B,
1334 [HFI1_PKT_TYPE_16B] = &hfi1_make_rc_ack_16B
1335};
1336
1337
1338
1339
1340
1341
1342
1343
1344void hfi1_send_rc_ack(struct hfi1_packet *packet, bool is_fecn)
1345{
1346 struct hfi1_ctxtdata *rcd = packet->rcd;
1347 struct rvt_qp *qp = packet->qp;
1348 struct hfi1_ibport *ibp = rcd_to_iport(rcd);
1349 struct hfi1_qp_priv *priv = qp->priv;
1350 struct hfi1_pportdata *ppd = ppd_from_ibp(ibp);
1351 u8 sc5 = ibp->sl_to_sc[rdma_ah_get_sl(&qp->remote_ah_attr)];
1352 u64 pbc, pbc_flags = 0;
1353 u32 hwords = 0;
1354 u32 nwords = 0;
1355 u32 plen;
1356 struct pio_buf *pbuf;
1357 struct hfi1_opa_header opa_hdr;
1358
1359
1360 qp->r_adefered = 0;
1361
1362
1363 if (qp->s_flags & RVT_S_RESP_PENDING) {
1364 hfi1_queue_rc_ack(packet, is_fecn);
1365 return;
1366 }
1367
1368
1369 if (qp->s_rdma_ack_cnt) {
1370 hfi1_queue_rc_ack(packet, is_fecn);
1371 return;
1372 }
1373
1374
1375 if (driver_lstate(ppd) != IB_PORT_ACTIVE)
1376 return;
1377
1378
1379 hfi1_make_rc_ack_tbl[priv->hdr_type](packet, &opa_hdr, sc5, is_fecn,
1380 &pbc_flags, &hwords, &nwords);
1381
1382 plen = 2 + hwords + nwords;
1383 pbc = create_pbc(ppd, pbc_flags, qp->srate_mbps,
1384 sc_to_vlt(ppd->dd, sc5), plen);
1385 pbuf = sc_buffer_alloc(rcd->sc, plen, NULL, NULL);
1386 if (IS_ERR_OR_NULL(pbuf)) {
1387
1388
1389
1390
1391
1392
1393 hfi1_queue_rc_ack(packet, is_fecn);
1394 return;
1395 }
1396 trace_ack_output_ibhdr(dd_from_ibdev(qp->ibqp.device),
1397 &opa_hdr, ib_is_sc5(sc5));
1398
1399
1400 ppd->dd->pio_inline_send(ppd->dd, pbuf, pbc,
1401 (priv->hdr_type == HFI1_PKT_TYPE_9B ?
1402 (void *)&opa_hdr.ibh :
1403 (void *)&opa_hdr.opah), hwords);
1404 return;
1405}
1406
1407
1408
1409
1410
1411
1412
1413
1414
1415
1416
1417static void update_num_rd_atomic(struct rvt_qp *qp, u32 psn,
1418 struct rvt_swqe *wqe)
1419{
1420 u32 opcode = wqe->wr.opcode;
1421
1422 if (opcode == IB_WR_RDMA_READ ||
1423 opcode == IB_WR_ATOMIC_CMP_AND_SWP ||
1424 opcode == IB_WR_ATOMIC_FETCH_AND_ADD) {
1425 qp->s_num_rd_atomic++;
1426 } else if (opcode == IB_WR_TID_RDMA_READ) {
1427 struct tid_rdma_request *req = wqe_to_tid_req(wqe);
1428 struct hfi1_qp_priv *priv = qp->priv;
1429
1430 if (cmp_psn(psn, wqe->lpsn) <= 0) {
1431 u32 cur_seg;
1432
1433 cur_seg = (psn - wqe->psn) / priv->pkts_ps;
1434 req->ack_pending = cur_seg - req->comp_seg;
1435 priv->pending_tid_r_segs += req->ack_pending;
1436 qp->s_num_rd_atomic += req->ack_pending;
1437 trace_hfi1_tid_req_update_num_rd_atomic(qp, 0,
1438 wqe->wr.opcode,
1439 wqe->psn,
1440 wqe->lpsn,
1441 req);
1442 } else {
1443 priv->pending_tid_r_segs += req->total_segs;
1444 qp->s_num_rd_atomic += req->total_segs;
1445 }
1446 }
1447}
1448
1449
1450
1451
1452
1453
1454
1455
1456
1457
1458static void reset_psn(struct rvt_qp *qp, u32 psn)
1459{
1460 u32 n = qp->s_acked;
1461 struct rvt_swqe *wqe = rvt_get_swqe_ptr(qp, n);
1462 u32 opcode;
1463 struct hfi1_qp_priv *priv = qp->priv;
1464
1465 lockdep_assert_held(&qp->s_lock);
1466 qp->s_cur = n;
1467 priv->pending_tid_r_segs = 0;
1468 priv->pending_tid_w_resp = 0;
1469 qp->s_num_rd_atomic = 0;
1470
1471
1472
1473
1474
1475 if (cmp_psn(psn, wqe->psn) <= 0) {
1476 qp->s_state = OP(SEND_LAST);
1477 goto done;
1478 }
1479 update_num_rd_atomic(qp, psn, wqe);
1480
1481
1482 for (;;) {
1483 int diff;
1484
1485 if (++n == qp->s_size)
1486 n = 0;
1487 if (n == qp->s_tail)
1488 break;
1489 wqe = rvt_get_swqe_ptr(qp, n);
1490 diff = cmp_psn(psn, wqe->psn);
1491 if (diff < 0) {
1492
1493 wqe = rvt_get_swqe_ptr(qp, qp->s_cur);
1494 break;
1495 }
1496 qp->s_cur = n;
1497
1498
1499
1500
1501 if (diff == 0) {
1502 qp->s_state = OP(SEND_LAST);
1503 goto done;
1504 }
1505
1506 update_num_rd_atomic(qp, psn, wqe);
1507 }
1508 opcode = wqe->wr.opcode;
1509
1510
1511
1512
1513
1514
1515 switch (opcode) {
1516 case IB_WR_SEND:
1517 case IB_WR_SEND_WITH_IMM:
1518 qp->s_state = OP(RDMA_READ_RESPONSE_FIRST);
1519 break;
1520
1521 case IB_WR_RDMA_WRITE:
1522 case IB_WR_RDMA_WRITE_WITH_IMM:
1523 qp->s_state = OP(RDMA_READ_RESPONSE_LAST);
1524 break;
1525
1526 case IB_WR_TID_RDMA_WRITE:
1527 qp->s_state = TID_OP(WRITE_RESP);
1528 break;
1529
1530 case IB_WR_RDMA_READ:
1531 qp->s_state = OP(RDMA_READ_RESPONSE_MIDDLE);
1532 break;
1533
1534 case IB_WR_TID_RDMA_READ:
1535 qp->s_state = TID_OP(READ_RESP);
1536 break;
1537
1538 default:
1539
1540
1541
1542
1543 qp->s_state = OP(SEND_LAST);
1544 }
1545done:
1546 priv->s_flags &= ~HFI1_S_TID_WAIT_INTERLCK;
1547 qp->s_psn = psn;
1548
1549
1550
1551
1552
1553 if ((cmp_psn(qp->s_psn, qp->s_sending_hpsn) <= 0) &&
1554 (cmp_psn(qp->s_sending_psn, qp->s_sending_hpsn) <= 0))
1555 qp->s_flags |= RVT_S_WAIT_PSN;
1556 qp->s_flags &= ~HFI1_S_AHG_VALID;
1557 trace_hfi1_sender_reset_psn(qp);
1558}
1559
1560
1561
1562
1563
1564void hfi1_restart_rc(struct rvt_qp *qp, u32 psn, int wait)
1565{
1566 struct hfi1_qp_priv *priv = qp->priv;
1567 struct rvt_swqe *wqe = rvt_get_swqe_ptr(qp, qp->s_acked);
1568 struct hfi1_ibport *ibp;
1569
1570 lockdep_assert_held(&qp->r_lock);
1571 lockdep_assert_held(&qp->s_lock);
1572 trace_hfi1_sender_restart_rc(qp);
1573 if (qp->s_retry == 0) {
1574 if (qp->s_mig_state == IB_MIG_ARMED) {
1575 hfi1_migrate_qp(qp);
1576 qp->s_retry = qp->s_retry_cnt;
1577 } else if (qp->s_last == qp->s_acked) {
1578
1579
1580
1581
1582 if (wqe->wr.opcode == IB_WR_OPFN) {
1583 struct hfi1_ibport *ibp =
1584 to_iport(qp->ibqp.device, qp->port_num);
1585
1586
1587
1588
1589
1590 opfn_conn_reply(qp, priv->opfn.curr);
1591 wqe = do_rc_completion(qp, wqe, ibp);
1592 qp->s_flags &= ~RVT_S_WAIT_ACK;
1593 } else {
1594 trace_hfi1_tid_write_sender_restart_rc(qp, 0);
1595 if (wqe->wr.opcode == IB_WR_TID_RDMA_READ) {
1596 struct tid_rdma_request *req;
1597
1598 req = wqe_to_tid_req(wqe);
1599 hfi1_kern_exp_rcv_clear_all(req);
1600 hfi1_kern_clear_hw_flow(priv->rcd, qp);
1601 }
1602
1603 hfi1_trdma_send_complete(qp, wqe,
1604 IB_WC_RETRY_EXC_ERR);
1605 rvt_error_qp(qp, IB_WC_WR_FLUSH_ERR);
1606 }
1607 return;
1608 } else {
1609 return;
1610 }
1611 } else {
1612 qp->s_retry--;
1613 }
1614
1615 ibp = to_iport(qp->ibqp.device, qp->port_num);
1616 if (wqe->wr.opcode == IB_WR_RDMA_READ ||
1617 wqe->wr.opcode == IB_WR_TID_RDMA_READ)
1618 ibp->rvp.n_rc_resends++;
1619 else
1620 ibp->rvp.n_rc_resends += delta_psn(qp->s_psn, psn);
1621
1622 qp->s_flags &= ~(RVT_S_WAIT_FENCE | RVT_S_WAIT_RDMAR |
1623 RVT_S_WAIT_SSN_CREDIT | RVT_S_WAIT_PSN |
1624 RVT_S_WAIT_ACK | HFI1_S_WAIT_TID_RESP);
1625 if (wait)
1626 qp->s_flags |= RVT_S_SEND_ONE;
1627 reset_psn(qp, psn);
1628}
1629
1630
1631
1632
1633
1634
1635static void reset_sending_psn(struct rvt_qp *qp, u32 psn)
1636{
1637 struct rvt_swqe *wqe;
1638 u32 n = qp->s_last;
1639
1640 lockdep_assert_held(&qp->s_lock);
1641
1642 for (;;) {
1643 wqe = rvt_get_swqe_ptr(qp, n);
1644 if (cmp_psn(psn, wqe->lpsn) <= 0) {
1645 if (wqe->wr.opcode == IB_WR_RDMA_READ ||
1646 wqe->wr.opcode == IB_WR_TID_RDMA_READ ||
1647 wqe->wr.opcode == IB_WR_TID_RDMA_WRITE)
1648 qp->s_sending_psn = wqe->lpsn + 1;
1649 else
1650 qp->s_sending_psn = psn + 1;
1651 break;
1652 }
1653 if (++n == qp->s_size)
1654 n = 0;
1655 if (n == qp->s_tail)
1656 break;
1657 }
1658}
1659
1660
1661
1662
1663
1664
1665
1666
1667
1668
1669
1670
1671
1672void hfi1_rc_verbs_aborted(struct rvt_qp *qp, struct hfi1_opa_header *opah)
1673{
1674 struct ib_other_headers *ohdr = hfi1_get_rc_ohdr(opah);
1675 u8 opcode = ib_bth_get_opcode(ohdr);
1676 u32 psn;
1677
1678
1679 if ((opcode >= OP(RDMA_READ_RESPONSE_FIRST) &&
1680 opcode <= OP(ATOMIC_ACKNOWLEDGE)) ||
1681 opcode == TID_OP(READ_RESP) ||
1682 opcode == TID_OP(WRITE_RESP))
1683 return;
1684
1685 psn = ib_bth_get_psn(ohdr) | IB_BTH_REQ_ACK;
1686 ohdr->bth[2] = cpu_to_be32(psn);
1687 qp->s_flags |= RVT_S_SEND_ONE;
1688}
1689
1690
1691
1692
1693void hfi1_rc_send_complete(struct rvt_qp *qp, struct hfi1_opa_header *opah)
1694{
1695 struct ib_other_headers *ohdr;
1696 struct hfi1_qp_priv *priv = qp->priv;
1697 struct rvt_swqe *wqe;
1698 u32 opcode, head, tail;
1699 u32 psn;
1700 struct tid_rdma_request *req;
1701
1702 lockdep_assert_held(&qp->s_lock);
1703 if (!(ib_rvt_state_ops[qp->state] & RVT_SEND_OR_FLUSH_OR_RECV_OK))
1704 return;
1705
1706 ohdr = hfi1_get_rc_ohdr(opah);
1707 opcode = ib_bth_get_opcode(ohdr);
1708 if ((opcode >= OP(RDMA_READ_RESPONSE_FIRST) &&
1709 opcode <= OP(ATOMIC_ACKNOWLEDGE)) ||
1710 opcode == TID_OP(READ_RESP) ||
1711 opcode == TID_OP(WRITE_RESP)) {
1712 WARN_ON(!qp->s_rdma_ack_cnt);
1713 qp->s_rdma_ack_cnt--;
1714 return;
1715 }
1716
1717 psn = ib_bth_get_psn(ohdr);
1718
1719
1720
1721
1722 if (opcode != TID_OP(WRITE_DATA) &&
1723 opcode != TID_OP(WRITE_DATA_LAST) &&
1724 opcode != TID_OP(ACK) && opcode != TID_OP(RESYNC))
1725 reset_sending_psn(qp, psn);
1726
1727
1728 if (opcode >= TID_OP(WRITE_REQ) &&
1729 opcode <= TID_OP(WRITE_DATA_LAST)) {
1730 head = priv->s_tid_head;
1731 tail = priv->s_tid_cur;
1732
1733
1734
1735
1736
1737
1738
1739
1740 wqe = rvt_get_swqe_ptr(qp, tail);
1741 req = wqe_to_tid_req(wqe);
1742 if (head == tail && req->comp_seg < req->total_segs) {
1743 if (tail == 0)
1744 tail = qp->s_size - 1;
1745 else
1746 tail -= 1;
1747 }
1748 } else {
1749 head = qp->s_tail;
1750 tail = qp->s_acked;
1751 }
1752
1753
1754
1755
1756
1757 if ((psn & IB_BTH_REQ_ACK) && tail != head &&
1758 opcode != TID_OP(WRITE_DATA) && opcode != TID_OP(WRITE_DATA_LAST) &&
1759 opcode != TID_OP(RESYNC) &&
1760 !(qp->s_flags &
1761 (RVT_S_TIMER | RVT_S_WAIT_RNR | RVT_S_WAIT_PSN)) &&
1762 (ib_rvt_state_ops[qp->state] & RVT_PROCESS_RECV_OK)) {
1763 if (opcode == TID_OP(READ_REQ))
1764 rvt_add_retry_timer_ext(qp, priv->timeout_shift);
1765 else
1766 rvt_add_retry_timer(qp);
1767 }
1768
1769
1770 if ((opcode == TID_OP(WRITE_DATA) ||
1771 opcode == TID_OP(WRITE_DATA_LAST) ||
1772 opcode == TID_OP(RESYNC)) &&
1773 (psn & IB_BTH_REQ_ACK) &&
1774 !(priv->s_flags & HFI1_S_TID_RETRY_TIMER) &&
1775 (ib_rvt_state_ops[qp->state] & RVT_PROCESS_RECV_OK)) {
1776
1777
1778
1779
1780
1781 wqe = rvt_get_swqe_ptr(qp, qp->s_acked);
1782 req = wqe_to_tid_req(wqe);
1783 if (wqe->wr.opcode == IB_WR_TID_RDMA_WRITE &&
1784 req->ack_seg < req->cur_seg)
1785 hfi1_add_tid_retry_timer(qp);
1786 }
1787
1788 while (qp->s_last != qp->s_acked) {
1789 wqe = rvt_get_swqe_ptr(qp, qp->s_last);
1790 if (cmp_psn(wqe->lpsn, qp->s_sending_psn) >= 0 &&
1791 cmp_psn(qp->s_sending_psn, qp->s_sending_hpsn) <= 0)
1792 break;
1793 trdma_clean_swqe(qp, wqe);
1794 trace_hfi1_qp_send_completion(qp, wqe, qp->s_last);
1795 rvt_qp_complete_swqe(qp,
1796 wqe,
1797 ib_hfi1_wc_opcode[wqe->wr.opcode],
1798 IB_WC_SUCCESS);
1799 }
1800
1801
1802
1803
1804 trace_hfi1_sendcomplete(qp, psn);
1805 if (qp->s_flags & RVT_S_WAIT_PSN &&
1806 cmp_psn(qp->s_sending_psn, qp->s_sending_hpsn) > 0) {
1807 qp->s_flags &= ~RVT_S_WAIT_PSN;
1808 qp->s_sending_psn = qp->s_psn;
1809 qp->s_sending_hpsn = qp->s_psn - 1;
1810 hfi1_schedule_send(qp);
1811 }
1812}
1813
1814static inline void update_last_psn(struct rvt_qp *qp, u32 psn)
1815{
1816 qp->s_last_psn = psn;
1817}
1818
1819
1820
1821
1822
1823
1824struct rvt_swqe *do_rc_completion(struct rvt_qp *qp,
1825 struct rvt_swqe *wqe,
1826 struct hfi1_ibport *ibp)
1827{
1828 struct hfi1_qp_priv *priv = qp->priv;
1829
1830 lockdep_assert_held(&qp->s_lock);
1831
1832
1833
1834
1835
1836 trace_hfi1_rc_completion(qp, wqe->lpsn);
1837 if (cmp_psn(wqe->lpsn, qp->s_sending_psn) < 0 ||
1838 cmp_psn(qp->s_sending_psn, qp->s_sending_hpsn) > 0) {
1839 trdma_clean_swqe(qp, wqe);
1840 trace_hfi1_qp_send_completion(qp, wqe, qp->s_last);
1841 rvt_qp_complete_swqe(qp,
1842 wqe,
1843 ib_hfi1_wc_opcode[wqe->wr.opcode],
1844 IB_WC_SUCCESS);
1845 } else {
1846 struct hfi1_pportdata *ppd = ppd_from_ibp(ibp);
1847
1848 this_cpu_inc(*ibp->rvp.rc_delayed_comp);
1849
1850
1851
1852
1853 if (ppd->dd->flags & HFI1_HAS_SEND_DMA) {
1854 struct sdma_engine *engine;
1855 u8 sl = rdma_ah_get_sl(&qp->remote_ah_attr);
1856 u8 sc5;
1857
1858
1859 sc5 = ibp->sl_to_sc[sl];
1860 engine = qp_to_sdma_engine(qp, sc5);
1861 sdma_engine_progress_schedule(engine);
1862 }
1863 }
1864
1865 qp->s_retry = qp->s_retry_cnt;
1866
1867
1868
1869
1870
1871
1872
1873
1874 if (wqe->wr.opcode != IB_WR_TID_RDMA_WRITE)
1875 update_last_psn(qp, wqe->lpsn);
1876
1877
1878
1879
1880
1881
1882 if (qp->s_acked == qp->s_cur) {
1883 if (++qp->s_cur >= qp->s_size)
1884 qp->s_cur = 0;
1885 qp->s_acked = qp->s_cur;
1886 wqe = rvt_get_swqe_ptr(qp, qp->s_cur);
1887 if (qp->s_acked != qp->s_tail) {
1888 qp->s_state = OP(SEND_LAST);
1889 qp->s_psn = wqe->psn;
1890 }
1891 } else {
1892 if (++qp->s_acked >= qp->s_size)
1893 qp->s_acked = 0;
1894 if (qp->state == IB_QPS_SQD && qp->s_acked == qp->s_cur)
1895 qp->s_draining = 0;
1896 wqe = rvt_get_swqe_ptr(qp, qp->s_acked);
1897 }
1898 if (priv->s_flags & HFI1_S_TID_WAIT_INTERLCK) {
1899 priv->s_flags &= ~HFI1_S_TID_WAIT_INTERLCK;
1900 hfi1_schedule_send(qp);
1901 }
1902 return wqe;
1903}
1904
1905static void set_restart_qp(struct rvt_qp *qp, struct hfi1_ctxtdata *rcd)
1906{
1907
1908 if (!(qp->r_flags & RVT_R_RDMAR_SEQ)) {
1909 qp->r_flags |= RVT_R_RDMAR_SEQ;
1910 hfi1_restart_rc(qp, qp->s_last_psn + 1, 0);
1911 if (list_empty(&qp->rspwait)) {
1912 qp->r_flags |= RVT_R_RSP_SEND;
1913 rvt_get_qp(qp);
1914 list_add_tail(&qp->rspwait, &rcd->qp_wait_list);
1915 }
1916 }
1917}
1918
1919
1920
1921
1922
1923
1924
1925
1926
1927
1928
1929
1930static void update_qp_retry_state(struct rvt_qp *qp, u32 psn, u32 spsn,
1931 u32 lpsn)
1932{
1933 struct hfi1_qp_priv *qpriv = qp->priv;
1934
1935 qp->s_psn = psn + 1;
1936
1937
1938
1939
1940
1941
1942 if (cmp_psn(psn, lpsn) >= 0) {
1943 qp->s_cur = qpriv->s_tid_cur + 1;
1944 if (qp->s_cur >= qp->s_size)
1945 qp->s_cur = 0;
1946 qp->s_state = TID_OP(WRITE_REQ);
1947 } else if (!cmp_psn(psn, spsn)) {
1948 qp->s_cur = qpriv->s_tid_cur;
1949 qp->s_state = TID_OP(WRITE_RESP);
1950 }
1951}
1952
1953
1954
1955
1956
1957
1958
1959
1960
1961
1962
1963
1964int do_rc_ack(struct rvt_qp *qp, u32 aeth, u32 psn, int opcode,
1965 u64 val, struct hfi1_ctxtdata *rcd)
1966{
1967 struct hfi1_ibport *ibp;
1968 enum ib_wc_status status;
1969 struct hfi1_qp_priv *qpriv = qp->priv;
1970 struct rvt_swqe *wqe;
1971 int ret = 0;
1972 u32 ack_psn;
1973 int diff;
1974 struct rvt_dev_info *rdi;
1975
1976 lockdep_assert_held(&qp->s_lock);
1977
1978
1979
1980
1981
1982
1983 ack_psn = psn;
1984 if (aeth >> IB_AETH_NAK_SHIFT)
1985 ack_psn--;
1986 wqe = rvt_get_swqe_ptr(qp, qp->s_acked);
1987 ibp = rcd_to_iport(rcd);
1988
1989
1990
1991
1992
1993 while ((diff = delta_psn(ack_psn, wqe->lpsn)) >= 0) {
1994
1995
1996
1997
1998
1999
2000 if (wqe->wr.opcode == IB_WR_RDMA_READ &&
2001 opcode == OP(RDMA_READ_RESPONSE_ONLY) &&
2002 diff == 0) {
2003 ret = 1;
2004 goto bail_stop;
2005 }
2006
2007
2008
2009
2010
2011
2012
2013
2014
2015 if ((wqe->wr.opcode == IB_WR_RDMA_READ &&
2016 (opcode != OP(RDMA_READ_RESPONSE_LAST) || diff != 0)) ||
2017 (wqe->wr.opcode == IB_WR_TID_RDMA_READ &&
2018 (opcode != TID_OP(READ_RESP) || diff != 0)) ||
2019 ((wqe->wr.opcode == IB_WR_ATOMIC_CMP_AND_SWP ||
2020 wqe->wr.opcode == IB_WR_ATOMIC_FETCH_AND_ADD) &&
2021 (opcode != OP(ATOMIC_ACKNOWLEDGE) || diff != 0)) ||
2022 (wqe->wr.opcode == IB_WR_TID_RDMA_WRITE &&
2023 (delta_psn(psn, qp->s_last_psn) != 1))) {
2024 set_restart_qp(qp, rcd);
2025
2026
2027
2028
2029 goto bail_stop;
2030 }
2031 if (wqe->wr.opcode == IB_WR_ATOMIC_CMP_AND_SWP ||
2032 wqe->wr.opcode == IB_WR_ATOMIC_FETCH_AND_ADD) {
2033 u64 *vaddr = wqe->sg_list[0].vaddr;
2034 *vaddr = val;
2035 }
2036 if (wqe->wr.opcode == IB_WR_OPFN)
2037 opfn_conn_reply(qp, val);
2038
2039 if (qp->s_num_rd_atomic &&
2040 (wqe->wr.opcode == IB_WR_RDMA_READ ||
2041 wqe->wr.opcode == IB_WR_ATOMIC_CMP_AND_SWP ||
2042 wqe->wr.opcode == IB_WR_ATOMIC_FETCH_AND_ADD)) {
2043 qp->s_num_rd_atomic--;
2044
2045 if ((qp->s_flags & RVT_S_WAIT_FENCE) &&
2046 !qp->s_num_rd_atomic) {
2047 qp->s_flags &= ~(RVT_S_WAIT_FENCE |
2048 RVT_S_WAIT_ACK);
2049 hfi1_schedule_send(qp);
2050 } else if (qp->s_flags & RVT_S_WAIT_RDMAR) {
2051 qp->s_flags &= ~(RVT_S_WAIT_RDMAR |
2052 RVT_S_WAIT_ACK);
2053 hfi1_schedule_send(qp);
2054 }
2055 }
2056
2057
2058
2059
2060
2061 if (wqe->wr.opcode == IB_WR_TID_RDMA_WRITE)
2062 break;
2063
2064 wqe = do_rc_completion(qp, wqe, ibp);
2065 if (qp->s_acked == qp->s_tail)
2066 break;
2067 }
2068
2069 trace_hfi1_rc_ack_do(qp, aeth, psn, wqe);
2070 trace_hfi1_sender_do_rc_ack(qp);
2071 switch (aeth >> IB_AETH_NAK_SHIFT) {
2072 case 0:
2073 this_cpu_inc(*ibp->rvp.rc_acks);
2074 if (wqe->wr.opcode == IB_WR_TID_RDMA_READ) {
2075 if (wqe_to_tid_req(wqe)->ack_pending)
2076 rvt_mod_retry_timer_ext(qp,
2077 qpriv->timeout_shift);
2078 else
2079 rvt_stop_rc_timers(qp);
2080 } else if (qp->s_acked != qp->s_tail) {
2081 struct rvt_swqe *__w = NULL;
2082
2083 if (qpriv->s_tid_cur != HFI1_QP_WQE_INVALID)
2084 __w = rvt_get_swqe_ptr(qp, qpriv->s_tid_cur);
2085
2086
2087
2088
2089
2090 if (__w && __w->wr.opcode == IB_WR_TID_RDMA_WRITE &&
2091 opcode == TID_OP(WRITE_RESP)) {
2092
2093
2094
2095
2096
2097
2098
2099
2100
2101
2102
2103
2104 if (cmp_psn(psn, qp->s_last_psn + 1)) {
2105 set_restart_qp(qp, rcd);
2106 goto bail_stop;
2107 }
2108
2109
2110
2111
2112 if (qp->s_cur != qp->s_tail &&
2113 cmp_psn(qp->s_psn, psn) <= 0)
2114 update_qp_retry_state(qp, psn,
2115 __w->psn,
2116 __w->lpsn);
2117 else if (--qpriv->pending_tid_w_resp)
2118 rvt_mod_retry_timer(qp);
2119 else
2120 rvt_stop_rc_timers(qp);
2121 } else {
2122
2123
2124
2125
2126 rvt_mod_retry_timer(qp);
2127
2128
2129
2130
2131
2132 if (cmp_psn(qp->s_psn, psn) <= 0)
2133 reset_psn(qp, psn + 1);
2134 }
2135 } else {
2136
2137 rvt_stop_rc_timers(qp);
2138 if (cmp_psn(qp->s_psn, psn) <= 0) {
2139 qp->s_state = OP(SEND_LAST);
2140 qp->s_psn = psn + 1;
2141 }
2142 }
2143 if (qp->s_flags & RVT_S_WAIT_ACK) {
2144 qp->s_flags &= ~RVT_S_WAIT_ACK;
2145 hfi1_schedule_send(qp);
2146 }
2147 rvt_get_credit(qp, aeth);
2148 qp->s_rnr_retry = qp->s_rnr_retry_cnt;
2149 qp->s_retry = qp->s_retry_cnt;
2150
2151
2152
2153
2154
2155 if (wqe->wr.opcode == IB_WR_TID_RDMA_WRITE &&
2156 opcode != TID_OP(WRITE_RESP) &&
2157 cmp_psn(psn, wqe->psn) >= 0)
2158 return 1;
2159 update_last_psn(qp, psn);
2160 return 1;
2161
2162 case 1:
2163 ibp->rvp.n_rnr_naks++;
2164 if (qp->s_acked == qp->s_tail)
2165 goto bail_stop;
2166 if (qp->s_flags & RVT_S_WAIT_RNR)
2167 goto bail_stop;
2168 rdi = ib_to_rvt(qp->ibqp.device);
2169 if (!(rdi->post_parms[wqe->wr.opcode].flags &
2170 RVT_OPERATION_IGN_RNR_CNT)) {
2171 if (qp->s_rnr_retry == 0) {
2172 status = IB_WC_RNR_RETRY_EXC_ERR;
2173 goto class_b;
2174 }
2175 if (qp->s_rnr_retry_cnt < 7 && qp->s_rnr_retry_cnt > 0)
2176 qp->s_rnr_retry--;
2177 }
2178
2179
2180
2181
2182
2183
2184
2185 if (wqe->wr.opcode == IB_WR_TID_RDMA_WRITE) {
2186 reset_psn(qp, qp->s_last_psn + 1);
2187 } else {
2188 update_last_psn(qp, psn - 1);
2189 reset_psn(qp, psn);
2190 }
2191
2192 ibp->rvp.n_rc_resends += delta_psn(qp->s_psn, psn);
2193 qp->s_flags &= ~(RVT_S_WAIT_SSN_CREDIT | RVT_S_WAIT_ACK);
2194 rvt_stop_rc_timers(qp);
2195 rvt_add_rnr_timer(qp, aeth);
2196 return 0;
2197
2198 case 3:
2199 if (qp->s_acked == qp->s_tail)
2200 goto bail_stop;
2201
2202 update_last_psn(qp, psn - 1);
2203 switch ((aeth >> IB_AETH_CREDIT_SHIFT) &
2204 IB_AETH_CREDIT_MASK) {
2205 case 0:
2206 ibp->rvp.n_seq_naks++;
2207
2208
2209
2210
2211
2212
2213 hfi1_restart_rc(qp, psn, 0);
2214 hfi1_schedule_send(qp);
2215 break;
2216
2217 case 1:
2218 status = IB_WC_REM_INV_REQ_ERR;
2219 ibp->rvp.n_other_naks++;
2220 goto class_b;
2221
2222 case 2:
2223 status = IB_WC_REM_ACCESS_ERR;
2224 ibp->rvp.n_other_naks++;
2225 goto class_b;
2226
2227 case 3:
2228 status = IB_WC_REM_OP_ERR;
2229 ibp->rvp.n_other_naks++;
2230class_b:
2231 if (qp->s_last == qp->s_acked) {
2232 if (wqe->wr.opcode == IB_WR_TID_RDMA_READ)
2233 hfi1_kern_read_tid_flow_free(qp);
2234
2235 hfi1_trdma_send_complete(qp, wqe, status);
2236 rvt_error_qp(qp, IB_WC_WR_FLUSH_ERR);
2237 }
2238 break;
2239
2240 default:
2241
2242 goto reserved;
2243 }
2244 qp->s_retry = qp->s_retry_cnt;
2245 qp->s_rnr_retry = qp->s_rnr_retry_cnt;
2246 goto bail_stop;
2247
2248 default:
2249reserved:
2250
2251 goto bail_stop;
2252 }
2253
2254bail_stop:
2255 rvt_stop_rc_timers(qp);
2256 return ret;
2257}
2258
2259
2260
2261
2262
2263static void rdma_seq_err(struct rvt_qp *qp, struct hfi1_ibport *ibp, u32 psn,
2264 struct hfi1_ctxtdata *rcd)
2265{
2266 struct rvt_swqe *wqe;
2267
2268 lockdep_assert_held(&qp->s_lock);
2269
2270 rvt_stop_rc_timers(qp);
2271
2272 wqe = rvt_get_swqe_ptr(qp, qp->s_acked);
2273
2274 while (cmp_psn(psn, wqe->lpsn) > 0) {
2275 if (wqe->wr.opcode == IB_WR_RDMA_READ ||
2276 wqe->wr.opcode == IB_WR_TID_RDMA_READ ||
2277 wqe->wr.opcode == IB_WR_TID_RDMA_WRITE ||
2278 wqe->wr.opcode == IB_WR_ATOMIC_CMP_AND_SWP ||
2279 wqe->wr.opcode == IB_WR_ATOMIC_FETCH_AND_ADD)
2280 break;
2281 wqe = do_rc_completion(qp, wqe, ibp);
2282 }
2283
2284 ibp->rvp.n_rdma_seq++;
2285 qp->r_flags |= RVT_R_RDMAR_SEQ;
2286 hfi1_restart_rc(qp, qp->s_last_psn + 1, 0);
2287 if (list_empty(&qp->rspwait)) {
2288 qp->r_flags |= RVT_R_RSP_SEND;
2289 rvt_get_qp(qp);
2290 list_add_tail(&qp->rspwait, &rcd->qp_wait_list);
2291 }
2292}
2293
2294
2295
2296
2297
2298
2299
2300
2301
2302static void rc_rcv_resp(struct hfi1_packet *packet)
2303{
2304 struct hfi1_ctxtdata *rcd = packet->rcd;
2305 void *data = packet->payload;
2306 u32 tlen = packet->tlen;
2307 struct rvt_qp *qp = packet->qp;
2308 struct hfi1_ibport *ibp;
2309 struct ib_other_headers *ohdr = packet->ohdr;
2310 struct rvt_swqe *wqe;
2311 enum ib_wc_status status;
2312 unsigned long flags;
2313 int diff;
2314 u64 val;
2315 u32 aeth;
2316 u32 psn = ib_bth_get_psn(packet->ohdr);
2317 u32 pmtu = qp->pmtu;
2318 u16 hdrsize = packet->hlen;
2319 u8 opcode = packet->opcode;
2320 u8 pad = packet->pad;
2321 u8 extra_bytes = pad + packet->extra_byte + (SIZE_OF_CRC << 2);
2322
2323 spin_lock_irqsave(&qp->s_lock, flags);
2324 trace_hfi1_ack(qp, psn);
2325
2326
2327 if (cmp_psn(psn, READ_ONCE(qp->s_next_psn)) >= 0)
2328 goto ack_done;
2329
2330
2331 diff = cmp_psn(psn, qp->s_last_psn);
2332 if (unlikely(diff <= 0)) {
2333
2334 if (diff == 0 && opcode == OP(ACKNOWLEDGE)) {
2335 aeth = be32_to_cpu(ohdr->u.aeth);
2336 if ((aeth >> IB_AETH_NAK_SHIFT) == 0)
2337 rvt_get_credit(qp, aeth);
2338 }
2339 goto ack_done;
2340 }
2341
2342
2343
2344
2345
2346 if (qp->r_flags & RVT_R_RDMAR_SEQ) {
2347 if (cmp_psn(psn, qp->s_last_psn + 1) != 0)
2348 goto ack_done;
2349 qp->r_flags &= ~RVT_R_RDMAR_SEQ;
2350 }
2351
2352 if (unlikely(qp->s_acked == qp->s_tail))
2353 goto ack_done;
2354 wqe = rvt_get_swqe_ptr(qp, qp->s_acked);
2355 status = IB_WC_SUCCESS;
2356
2357 switch (opcode) {
2358 case OP(ACKNOWLEDGE):
2359 case OP(ATOMIC_ACKNOWLEDGE):
2360 case OP(RDMA_READ_RESPONSE_FIRST):
2361 aeth = be32_to_cpu(ohdr->u.aeth);
2362 if (opcode == OP(ATOMIC_ACKNOWLEDGE))
2363 val = ib_u64_get(&ohdr->u.at.atomic_ack_eth);
2364 else
2365 val = 0;
2366 if (!do_rc_ack(qp, aeth, psn, opcode, val, rcd) ||
2367 opcode != OP(RDMA_READ_RESPONSE_FIRST))
2368 goto ack_done;
2369 wqe = rvt_get_swqe_ptr(qp, qp->s_acked);
2370 if (unlikely(wqe->wr.opcode != IB_WR_RDMA_READ))
2371 goto ack_op_err;
2372
2373
2374
2375
2376
2377 qp->s_rdma_read_len = restart_sge(&qp->s_rdma_read_sge,
2378 wqe, psn, pmtu);
2379 goto read_middle;
2380
2381 case OP(RDMA_READ_RESPONSE_MIDDLE):
2382
2383 if (unlikely(cmp_psn(psn, qp->s_last_psn + 1)))
2384 goto ack_seq_err;
2385 if (unlikely(wqe->wr.opcode != IB_WR_RDMA_READ))
2386 goto ack_op_err;
2387read_middle:
2388 if (unlikely(tlen != (hdrsize + pmtu + extra_bytes)))
2389 goto ack_len_err;
2390 if (unlikely(pmtu >= qp->s_rdma_read_len))
2391 goto ack_len_err;
2392
2393
2394
2395
2396
2397 rvt_mod_retry_timer(qp);
2398 if (qp->s_flags & RVT_S_WAIT_ACK) {
2399 qp->s_flags &= ~RVT_S_WAIT_ACK;
2400 hfi1_schedule_send(qp);
2401 }
2402
2403 if (opcode == OP(RDMA_READ_RESPONSE_MIDDLE))
2404 qp->s_retry = qp->s_retry_cnt;
2405
2406
2407
2408
2409
2410 qp->s_rdma_read_len -= pmtu;
2411 update_last_psn(qp, psn);
2412 spin_unlock_irqrestore(&qp->s_lock, flags);
2413 rvt_copy_sge(qp, &qp->s_rdma_read_sge,
2414 data, pmtu, false, false);
2415 goto bail;
2416
2417 case OP(RDMA_READ_RESPONSE_ONLY):
2418 aeth = be32_to_cpu(ohdr->u.aeth);
2419 if (!do_rc_ack(qp, aeth, psn, opcode, 0, rcd))
2420 goto ack_done;
2421
2422
2423
2424
2425 if (unlikely(tlen < (hdrsize + extra_bytes)))
2426 goto ack_len_err;
2427
2428
2429
2430
2431
2432 wqe = rvt_get_swqe_ptr(qp, qp->s_acked);
2433 qp->s_rdma_read_len = restart_sge(&qp->s_rdma_read_sge,
2434 wqe, psn, pmtu);
2435 goto read_last;
2436
2437 case OP(RDMA_READ_RESPONSE_LAST):
2438
2439 if (unlikely(cmp_psn(psn, qp->s_last_psn + 1)))
2440 goto ack_seq_err;
2441 if (unlikely(wqe->wr.opcode != IB_WR_RDMA_READ))
2442 goto ack_op_err;
2443
2444
2445
2446
2447 if (unlikely(tlen <= (hdrsize + extra_bytes)))
2448 goto ack_len_err;
2449read_last:
2450 tlen -= hdrsize + extra_bytes;
2451 if (unlikely(tlen != qp->s_rdma_read_len))
2452 goto ack_len_err;
2453 aeth = be32_to_cpu(ohdr->u.aeth);
2454 rvt_copy_sge(qp, &qp->s_rdma_read_sge,
2455 data, tlen, false, false);
2456 WARN_ON(qp->s_rdma_read_sge.num_sge);
2457 (void)do_rc_ack(qp, aeth, psn,
2458 OP(RDMA_READ_RESPONSE_LAST), 0, rcd);
2459 goto ack_done;
2460 }
2461
2462ack_op_err:
2463 status = IB_WC_LOC_QP_OP_ERR;
2464 goto ack_err;
2465
2466ack_seq_err:
2467 ibp = rcd_to_iport(rcd);
2468 rdma_seq_err(qp, ibp, psn, rcd);
2469 goto ack_done;
2470
2471ack_len_err:
2472 status = IB_WC_LOC_LEN_ERR;
2473ack_err:
2474 if (qp->s_last == qp->s_acked) {
2475 rvt_send_complete(qp, wqe, status);
2476 rvt_error_qp(qp, IB_WC_WR_FLUSH_ERR);
2477 }
2478ack_done:
2479 spin_unlock_irqrestore(&qp->s_lock, flags);
2480bail:
2481 return;
2482}
2483
2484static inline void rc_cancel_ack(struct rvt_qp *qp)
2485{
2486 qp->r_adefered = 0;
2487 if (list_empty(&qp->rspwait))
2488 return;
2489 list_del_init(&qp->rspwait);
2490 qp->r_flags &= ~RVT_R_RSP_NAK;
2491 rvt_put_qp(qp);
2492}
2493
2494
2495
2496
2497
2498
2499
2500
2501
2502
2503
2504
2505
2506
2507
2508
2509
2510static noinline int rc_rcv_error(struct ib_other_headers *ohdr, void *data,
2511 struct rvt_qp *qp, u32 opcode, u32 psn,
2512 int diff, struct hfi1_ctxtdata *rcd)
2513{
2514 struct hfi1_ibport *ibp = rcd_to_iport(rcd);
2515 struct rvt_ack_entry *e;
2516 unsigned long flags;
2517 u8 prev;
2518 u8 mra;
2519 bool old_req;
2520
2521 trace_hfi1_rcv_error(qp, psn);
2522 if (diff > 0) {
2523
2524
2525
2526
2527
2528 if (!qp->r_nak_state) {
2529 ibp->rvp.n_rc_seqnak++;
2530 qp->r_nak_state = IB_NAK_PSN_ERROR;
2531
2532 qp->r_ack_psn = qp->r_psn;
2533
2534
2535
2536
2537
2538 rc_defered_ack(rcd, qp);
2539 }
2540 goto done;
2541 }
2542
2543
2544
2545
2546
2547
2548
2549
2550
2551
2552
2553
2554
2555
2556
2557
2558
2559 e = NULL;
2560 old_req = true;
2561 ibp->rvp.n_rc_dupreq++;
2562
2563 spin_lock_irqsave(&qp->s_lock, flags);
2564
2565 e = find_prev_entry(qp, psn, &prev, &mra, &old_req);
2566
2567 switch (opcode) {
2568 case OP(RDMA_READ_REQUEST): {
2569 struct ib_reth *reth;
2570 u32 offset;
2571 u32 len;
2572
2573
2574
2575
2576
2577 if (!e || e->opcode != OP(RDMA_READ_REQUEST))
2578 goto unlock_done;
2579
2580 reth = &ohdr->u.rc.reth;
2581
2582
2583
2584
2585
2586
2587
2588 offset = delta_psn(psn, e->psn) * qp->pmtu;
2589 len = be32_to_cpu(reth->length);
2590 if (unlikely(offset + len != e->rdma_sge.sge_length))
2591 goto unlock_done;
2592 release_rdma_sge_mr(e);
2593 if (len != 0) {
2594 u32 rkey = be32_to_cpu(reth->rkey);
2595 u64 vaddr = get_ib_reth_vaddr(reth);
2596 int ok;
2597
2598 ok = rvt_rkey_ok(qp, &e->rdma_sge, len, vaddr, rkey,
2599 IB_ACCESS_REMOTE_READ);
2600 if (unlikely(!ok))
2601 goto unlock_done;
2602 } else {
2603 e->rdma_sge.vaddr = NULL;
2604 e->rdma_sge.length = 0;
2605 e->rdma_sge.sge_length = 0;
2606 }
2607 e->psn = psn;
2608 if (old_req)
2609 goto unlock_done;
2610 if (qp->s_acked_ack_queue == qp->s_tail_ack_queue)
2611 qp->s_acked_ack_queue = prev;
2612 qp->s_tail_ack_queue = prev;
2613 break;
2614 }
2615
2616 case OP(COMPARE_SWAP):
2617 case OP(FETCH_ADD): {
2618
2619
2620
2621
2622
2623 if (!e || e->opcode != (u8)opcode || old_req)
2624 goto unlock_done;
2625 if (qp->s_tail_ack_queue == qp->s_acked_ack_queue)
2626 qp->s_acked_ack_queue = prev;
2627 qp->s_tail_ack_queue = prev;
2628 break;
2629 }
2630
2631 default:
2632
2633
2634
2635
2636 if (!(psn & IB_BTH_REQ_ACK) || old_req)
2637 goto unlock_done;
2638
2639
2640
2641
2642 if (mra == qp->r_head_ack_queue) {
2643 spin_unlock_irqrestore(&qp->s_lock, flags);
2644 qp->r_nak_state = 0;
2645 qp->r_ack_psn = qp->r_psn - 1;
2646 goto send_ack;
2647 }
2648
2649
2650
2651
2652
2653 if (qp->s_tail_ack_queue == qp->s_acked_ack_queue)
2654 qp->s_acked_ack_queue = mra;
2655 qp->s_tail_ack_queue = mra;
2656 break;
2657 }
2658 qp->s_ack_state = OP(ACKNOWLEDGE);
2659 qp->s_flags |= RVT_S_RESP_PENDING;
2660 qp->r_nak_state = 0;
2661 hfi1_schedule_send(qp);
2662
2663unlock_done:
2664 spin_unlock_irqrestore(&qp->s_lock, flags);
2665done:
2666 return 1;
2667
2668send_ack:
2669 return 0;
2670}
2671
2672static void log_cca_event(struct hfi1_pportdata *ppd, u8 sl, u32 rlid,
2673 u32 lqpn, u32 rqpn, u8 svc_type)
2674{
2675 struct opa_hfi1_cong_log_event_internal *cc_event;
2676 unsigned long flags;
2677
2678 if (sl >= OPA_MAX_SLS)
2679 return;
2680
2681 spin_lock_irqsave(&ppd->cc_log_lock, flags);
2682
2683 ppd->threshold_cong_event_map[sl / 8] |= 1 << (sl % 8);
2684 ppd->threshold_event_counter++;
2685
2686 cc_event = &ppd->cc_events[ppd->cc_log_idx++];
2687 if (ppd->cc_log_idx == OPA_CONG_LOG_ELEMS)
2688 ppd->cc_log_idx = 0;
2689 cc_event->lqpn = lqpn & RVT_QPN_MASK;
2690 cc_event->rqpn = rqpn & RVT_QPN_MASK;
2691 cc_event->sl = sl;
2692 cc_event->svc_type = svc_type;
2693 cc_event->rlid = rlid;
2694
2695 cc_event->timestamp = ktime_get_ns() / 1024;
2696
2697 spin_unlock_irqrestore(&ppd->cc_log_lock, flags);
2698}
2699
2700void process_becn(struct hfi1_pportdata *ppd, u8 sl, u32 rlid, u32 lqpn,
2701 u32 rqpn, u8 svc_type)
2702{
2703 struct cca_timer *cca_timer;
2704 u16 ccti, ccti_incr, ccti_timer, ccti_limit;
2705 u8 trigger_threshold;
2706 struct cc_state *cc_state;
2707 unsigned long flags;
2708
2709 if (sl >= OPA_MAX_SLS)
2710 return;
2711
2712 cc_state = get_cc_state(ppd);
2713
2714 if (!cc_state)
2715 return;
2716
2717
2718
2719
2720
2721
2722 ccti_limit = cc_state->cct.ccti_limit;
2723 ccti_incr = cc_state->cong_setting.entries[sl].ccti_increase;
2724 ccti_timer = cc_state->cong_setting.entries[sl].ccti_timer;
2725 trigger_threshold =
2726 cc_state->cong_setting.entries[sl].trigger_threshold;
2727
2728 spin_lock_irqsave(&ppd->cca_timer_lock, flags);
2729
2730 cca_timer = &ppd->cca_timer[sl];
2731 if (cca_timer->ccti < ccti_limit) {
2732 if (cca_timer->ccti + ccti_incr <= ccti_limit)
2733 cca_timer->ccti += ccti_incr;
2734 else
2735 cca_timer->ccti = ccti_limit;
2736 set_link_ipg(ppd);
2737 }
2738
2739 ccti = cca_timer->ccti;
2740
2741 if (!hrtimer_active(&cca_timer->hrtimer)) {
2742
2743 unsigned long nsec = 1024 * ccti_timer;
2744
2745 hrtimer_start(&cca_timer->hrtimer, ns_to_ktime(nsec),
2746 HRTIMER_MODE_REL_PINNED);
2747 }
2748
2749 spin_unlock_irqrestore(&ppd->cca_timer_lock, flags);
2750
2751 if ((trigger_threshold != 0) && (ccti >= trigger_threshold))
2752 log_cca_event(ppd, sl, rlid, lqpn, rqpn, svc_type);
2753}
2754
2755
2756
2757
2758
2759
2760
2761
2762
2763void hfi1_rc_rcv(struct hfi1_packet *packet)
2764{
2765 struct hfi1_ctxtdata *rcd = packet->rcd;
2766 void *data = packet->payload;
2767 u32 tlen = packet->tlen;
2768 struct rvt_qp *qp = packet->qp;
2769 struct hfi1_qp_priv *qpriv = qp->priv;
2770 struct hfi1_ibport *ibp = rcd_to_iport(rcd);
2771 struct ib_other_headers *ohdr = packet->ohdr;
2772 u32 opcode = packet->opcode;
2773 u32 hdrsize = packet->hlen;
2774 u32 psn = ib_bth_get_psn(packet->ohdr);
2775 u32 pad = packet->pad;
2776 struct ib_wc wc;
2777 u32 pmtu = qp->pmtu;
2778 int diff;
2779 struct ib_reth *reth;
2780 unsigned long flags;
2781 int ret;
2782 bool copy_last = false, fecn;
2783 u32 rkey;
2784 u8 extra_bytes = pad + packet->extra_byte + (SIZE_OF_CRC << 2);
2785
2786 lockdep_assert_held(&qp->r_lock);
2787
2788 if (hfi1_ruc_check_hdr(ibp, packet))
2789 return;
2790
2791 fecn = process_ecn(qp, packet);
2792 opfn_trigger_conn_request(qp, be32_to_cpu(ohdr->bth[1]));
2793
2794
2795
2796
2797
2798
2799
2800 if (opcode >= OP(RDMA_READ_RESPONSE_FIRST) &&
2801 opcode <= OP(ATOMIC_ACKNOWLEDGE)) {
2802 rc_rcv_resp(packet);
2803 return;
2804 }
2805
2806
2807 diff = delta_psn(psn, qp->r_psn);
2808 if (unlikely(diff)) {
2809 if (rc_rcv_error(ohdr, data, qp, opcode, psn, diff, rcd))
2810 return;
2811 goto send_ack;
2812 }
2813
2814
2815 switch (qp->r_state) {
2816 case OP(SEND_FIRST):
2817 case OP(SEND_MIDDLE):
2818 if (opcode == OP(SEND_MIDDLE) ||
2819 opcode == OP(SEND_LAST) ||
2820 opcode == OP(SEND_LAST_WITH_IMMEDIATE) ||
2821 opcode == OP(SEND_LAST_WITH_INVALIDATE))
2822 break;
2823 goto nack_inv;
2824
2825 case OP(RDMA_WRITE_FIRST):
2826 case OP(RDMA_WRITE_MIDDLE):
2827 if (opcode == OP(RDMA_WRITE_MIDDLE) ||
2828 opcode == OP(RDMA_WRITE_LAST) ||
2829 opcode == OP(RDMA_WRITE_LAST_WITH_IMMEDIATE))
2830 break;
2831 goto nack_inv;
2832
2833 default:
2834 if (opcode == OP(SEND_MIDDLE) ||
2835 opcode == OP(SEND_LAST) ||
2836 opcode == OP(SEND_LAST_WITH_IMMEDIATE) ||
2837 opcode == OP(SEND_LAST_WITH_INVALIDATE) ||
2838 opcode == OP(RDMA_WRITE_MIDDLE) ||
2839 opcode == OP(RDMA_WRITE_LAST) ||
2840 opcode == OP(RDMA_WRITE_LAST_WITH_IMMEDIATE))
2841 goto nack_inv;
2842
2843
2844
2845
2846
2847 break;
2848 }
2849
2850 if (qp->state == IB_QPS_RTR && !(qp->r_flags & RVT_R_COMM_EST))
2851 rvt_comm_est(qp);
2852
2853
2854 switch (opcode) {
2855 case OP(SEND_FIRST):
2856 ret = rvt_get_rwqe(qp, false);
2857 if (ret < 0)
2858 goto nack_op_err;
2859 if (!ret)
2860 goto rnr_nak;
2861 qp->r_rcv_len = 0;
2862 fallthrough;
2863 case OP(SEND_MIDDLE):
2864 case OP(RDMA_WRITE_MIDDLE):
2865send_middle:
2866
2867
2868
2869
2870
2871
2872 if (unlikely(tlen != (hdrsize + pmtu + extra_bytes)))
2873 goto nack_inv;
2874 qp->r_rcv_len += pmtu;
2875 if (unlikely(qp->r_rcv_len > qp->r_len))
2876 goto nack_inv;
2877 rvt_copy_sge(qp, &qp->r_sge, data, pmtu, true, false);
2878 break;
2879
2880 case OP(RDMA_WRITE_LAST_WITH_IMMEDIATE):
2881
2882 ret = rvt_get_rwqe(qp, true);
2883 if (ret < 0)
2884 goto nack_op_err;
2885 if (!ret)
2886 goto rnr_nak;
2887 goto send_last_imm;
2888
2889 case OP(SEND_ONLY):
2890 case OP(SEND_ONLY_WITH_IMMEDIATE):
2891 case OP(SEND_ONLY_WITH_INVALIDATE):
2892 ret = rvt_get_rwqe(qp, false);
2893 if (ret < 0)
2894 goto nack_op_err;
2895 if (!ret)
2896 goto rnr_nak;
2897 qp->r_rcv_len = 0;
2898 if (opcode == OP(SEND_ONLY))
2899 goto no_immediate_data;
2900 if (opcode == OP(SEND_ONLY_WITH_INVALIDATE))
2901 goto send_last_inv;
2902 fallthrough;
2903 case OP(SEND_LAST_WITH_IMMEDIATE):
2904send_last_imm:
2905 wc.ex.imm_data = ohdr->u.imm_data;
2906 wc.wc_flags = IB_WC_WITH_IMM;
2907 goto send_last;
2908 case OP(SEND_LAST_WITH_INVALIDATE):
2909send_last_inv:
2910 rkey = be32_to_cpu(ohdr->u.ieth);
2911 if (rvt_invalidate_rkey(qp, rkey))
2912 goto no_immediate_data;
2913 wc.ex.invalidate_rkey = rkey;
2914 wc.wc_flags = IB_WC_WITH_INVALIDATE;
2915 goto send_last;
2916 case OP(RDMA_WRITE_LAST):
2917 copy_last = rvt_is_user_qp(qp);
2918 fallthrough;
2919 case OP(SEND_LAST):
2920no_immediate_data:
2921 wc.wc_flags = 0;
2922 wc.ex.imm_data = 0;
2923send_last:
2924
2925
2926 if (unlikely(tlen < (hdrsize + extra_bytes)))
2927 goto nack_inv;
2928
2929 tlen -= (hdrsize + extra_bytes);
2930 wc.byte_len = tlen + qp->r_rcv_len;
2931 if (unlikely(wc.byte_len > qp->r_len))
2932 goto nack_inv;
2933 rvt_copy_sge(qp, &qp->r_sge, data, tlen, true, copy_last);
2934 rvt_put_ss(&qp->r_sge);
2935 qp->r_msn++;
2936 if (!__test_and_clear_bit(RVT_R_WRID_VALID, &qp->r_aflags))
2937 break;
2938 wc.wr_id = qp->r_wr_id;
2939 wc.status = IB_WC_SUCCESS;
2940 if (opcode == OP(RDMA_WRITE_LAST_WITH_IMMEDIATE) ||
2941 opcode == OP(RDMA_WRITE_ONLY_WITH_IMMEDIATE))
2942 wc.opcode = IB_WC_RECV_RDMA_WITH_IMM;
2943 else
2944 wc.opcode = IB_WC_RECV;
2945 wc.qp = &qp->ibqp;
2946 wc.src_qp = qp->remote_qpn;
2947 wc.slid = rdma_ah_get_dlid(&qp->remote_ah_attr) & U16_MAX;
2948
2949
2950
2951
2952
2953
2954
2955
2956
2957
2958
2959 wc.sl = rdma_ah_get_sl(&qp->remote_ah_attr);
2960
2961 wc.vendor_err = 0;
2962 wc.pkey_index = 0;
2963 wc.dlid_path_bits = 0;
2964 wc.port_num = 0;
2965
2966 rvt_recv_cq(qp, &wc, ib_bth_is_solicited(ohdr));
2967 break;
2968
2969 case OP(RDMA_WRITE_ONLY):
2970 copy_last = rvt_is_user_qp(qp);
2971 fallthrough;
2972 case OP(RDMA_WRITE_FIRST):
2973 case OP(RDMA_WRITE_ONLY_WITH_IMMEDIATE):
2974 if (unlikely(!(qp->qp_access_flags & IB_ACCESS_REMOTE_WRITE)))
2975 goto nack_inv;
2976
2977 reth = &ohdr->u.rc.reth;
2978 qp->r_len = be32_to_cpu(reth->length);
2979 qp->r_rcv_len = 0;
2980 qp->r_sge.sg_list = NULL;
2981 if (qp->r_len != 0) {
2982 u32 rkey = be32_to_cpu(reth->rkey);
2983 u64 vaddr = get_ib_reth_vaddr(reth);
2984 int ok;
2985
2986
2987 ok = rvt_rkey_ok(qp, &qp->r_sge.sge, qp->r_len, vaddr,
2988 rkey, IB_ACCESS_REMOTE_WRITE);
2989 if (unlikely(!ok))
2990 goto nack_acc;
2991 qp->r_sge.num_sge = 1;
2992 } else {
2993 qp->r_sge.num_sge = 0;
2994 qp->r_sge.sge.mr = NULL;
2995 qp->r_sge.sge.vaddr = NULL;
2996 qp->r_sge.sge.length = 0;
2997 qp->r_sge.sge.sge_length = 0;
2998 }
2999 if (opcode == OP(RDMA_WRITE_FIRST))
3000 goto send_middle;
3001 else if (opcode == OP(RDMA_WRITE_ONLY))
3002 goto no_immediate_data;
3003 ret = rvt_get_rwqe(qp, true);
3004 if (ret < 0)
3005 goto nack_op_err;
3006 if (!ret) {
3007
3008 rvt_put_ss(&qp->r_sge);
3009 goto rnr_nak;
3010 }
3011 wc.ex.imm_data = ohdr->u.rc.imm_data;
3012 wc.wc_flags = IB_WC_WITH_IMM;
3013 goto send_last;
3014
3015 case OP(RDMA_READ_REQUEST): {
3016 struct rvt_ack_entry *e;
3017 u32 len;
3018 u8 next;
3019
3020 if (unlikely(!(qp->qp_access_flags & IB_ACCESS_REMOTE_READ)))
3021 goto nack_inv;
3022 next = qp->r_head_ack_queue + 1;
3023
3024 if (next > rvt_size_atomic(ib_to_rvt(qp->ibqp.device)))
3025 next = 0;
3026 spin_lock_irqsave(&qp->s_lock, flags);
3027 if (unlikely(next == qp->s_acked_ack_queue)) {
3028 if (!qp->s_ack_queue[next].sent)
3029 goto nack_inv_unlck;
3030 update_ack_queue(qp, next);
3031 }
3032 e = &qp->s_ack_queue[qp->r_head_ack_queue];
3033 release_rdma_sge_mr(e);
3034 reth = &ohdr->u.rc.reth;
3035 len = be32_to_cpu(reth->length);
3036 if (len) {
3037 u32 rkey = be32_to_cpu(reth->rkey);
3038 u64 vaddr = get_ib_reth_vaddr(reth);
3039 int ok;
3040
3041
3042 ok = rvt_rkey_ok(qp, &e->rdma_sge, len, vaddr,
3043 rkey, IB_ACCESS_REMOTE_READ);
3044 if (unlikely(!ok))
3045 goto nack_acc_unlck;
3046
3047
3048
3049
3050 qp->r_psn += rvt_div_mtu(qp, len - 1);
3051 } else {
3052 e->rdma_sge.mr = NULL;
3053 e->rdma_sge.vaddr = NULL;
3054 e->rdma_sge.length = 0;
3055 e->rdma_sge.sge_length = 0;
3056 }
3057 e->opcode = opcode;
3058 e->sent = 0;
3059 e->psn = psn;
3060 e->lpsn = qp->r_psn;
3061
3062
3063
3064
3065
3066 qp->r_msn++;
3067 qp->r_psn++;
3068 qp->r_state = opcode;
3069 qp->r_nak_state = 0;
3070 qp->r_head_ack_queue = next;
3071 qpriv->r_tid_alloc = qp->r_head_ack_queue;
3072
3073
3074 qp->s_flags |= RVT_S_RESP_PENDING;
3075 if (fecn)
3076 qp->s_flags |= RVT_S_ECN;
3077 hfi1_schedule_send(qp);
3078
3079 spin_unlock_irqrestore(&qp->s_lock, flags);
3080 return;
3081 }
3082
3083 case OP(COMPARE_SWAP):
3084 case OP(FETCH_ADD): {
3085 struct ib_atomic_eth *ateth = &ohdr->u.atomic_eth;
3086 u64 vaddr = get_ib_ateth_vaddr(ateth);
3087 bool opfn = opcode == OP(COMPARE_SWAP) &&
3088 vaddr == HFI1_VERBS_E_ATOMIC_VADDR;
3089 struct rvt_ack_entry *e;
3090 atomic64_t *maddr;
3091 u64 sdata;
3092 u32 rkey;
3093 u8 next;
3094
3095 if (unlikely(!(qp->qp_access_flags & IB_ACCESS_REMOTE_ATOMIC) &&
3096 !opfn))
3097 goto nack_inv;
3098 next = qp->r_head_ack_queue + 1;
3099 if (next > rvt_size_atomic(ib_to_rvt(qp->ibqp.device)))
3100 next = 0;
3101 spin_lock_irqsave(&qp->s_lock, flags);
3102 if (unlikely(next == qp->s_acked_ack_queue)) {
3103 if (!qp->s_ack_queue[next].sent)
3104 goto nack_inv_unlck;
3105 update_ack_queue(qp, next);
3106 }
3107 e = &qp->s_ack_queue[qp->r_head_ack_queue];
3108 release_rdma_sge_mr(e);
3109
3110 if (opfn) {
3111 opfn_conn_response(qp, e, ateth);
3112 goto ack;
3113 }
3114 if (unlikely(vaddr & (sizeof(u64) - 1)))
3115 goto nack_inv_unlck;
3116 rkey = be32_to_cpu(ateth->rkey);
3117
3118 if (unlikely(!rvt_rkey_ok(qp, &qp->r_sge.sge, sizeof(u64),
3119 vaddr, rkey,
3120 IB_ACCESS_REMOTE_ATOMIC)))
3121 goto nack_acc_unlck;
3122
3123 maddr = (atomic64_t *)qp->r_sge.sge.vaddr;
3124 sdata = get_ib_ateth_swap(ateth);
3125 e->atomic_data = (opcode == OP(FETCH_ADD)) ?
3126 (u64)atomic64_add_return(sdata, maddr) - sdata :
3127 (u64)cmpxchg((u64 *)qp->r_sge.sge.vaddr,
3128 get_ib_ateth_compare(ateth),
3129 sdata);
3130 rvt_put_mr(qp->r_sge.sge.mr);
3131 qp->r_sge.num_sge = 0;
3132ack:
3133 e->opcode = opcode;
3134 e->sent = 0;
3135 e->psn = psn;
3136 e->lpsn = psn;
3137 qp->r_msn++;
3138 qp->r_psn++;
3139 qp->r_state = opcode;
3140 qp->r_nak_state = 0;
3141 qp->r_head_ack_queue = next;
3142 qpriv->r_tid_alloc = qp->r_head_ack_queue;
3143
3144
3145 qp->s_flags |= RVT_S_RESP_PENDING;
3146 if (fecn)
3147 qp->s_flags |= RVT_S_ECN;
3148 hfi1_schedule_send(qp);
3149
3150 spin_unlock_irqrestore(&qp->s_lock, flags);
3151 return;
3152 }
3153
3154 default:
3155
3156 goto nack_inv;
3157 }
3158 qp->r_psn++;
3159 qp->r_state = opcode;
3160 qp->r_ack_psn = psn;
3161 qp->r_nak_state = 0;
3162
3163 if (psn & IB_BTH_REQ_ACK || fecn) {
3164 if (packet->numpkt == 0 || fecn ||
3165 qp->r_adefered >= HFI1_PSN_CREDIT) {
3166 rc_cancel_ack(qp);
3167 goto send_ack;
3168 }
3169 qp->r_adefered++;
3170 rc_defered_ack(rcd, qp);
3171 }
3172 return;
3173
3174rnr_nak:
3175 qp->r_nak_state = qp->r_min_rnr_timer | IB_RNR_NAK;
3176 qp->r_ack_psn = qp->r_psn;
3177
3178 rc_defered_ack(rcd, qp);
3179 return;
3180
3181nack_op_err:
3182 rvt_rc_error(qp, IB_WC_LOC_QP_OP_ERR);
3183 qp->r_nak_state = IB_NAK_REMOTE_OPERATIONAL_ERROR;
3184 qp->r_ack_psn = qp->r_psn;
3185
3186 rc_defered_ack(rcd, qp);
3187 return;
3188
3189nack_inv_unlck:
3190 spin_unlock_irqrestore(&qp->s_lock, flags);
3191nack_inv:
3192 rvt_rc_error(qp, IB_WC_LOC_QP_OP_ERR);
3193 qp->r_nak_state = IB_NAK_INVALID_REQUEST;
3194 qp->r_ack_psn = qp->r_psn;
3195
3196 rc_defered_ack(rcd, qp);
3197 return;
3198
3199nack_acc_unlck:
3200 spin_unlock_irqrestore(&qp->s_lock, flags);
3201nack_acc:
3202 rvt_rc_error(qp, IB_WC_LOC_PROT_ERR);
3203 qp->r_nak_state = IB_NAK_REMOTE_ACCESS_ERROR;
3204 qp->r_ack_psn = qp->r_psn;
3205send_ack:
3206 hfi1_send_rc_ack(packet, fecn);
3207}
3208
3209void hfi1_rc_hdrerr(
3210 struct hfi1_ctxtdata *rcd,
3211 struct hfi1_packet *packet,
3212 struct rvt_qp *qp)
3213{
3214 struct hfi1_ibport *ibp = rcd_to_iport(rcd);
3215 int diff;
3216 u32 opcode;
3217 u32 psn;
3218
3219 if (hfi1_ruc_check_hdr(ibp, packet))
3220 return;
3221
3222 psn = ib_bth_get_psn(packet->ohdr);
3223 opcode = ib_bth_get_opcode(packet->ohdr);
3224
3225
3226 if (opcode < IB_OPCODE_RC_RDMA_READ_RESPONSE_FIRST) {
3227 diff = delta_psn(psn, qp->r_psn);
3228 if (!qp->r_nak_state && diff >= 0) {
3229 ibp->rvp.n_rc_seqnak++;
3230 qp->r_nak_state = IB_NAK_PSN_ERROR;
3231
3232 qp->r_ack_psn = qp->r_psn;
3233
3234
3235
3236
3237
3238
3239
3240
3241 rc_defered_ack(rcd, qp);
3242 }
3243 }
3244}
3245