1
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5
6
7#include <asm/unaligned.h>
8
9#include <linux/clk.h>
10#include <linux/delay.h>
11#include <linux/i2c.h>
12#include <linux/module.h>
13#include <linux/pm_runtime.h>
14#include <linux/regulator/consumer.h>
15
16#include <media/v4l2-ctrls.h>
17#include <media/v4l2-fwnode.h>
18#include <media/v4l2-subdev.h>
19
20
21#define IMX412_REG_MODE_SELECT 0x0100
22#define IMX412_MODE_STANDBY 0x00
23#define IMX412_MODE_STREAMING 0x01
24
25
26#define IMX412_REG_LPFR 0x0340
27
28
29#define IMX412_REG_ID 0x0016
30#define IMX412_ID 0x577
31
32
33#define IMX412_REG_EXPOSURE_CIT 0x0202
34#define IMX412_EXPOSURE_MIN 8
35#define IMX412_EXPOSURE_OFFSET 22
36#define IMX412_EXPOSURE_STEP 1
37#define IMX412_EXPOSURE_DEFAULT 0x0648
38
39
40#define IMX412_REG_AGAIN 0x0204
41#define IMX412_AGAIN_MIN 0
42#define IMX412_AGAIN_MAX 978
43#define IMX412_AGAIN_STEP 1
44#define IMX412_AGAIN_DEFAULT 0
45
46
47#define IMX412_REG_HOLD 0x0104
48
49
50#define IMX412_INCLK_RATE 24000000
51
52
53#define IMX412_LINK_FREQ 600000000
54#define IMX412_NUM_DATA_LANES 4
55
56#define IMX412_REG_MIN 0x00
57#define IMX412_REG_MAX 0xffff
58
59
60
61
62
63
64struct imx412_reg {
65 u16 address;
66 u8 val;
67};
68
69
70
71
72
73
74struct imx412_reg_list {
75 u32 num_of_regs;
76 const struct imx412_reg *regs;
77};
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92struct imx412_mode {
93 u32 width;
94 u32 height;
95 u32 code;
96 u32 hblank;
97 u32 vblank;
98 u32 vblank_min;
99 u32 vblank_max;
100 u64 pclk;
101 u32 link_freq_idx;
102 struct imx412_reg_list reg_list;
103};
104
105static const char * const imx412_supply_names[] = {
106 "dovdd",
107 "avdd",
108 "dvdd",
109};
110
111
112
113
114
115
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117
118
119
120
121
122
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130
131
132struct imx412 {
133 struct device *dev;
134 struct i2c_client *client;
135 struct v4l2_subdev sd;
136 struct media_pad pad;
137 struct gpio_desc *reset_gpio;
138 struct clk *inclk;
139 struct regulator_bulk_data supplies[ARRAY_SIZE(imx412_supply_names)];
140 struct v4l2_ctrl_handler ctrl_handler;
141 struct v4l2_ctrl *link_freq_ctrl;
142 struct v4l2_ctrl *pclk_ctrl;
143 struct v4l2_ctrl *hblank_ctrl;
144 struct v4l2_ctrl *vblank_ctrl;
145 struct {
146 struct v4l2_ctrl *exp_ctrl;
147 struct v4l2_ctrl *again_ctrl;
148 };
149 u32 vblank;
150 const struct imx412_mode *cur_mode;
151 struct mutex mutex;
152 bool streaming;
153};
154
155static const s64 link_freq[] = {
156 IMX412_LINK_FREQ,
157};
158
159
160static const struct imx412_reg mode_4056x3040_regs[] = {
161 {0x0136, 0x18},
162 {0x0137, 0x00},
163 {0x3c7e, 0x08},
164 {0x3c7f, 0x02},
165 {0x38a8, 0x1f},
166 {0x38a9, 0xff},
167 {0x38aa, 0x1f},
168 {0x38ab, 0xff},
169 {0x55d4, 0x00},
170 {0x55d5, 0x00},
171 {0x55d6, 0x07},
172 {0x55d7, 0xff},
173 {0x55e8, 0x07},
174 {0x55e9, 0xff},
175 {0x55ea, 0x00},
176 {0x55eb, 0x00},
177 {0x575c, 0x07},
178 {0x575d, 0xff},
179 {0x575e, 0x00},
180 {0x575f, 0x00},
181 {0x5764, 0x00},
182 {0x5765, 0x00},
183 {0x5766, 0x07},
184 {0x5767, 0xff},
185 {0x5974, 0x04},
186 {0x5975, 0x01},
187 {0x5f10, 0x09},
188 {0x5f11, 0x92},
189 {0x5f12, 0x32},
190 {0x5f13, 0x72},
191 {0x5f14, 0x16},
192 {0x5f15, 0xba},
193 {0x5f17, 0x13},
194 {0x5f18, 0x24},
195 {0x5f19, 0x60},
196 {0x5f1a, 0xe3},
197 {0x5f1b, 0xad},
198 {0x5f1c, 0x74},
199 {0x5f2d, 0x25},
200 {0x5f5c, 0xd0},
201 {0x6a22, 0x00},
202 {0x6a23, 0x1d},
203 {0x7ba8, 0x00},
204 {0x7ba9, 0x00},
205 {0x886b, 0x00},
206 {0x9002, 0x0a},
207 {0x9004, 0x1a},
208 {0x9214, 0x93},
209 {0x9215, 0x69},
210 {0x9216, 0x93},
211 {0x9217, 0x6b},
212 {0x9218, 0x93},
213 {0x9219, 0x6d},
214 {0x921a, 0x57},
215 {0x921b, 0x58},
216 {0x921c, 0x57},
217 {0x921d, 0x59},
218 {0x921e, 0x57},
219 {0x921f, 0x5a},
220 {0x9220, 0x57},
221 {0x9221, 0x5b},
222 {0x9222, 0x93},
223 {0x9223, 0x02},
224 {0x9224, 0x93},
225 {0x9225, 0x03},
226 {0x9226, 0x93},
227 {0x9227, 0x04},
228 {0x9228, 0x93},
229 {0x9229, 0x05},
230 {0x922a, 0x98},
231 {0x922b, 0x21},
232 {0x922c, 0xb2},
233 {0x922d, 0xdb},
234 {0x922e, 0xb2},
235 {0x922f, 0xdc},
236 {0x9230, 0xb2},
237 {0x9231, 0xdd},
238 {0x9232, 0xe2},
239 {0x9233, 0xe1},
240 {0x9234, 0xb2},
241 {0x9235, 0xe2},
242 {0x9236, 0xb2},
243 {0x9237, 0xe3},
244 {0x9238, 0xb7},
245 {0x9239, 0xb9},
246 {0x923a, 0xb7},
247 {0x923b, 0xbb},
248 {0x923c, 0xb7},
249 {0x923d, 0xbc},
250 {0x923e, 0xb7},
251 {0x923f, 0xc5},
252 {0x9240, 0xb7},
253 {0x9241, 0xc7},
254 {0x9242, 0xb7},
255 {0x9243, 0xc9},
256 {0x9244, 0x98},
257 {0x9245, 0x56},
258 {0x9246, 0x98},
259 {0x9247, 0x55},
260 {0x9380, 0x00},
261 {0x9381, 0x62},
262 {0x9382, 0x00},
263 {0x9383, 0x56},
264 {0x9384, 0x00},
265 {0x9385, 0x52},
266 {0x9388, 0x00},
267 {0x9389, 0x55},
268 {0x938a, 0x00},
269 {0x938b, 0x55},
270 {0x938c, 0x00},
271 {0x938d, 0x41},
272 {0x5078, 0x01},
273 {0x0112, 0x0a},
274 {0x0113, 0x0a},
275 {0x0114, 0x03},
276 {0x0342, 0x11},
277 {0x0343, 0xa0},
278 {0x0340, 0x0d},
279 {0x0341, 0xda},
280 {0x3210, 0x00},
281 {0x0344, 0x00},
282 {0x0345, 0x00},
283 {0x0346, 0x00},
284 {0x0347, 0x00},
285 {0x0348, 0x0f},
286 {0x0349, 0xd7},
287 {0x034a, 0x0b},
288 {0x034b, 0xdf},
289 {0x00e3, 0x00},
290 {0x00e4, 0x00},
291 {0x00e5, 0x01},
292 {0x00fc, 0x0a},
293 {0x00fd, 0x0a},
294 {0x00fe, 0x0a},
295 {0x00ff, 0x0a},
296 {0xe013, 0x00},
297 {0x0220, 0x00},
298 {0x0221, 0x11},
299 {0x0381, 0x01},
300 {0x0383, 0x01},
301 {0x0385, 0x01},
302 {0x0387, 0x01},
303 {0x0900, 0x00},
304 {0x0901, 0x11},
305 {0x0902, 0x00},
306 {0x3140, 0x02},
307 {0x3241, 0x11},
308 {0x3250, 0x03},
309 {0x3e10, 0x00},
310 {0x3e11, 0x00},
311 {0x3f0d, 0x00},
312 {0x3f42, 0x00},
313 {0x3f43, 0x00},
314 {0x0401, 0x00},
315 {0x0404, 0x00},
316 {0x0405, 0x10},
317 {0x0408, 0x00},
318 {0x0409, 0x00},
319 {0x040a, 0x00},
320 {0x040b, 0x00},
321 {0x040c, 0x0f},
322 {0x040d, 0xd8},
323 {0x040e, 0x0b},
324 {0x040f, 0xe0},
325 {0x034c, 0x0f},
326 {0x034d, 0xd8},
327 {0x034e, 0x0b},
328 {0x034f, 0xe0},
329 {0x0301, 0x05},
330 {0x0303, 0x02},
331 {0x0305, 0x04},
332 {0x0306, 0x00},
333 {0x0307, 0xc8},
334 {0x0309, 0x0a},
335 {0x030b, 0x01},
336 {0x030d, 0x02},
337 {0x030e, 0x01},
338 {0x030f, 0x5e},
339 {0x0310, 0x00},
340 {0x0820, 0x12},
341 {0x0821, 0xc0},
342 {0x0822, 0x00},
343 {0x0823, 0x00},
344 {0x3e20, 0x01},
345 {0x3e37, 0x00},
346 {0x3f50, 0x00},
347 {0x3f56, 0x00},
348 {0x3f57, 0xe2},
349 {0x3c0a, 0x5a},
350 {0x3c0b, 0x55},
351 {0x3c0c, 0x28},
352 {0x3c0d, 0x07},
353 {0x3c0e, 0xff},
354 {0x3c0f, 0x00},
355 {0x3c10, 0x00},
356 {0x3c11, 0x02},
357 {0x3c12, 0x00},
358 {0x3c13, 0x03},
359 {0x3c14, 0x00},
360 {0x3c15, 0x00},
361 {0x3c16, 0x0c},
362 {0x3c17, 0x0c},
363 {0x3c18, 0x0c},
364 {0x3c19, 0x0a},
365 {0x3c1a, 0x0a},
366 {0x3c1b, 0x0a},
367 {0x3c1c, 0x00},
368 {0x3c1d, 0x00},
369 {0x3c1e, 0x00},
370 {0x3c1f, 0x00},
371 {0x3c20, 0x00},
372 {0x3c21, 0x00},
373 {0x3c22, 0x3f},
374 {0x3c23, 0x0a},
375 {0x3e35, 0x01},
376 {0x3f4a, 0x03},
377 {0x3f4b, 0xbf},
378 {0x3f26, 0x00},
379 {0x0202, 0x0d},
380 {0x0203, 0xc4},
381 {0x0204, 0x00},
382 {0x0205, 0x00},
383 {0x020e, 0x01},
384 {0x020f, 0x00},
385 {0x0210, 0x01},
386 {0x0211, 0x00},
387 {0x0212, 0x01},
388 {0x0213, 0x00},
389 {0x0214, 0x01},
390 {0x0215, 0x00},
391 {0xbcf1, 0x00},
392};
393
394
395static const struct imx412_mode supported_mode = {
396 .width = 4056,
397 .height = 3040,
398 .hblank = 456,
399 .vblank = 506,
400 .vblank_min = 506,
401 .vblank_max = 32420,
402 .pclk = 480000000,
403 .link_freq_idx = 0,
404 .code = MEDIA_BUS_FMT_SRGGB10_1X10,
405 .reg_list = {
406 .num_of_regs = ARRAY_SIZE(mode_4056x3040_regs),
407 .regs = mode_4056x3040_regs,
408 },
409};
410
411
412
413
414
415
416
417static inline struct imx412 *to_imx412(struct v4l2_subdev *subdev)
418{
419 return container_of(subdev, struct imx412, sd);
420}
421
422
423
424
425
426
427
428
429
430
431static int imx412_read_reg(struct imx412 *imx412, u16 reg, u32 len, u32 *val)
432{
433 struct i2c_client *client = v4l2_get_subdevdata(&imx412->sd);
434 struct i2c_msg msgs[2] = {0};
435 u8 addr_buf[2] = {0};
436 u8 data_buf[4] = {0};
437 int ret;
438
439 if (WARN_ON(len > 4))
440 return -EINVAL;
441
442 put_unaligned_be16(reg, addr_buf);
443
444
445 msgs[0].addr = client->addr;
446 msgs[0].flags = 0;
447 msgs[0].len = ARRAY_SIZE(addr_buf);
448 msgs[0].buf = addr_buf;
449
450
451 msgs[1].addr = client->addr;
452 msgs[1].flags = I2C_M_RD;
453 msgs[1].len = len;
454 msgs[1].buf = &data_buf[4 - len];
455
456 ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
457 if (ret != ARRAY_SIZE(msgs))
458 return -EIO;
459
460 *val = get_unaligned_be32(data_buf);
461
462 return 0;
463}
464
465
466
467
468
469
470
471
472
473
474static int imx412_write_reg(struct imx412 *imx412, u16 reg, u32 len, u32 val)
475{
476 struct i2c_client *client = v4l2_get_subdevdata(&imx412->sd);
477 u8 buf[6] = {0};
478
479 if (WARN_ON(len > 4))
480 return -EINVAL;
481
482 put_unaligned_be16(reg, buf);
483 put_unaligned_be32(val << (8 * (4 - len)), buf + 2);
484 if (i2c_master_send(client, buf, len + 2) != len + 2)
485 return -EIO;
486
487 return 0;
488}
489
490
491
492
493
494
495
496
497
498static int imx412_write_regs(struct imx412 *imx412,
499 const struct imx412_reg *regs, u32 len)
500{
501 unsigned int i;
502 int ret;
503
504 for (i = 0; i < len; i++) {
505 ret = imx412_write_reg(imx412, regs[i].address, 1, regs[i].val);
506 if (ret)
507 return ret;
508 }
509
510 return 0;
511}
512
513
514
515
516
517
518
519
520static int imx412_update_controls(struct imx412 *imx412,
521 const struct imx412_mode *mode)
522{
523 int ret;
524
525 ret = __v4l2_ctrl_s_ctrl(imx412->link_freq_ctrl, mode->link_freq_idx);
526 if (ret)
527 return ret;
528
529 ret = __v4l2_ctrl_s_ctrl(imx412->hblank_ctrl, mode->hblank);
530 if (ret)
531 return ret;
532
533 return __v4l2_ctrl_modify_range(imx412->vblank_ctrl, mode->vblank_min,
534 mode->vblank_max, 1, mode->vblank);
535}
536
537
538
539
540
541
542
543
544
545static int imx412_update_exp_gain(struct imx412 *imx412, u32 exposure, u32 gain)
546{
547 u32 lpfr, shutter;
548 int ret;
549
550 lpfr = imx412->vblank + imx412->cur_mode->height;
551 shutter = lpfr - exposure;
552
553 dev_dbg(imx412->dev, "Set exp %u, analog gain %u, shutter %u, lpfr %u",
554 exposure, gain, shutter, lpfr);
555
556 ret = imx412_write_reg(imx412, IMX412_REG_HOLD, 1, 1);
557 if (ret)
558 return ret;
559
560 ret = imx412_write_reg(imx412, IMX412_REG_LPFR, 2, lpfr);
561 if (ret)
562 goto error_release_group_hold;
563
564 ret = imx412_write_reg(imx412, IMX412_REG_EXPOSURE_CIT, 2, shutter);
565 if (ret)
566 goto error_release_group_hold;
567
568 ret = imx412_write_reg(imx412, IMX412_REG_AGAIN, 2, gain);
569
570error_release_group_hold:
571 imx412_write_reg(imx412, IMX412_REG_HOLD, 1, 0);
572
573 return ret;
574}
575
576
577
578
579
580
581
582
583
584
585
586
587
588static int imx412_set_ctrl(struct v4l2_ctrl *ctrl)
589{
590 struct imx412 *imx412 =
591 container_of(ctrl->handler, struct imx412, ctrl_handler);
592 u32 analog_gain;
593 u32 exposure;
594 int ret;
595
596 switch (ctrl->id) {
597 case V4L2_CID_VBLANK:
598 imx412->vblank = imx412->vblank_ctrl->val;
599
600 dev_dbg(imx412->dev, "Received vblank %u, new lpfr %u",
601 imx412->vblank,
602 imx412->vblank + imx412->cur_mode->height);
603
604 ret = __v4l2_ctrl_modify_range(imx412->exp_ctrl,
605 IMX412_EXPOSURE_MIN,
606 imx412->vblank +
607 imx412->cur_mode->height -
608 IMX412_EXPOSURE_OFFSET,
609 1, IMX412_EXPOSURE_DEFAULT);
610 break;
611 case V4L2_CID_EXPOSURE:
612
613 if (!pm_runtime_get_if_in_use(imx412->dev))
614 return 0;
615
616 exposure = ctrl->val;
617 analog_gain = imx412->again_ctrl->val;
618
619 dev_dbg(imx412->dev, "Received exp %u, analog gain %u",
620 exposure, analog_gain);
621
622 ret = imx412_update_exp_gain(imx412, exposure, analog_gain);
623
624 pm_runtime_put(imx412->dev);
625
626 break;
627 default:
628 dev_err(imx412->dev, "Invalid control %d", ctrl->id);
629 ret = -EINVAL;
630 }
631
632 return ret;
633}
634
635
636static const struct v4l2_ctrl_ops imx412_ctrl_ops = {
637 .s_ctrl = imx412_set_ctrl,
638};
639
640
641
642
643
644
645
646
647
648static int imx412_enum_mbus_code(struct v4l2_subdev *sd,
649 struct v4l2_subdev_state *sd_state,
650 struct v4l2_subdev_mbus_code_enum *code)
651{
652 if (code->index > 0)
653 return -EINVAL;
654
655 code->code = supported_mode.code;
656
657 return 0;
658}
659
660
661
662
663
664
665
666
667
668static int imx412_enum_frame_size(struct v4l2_subdev *sd,
669 struct v4l2_subdev_state *sd_state,
670 struct v4l2_subdev_frame_size_enum *fsize)
671{
672 if (fsize->index > 0)
673 return -EINVAL;
674
675 if (fsize->code != supported_mode.code)
676 return -EINVAL;
677
678 fsize->min_width = supported_mode.width;
679 fsize->max_width = fsize->min_width;
680 fsize->min_height = supported_mode.height;
681 fsize->max_height = fsize->min_height;
682
683 return 0;
684}
685
686
687
688
689
690
691
692
693static void imx412_fill_pad_format(struct imx412 *imx412,
694 const struct imx412_mode *mode,
695 struct v4l2_subdev_format *fmt)
696{
697 fmt->format.width = mode->width;
698 fmt->format.height = mode->height;
699 fmt->format.code = mode->code;
700 fmt->format.field = V4L2_FIELD_NONE;
701 fmt->format.colorspace = V4L2_COLORSPACE_RAW;
702 fmt->format.ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT;
703 fmt->format.quantization = V4L2_QUANTIZATION_DEFAULT;
704 fmt->format.xfer_func = V4L2_XFER_FUNC_NONE;
705}
706
707
708
709
710
711
712
713
714
715static int imx412_get_pad_format(struct v4l2_subdev *sd,
716 struct v4l2_subdev_state *sd_state,
717 struct v4l2_subdev_format *fmt)
718{
719 struct imx412 *imx412 = to_imx412(sd);
720
721 mutex_lock(&imx412->mutex);
722
723 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
724 struct v4l2_mbus_framefmt *framefmt;
725
726 framefmt = v4l2_subdev_get_try_format(sd, sd_state, fmt->pad);
727 fmt->format = *framefmt;
728 } else {
729 imx412_fill_pad_format(imx412, imx412->cur_mode, fmt);
730 }
731
732 mutex_unlock(&imx412->mutex);
733
734 return 0;
735}
736
737
738
739
740
741
742
743
744
745static int imx412_set_pad_format(struct v4l2_subdev *sd,
746 struct v4l2_subdev_state *sd_state,
747 struct v4l2_subdev_format *fmt)
748{
749 struct imx412 *imx412 = to_imx412(sd);
750 const struct imx412_mode *mode;
751 int ret = 0;
752
753 mutex_lock(&imx412->mutex);
754
755 mode = &supported_mode;
756 imx412_fill_pad_format(imx412, mode, fmt);
757
758 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
759 struct v4l2_mbus_framefmt *framefmt;
760
761 framefmt = v4l2_subdev_get_try_format(sd, sd_state, fmt->pad);
762 *framefmt = fmt->format;
763 } else {
764 ret = imx412_update_controls(imx412, mode);
765 if (!ret)
766 imx412->cur_mode = mode;
767 }
768
769 mutex_unlock(&imx412->mutex);
770
771 return ret;
772}
773
774
775
776
777
778
779
780
781static int imx412_init_pad_cfg(struct v4l2_subdev *sd,
782 struct v4l2_subdev_state *sd_state)
783{
784 struct imx412 *imx412 = to_imx412(sd);
785 struct v4l2_subdev_format fmt = { 0 };
786
787 fmt.which = sd_state ? V4L2_SUBDEV_FORMAT_TRY : V4L2_SUBDEV_FORMAT_ACTIVE;
788 imx412_fill_pad_format(imx412, &supported_mode, &fmt);
789
790 return imx412_set_pad_format(sd, sd_state, &fmt);
791}
792
793
794
795
796
797
798
799static int imx412_start_streaming(struct imx412 *imx412)
800{
801 const struct imx412_reg_list *reg_list;
802 int ret;
803
804
805 reg_list = &imx412->cur_mode->reg_list;
806 ret = imx412_write_regs(imx412, reg_list->regs,
807 reg_list->num_of_regs);
808 if (ret) {
809 dev_err(imx412->dev, "fail to write initial registers");
810 return ret;
811 }
812
813
814 ret = __v4l2_ctrl_handler_setup(imx412->sd.ctrl_handler);
815 if (ret) {
816 dev_err(imx412->dev, "fail to setup handler");
817 return ret;
818 }
819
820
821 usleep_range(7400, 8000);
822
823
824 ret = imx412_write_reg(imx412, IMX412_REG_MODE_SELECT,
825 1, IMX412_MODE_STREAMING);
826 if (ret) {
827 dev_err(imx412->dev, "fail to start streaming");
828 return ret;
829 }
830
831 return 0;
832}
833
834
835
836
837
838
839
840static int imx412_stop_streaming(struct imx412 *imx412)
841{
842 return imx412_write_reg(imx412, IMX412_REG_MODE_SELECT,
843 1, IMX412_MODE_STANDBY);
844}
845
846
847
848
849
850
851
852
853static int imx412_set_stream(struct v4l2_subdev *sd, int enable)
854{
855 struct imx412 *imx412 = to_imx412(sd);
856 int ret;
857
858 mutex_lock(&imx412->mutex);
859
860 if (imx412->streaming == enable) {
861 mutex_unlock(&imx412->mutex);
862 return 0;
863 }
864
865 if (enable) {
866 ret = pm_runtime_resume_and_get(imx412->dev);
867 if (ret)
868 goto error_unlock;
869
870 ret = imx412_start_streaming(imx412);
871 if (ret)
872 goto error_power_off;
873 } else {
874 imx412_stop_streaming(imx412);
875 pm_runtime_put(imx412->dev);
876 }
877
878 imx412->streaming = enable;
879
880 mutex_unlock(&imx412->mutex);
881
882 return 0;
883
884error_power_off:
885 pm_runtime_put(imx412->dev);
886error_unlock:
887 mutex_unlock(&imx412->mutex);
888
889 return ret;
890}
891
892
893
894
895
896
897
898static int imx412_detect(struct imx412 *imx412)
899{
900 int ret;
901 u32 val;
902
903 ret = imx412_read_reg(imx412, IMX412_REG_ID, 2, &val);
904 if (ret)
905 return ret;
906
907 if (val != IMX412_ID) {
908 dev_err(imx412->dev, "chip id mismatch: %x!=%x",
909 IMX412_ID, val);
910 return -ENXIO;
911 }
912
913 return 0;
914}
915
916
917
918
919
920
921
922static int imx412_parse_hw_config(struct imx412 *imx412)
923{
924 struct fwnode_handle *fwnode = dev_fwnode(imx412->dev);
925 struct v4l2_fwnode_endpoint bus_cfg = {
926 .bus_type = V4L2_MBUS_CSI2_DPHY
927 };
928 struct fwnode_handle *ep;
929 unsigned long rate;
930 unsigned int i;
931 int ret;
932
933 if (!fwnode)
934 return -ENXIO;
935
936
937 imx412->reset_gpio = devm_gpiod_get_optional(imx412->dev, "reset",
938 GPIOD_OUT_LOW);
939 if (IS_ERR(imx412->reset_gpio)) {
940 dev_err(imx412->dev, "failed to get reset gpio %ld",
941 PTR_ERR(imx412->reset_gpio));
942 return PTR_ERR(imx412->reset_gpio);
943 }
944
945
946 imx412->inclk = devm_clk_get(imx412->dev, NULL);
947 if (IS_ERR(imx412->inclk)) {
948 dev_err(imx412->dev, "could not get inclk");
949 return PTR_ERR(imx412->inclk);
950 }
951
952 rate = clk_get_rate(imx412->inclk);
953 if (rate != IMX412_INCLK_RATE) {
954 dev_err(imx412->dev, "inclk frequency mismatch");
955 return -EINVAL;
956 }
957
958
959 for (i = 0; i < ARRAY_SIZE(imx412_supply_names); i++)
960 imx412->supplies[i].supply = imx412_supply_names[i];
961
962 ret = devm_regulator_bulk_get(imx412->dev,
963 ARRAY_SIZE(imx412_supply_names),
964 imx412->supplies);
965 if (ret)
966 return ret;
967
968 ep = fwnode_graph_get_next_endpoint(fwnode, NULL);
969 if (!ep)
970 return -ENXIO;
971
972 ret = v4l2_fwnode_endpoint_alloc_parse(ep, &bus_cfg);
973 fwnode_handle_put(ep);
974 if (ret)
975 return ret;
976
977 if (bus_cfg.bus.mipi_csi2.num_data_lanes != IMX412_NUM_DATA_LANES) {
978 dev_err(imx412->dev,
979 "number of CSI2 data lanes %d is not supported",
980 bus_cfg.bus.mipi_csi2.num_data_lanes);
981 ret = -EINVAL;
982 goto done_endpoint_free;
983 }
984
985 if (!bus_cfg.nr_of_link_frequencies) {
986 dev_err(imx412->dev, "no link frequencies defined");
987 ret = -EINVAL;
988 goto done_endpoint_free;
989 }
990
991 for (i = 0; i < bus_cfg.nr_of_link_frequencies; i++)
992 if (bus_cfg.link_frequencies[i] == IMX412_LINK_FREQ)
993 goto done_endpoint_free;
994
995 ret = -EINVAL;
996
997done_endpoint_free:
998 v4l2_fwnode_endpoint_free(&bus_cfg);
999
1000 return ret;
1001}
1002
1003
1004static const struct v4l2_subdev_video_ops imx412_video_ops = {
1005 .s_stream = imx412_set_stream,
1006};
1007
1008static const struct v4l2_subdev_pad_ops imx412_pad_ops = {
1009 .init_cfg = imx412_init_pad_cfg,
1010 .enum_mbus_code = imx412_enum_mbus_code,
1011 .enum_frame_size = imx412_enum_frame_size,
1012 .get_fmt = imx412_get_pad_format,
1013 .set_fmt = imx412_set_pad_format,
1014};
1015
1016static const struct v4l2_subdev_ops imx412_subdev_ops = {
1017 .video = &imx412_video_ops,
1018 .pad = &imx412_pad_ops,
1019};
1020
1021
1022
1023
1024
1025
1026
1027static int imx412_power_on(struct device *dev)
1028{
1029 struct v4l2_subdev *sd = dev_get_drvdata(dev);
1030 struct imx412 *imx412 = to_imx412(sd);
1031 int ret;
1032
1033 ret = regulator_bulk_enable(ARRAY_SIZE(imx412_supply_names),
1034 imx412->supplies);
1035 if (ret < 0) {
1036 dev_err(dev, "failed to enable regulators\n");
1037 return ret;
1038 }
1039
1040 gpiod_set_value_cansleep(imx412->reset_gpio, 0);
1041
1042 ret = clk_prepare_enable(imx412->inclk);
1043 if (ret) {
1044 dev_err(imx412->dev, "fail to enable inclk");
1045 goto error_reset;
1046 }
1047
1048 usleep_range(1000, 1200);
1049
1050 return 0;
1051
1052error_reset:
1053 gpiod_set_value_cansleep(imx412->reset_gpio, 1);
1054 regulator_bulk_disable(ARRAY_SIZE(imx412_supply_names),
1055 imx412->supplies);
1056
1057 return ret;
1058}
1059
1060
1061
1062
1063
1064
1065
1066static int imx412_power_off(struct device *dev)
1067{
1068 struct v4l2_subdev *sd = dev_get_drvdata(dev);
1069 struct imx412 *imx412 = to_imx412(sd);
1070
1071 clk_disable_unprepare(imx412->inclk);
1072
1073 gpiod_set_value_cansleep(imx412->reset_gpio, 1);
1074
1075 regulator_bulk_disable(ARRAY_SIZE(imx412_supply_names),
1076 imx412->supplies);
1077
1078 return 0;
1079}
1080
1081
1082
1083
1084
1085
1086
1087static int imx412_init_controls(struct imx412 *imx412)
1088{
1089 struct v4l2_ctrl_handler *ctrl_hdlr = &imx412->ctrl_handler;
1090 const struct imx412_mode *mode = imx412->cur_mode;
1091 u32 lpfr;
1092 int ret;
1093
1094 ret = v4l2_ctrl_handler_init(ctrl_hdlr, 6);
1095 if (ret)
1096 return ret;
1097
1098
1099 ctrl_hdlr->lock = &imx412->mutex;
1100
1101
1102 lpfr = mode->vblank + mode->height;
1103 imx412->exp_ctrl = v4l2_ctrl_new_std(ctrl_hdlr,
1104 &imx412_ctrl_ops,
1105 V4L2_CID_EXPOSURE,
1106 IMX412_EXPOSURE_MIN,
1107 lpfr - IMX412_EXPOSURE_OFFSET,
1108 IMX412_EXPOSURE_STEP,
1109 IMX412_EXPOSURE_DEFAULT);
1110
1111 imx412->again_ctrl = v4l2_ctrl_new_std(ctrl_hdlr,
1112 &imx412_ctrl_ops,
1113 V4L2_CID_ANALOGUE_GAIN,
1114 IMX412_AGAIN_MIN,
1115 IMX412_AGAIN_MAX,
1116 IMX412_AGAIN_STEP,
1117 IMX412_AGAIN_DEFAULT);
1118
1119 v4l2_ctrl_cluster(2, &imx412->exp_ctrl);
1120
1121 imx412->vblank_ctrl = v4l2_ctrl_new_std(ctrl_hdlr,
1122 &imx412_ctrl_ops,
1123 V4L2_CID_VBLANK,
1124 mode->vblank_min,
1125 mode->vblank_max,
1126 1, mode->vblank);
1127
1128
1129 imx412->pclk_ctrl = v4l2_ctrl_new_std(ctrl_hdlr,
1130 &imx412_ctrl_ops,
1131 V4L2_CID_PIXEL_RATE,
1132 mode->pclk, mode->pclk,
1133 1, mode->pclk);
1134
1135 imx412->link_freq_ctrl = v4l2_ctrl_new_int_menu(ctrl_hdlr,
1136 &imx412_ctrl_ops,
1137 V4L2_CID_LINK_FREQ,
1138 ARRAY_SIZE(link_freq) -
1139 1,
1140 mode->link_freq_idx,
1141 link_freq);
1142 if (imx412->link_freq_ctrl)
1143 imx412->link_freq_ctrl->flags |= V4L2_CTRL_FLAG_READ_ONLY;
1144
1145 imx412->hblank_ctrl = v4l2_ctrl_new_std(ctrl_hdlr,
1146 &imx412_ctrl_ops,
1147 V4L2_CID_HBLANK,
1148 IMX412_REG_MIN,
1149 IMX412_REG_MAX,
1150 1, mode->hblank);
1151 if (imx412->hblank_ctrl)
1152 imx412->hblank_ctrl->flags |= V4L2_CTRL_FLAG_READ_ONLY;
1153
1154 if (ctrl_hdlr->error) {
1155 dev_err(imx412->dev, "control init failed: %d",
1156 ctrl_hdlr->error);
1157 v4l2_ctrl_handler_free(ctrl_hdlr);
1158 return ctrl_hdlr->error;
1159 }
1160
1161 imx412->sd.ctrl_handler = ctrl_hdlr;
1162
1163 return 0;
1164}
1165
1166
1167
1168
1169
1170
1171
1172static int imx412_probe(struct i2c_client *client)
1173{
1174 struct imx412 *imx412;
1175 int ret;
1176
1177 imx412 = devm_kzalloc(&client->dev, sizeof(*imx412), GFP_KERNEL);
1178 if (!imx412)
1179 return -ENOMEM;
1180
1181 imx412->dev = &client->dev;
1182
1183
1184 v4l2_i2c_subdev_init(&imx412->sd, client, &imx412_subdev_ops);
1185
1186 ret = imx412_parse_hw_config(imx412);
1187 if (ret) {
1188 dev_err(imx412->dev, "HW configuration is not supported");
1189 return ret;
1190 }
1191
1192 mutex_init(&imx412->mutex);
1193
1194 ret = imx412_power_on(imx412->dev);
1195 if (ret) {
1196 dev_err(imx412->dev, "failed to power-on the sensor");
1197 goto error_mutex_destroy;
1198 }
1199
1200
1201 ret = imx412_detect(imx412);
1202 if (ret) {
1203 dev_err(imx412->dev, "failed to find sensor: %d", ret);
1204 goto error_power_off;
1205 }
1206
1207
1208 imx412->cur_mode = &supported_mode;
1209 imx412->vblank = imx412->cur_mode->vblank;
1210
1211 ret = imx412_init_controls(imx412);
1212 if (ret) {
1213 dev_err(imx412->dev, "failed to init controls: %d", ret);
1214 goto error_power_off;
1215 }
1216
1217
1218 imx412->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1219 imx412->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;
1220
1221
1222 imx412->pad.flags = MEDIA_PAD_FL_SOURCE;
1223 ret = media_entity_pads_init(&imx412->sd.entity, 1, &imx412->pad);
1224 if (ret) {
1225 dev_err(imx412->dev, "failed to init entity pads: %d", ret);
1226 goto error_handler_free;
1227 }
1228
1229 ret = v4l2_async_register_subdev_sensor(&imx412->sd);
1230 if (ret < 0) {
1231 dev_err(imx412->dev,
1232 "failed to register async subdev: %d", ret);
1233 goto error_media_entity;
1234 }
1235
1236 pm_runtime_set_active(imx412->dev);
1237 pm_runtime_enable(imx412->dev);
1238 pm_runtime_idle(imx412->dev);
1239
1240 return 0;
1241
1242error_media_entity:
1243 media_entity_cleanup(&imx412->sd.entity);
1244error_handler_free:
1245 v4l2_ctrl_handler_free(imx412->sd.ctrl_handler);
1246error_power_off:
1247 imx412_power_off(imx412->dev);
1248error_mutex_destroy:
1249 mutex_destroy(&imx412->mutex);
1250
1251 return ret;
1252}
1253
1254
1255
1256
1257
1258
1259
1260static int imx412_remove(struct i2c_client *client)
1261{
1262 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1263 struct imx412 *imx412 = to_imx412(sd);
1264
1265 v4l2_async_unregister_subdev(sd);
1266 media_entity_cleanup(&sd->entity);
1267 v4l2_ctrl_handler_free(sd->ctrl_handler);
1268
1269 pm_runtime_disable(&client->dev);
1270 if (!pm_runtime_status_suspended(&client->dev))
1271 imx412_power_off(&client->dev);
1272 pm_runtime_set_suspended(&client->dev);
1273
1274 mutex_destroy(&imx412->mutex);
1275
1276 return 0;
1277}
1278
1279static const struct dev_pm_ops imx412_pm_ops = {
1280 SET_RUNTIME_PM_OPS(imx412_power_off, imx412_power_on, NULL)
1281};
1282
1283static const struct of_device_id imx412_of_match[] = {
1284 { .compatible = "sony,imx412" },
1285 { }
1286};
1287
1288MODULE_DEVICE_TABLE(of, imx412_of_match);
1289
1290static struct i2c_driver imx412_driver = {
1291 .probe_new = imx412_probe,
1292 .remove = imx412_remove,
1293 .driver = {
1294 .name = "imx412",
1295 .pm = &imx412_pm_ops,
1296 .of_match_table = imx412_of_match,
1297 },
1298};
1299
1300module_i2c_driver(imx412_driver);
1301
1302MODULE_DESCRIPTION("Sony imx412 sensor driver");
1303MODULE_LICENSE("GPL");
1304