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9#include <linux/module.h>
10#include <linux/kernel.h>
11#include <linux/slab.h>
12#include <linux/usb.h>
13#include <linux/i2c.h>
14#include "tm6000.h"
15#include "tm6000-regs.h"
16#include <media/v4l2-common.h>
17#include <media/tuner.h>
18
19#define USB_TIMEOUT (5 * HZ)
20
21int tm6000_read_write_usb(struct tm6000_core *dev, u8 req_type, u8 req,
22 u16 value, u16 index, u8 *buf, u16 len)
23{
24 int ret, i;
25 unsigned int pipe;
26 u8 *data = NULL;
27 int delay = 5000;
28
29 if (len) {
30 data = kzalloc(len, GFP_KERNEL);
31 if (!data)
32 return -ENOMEM;
33 }
34
35 mutex_lock(&dev->usb_lock);
36
37 if (req_type & USB_DIR_IN)
38 pipe = usb_rcvctrlpipe(dev->udev, 0);
39 else {
40 pipe = usb_sndctrlpipe(dev->udev, 0);
41 memcpy(data, buf, len);
42 }
43
44 if (tm6000_debug & V4L2_DEBUG_I2C) {
45 printk(KERN_DEBUG "(dev %p, pipe %08x): ", dev->udev, pipe);
46
47 printk(KERN_CONT "%s: %02x %02x %02x %02x %02x %02x %02x %02x ",
48 (req_type & USB_DIR_IN) ? " IN" : "OUT",
49 req_type, req, value&0xff, value>>8, index&0xff,
50 index>>8, len&0xff, len>>8);
51
52 if (!(req_type & USB_DIR_IN)) {
53 printk(KERN_CONT ">>> ");
54 for (i = 0; i < len; i++)
55 printk(KERN_CONT " %02x", buf[i]);
56 printk(KERN_CONT "\n");
57 }
58 }
59
60 ret = usb_control_msg(dev->udev, pipe, req, req_type, value, index,
61 data, len, USB_TIMEOUT);
62
63 if (req_type & USB_DIR_IN)
64 memcpy(buf, data, len);
65
66 if (tm6000_debug & V4L2_DEBUG_I2C) {
67 if (ret < 0) {
68 if (req_type & USB_DIR_IN)
69 printk(KERN_DEBUG "<<< (len=%d)\n", len);
70
71 printk(KERN_CONT "%s: Error #%d\n", __func__, ret);
72 } else if (req_type & USB_DIR_IN) {
73 printk(KERN_CONT "<<< ");
74 for (i = 0; i < len; i++)
75 printk(KERN_CONT " %02x", buf[i]);
76 printk(KERN_CONT "\n");
77 }
78 }
79
80 kfree(data);
81
82 if (dev->quirks & TM6000_QUIRK_NO_USB_DELAY)
83 delay = 0;
84
85 if (req == REQ_16_SET_GET_I2C_WR1_RDN && !(req_type & USB_DIR_IN)) {
86 unsigned int tsleep;
87
88 tsleep = (len * 200) + 200;
89 if (tsleep < delay)
90 tsleep = delay;
91 usleep_range(tsleep, tsleep + 1000);
92 }
93 else if (delay)
94 usleep_range(delay, delay + 1000);
95
96 mutex_unlock(&dev->usb_lock);
97 return ret;
98}
99
100int tm6000_set_reg(struct tm6000_core *dev, u8 req, u16 value, u16 index)
101{
102 return
103 tm6000_read_write_usb(dev, USB_DIR_OUT | USB_TYPE_VENDOR,
104 req, value, index, NULL, 0);
105}
106EXPORT_SYMBOL_GPL(tm6000_set_reg);
107
108int tm6000_get_reg(struct tm6000_core *dev, u8 req, u16 value, u16 index)
109{
110 int rc;
111 u8 buf[1];
112
113 rc = tm6000_read_write_usb(dev, USB_DIR_IN | USB_TYPE_VENDOR, req,
114 value, index, buf, 1);
115
116 if (rc < 0)
117 return rc;
118
119 return *buf;
120}
121EXPORT_SYMBOL_GPL(tm6000_get_reg);
122
123int tm6000_set_reg_mask(struct tm6000_core *dev, u8 req, u16 value,
124 u16 index, u16 mask)
125{
126 int rc;
127 u8 buf[1];
128 u8 new_index;
129
130 rc = tm6000_read_write_usb(dev, USB_DIR_IN | USB_TYPE_VENDOR, req,
131 value, 0, buf, 1);
132
133 if (rc < 0)
134 return rc;
135
136 new_index = (buf[0] & ~mask) | (index & mask);
137
138 if (new_index == buf[0])
139 return 0;
140
141 return tm6000_read_write_usb(dev, USB_DIR_OUT | USB_TYPE_VENDOR,
142 req, value, new_index, NULL, 0);
143}
144EXPORT_SYMBOL_GPL(tm6000_set_reg_mask);
145
146int tm6000_get_reg16(struct tm6000_core *dev, u8 req, u16 value, u16 index)
147{
148 int rc;
149 u8 buf[2];
150
151 rc = tm6000_read_write_usb(dev, USB_DIR_IN | USB_TYPE_VENDOR, req,
152 value, index, buf, 2);
153
154 if (rc < 0)
155 return rc;
156
157 return buf[1]|buf[0]<<8;
158}
159
160int tm6000_get_reg32(struct tm6000_core *dev, u8 req, u16 value, u16 index)
161{
162 int rc;
163 u8 buf[4];
164
165 rc = tm6000_read_write_usb(dev, USB_DIR_IN | USB_TYPE_VENDOR, req,
166 value, index, buf, 4);
167
168 if (rc < 0)
169 return rc;
170
171 return buf[3] | buf[2] << 8 | buf[1] << 16 | buf[0] << 24;
172}
173
174int tm6000_i2c_reset(struct tm6000_core *dev, u16 tsleep)
175{
176 int rc;
177
178 rc = tm6000_set_reg(dev, REQ_03_SET_GET_MCU_PIN, TM6000_GPIO_CLK, 0);
179 if (rc < 0)
180 return rc;
181
182 msleep(tsleep);
183
184 rc = tm6000_set_reg(dev, REQ_03_SET_GET_MCU_PIN, TM6000_GPIO_CLK, 1);
185 msleep(tsleep);
186
187 return rc;
188}
189
190void tm6000_set_fourcc_format(struct tm6000_core *dev)
191{
192 if (dev->dev_type == TM6010) {
193 int val;
194
195 val = tm6000_get_reg(dev, TM6010_REQ07_RCC_ACTIVE_IF, 0) & 0xfc;
196 if (dev->fourcc == V4L2_PIX_FMT_UYVY)
197 tm6000_set_reg(dev, TM6010_REQ07_RCC_ACTIVE_IF, val);
198 else
199 tm6000_set_reg(dev, TM6010_REQ07_RCC_ACTIVE_IF, val | 1);
200 } else {
201 if (dev->fourcc == V4L2_PIX_FMT_UYVY)
202 tm6000_set_reg(dev, TM6010_REQ07_RC1_TRESHOLD, 0xd0);
203 else
204 tm6000_set_reg(dev, TM6010_REQ07_RC1_TRESHOLD, 0x90);
205 }
206}
207
208static void tm6000_set_vbi(struct tm6000_core *dev)
209{
210
211
212
213
214
215
216
217
218 if (dev->dev_type == TM6010) {
219 tm6000_set_reg(dev, TM6010_REQ07_R3F_RESET, 0x01);
220 tm6000_set_reg(dev, TM6010_REQ07_R41_TELETEXT_VBI_CODE1, 0x27);
221 tm6000_set_reg(dev, TM6010_REQ07_R42_VBI_DATA_HIGH_LEVEL, 0x55);
222 tm6000_set_reg(dev, TM6010_REQ07_R43_VBI_DATA_TYPE_LINE7, 0x66);
223 tm6000_set_reg(dev, TM6010_REQ07_R44_VBI_DATA_TYPE_LINE8, 0x66);
224 tm6000_set_reg(dev, TM6010_REQ07_R45_VBI_DATA_TYPE_LINE9, 0x66);
225 tm6000_set_reg(dev,
226 TM6010_REQ07_R46_VBI_DATA_TYPE_LINE10, 0x66);
227 tm6000_set_reg(dev,
228 TM6010_REQ07_R47_VBI_DATA_TYPE_LINE11, 0x66);
229 tm6000_set_reg(dev,
230 TM6010_REQ07_R48_VBI_DATA_TYPE_LINE12, 0x66);
231 tm6000_set_reg(dev,
232 TM6010_REQ07_R49_VBI_DATA_TYPE_LINE13, 0x66);
233 tm6000_set_reg(dev,
234 TM6010_REQ07_R4A_VBI_DATA_TYPE_LINE14, 0x66);
235 tm6000_set_reg(dev,
236 TM6010_REQ07_R4B_VBI_DATA_TYPE_LINE15, 0x66);
237 tm6000_set_reg(dev,
238 TM6010_REQ07_R4C_VBI_DATA_TYPE_LINE16, 0x66);
239 tm6000_set_reg(dev,
240 TM6010_REQ07_R4D_VBI_DATA_TYPE_LINE17, 0x66);
241 tm6000_set_reg(dev,
242 TM6010_REQ07_R4E_VBI_DATA_TYPE_LINE18, 0x66);
243 tm6000_set_reg(dev,
244 TM6010_REQ07_R4F_VBI_DATA_TYPE_LINE19, 0x66);
245 tm6000_set_reg(dev,
246 TM6010_REQ07_R50_VBI_DATA_TYPE_LINE20, 0x66);
247 tm6000_set_reg(dev,
248 TM6010_REQ07_R51_VBI_DATA_TYPE_LINE21, 0x66);
249 tm6000_set_reg(dev,
250 TM6010_REQ07_R52_VBI_DATA_TYPE_LINE22, 0x66);
251 tm6000_set_reg(dev,
252 TM6010_REQ07_R53_VBI_DATA_TYPE_LINE23, 0x00);
253 tm6000_set_reg(dev,
254 TM6010_REQ07_R54_VBI_DATA_TYPE_RLINES, 0x00);
255 tm6000_set_reg(dev,
256 TM6010_REQ07_R55_VBI_LOOP_FILTER_GAIN, 0x01);
257 tm6000_set_reg(dev,
258 TM6010_REQ07_R56_VBI_LOOP_FILTER_I_GAIN, 0x00);
259 tm6000_set_reg(dev,
260 TM6010_REQ07_R57_VBI_LOOP_FILTER_P_GAIN, 0x02);
261 tm6000_set_reg(dev, TM6010_REQ07_R58_VBI_CAPTION_DTO1, 0x35);
262 tm6000_set_reg(dev, TM6010_REQ07_R59_VBI_CAPTION_DTO0, 0xa0);
263 tm6000_set_reg(dev, TM6010_REQ07_R5A_VBI_TELETEXT_DTO1, 0x11);
264 tm6000_set_reg(dev, TM6010_REQ07_R5B_VBI_TELETEXT_DTO0, 0x4c);
265 tm6000_set_reg(dev, TM6010_REQ07_R40_TELETEXT_VBI_CODE0, 0x01);
266 tm6000_set_reg(dev, TM6010_REQ07_R3F_RESET, 0x00);
267 }
268}
269
270int tm6000_init_analog_mode(struct tm6000_core *dev)
271{
272 struct v4l2_frequency f;
273
274 if (dev->dev_type == TM6010) {
275 u8 active = TM6010_REQ07_RCC_ACTIVE_IF_AUDIO_ENABLE;
276
277 if (!dev->radio)
278 active |= TM6010_REQ07_RCC_ACTIVE_IF_VIDEO_ENABLE;
279
280
281 tm6000_set_reg_mask(dev, TM6010_REQ07_RCC_ACTIVE_IF,
282 active, 0x60);
283
284 tm6000_set_reg_mask(dev, TM6010_REQ07_RC0_ACTIVE_VIDEO_SOURCE,
285 0x00, 0x40);
286 } else {
287
288 tm6000_set_reg(dev, TM6010_REQ07_R3F_RESET, 0x01);
289
290 if (dev->scaler)
291
292 tm6000_set_reg(dev, TM6010_REQ07_RC0_ACTIVE_VIDEO_SOURCE, 0x20);
293 else
294 tm6000_set_reg(dev, TM6010_REQ07_RC0_ACTIVE_VIDEO_SOURCE, 0x80);
295
296 tm6000_set_reg(dev, TM6010_REQ07_RC3_HSTART1, 0x88);
297 tm6000_set_reg(dev, TM6000_REQ07_RDA_CLK_SEL, 0x23);
298 tm6000_set_reg(dev, TM6010_REQ07_RD1_ADDR_FOR_REQ1, 0xc0);
299 tm6000_set_reg(dev, TM6010_REQ07_RD2_ADDR_FOR_REQ2, 0xd8);
300 tm6000_set_reg(dev, TM6010_REQ07_RD6_ENDP_REQ1_REQ2, 0x06);
301 tm6000_set_reg(dev, TM6000_REQ07_RDF_PWDOWN_ACLK, 0x1f);
302
303
304 tm6000_set_reg(dev, TM6010_REQ07_RFF_SOFT_RESET, 0x08);
305 tm6000_set_reg(dev, TM6010_REQ07_RFF_SOFT_RESET, 0x00);
306
307 tm6000_set_fourcc_format(dev);
308
309
310 tm6000_set_reg(dev, TM6010_REQ07_R3F_RESET, 0x00);
311 }
312 msleep(20);
313
314
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320
321
322
323
324
325
326 f.frequency = dev->freq;
327 v4l2_device_call_all(&dev->v4l2_dev, 0, tuner, s_frequency, &f);
328
329 msleep(100);
330 tm6000_set_standard(dev);
331 tm6000_set_vbi(dev);
332 tm6000_set_audio_bitrate(dev, 48000);
333
334
335 if (dev->gpio.dvb_led) {
336 tm6000_set_reg(dev, REQ_03_SET_GET_MCU_PIN,
337 dev->gpio.dvb_led, 0x01);
338 }
339
340 return 0;
341}
342
343int tm6000_init_digital_mode(struct tm6000_core *dev)
344{
345 if (dev->dev_type == TM6010) {
346
347 tm6000_set_reg_mask(dev, TM6010_REQ07_RCC_ACTIVE_IF,
348 0x00, 0x60);
349
350 tm6000_set_reg_mask(dev, TM6010_REQ07_RC0_ACTIVE_VIDEO_SOURCE,
351 0x40, 0x40);
352
353 tm6000_set_reg(dev, TM6010_REQ07_RFE_POWER_DOWN, 0x28);
354 tm6000_set_reg(dev, TM6010_REQ08_RE2_POWER_DOWN_CTRL1, 0xfc);
355 tm6000_set_reg(dev, TM6010_REQ08_RE6_POWER_DOWN_CTRL2, 0xff);
356 } else {
357 tm6000_set_reg(dev, TM6010_REQ07_RFF_SOFT_RESET, 0x08);
358 tm6000_set_reg(dev, TM6010_REQ07_RFF_SOFT_RESET, 0x00);
359 tm6000_set_reg(dev, TM6010_REQ07_R3F_RESET, 0x01);
360 tm6000_set_reg(dev, TM6000_REQ07_RDF_PWDOWN_ACLK, 0x08);
361 tm6000_set_reg(dev, TM6000_REQ07_RE2_VADC_STATUS_CTL, 0x0c);
362 tm6000_set_reg(dev, TM6000_REQ07_RE8_VADC_PWDOWN_CTL, 0xff);
363 tm6000_set_reg(dev, TM6000_REQ07_REB_VADC_AADC_MODE, 0xd8);
364 tm6000_set_reg(dev, TM6010_REQ07_RC0_ACTIVE_VIDEO_SOURCE, 0x40);
365 tm6000_set_reg(dev, TM6010_REQ07_RC1_TRESHOLD, 0xd0);
366 tm6000_set_reg(dev, TM6010_REQ07_RC3_HSTART1, 0x09);
367 tm6000_set_reg(dev, TM6000_REQ07_RDA_CLK_SEL, 0x37);
368 tm6000_set_reg(dev, TM6010_REQ07_RD1_ADDR_FOR_REQ1, 0xd8);
369 tm6000_set_reg(dev, TM6010_REQ07_RD2_ADDR_FOR_REQ2, 0xc0);
370 tm6000_set_reg(dev, TM6010_REQ07_RD6_ENDP_REQ1_REQ2, 0x60);
371
372 tm6000_set_reg(dev, TM6000_REQ07_RE2_VADC_STATUS_CTL, 0x0c);
373 tm6000_set_reg(dev, TM6000_REQ07_RE8_VADC_PWDOWN_CTL, 0xff);
374 tm6000_set_reg(dev, TM6000_REQ07_REB_VADC_AADC_MODE, 0x08);
375 msleep(50);
376
377 tm6000_set_reg(dev, REQ_04_EN_DISABLE_MCU_INT, 0x0020, 0x00);
378 msleep(50);
379 tm6000_set_reg(dev, REQ_04_EN_DISABLE_MCU_INT, 0x0020, 0x01);
380 msleep(50);
381 tm6000_set_reg(dev, REQ_04_EN_DISABLE_MCU_INT, 0x0020, 0x00);
382 msleep(100);
383 }
384
385
386 if (dev->gpio.dvb_led) {
387 tm6000_set_reg(dev, REQ_03_SET_GET_MCU_PIN,
388 dev->gpio.dvb_led, 0x00);
389 }
390
391 return 0;
392}
393EXPORT_SYMBOL(tm6000_init_digital_mode);
394
395struct reg_init {
396 u8 req;
397 u8 reg;
398 u8 val;
399};
400
401
402static struct reg_init tm6000_init_tab[] = {
403
404 { TM6000_REQ07_RDF_PWDOWN_ACLK, 0x1f },
405 { TM6010_REQ07_RFF_SOFT_RESET, 0x08 },
406 { TM6010_REQ07_RFF_SOFT_RESET, 0x00 },
407 { TM6010_REQ07_RD5_POWERSAVE, 0x4f },
408 { TM6000_REQ07_RDA_CLK_SEL, 0x23 },
409 { TM6000_REQ07_RDB_OUT_SEL, 0x08 },
410 { TM6000_REQ07_RE2_VADC_STATUS_CTL, 0x00 },
411 { TM6000_REQ07_RE3_VADC_INP_LPF_SEL1, 0x10 },
412 { TM6000_REQ07_RE5_VADC_INP_LPF_SEL2, 0x00 },
413 { TM6000_REQ07_RE8_VADC_PWDOWN_CTL, 0x00 },
414 { TM6000_REQ07_REB_VADC_AADC_MODE, 0x64 },
415 { TM6000_REQ07_REE_VADC_CTRL_SEL_CONTROL, 0xc2 },
416
417 { TM6010_REQ07_R3F_RESET, 0x01 },
418 { TM6010_REQ07_R00_VIDEO_CONTROL0, 0x00 },
419 { TM6010_REQ07_R01_VIDEO_CONTROL1, 0x07 },
420 { TM6010_REQ07_R02_VIDEO_CONTROL2, 0x5f },
421 { TM6010_REQ07_R03_YC_SEP_CONTROL, 0x00 },
422 { TM6010_REQ07_R05_NOISE_THRESHOLD, 0x64 },
423 { TM6010_REQ07_R07_OUTPUT_CONTROL, 0x01 },
424 { TM6010_REQ07_R08_LUMA_CONTRAST_ADJ, 0x82 },
425 { TM6010_REQ07_R09_LUMA_BRIGHTNESS_ADJ, 0x36 },
426 { TM6010_REQ07_R0A_CHROMA_SATURATION_ADJ, 0x50 },
427 { TM6010_REQ07_R0C_CHROMA_AGC_CONTROL, 0x6a },
428 { TM6010_REQ07_R11_AGC_PEAK_CONTROL, 0xc9 },
429 { TM6010_REQ07_R12_AGC_GATE_STARTH, 0x07 },
430 { TM6010_REQ07_R13_AGC_GATE_STARTL, 0x3b },
431 { TM6010_REQ07_R14_AGC_GATE_WIDTH, 0x47 },
432 { TM6010_REQ07_R15_AGC_BP_DELAY, 0x6f },
433 { TM6010_REQ07_R17_HLOOP_MAXSTATE, 0xcd },
434 { TM6010_REQ07_R18_CHROMA_DTO_INCREMENT3, 0x1e },
435 { TM6010_REQ07_R19_CHROMA_DTO_INCREMENT2, 0x8b },
436 { TM6010_REQ07_R1A_CHROMA_DTO_INCREMENT1, 0xa2 },
437 { TM6010_REQ07_R1B_CHROMA_DTO_INCREMENT0, 0xe9 },
438 { TM6010_REQ07_R1C_HSYNC_DTO_INCREMENT3, 0x1c },
439 { TM6010_REQ07_R1D_HSYNC_DTO_INCREMENT2, 0xcc },
440 { TM6010_REQ07_R1E_HSYNC_DTO_INCREMENT1, 0xcc },
441 { TM6010_REQ07_R1F_HSYNC_DTO_INCREMENT0, 0xcd },
442 { TM6010_REQ07_R20_HSYNC_RISING_EDGE_TIME, 0x3c },
443 { TM6010_REQ07_R21_HSYNC_PHASE_OFFSET, 0x3c },
444 { TM6010_REQ07_R2D_CHROMA_BURST_END, 0x48 },
445 { TM6010_REQ07_R2E_ACTIVE_VIDEO_HSTART, 0x88 },
446 { TM6010_REQ07_R30_ACTIVE_VIDEO_VSTART, 0x22 },
447 { TM6010_REQ07_R31_ACTIVE_VIDEO_VHIGHT, 0x61 },
448 { TM6010_REQ07_R32_VSYNC_HLOCK_MIN, 0x74 },
449 { TM6010_REQ07_R33_VSYNC_HLOCK_MAX, 0x1c },
450 { TM6010_REQ07_R34_VSYNC_AGC_MIN, 0x74 },
451 { TM6010_REQ07_R35_VSYNC_AGC_MAX, 0x1c },
452 { TM6010_REQ07_R36_VSYNC_VBI_MIN, 0x7a },
453 { TM6010_REQ07_R37_VSYNC_VBI_MAX, 0x26 },
454 { TM6010_REQ07_R38_VSYNC_THRESHOLD, 0x40 },
455 { TM6010_REQ07_R39_VSYNC_TIME_CONSTANT, 0x0a },
456 { TM6010_REQ07_R42_VBI_DATA_HIGH_LEVEL, 0x55 },
457 { TM6010_REQ07_R51_VBI_DATA_TYPE_LINE21, 0x11 },
458 { TM6010_REQ07_R55_VBI_LOOP_FILTER_GAIN, 0x01 },
459 { TM6010_REQ07_R57_VBI_LOOP_FILTER_P_GAIN, 0x02 },
460 { TM6010_REQ07_R58_VBI_CAPTION_DTO1, 0x35 },
461 { TM6010_REQ07_R59_VBI_CAPTION_DTO0, 0xa0 },
462 { TM6010_REQ07_R80_COMB_FILTER_TRESHOLD, 0x15 },
463 { TM6010_REQ07_R82_COMB_FILTER_CONFIG, 0x42 },
464 { TM6010_REQ07_RC1_TRESHOLD, 0xd0 },
465 { TM6010_REQ07_RC3_HSTART1, 0x88 },
466 { TM6010_REQ07_R3F_RESET, 0x00 },
467 { TM6010_REQ05_R18_IMASK7, 0x00 },
468};
469
470static struct reg_init tm6010_init_tab[] = {
471 { TM6010_REQ07_RC0_ACTIVE_VIDEO_SOURCE, 0x00 },
472 { TM6010_REQ07_RC4_HSTART0, 0xa0 },
473 { TM6010_REQ07_RC6_HEND0, 0x40 },
474 { TM6010_REQ07_RCA_VEND0, 0x31 },
475 { TM6010_REQ07_RCC_ACTIVE_IF, 0xe1 },
476 { TM6010_REQ07_RE0_DVIDEO_SOURCE, 0x03 },
477 { TM6010_REQ07_RFE_POWER_DOWN, 0x7f },
478
479 { TM6010_REQ08_RE2_POWER_DOWN_CTRL1, 0xf0 },
480 { TM6010_REQ08_RE3_ADC_IN1_SEL, 0xf4 },
481 { TM6010_REQ08_RE4_ADC_IN2_SEL, 0xf8 },
482 { TM6010_REQ08_RE6_POWER_DOWN_CTRL2, 0x00 },
483 { TM6010_REQ08_REA_BUFF_DRV_CTRL, 0xf2 },
484 { TM6010_REQ08_REB_SIF_GAIN_CTRL, 0xf0 },
485 { TM6010_REQ08_REC_REVERSE_YC_CTRL, 0xc2 },
486 { TM6010_REQ08_RF0_DAUDIO_INPUT_CONFIG, 0x60 },
487 { TM6010_REQ08_RF1_AADC_POWER_DOWN, 0xfc },
488
489 { TM6010_REQ07_R3F_RESET, 0x01 },
490 { TM6010_REQ07_R00_VIDEO_CONTROL0, 0x00 },
491 { TM6010_REQ07_R01_VIDEO_CONTROL1, 0x07 },
492 { TM6010_REQ07_R02_VIDEO_CONTROL2, 0x5f },
493 { TM6010_REQ07_R03_YC_SEP_CONTROL, 0x00 },
494 { TM6010_REQ07_R05_NOISE_THRESHOLD, 0x64 },
495 { TM6010_REQ07_R07_OUTPUT_CONTROL, 0x01 },
496 { TM6010_REQ07_R08_LUMA_CONTRAST_ADJ, 0x82 },
497 { TM6010_REQ07_R09_LUMA_BRIGHTNESS_ADJ, 0x36 },
498 { TM6010_REQ07_R0A_CHROMA_SATURATION_ADJ, 0x50 },
499 { TM6010_REQ07_R0C_CHROMA_AGC_CONTROL, 0x6a },
500 { TM6010_REQ07_R11_AGC_PEAK_CONTROL, 0xc9 },
501 { TM6010_REQ07_R12_AGC_GATE_STARTH, 0x07 },
502 { TM6010_REQ07_R13_AGC_GATE_STARTL, 0x3b },
503 { TM6010_REQ07_R14_AGC_GATE_WIDTH, 0x47 },
504 { TM6010_REQ07_R15_AGC_BP_DELAY, 0x6f },
505 { TM6010_REQ07_R17_HLOOP_MAXSTATE, 0xcd },
506 { TM6010_REQ07_R18_CHROMA_DTO_INCREMENT3, 0x1e },
507 { TM6010_REQ07_R19_CHROMA_DTO_INCREMENT2, 0x8b },
508 { TM6010_REQ07_R1A_CHROMA_DTO_INCREMENT1, 0xa2 },
509 { TM6010_REQ07_R1B_CHROMA_DTO_INCREMENT0, 0xe9 },
510 { TM6010_REQ07_R1C_HSYNC_DTO_INCREMENT3, 0x1c },
511 { TM6010_REQ07_R1D_HSYNC_DTO_INCREMENT2, 0xcc },
512 { TM6010_REQ07_R1E_HSYNC_DTO_INCREMENT1, 0xcc },
513 { TM6010_REQ07_R1F_HSYNC_DTO_INCREMENT0, 0xcd },
514 { TM6010_REQ07_R20_HSYNC_RISING_EDGE_TIME, 0x3c },
515 { TM6010_REQ07_R21_HSYNC_PHASE_OFFSET, 0x3c },
516 { TM6010_REQ07_R2D_CHROMA_BURST_END, 0x48 },
517 { TM6010_REQ07_R2E_ACTIVE_VIDEO_HSTART, 0x88 },
518 { TM6010_REQ07_R30_ACTIVE_VIDEO_VSTART, 0x22 },
519 { TM6010_REQ07_R31_ACTIVE_VIDEO_VHIGHT, 0x61 },
520 { TM6010_REQ07_R32_VSYNC_HLOCK_MIN, 0x74 },
521 { TM6010_REQ07_R33_VSYNC_HLOCK_MAX, 0x1c },
522 { TM6010_REQ07_R34_VSYNC_AGC_MIN, 0x74 },
523 { TM6010_REQ07_R35_VSYNC_AGC_MAX, 0x1c },
524 { TM6010_REQ07_R36_VSYNC_VBI_MIN, 0x7a },
525 { TM6010_REQ07_R37_VSYNC_VBI_MAX, 0x26 },
526 { TM6010_REQ07_R38_VSYNC_THRESHOLD, 0x40 },
527 { TM6010_REQ07_R39_VSYNC_TIME_CONSTANT, 0x0a },
528 { TM6010_REQ07_R42_VBI_DATA_HIGH_LEVEL, 0x55 },
529 { TM6010_REQ07_R51_VBI_DATA_TYPE_LINE21, 0x11 },
530 { TM6010_REQ07_R55_VBI_LOOP_FILTER_GAIN, 0x01 },
531 { TM6010_REQ07_R57_VBI_LOOP_FILTER_P_GAIN, 0x02 },
532 { TM6010_REQ07_R58_VBI_CAPTION_DTO1, 0x35 },
533 { TM6010_REQ07_R59_VBI_CAPTION_DTO0, 0xa0 },
534 { TM6010_REQ07_R80_COMB_FILTER_TRESHOLD, 0x15 },
535 { TM6010_REQ07_R82_COMB_FILTER_CONFIG, 0x42 },
536 { TM6010_REQ07_RC1_TRESHOLD, 0xd0 },
537 { TM6010_REQ07_RC3_HSTART1, 0x88 },
538 { TM6010_REQ07_R3F_RESET, 0x00 },
539
540 { TM6010_REQ05_R18_IMASK7, 0x00 },
541
542 { TM6010_REQ07_RDC_IR_LEADER1, 0xaa },
543 { TM6010_REQ07_RDD_IR_LEADER0, 0x30 },
544 { TM6010_REQ07_RDE_IR_PULSE_CNT1, 0x20 },
545 { TM6010_REQ07_RDF_IR_PULSE_CNT0, 0xd0 },
546 { REQ_04_EN_DISABLE_MCU_INT, 0x02, 0x00 },
547 { TM6010_REQ07_RD8_IR, 0x0f },
548
549
550 { TM6010_REQ07_RE5_REMOTE_WAKEUP, 0xfe },
551 { TM6010_REQ07_RDA_IR_WAKEUP_SEL, 0xff },
552};
553
554int tm6000_init(struct tm6000_core *dev)
555{
556 int board, rc = 0, i, size;
557 struct reg_init *tab;
558
559
560 board = tm6000_get_reg32(dev, REQ_40_GET_VERSION, 0, 0);
561 if (board >= 0) {
562 switch (board & 0xff) {
563 case 0xf3:
564 printk(KERN_INFO "Found tm6000\n");
565 if (dev->dev_type != TM6000)
566 dev->dev_type = TM6000;
567 break;
568 case 0xf4:
569 printk(KERN_INFO "Found tm6010\n");
570 if (dev->dev_type != TM6010)
571 dev->dev_type = TM6010;
572 break;
573 default:
574 printk(KERN_INFO "Unknown board version = 0x%08x\n", board);
575 }
576 } else
577 printk(KERN_ERR "Error %i while retrieving board version\n", board);
578
579 if (dev->dev_type == TM6010) {
580 tab = tm6010_init_tab;
581 size = ARRAY_SIZE(tm6010_init_tab);
582 } else {
583 tab = tm6000_init_tab;
584 size = ARRAY_SIZE(tm6000_init_tab);
585 }
586
587
588 for (i = 0; i < size; i++) {
589 rc = tm6000_set_reg(dev, tab[i].req, tab[i].reg, tab[i].val);
590 if (rc < 0) {
591 printk(KERN_ERR "Error %i while setting req %d, reg %d to value %d\n",
592 rc,
593 tab[i].req, tab[i].reg, tab[i].val);
594 return rc;
595 }
596 }
597
598 msleep(5);
599
600 rc = tm6000_cards_setup(dev);
601
602 return rc;
603}
604
605
606int tm6000_set_audio_bitrate(struct tm6000_core *dev, int bitrate)
607{
608 int val = 0;
609 u8 areg_f0 = 0x60;
610 u8 areg_0a = 0x91;
611
612 switch (bitrate) {
613 case 48000:
614 areg_f0 = 0x60;
615 areg_0a = 0x91;
616 dev->audio_bitrate = bitrate;
617 break;
618 case 32000:
619 areg_f0 = 0x00;
620 areg_0a = 0x90;
621 dev->audio_bitrate = bitrate;
622 break;
623 default:
624 return -EINVAL;
625 }
626
627
628
629 if (dev->dev_type == TM6010) {
630 val = tm6000_set_reg(dev, TM6010_REQ08_R0A_A_I2S_MOD, areg_0a);
631 if (val < 0)
632 return val;
633
634 val = tm6000_set_reg_mask(dev, TM6010_REQ08_RF0_DAUDIO_INPUT_CONFIG,
635 areg_f0, 0xf0);
636 if (val < 0)
637 return val;
638 } else {
639 val = tm6000_set_reg_mask(dev, TM6000_REQ07_REB_VADC_AADC_MODE,
640 areg_f0, 0xf0);
641 if (val < 0)
642 return val;
643 }
644 return 0;
645}
646EXPORT_SYMBOL_GPL(tm6000_set_audio_bitrate);
647
648int tm6000_set_audio_rinput(struct tm6000_core *dev)
649{
650 if (dev->dev_type == TM6010) {
651
652 u8 areg_f0;
653 u8 areg_07 = 0x10;
654
655 switch (dev->rinput.amux) {
656 case TM6000_AMUX_SIF1:
657 case TM6000_AMUX_SIF2:
658 areg_f0 = 0x03;
659 areg_07 = 0x30;
660 break;
661 case TM6000_AMUX_ADC1:
662 areg_f0 = 0x00;
663 break;
664 case TM6000_AMUX_ADC2:
665 areg_f0 = 0x08;
666 break;
667 case TM6000_AMUX_I2S:
668 areg_f0 = 0x04;
669 break;
670 default:
671 printk(KERN_INFO "%s: audio input doesn't support\n",
672 dev->name);
673 return 0;
674 break;
675 }
676
677 tm6000_set_reg_mask(dev, TM6010_REQ08_RF0_DAUDIO_INPUT_CONFIG,
678 areg_f0, 0x0f);
679
680 tm6000_set_reg_mask(dev, TM6010_REQ07_R07_OUTPUT_CONTROL,
681 areg_07, 0xf0);
682 } else {
683 u8 areg_eb;
684
685 switch (dev->rinput.amux) {
686 case TM6000_AMUX_ADC1:
687 areg_eb = 0x00;
688 break;
689 case TM6000_AMUX_ADC2:
690 areg_eb = 0x04;
691 break;
692 default:
693 printk(KERN_INFO "%s: audio input doesn't support\n",
694 dev->name);
695 return 0;
696 break;
697 }
698
699 tm6000_set_reg_mask(dev, TM6000_REQ07_REB_VADC_AADC_MODE,
700 areg_eb, 0x0f);
701 }
702 return 0;
703}
704
705static void tm6010_set_mute_sif(struct tm6000_core *dev, u8 mute)
706{
707 u8 mute_reg = 0;
708
709 if (mute)
710 mute_reg = 0x08;
711
712 tm6000_set_reg_mask(dev, TM6010_REQ08_R0A_A_I2S_MOD, mute_reg, 0x08);
713}
714
715static void tm6010_set_mute_adc(struct tm6000_core *dev, u8 mute)
716{
717 u8 mute_reg = 0;
718
719 if (mute)
720 mute_reg = 0x20;
721
722 if (dev->dev_type == TM6010) {
723 tm6000_set_reg_mask(dev, TM6010_REQ08_RF2_LEFT_CHANNEL_VOL,
724 mute_reg, 0x20);
725 tm6000_set_reg_mask(dev, TM6010_REQ08_RF3_RIGHT_CHANNEL_VOL,
726 mute_reg, 0x20);
727 } else {
728 tm6000_set_reg_mask(dev, TM6000_REQ07_REC_VADC_AADC_LVOL,
729 mute_reg, 0x20);
730 tm6000_set_reg_mask(dev, TM6000_REQ07_RED_VADC_AADC_RVOL,
731 mute_reg, 0x20);
732 }
733}
734
735int tm6000_tvaudio_set_mute(struct tm6000_core *dev, u8 mute)
736{
737 enum tm6000_mux mux;
738
739 if (dev->radio)
740 mux = dev->rinput.amux;
741 else
742 mux = dev->vinput[dev->input].amux;
743
744 switch (mux) {
745 case TM6000_AMUX_SIF1:
746 case TM6000_AMUX_SIF2:
747 if (dev->dev_type == TM6010)
748 tm6010_set_mute_sif(dev, mute);
749 else {
750 printk(KERN_INFO "ERROR: TM5600 and TM6000 don't has SIF audio inputs. Please check the %s configuration.\n",
751 dev->name);
752 return -EINVAL;
753 }
754 break;
755 case TM6000_AMUX_ADC1:
756 case TM6000_AMUX_ADC2:
757 tm6010_set_mute_adc(dev, mute);
758 break;
759 default:
760 return -EINVAL;
761 break;
762 }
763 return 0;
764}
765
766static void tm6010_set_volume_sif(struct tm6000_core *dev, int vol)
767{
768 u8 vol_reg;
769
770 vol_reg = vol & 0x0F;
771
772 if (vol < 0)
773 vol_reg |= 0x40;
774
775 tm6000_set_reg(dev, TM6010_REQ08_R07_A_LEFT_VOL, vol_reg);
776 tm6000_set_reg(dev, TM6010_REQ08_R08_A_RIGHT_VOL, vol_reg);
777}
778
779static void tm6010_set_volume_adc(struct tm6000_core *dev, int vol)
780{
781 u8 vol_reg;
782
783 vol_reg = (vol + 0x10) & 0x1f;
784
785 if (dev->dev_type == TM6010) {
786 tm6000_set_reg(dev, TM6010_REQ08_RF2_LEFT_CHANNEL_VOL, vol_reg);
787 tm6000_set_reg(dev, TM6010_REQ08_RF3_RIGHT_CHANNEL_VOL, vol_reg);
788 } else {
789 tm6000_set_reg(dev, TM6000_REQ07_REC_VADC_AADC_LVOL, vol_reg);
790 tm6000_set_reg(dev, TM6000_REQ07_RED_VADC_AADC_RVOL, vol_reg);
791 }
792}
793
794void tm6000_set_volume(struct tm6000_core *dev, int vol)
795{
796 enum tm6000_mux mux;
797
798 if (dev->radio) {
799 mux = dev->rinput.amux;
800 vol += 8;
801 } else
802 mux = dev->vinput[dev->input].amux;
803
804 switch (mux) {
805 case TM6000_AMUX_SIF1:
806 case TM6000_AMUX_SIF2:
807 if (dev->dev_type == TM6010)
808 tm6010_set_volume_sif(dev, vol);
809 else
810 printk(KERN_INFO "ERROR: TM5600 and TM6000 don't has SIF audio inputs. Please check the %s configuration.\n",
811 dev->name);
812 break;
813 case TM6000_AMUX_ADC1:
814 case TM6000_AMUX_ADC2:
815 tm6010_set_volume_adc(dev, vol);
816 break;
817 default:
818 break;
819 }
820}
821
822static LIST_HEAD(tm6000_devlist);
823static DEFINE_MUTEX(tm6000_devlist_mutex);
824
825
826
827
828
829void tm6000_remove_from_devlist(struct tm6000_core *dev)
830{
831 mutex_lock(&tm6000_devlist_mutex);
832 list_del(&dev->devlist);
833 mutex_unlock(&tm6000_devlist_mutex);
834};
835
836void tm6000_add_into_devlist(struct tm6000_core *dev)
837{
838 mutex_lock(&tm6000_devlist_mutex);
839 list_add_tail(&dev->devlist, &tm6000_devlist);
840 mutex_unlock(&tm6000_devlist_mutex);
841};
842
843
844
845
846
847static LIST_HEAD(tm6000_extension_devlist);
848
849int tm6000_call_fillbuf(struct tm6000_core *dev, enum tm6000_ops_type type,
850 char *buf, int size)
851{
852 struct tm6000_ops *ops = NULL;
853
854
855
856 list_for_each_entry(ops, &tm6000_extension_devlist, next) {
857 if (ops->fillbuf && ops->type == type)
858 ops->fillbuf(dev, buf, size);
859 }
860
861 return 0;
862}
863
864int tm6000_register_extension(struct tm6000_ops *ops)
865{
866 struct tm6000_core *dev = NULL;
867
868 mutex_lock(&tm6000_devlist_mutex);
869 list_add_tail(&ops->next, &tm6000_extension_devlist);
870 list_for_each_entry(dev, &tm6000_devlist, devlist) {
871 ops->init(dev);
872 printk(KERN_INFO "%s: Initialized (%s) extension\n",
873 dev->name, ops->name);
874 }
875 mutex_unlock(&tm6000_devlist_mutex);
876 return 0;
877}
878EXPORT_SYMBOL(tm6000_register_extension);
879
880void tm6000_unregister_extension(struct tm6000_ops *ops)
881{
882 struct tm6000_core *dev = NULL;
883
884 mutex_lock(&tm6000_devlist_mutex);
885 list_for_each_entry(dev, &tm6000_devlist, devlist)
886 ops->fini(dev);
887
888 printk(KERN_INFO "tm6000: Remove (%s) extension\n", ops->name);
889 list_del(&ops->next);
890 mutex_unlock(&tm6000_devlist_mutex);
891}
892EXPORT_SYMBOL(tm6000_unregister_extension);
893
894void tm6000_init_extension(struct tm6000_core *dev)
895{
896 struct tm6000_ops *ops = NULL;
897
898 mutex_lock(&tm6000_devlist_mutex);
899 list_for_each_entry(ops, &tm6000_extension_devlist, next) {
900 if (ops->init)
901 ops->init(dev);
902 }
903 mutex_unlock(&tm6000_devlist_mutex);
904}
905
906void tm6000_close_extension(struct tm6000_core *dev)
907{
908 struct tm6000_ops *ops = NULL;
909
910 mutex_lock(&tm6000_devlist_mutex);
911 list_for_each_entry(ops, &tm6000_extension_devlist, next) {
912 if (ops->fini)
913 ops->fini(dev);
914 }
915 mutex_unlock(&tm6000_devlist_mutex);
916}
917
