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13#include <linux/sched.h>
14#include <linux/delay.h>
15#include <linux/slab.h>
16#include <linux/module.h>
17#include <linux/bio.h>
18#include <linux/dma-mapping.h>
19#include <linux/crc7.h>
20#include <linux/crc-itu-t.h>
21#include <linux/scatterlist.h>
22
23#include <linux/mmc/host.h>
24#include <linux/mmc/mmc.h>
25#include <linux/mmc/slot-gpio.h>
26
27#include <linux/spi/spi.h>
28#include <linux/spi/mmc_spi.h>
29
30#include <asm/unaligned.h>
31
32
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64
65
66#define SPI_MMC_RESPONSE_CODE(x) ((x) & 0x1f)
67#define SPI_RESPONSE_ACCEPTED ((2 << 1)|1)
68#define SPI_RESPONSE_CRC_ERR ((5 << 1)|1)
69#define SPI_RESPONSE_WRITE_ERR ((6 << 1)|1)
70
71
72
73
74#define SPI_TOKEN_SINGLE 0xfe
75#define SPI_TOKEN_MULTI_WRITE 0xfc
76#define SPI_TOKEN_STOP_TRAN 0xfd
77
78#define MMC_SPI_BLOCKSIZE 512
79
80#define MMC_SPI_R1B_TIMEOUT_MS 3000
81#define MMC_SPI_INIT_TIMEOUT_MS 3000
82
83
84
85
86
87
88
89
90#define MMC_SPI_BLOCKSATONCE 128
91
92
93
94
95
96
97
98
99struct scratch {
100 u8 status[29];
101 u8 data_token;
102 __be16 crc_val;
103};
104
105struct mmc_spi_host {
106 struct mmc_host *mmc;
107 struct spi_device *spi;
108
109 unsigned char power_mode;
110 u16 powerup_msecs;
111
112 struct mmc_spi_platform_data *pdata;
113
114
115 struct spi_transfer token, t, crc, early_status;
116 struct spi_message m;
117
118
119 struct spi_transfer status;
120 struct spi_message readback;
121
122
123 struct device *dma_dev;
124
125
126 struct scratch *data;
127 dma_addr_t data_dma;
128
129
130
131
132
133 void *ones;
134 dma_addr_t ones_dma;
135};
136
137
138
139
140
141
142
143
144static inline int mmc_cs_off(struct mmc_spi_host *host)
145{
146
147 return spi_setup(host->spi);
148}
149
150static int
151mmc_spi_readbytes(struct mmc_spi_host *host, unsigned len)
152{
153 int status;
154
155 if (len > sizeof(*host->data)) {
156 WARN_ON(1);
157 return -EIO;
158 }
159
160 host->status.len = len;
161
162 if (host->dma_dev)
163 dma_sync_single_for_device(host->dma_dev,
164 host->data_dma, sizeof(*host->data),
165 DMA_FROM_DEVICE);
166
167 status = spi_sync_locked(host->spi, &host->readback);
168
169 if (host->dma_dev)
170 dma_sync_single_for_cpu(host->dma_dev,
171 host->data_dma, sizeof(*host->data),
172 DMA_FROM_DEVICE);
173
174 return status;
175}
176
177static int mmc_spi_skip(struct mmc_spi_host *host, unsigned long timeout,
178 unsigned n, u8 byte)
179{
180 u8 *cp = host->data->status;
181 unsigned long start = jiffies;
182
183 do {
184 int status;
185 unsigned i;
186
187 status = mmc_spi_readbytes(host, n);
188 if (status < 0)
189 return status;
190
191 for (i = 0; i < n; i++) {
192 if (cp[i] != byte)
193 return cp[i];
194 }
195
196
197 cond_resched();
198 } while (time_is_after_jiffies(start + timeout));
199 return -ETIMEDOUT;
200}
201
202static inline int
203mmc_spi_wait_unbusy(struct mmc_spi_host *host, unsigned long timeout)
204{
205 return mmc_spi_skip(host, timeout, sizeof(host->data->status), 0);
206}
207
208static int mmc_spi_readtoken(struct mmc_spi_host *host, unsigned long timeout)
209{
210 return mmc_spi_skip(host, timeout, 1, 0xff);
211}
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221
222
223static char *maptype(struct mmc_command *cmd)
224{
225 switch (mmc_spi_resp_type(cmd)) {
226 case MMC_RSP_SPI_R1: return "R1";
227 case MMC_RSP_SPI_R1B: return "R1B";
228 case MMC_RSP_SPI_R2: return "R2/R5";
229 case MMC_RSP_SPI_R3: return "R3/R4/R7";
230 default: return "?";
231 }
232}
233
234
235static int mmc_spi_response_get(struct mmc_spi_host *host,
236 struct mmc_command *cmd, int cs_on)
237{
238 unsigned long timeout_ms;
239 u8 *cp = host->data->status;
240 u8 *end = cp + host->t.len;
241 int value = 0;
242 int bitshift;
243 u8 leftover = 0;
244 unsigned short rotator;
245 int i;
246 char tag[32];
247
248 snprintf(tag, sizeof(tag), " ... CMD%d response SPI_%s",
249 cmd->opcode, maptype(cmd));
250
251
252
253
254
255
256
257 cp += 8;
258 while (cp < end && *cp == 0xff)
259 cp++;
260
261
262 if (cp == end) {
263 cp = host->data->status;
264 end = cp+1;
265
266
267
268
269
270
271
272
273
274
275
276
277 for (i = 2; i < 16; i++) {
278 value = mmc_spi_readbytes(host, 1);
279 if (value < 0)
280 goto done;
281 if (*cp != 0xff)
282 goto checkstatus;
283 }
284 value = -ETIMEDOUT;
285 goto done;
286 }
287
288checkstatus:
289 bitshift = 0;
290 if (*cp & 0x80) {
291
292 rotator = *cp++ << 8;
293
294 if (cp == end) {
295 value = mmc_spi_readbytes(host, 1);
296 if (value < 0)
297 goto done;
298 cp = host->data->status;
299 end = cp+1;
300 }
301 rotator |= *cp++;
302 while (rotator & 0x8000) {
303 bitshift++;
304 rotator <<= 1;
305 }
306 cmd->resp[0] = rotator >> 8;
307 leftover = rotator;
308 } else {
309 cmd->resp[0] = *cp++;
310 }
311 cmd->error = 0;
312
313
314 if (cmd->resp[0] != 0) {
315 if ((R1_SPI_PARAMETER | R1_SPI_ADDRESS)
316 & cmd->resp[0])
317 value = -EFAULT;
318 else if (R1_SPI_ILLEGAL_COMMAND & cmd->resp[0])
319 value = -ENOSYS;
320 else if (R1_SPI_COM_CRC & cmd->resp[0])
321 value = -EILSEQ;
322 else if ((R1_SPI_ERASE_SEQ | R1_SPI_ERASE_RESET)
323 & cmd->resp[0])
324 value = -EIO;
325
326 }
327
328 switch (mmc_spi_resp_type(cmd)) {
329
330
331
332
333 case MMC_RSP_SPI_R1B:
334
335 while (cp < end && *cp == 0)
336 cp++;
337 if (cp == end) {
338 timeout_ms = cmd->busy_timeout ? cmd->busy_timeout :
339 MMC_SPI_R1B_TIMEOUT_MS;
340 mmc_spi_wait_unbusy(host, msecs_to_jiffies(timeout_ms));
341 }
342 break;
343
344
345
346
347 case MMC_RSP_SPI_R2:
348
349 if (cp == end) {
350 value = mmc_spi_readbytes(host, 1);
351 if (value < 0)
352 goto done;
353 cp = host->data->status;
354 end = cp+1;
355 }
356 if (bitshift) {
357 rotator = leftover << 8;
358 rotator |= *cp << bitshift;
359 cmd->resp[0] |= (rotator & 0xFF00);
360 } else {
361 cmd->resp[0] |= *cp << 8;
362 }
363 break;
364
365
366 case MMC_RSP_SPI_R3:
367 rotator = leftover << 8;
368 cmd->resp[1] = 0;
369 for (i = 0; i < 4; i++) {
370 cmd->resp[1] <<= 8;
371
372 if (cp == end) {
373 value = mmc_spi_readbytes(host, 1);
374 if (value < 0)
375 goto done;
376 cp = host->data->status;
377 end = cp+1;
378 }
379 if (bitshift) {
380 rotator |= *cp++ << bitshift;
381 cmd->resp[1] |= (rotator >> 8);
382 rotator <<= 8;
383 } else {
384 cmd->resp[1] |= *cp++;
385 }
386 }
387 break;
388
389
390 case MMC_RSP_SPI_R1:
391 break;
392
393 default:
394 dev_dbg(&host->spi->dev, "bad response type %04x\n",
395 mmc_spi_resp_type(cmd));
396 if (value >= 0)
397 value = -EINVAL;
398 goto done;
399 }
400
401 if (value < 0)
402 dev_dbg(&host->spi->dev, "%s: resp %04x %08x\n",
403 tag, cmd->resp[0], cmd->resp[1]);
404
405
406 if (value >= 0 && cs_on)
407 return value;
408done:
409 if (value < 0)
410 cmd->error = value;
411 mmc_cs_off(host);
412 return value;
413}
414
415
416
417
418
419
420
421static int
422mmc_spi_command_send(struct mmc_spi_host *host,
423 struct mmc_request *mrq,
424 struct mmc_command *cmd, int cs_on)
425{
426 struct scratch *data = host->data;
427 u8 *cp = data->status;
428 int status;
429 struct spi_transfer *t;
430
431
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441
442
443
444 memset(cp, 0xff, sizeof(data->status));
445
446 cp[1] = 0x40 | cmd->opcode;
447 put_unaligned_be32(cmd->arg, cp + 2);
448 cp[6] = crc7_be(0, cp + 1, 5) | 0x01;
449 cp += 7;
450
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484
485
486 if (cs_on && (mrq->data->flags & MMC_DATA_READ)) {
487 cp += 2;
488
489 } else {
490 cp += 10;
491 if (cmd->flags & MMC_RSP_SPI_S2)
492 cp++;
493 else if (cmd->flags & MMC_RSP_SPI_B4)
494 cp += 4;
495 else if (cmd->flags & MMC_RSP_BUSY)
496 cp = data->status + sizeof(data->status);
497
498 }
499
500 dev_dbg(&host->spi->dev, " CMD%d, resp %s\n",
501 cmd->opcode, maptype(cmd));
502
503
504 spi_message_init(&host->m);
505
506 t = &host->t;
507 memset(t, 0, sizeof(*t));
508 t->tx_buf = t->rx_buf = data->status;
509 t->tx_dma = t->rx_dma = host->data_dma;
510 t->len = cp - data->status;
511 t->cs_change = 1;
512 spi_message_add_tail(t, &host->m);
513
514 if (host->dma_dev) {
515 host->m.is_dma_mapped = 1;
516 dma_sync_single_for_device(host->dma_dev,
517 host->data_dma, sizeof(*host->data),
518 DMA_BIDIRECTIONAL);
519 }
520 status = spi_sync_locked(host->spi, &host->m);
521
522 if (host->dma_dev)
523 dma_sync_single_for_cpu(host->dma_dev,
524 host->data_dma, sizeof(*host->data),
525 DMA_BIDIRECTIONAL);
526 if (status < 0) {
527 dev_dbg(&host->spi->dev, " ... write returned %d\n", status);
528 cmd->error = status;
529 return status;
530 }
531
532
533 return mmc_spi_response_get(host, cmd, cs_on);
534}
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545
546
547static void
548mmc_spi_setup_data_message(
549 struct mmc_spi_host *host,
550 bool multiple,
551 enum dma_data_direction direction)
552{
553 struct spi_transfer *t;
554 struct scratch *scratch = host->data;
555 dma_addr_t dma = host->data_dma;
556
557 spi_message_init(&host->m);
558 if (dma)
559 host->m.is_dma_mapped = 1;
560
561
562
563
564 if (direction == DMA_TO_DEVICE) {
565 t = &host->token;
566 memset(t, 0, sizeof(*t));
567 t->len = 1;
568 if (multiple)
569 scratch->data_token = SPI_TOKEN_MULTI_WRITE;
570 else
571 scratch->data_token = SPI_TOKEN_SINGLE;
572 t->tx_buf = &scratch->data_token;
573 if (dma)
574 t->tx_dma = dma + offsetof(struct scratch, data_token);
575 spi_message_add_tail(t, &host->m);
576 }
577
578
579
580
581 t = &host->t;
582 memset(t, 0, sizeof(*t));
583 t->tx_buf = host->ones;
584 t->tx_dma = host->ones_dma;
585
586 spi_message_add_tail(t, &host->m);
587
588 t = &host->crc;
589 memset(t, 0, sizeof(*t));
590 t->len = 2;
591 if (direction == DMA_TO_DEVICE) {
592
593 t->tx_buf = &scratch->crc_val;
594 if (dma)
595 t->tx_dma = dma + offsetof(struct scratch, crc_val);
596 } else {
597 t->tx_buf = host->ones;
598 t->tx_dma = host->ones_dma;
599 t->rx_buf = &scratch->crc_val;
600 if (dma)
601 t->rx_dma = dma + offsetof(struct scratch, crc_val);
602 }
603 spi_message_add_tail(t, &host->m);
604
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616
617
618
619 if (multiple || direction == DMA_TO_DEVICE) {
620 t = &host->early_status;
621 memset(t, 0, sizeof(*t));
622 t->len = (direction == DMA_TO_DEVICE) ? sizeof(scratch->status) : 1;
623 t->tx_buf = host->ones;
624 t->tx_dma = host->ones_dma;
625 t->rx_buf = scratch->status;
626 if (dma)
627 t->rx_dma = dma + offsetof(struct scratch, status);
628 t->cs_change = 1;
629 spi_message_add_tail(t, &host->m);
630 }
631}
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642
643
644
645static int
646mmc_spi_writeblock(struct mmc_spi_host *host, struct spi_transfer *t,
647 unsigned long timeout)
648{
649 struct spi_device *spi = host->spi;
650 int status, i;
651 struct scratch *scratch = host->data;
652 u32 pattern;
653
654 if (host->mmc->use_spi_crc)
655 scratch->crc_val = cpu_to_be16(crc_itu_t(0, t->tx_buf, t->len));
656 if (host->dma_dev)
657 dma_sync_single_for_device(host->dma_dev,
658 host->data_dma, sizeof(*scratch),
659 DMA_BIDIRECTIONAL);
660
661 status = spi_sync_locked(spi, &host->m);
662
663 if (status != 0) {
664 dev_dbg(&spi->dev, "write error (%d)\n", status);
665 return status;
666 }
667
668 if (host->dma_dev)
669 dma_sync_single_for_cpu(host->dma_dev,
670 host->data_dma, sizeof(*scratch),
671 DMA_BIDIRECTIONAL);
672
673
674
675
676
677
678
679
680
681
682
683
684
685 pattern = get_unaligned_be32(scratch->status);
686
687
688 pattern |= 0xE0000000;
689
690
691 while (pattern & 0x80000000)
692 pattern <<= 1;
693
694 pattern >>= 27;
695
696 switch (pattern) {
697 case SPI_RESPONSE_ACCEPTED:
698 status = 0;
699 break;
700 case SPI_RESPONSE_CRC_ERR:
701
702 status = -EILSEQ;
703 break;
704 case SPI_RESPONSE_WRITE_ERR:
705
706
707
708 status = -EIO;
709 break;
710 default:
711 status = -EPROTO;
712 break;
713 }
714 if (status != 0) {
715 dev_dbg(&spi->dev, "write error %02x (%d)\n",
716 scratch->status[0], status);
717 return status;
718 }
719
720 t->tx_buf += t->len;
721 if (host->dma_dev)
722 t->tx_dma += t->len;
723
724
725
726
727 for (i = 4; i < sizeof(scratch->status); i++) {
728
729 if (scratch->status[i] & 0x01)
730 return 0;
731 }
732 return mmc_spi_wait_unbusy(host, timeout);
733}
734
735
736
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739
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746
747
748
749
750
751static int
752mmc_spi_readblock(struct mmc_spi_host *host, struct spi_transfer *t,
753 unsigned long timeout)
754{
755 struct spi_device *spi = host->spi;
756 int status;
757 struct scratch *scratch = host->data;
758 unsigned int bitshift;
759 u8 leftover;
760
761
762
763
764 status = mmc_spi_readbytes(host, 1);
765 if (status < 0)
766 return status;
767 status = scratch->status[0];
768 if (status == 0xff || status == 0)
769 status = mmc_spi_readtoken(host, timeout);
770
771 if (status < 0) {
772 dev_dbg(&spi->dev, "read error %02x (%d)\n", status, status);
773 return status;
774 }
775
776
777
778
779 bitshift = 7;
780 while (status & 0x80) {
781 status <<= 1;
782 bitshift--;
783 }
784 leftover = status << 1;
785
786 if (host->dma_dev) {
787 dma_sync_single_for_device(host->dma_dev,
788 host->data_dma, sizeof(*scratch),
789 DMA_BIDIRECTIONAL);
790 dma_sync_single_for_device(host->dma_dev,
791 t->rx_dma, t->len,
792 DMA_FROM_DEVICE);
793 }
794
795 status = spi_sync_locked(spi, &host->m);
796 if (status < 0) {
797 dev_dbg(&spi->dev, "read error %d\n", status);
798 return status;
799 }
800
801 if (host->dma_dev) {
802 dma_sync_single_for_cpu(host->dma_dev,
803 host->data_dma, sizeof(*scratch),
804 DMA_BIDIRECTIONAL);
805 dma_sync_single_for_cpu(host->dma_dev,
806 t->rx_dma, t->len,
807 DMA_FROM_DEVICE);
808 }
809
810 if (bitshift) {
811
812
813
814 u8 *cp = t->rx_buf;
815 unsigned int len;
816 unsigned int bitright = 8 - bitshift;
817 u8 temp;
818 for (len = t->len; len; len--) {
819 temp = *cp;
820 *cp++ = leftover | (temp >> bitshift);
821 leftover = temp << bitright;
822 }
823 cp = (u8 *) &scratch->crc_val;
824 temp = *cp;
825 *cp++ = leftover | (temp >> bitshift);
826 leftover = temp << bitright;
827 temp = *cp;
828 *cp = leftover | (temp >> bitshift);
829 }
830
831 if (host->mmc->use_spi_crc) {
832 u16 crc = crc_itu_t(0, t->rx_buf, t->len);
833
834 be16_to_cpus(&scratch->crc_val);
835 if (scratch->crc_val != crc) {
836 dev_dbg(&spi->dev,
837 "read - crc error: crc_val=0x%04x, computed=0x%04x len=%d\n",
838 scratch->crc_val, crc, t->len);
839 return -EILSEQ;
840 }
841 }
842
843 t->rx_buf += t->len;
844 if (host->dma_dev)
845 t->rx_dma += t->len;
846
847 return 0;
848}
849
850
851
852
853
854
855static void
856mmc_spi_data_do(struct mmc_spi_host *host, struct mmc_command *cmd,
857 struct mmc_data *data, u32 blk_size)
858{
859 struct spi_device *spi = host->spi;
860 struct device *dma_dev = host->dma_dev;
861 struct spi_transfer *t;
862 enum dma_data_direction direction = mmc_get_dma_dir(data);
863 struct scatterlist *sg;
864 unsigned n_sg;
865 bool multiple = (data->blocks > 1);
866 const char *write_or_read = (direction == DMA_TO_DEVICE) ? "write" : "read";
867 u32 clock_rate;
868 unsigned long timeout;
869
870 mmc_spi_setup_data_message(host, multiple, direction);
871 t = &host->t;
872
873 if (t->speed_hz)
874 clock_rate = t->speed_hz;
875 else
876 clock_rate = spi->max_speed_hz;
877
878 timeout = data->timeout_ns / 1000 +
879 data->timeout_clks * 1000000 / clock_rate;
880 timeout = usecs_to_jiffies((unsigned int)timeout) + 1;
881
882
883
884
885 for_each_sg(data->sg, sg, data->sg_len, n_sg) {
886 int status = 0;
887 dma_addr_t dma_addr = 0;
888 void *kmap_addr;
889 unsigned length = sg->length;
890 enum dma_data_direction dir = direction;
891
892
893
894
895 if (dma_dev) {
896
897 if ((sg->offset != 0 || length != PAGE_SIZE)
898 && dir == DMA_FROM_DEVICE)
899 dir = DMA_BIDIRECTIONAL;
900
901 dma_addr = dma_map_page(dma_dev, sg_page(sg), 0,
902 PAGE_SIZE, dir);
903 if (dma_mapping_error(dma_dev, dma_addr)) {
904 data->error = -EFAULT;
905 break;
906 }
907 if (direction == DMA_TO_DEVICE)
908 t->tx_dma = dma_addr + sg->offset;
909 else
910 t->rx_dma = dma_addr + sg->offset;
911 }
912
913
914 kmap_addr = kmap(sg_page(sg));
915 if (direction == DMA_TO_DEVICE)
916 t->tx_buf = kmap_addr + sg->offset;
917 else
918 t->rx_buf = kmap_addr + sg->offset;
919
920
921 while (length) {
922 t->len = min(length, blk_size);
923
924 dev_dbg(&spi->dev, " %s block, %d bytes\n", write_or_read, t->len);
925
926 if (direction == DMA_TO_DEVICE)
927 status = mmc_spi_writeblock(host, t, timeout);
928 else
929 status = mmc_spi_readblock(host, t, timeout);
930 if (status < 0)
931 break;
932
933 data->bytes_xfered += t->len;
934 length -= t->len;
935
936 if (!multiple)
937 break;
938 }
939
940
941 if (direction == DMA_FROM_DEVICE)
942 flush_dcache_page(sg_page(sg));
943 kunmap(sg_page(sg));
944 if (dma_dev)
945 dma_unmap_page(dma_dev, dma_addr, PAGE_SIZE, dir);
946
947 if (status < 0) {
948 data->error = status;
949 dev_dbg(&spi->dev, "%s status %d\n", write_or_read, status);
950 break;
951 }
952 }
953
954
955
956
957
958
959
960 if (direction == DMA_TO_DEVICE && multiple) {
961 struct scratch *scratch = host->data;
962 int tmp;
963 const unsigned statlen = sizeof(scratch->status);
964
965 dev_dbg(&spi->dev, " STOP_TRAN\n");
966
967
968
969
970
971
972 INIT_LIST_HEAD(&host->m.transfers);
973 list_add(&host->early_status.transfer_list,
974 &host->m.transfers);
975
976 memset(scratch->status, 0xff, statlen);
977 scratch->status[0] = SPI_TOKEN_STOP_TRAN;
978
979 host->early_status.tx_buf = host->early_status.rx_buf;
980 host->early_status.tx_dma = host->early_status.rx_dma;
981 host->early_status.len = statlen;
982
983 if (host->dma_dev)
984 dma_sync_single_for_device(host->dma_dev,
985 host->data_dma, sizeof(*scratch),
986 DMA_BIDIRECTIONAL);
987
988 tmp = spi_sync_locked(spi, &host->m);
989
990 if (host->dma_dev)
991 dma_sync_single_for_cpu(host->dma_dev,
992 host->data_dma, sizeof(*scratch),
993 DMA_BIDIRECTIONAL);
994
995 if (tmp < 0) {
996 if (!data->error)
997 data->error = tmp;
998 return;
999 }
1000
1001
1002
1003
1004
1005 for (tmp = 2; tmp < statlen; tmp++) {
1006 if (scratch->status[tmp] != 0)
1007 return;
1008 }
1009 tmp = mmc_spi_wait_unbusy(host, timeout);
1010 if (tmp < 0 && !data->error)
1011 data->error = tmp;
1012 }
1013}
1014
1015
1016
1017
1018
1019
1020
1021static void mmc_spi_request(struct mmc_host *mmc, struct mmc_request *mrq)
1022{
1023 struct mmc_spi_host *host = mmc_priv(mmc);
1024 int status = -EINVAL;
1025 int crc_retry = 5;
1026 struct mmc_command stop;
1027
1028#ifdef DEBUG
1029
1030 {
1031 struct mmc_command *cmd;
1032 int invalid = 0;
1033
1034 cmd = mrq->cmd;
1035 if (!mmc_spi_resp_type(cmd)) {
1036 dev_dbg(&host->spi->dev, "bogus command\n");
1037 cmd->error = -EINVAL;
1038 invalid = 1;
1039 }
1040
1041 cmd = mrq->stop;
1042 if (cmd && !mmc_spi_resp_type(cmd)) {
1043 dev_dbg(&host->spi->dev, "bogus STOP command\n");
1044 cmd->error = -EINVAL;
1045 invalid = 1;
1046 }
1047
1048 if (invalid) {
1049 dump_stack();
1050 mmc_request_done(host->mmc, mrq);
1051 return;
1052 }
1053 }
1054#endif
1055
1056
1057 spi_bus_lock(host->spi->master);
1058
1059crc_recover:
1060
1061 status = mmc_spi_command_send(host, mrq, mrq->cmd, mrq->data != NULL);
1062 if (status == 0 && mrq->data) {
1063 mmc_spi_data_do(host, mrq->cmd, mrq->data, mrq->data->blksz);
1064
1065
1066
1067
1068
1069
1070
1071
1072 if (mrq->data->error == -EILSEQ && crc_retry) {
1073 stop.opcode = MMC_STOP_TRANSMISSION;
1074 stop.arg = 0;
1075 stop.flags = MMC_RSP_SPI_R1B | MMC_RSP_R1B | MMC_CMD_AC;
1076 status = mmc_spi_command_send(host, mrq, &stop, 0);
1077 crc_retry--;
1078 mrq->data->error = 0;
1079 goto crc_recover;
1080 }
1081
1082 if (mrq->stop)
1083 status = mmc_spi_command_send(host, mrq, mrq->stop, 0);
1084 else
1085 mmc_cs_off(host);
1086 }
1087
1088
1089 spi_bus_unlock(host->spi->master);
1090
1091 mmc_request_done(host->mmc, mrq);
1092}
1093
1094
1095
1096
1097
1098
1099
1100
1101
1102static void mmc_spi_initsequence(struct mmc_spi_host *host)
1103{
1104
1105
1106
1107 mmc_spi_wait_unbusy(host, msecs_to_jiffies(MMC_SPI_INIT_TIMEOUT_MS));
1108 mmc_spi_readbytes(host, 10);
1109
1110
1111
1112
1113
1114
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124
1125
1126
1127
1128
1129 host->spi->mode ^= SPI_CS_HIGH;
1130 if (spi_setup(host->spi) != 0) {
1131
1132 dev_warn(&host->spi->dev,
1133 "can't change chip-select polarity\n");
1134 host->spi->mode ^= SPI_CS_HIGH;
1135 } else {
1136 mmc_spi_readbytes(host, 18);
1137
1138 host->spi->mode ^= SPI_CS_HIGH;
1139 if (spi_setup(host->spi) != 0) {
1140
1141 dev_err(&host->spi->dev,
1142 "can't restore chip-select polarity\n");
1143 }
1144 }
1145}
1146
1147static char *mmc_powerstring(u8 power_mode)
1148{
1149 switch (power_mode) {
1150 case MMC_POWER_OFF: return "off";
1151 case MMC_POWER_UP: return "up";
1152 case MMC_POWER_ON: return "on";
1153 }
1154 return "?";
1155}
1156
1157static void mmc_spi_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1158{
1159 struct mmc_spi_host *host = mmc_priv(mmc);
1160
1161 if (host->power_mode != ios->power_mode) {
1162 int canpower;
1163
1164 canpower = host->pdata && host->pdata->setpower;
1165
1166 dev_dbg(&host->spi->dev, "power %s (%d)%s\n",
1167 mmc_powerstring(ios->power_mode),
1168 ios->vdd,
1169 canpower ? ", can switch" : "");
1170
1171
1172
1173
1174 if (canpower) {
1175 switch (ios->power_mode) {
1176 case MMC_POWER_OFF:
1177 case MMC_POWER_UP:
1178 host->pdata->setpower(&host->spi->dev,
1179 ios->vdd);
1180 if (ios->power_mode == MMC_POWER_UP)
1181 msleep(host->powerup_msecs);
1182 }
1183 }
1184
1185
1186 if (ios->power_mode == MMC_POWER_ON)
1187 mmc_spi_initsequence(host);
1188
1189
1190
1191
1192
1193
1194
1195
1196
1197
1198 if (canpower && ios->power_mode == MMC_POWER_OFF) {
1199 int mres;
1200 u8 nullbyte = 0;
1201
1202 host->spi->mode &= ~(SPI_CPOL|SPI_CPHA);
1203 mres = spi_setup(host->spi);
1204 if (mres < 0)
1205 dev_dbg(&host->spi->dev,
1206 "switch to SPI mode 0 failed\n");
1207
1208 if (spi_write(host->spi, &nullbyte, 1) < 0)
1209 dev_dbg(&host->spi->dev,
1210 "put spi signals to low failed\n");
1211
1212
1213
1214
1215
1216
1217
1218
1219
1220
1221 msleep(10);
1222 if (mres == 0) {
1223 host->spi->mode |= (SPI_CPOL|SPI_CPHA);
1224 mres = spi_setup(host->spi);
1225 if (mres < 0)
1226 dev_dbg(&host->spi->dev,
1227 "switch back to SPI mode 3 failed\n");
1228 }
1229 }
1230
1231 host->power_mode = ios->power_mode;
1232 }
1233
1234 if (host->spi->max_speed_hz != ios->clock && ios->clock != 0) {
1235 int status;
1236
1237 host->spi->max_speed_hz = ios->clock;
1238 status = spi_setup(host->spi);
1239 dev_dbg(&host->spi->dev, " clock to %d Hz, %d\n",
1240 host->spi->max_speed_hz, status);
1241 }
1242}
1243
1244static const struct mmc_host_ops mmc_spi_ops = {
1245 .request = mmc_spi_request,
1246 .set_ios = mmc_spi_set_ios,
1247 .get_ro = mmc_gpio_get_ro,
1248 .get_cd = mmc_gpio_get_cd,
1249};
1250
1251
1252
1253
1254
1255
1256
1257
1258static irqreturn_t
1259mmc_spi_detect_irq(int irq, void *mmc)
1260{
1261 struct mmc_spi_host *host = mmc_priv(mmc);
1262 u16 delay_msec = max(host->pdata->detect_delay, (u16)100);
1263
1264 mmc_detect_change(mmc, msecs_to_jiffies(delay_msec));
1265 return IRQ_HANDLED;
1266}
1267
1268#ifdef CONFIG_HAS_DMA
1269static int mmc_spi_dma_alloc(struct mmc_spi_host *host)
1270{
1271 struct spi_device *spi = host->spi;
1272 struct device *dev;
1273
1274 if (!spi->master->dev.parent->dma_mask)
1275 return 0;
1276
1277 dev = spi->master->dev.parent;
1278
1279 host->ones_dma = dma_map_single(dev, host->ones, MMC_SPI_BLOCKSIZE,
1280 DMA_TO_DEVICE);
1281 if (dma_mapping_error(dev, host->ones_dma))
1282 return -ENOMEM;
1283
1284 host->data_dma = dma_map_single(dev, host->data, sizeof(*host->data),
1285 DMA_BIDIRECTIONAL);
1286 if (dma_mapping_error(dev, host->data_dma)) {
1287 dma_unmap_single(dev, host->ones_dma, MMC_SPI_BLOCKSIZE,
1288 DMA_TO_DEVICE);
1289 return -ENOMEM;
1290 }
1291
1292 dma_sync_single_for_cpu(dev, host->data_dma, sizeof(*host->data),
1293 DMA_BIDIRECTIONAL);
1294
1295 host->dma_dev = dev;
1296 return 0;
1297}
1298
1299static void mmc_spi_dma_free(struct mmc_spi_host *host)
1300{
1301 if (!host->dma_dev)
1302 return;
1303
1304 dma_unmap_single(host->dma_dev, host->ones_dma, MMC_SPI_BLOCKSIZE,
1305 DMA_TO_DEVICE);
1306 dma_unmap_single(host->dma_dev, host->data_dma, sizeof(*host->data),
1307 DMA_BIDIRECTIONAL);
1308}
1309#else
1310static inline int mmc_spi_dma_alloc(struct mmc_spi_host *host) { return 0; }
1311static inline void mmc_spi_dma_free(struct mmc_spi_host *host) {}
1312#endif
1313
1314static int mmc_spi_probe(struct spi_device *spi)
1315{
1316 void *ones;
1317 struct mmc_host *mmc;
1318 struct mmc_spi_host *host;
1319 int status;
1320 bool has_ro = false;
1321
1322
1323
1324
1325 if (spi->master->flags & SPI_MASTER_HALF_DUPLEX)
1326 return -EINVAL;
1327
1328
1329
1330
1331
1332
1333
1334 if (spi->mode != SPI_MODE_3)
1335 spi->mode = SPI_MODE_0;
1336 spi->bits_per_word = 8;
1337
1338 status = spi_setup(spi);
1339 if (status < 0) {
1340 dev_dbg(&spi->dev, "needs SPI mode %02x, %d KHz; %d\n",
1341 spi->mode, spi->max_speed_hz / 1000,
1342 status);
1343 return status;
1344 }
1345
1346
1347
1348
1349
1350
1351
1352 status = -ENOMEM;
1353 ones = kmalloc(MMC_SPI_BLOCKSIZE, GFP_KERNEL);
1354 if (!ones)
1355 goto nomem;
1356 memset(ones, 0xff, MMC_SPI_BLOCKSIZE);
1357
1358 mmc = mmc_alloc_host(sizeof(*host), &spi->dev);
1359 if (!mmc)
1360 goto nomem;
1361
1362 mmc->ops = &mmc_spi_ops;
1363 mmc->max_blk_size = MMC_SPI_BLOCKSIZE;
1364 mmc->max_segs = MMC_SPI_BLOCKSATONCE;
1365 mmc->max_req_size = MMC_SPI_BLOCKSATONCE * MMC_SPI_BLOCKSIZE;
1366 mmc->max_blk_count = MMC_SPI_BLOCKSATONCE;
1367
1368 mmc->caps = MMC_CAP_SPI;
1369
1370
1371
1372
1373
1374
1375
1376
1377
1378 mmc->f_min = 400000;
1379 mmc->f_max = spi->max_speed_hz;
1380
1381 host = mmc_priv(mmc);
1382 host->mmc = mmc;
1383 host->spi = spi;
1384
1385 host->ones = ones;
1386
1387 dev_set_drvdata(&spi->dev, mmc);
1388
1389
1390
1391
1392 host->pdata = mmc_spi_get_pdata(spi);
1393 if (host->pdata)
1394 mmc->ocr_avail = host->pdata->ocr_mask;
1395 if (!mmc->ocr_avail) {
1396 dev_warn(&spi->dev, "ASSUMING 3.2-3.4 V slot power\n");
1397 mmc->ocr_avail = MMC_VDD_32_33|MMC_VDD_33_34;
1398 }
1399 if (host->pdata && host->pdata->setpower) {
1400 host->powerup_msecs = host->pdata->powerup_msecs;
1401 if (!host->powerup_msecs || host->powerup_msecs > 250)
1402 host->powerup_msecs = 250;
1403 }
1404
1405
1406 host->data = kmalloc(sizeof(*host->data), GFP_KERNEL);
1407 if (!host->data)
1408 goto fail_nobuf1;
1409
1410 status = mmc_spi_dma_alloc(host);
1411 if (status)
1412 goto fail_dma;
1413
1414
1415 spi_message_init(&host->readback);
1416 host->readback.is_dma_mapped = (host->dma_dev != NULL);
1417
1418 spi_message_add_tail(&host->status, &host->readback);
1419 host->status.tx_buf = host->ones;
1420 host->status.tx_dma = host->ones_dma;
1421 host->status.rx_buf = &host->data->status;
1422 host->status.rx_dma = host->data_dma + offsetof(struct scratch, status);
1423 host->status.cs_change = 1;
1424
1425
1426 if (host->pdata && host->pdata->init) {
1427 status = host->pdata->init(&spi->dev, mmc_spi_detect_irq, mmc);
1428 if (status != 0)
1429 goto fail_glue_init;
1430 }
1431
1432
1433 if (host->pdata) {
1434 mmc->caps |= host->pdata->caps;
1435 mmc->caps2 |= host->pdata->caps2;
1436 }
1437
1438 status = mmc_add_host(mmc);
1439 if (status != 0)
1440 goto fail_add_host;
1441
1442
1443
1444
1445
1446 status = mmc_gpiod_request_cd(mmc, NULL, 0, false, 1000);
1447 if (status == -EPROBE_DEFER)
1448 goto fail_add_host;
1449 if (!status) {
1450
1451
1452
1453
1454
1455 mmc->caps &= ~MMC_CAP_NEEDS_POLL;
1456 mmc_gpiod_request_cd_irq(mmc);
1457 }
1458 mmc_detect_change(mmc, 0);
1459
1460
1461 status = mmc_gpiod_request_ro(mmc, NULL, 1, 0);
1462 if (status == -EPROBE_DEFER)
1463 goto fail_add_host;
1464 if (!status)
1465 has_ro = true;
1466
1467 dev_info(&spi->dev, "SD/MMC host %s%s%s%s%s\n",
1468 dev_name(&mmc->class_dev),
1469 host->dma_dev ? "" : ", no DMA",
1470 has_ro ? "" : ", no WP",
1471 (host->pdata && host->pdata->setpower)
1472 ? "" : ", no poweroff",
1473 (mmc->caps & MMC_CAP_NEEDS_POLL)
1474 ? ", cd polling" : "");
1475 return 0;
1476
1477fail_add_host:
1478 mmc_remove_host(mmc);
1479fail_glue_init:
1480 mmc_spi_dma_free(host);
1481fail_dma:
1482 kfree(host->data);
1483fail_nobuf1:
1484 mmc_spi_put_pdata(spi);
1485 mmc_free_host(mmc);
1486nomem:
1487 kfree(ones);
1488 return status;
1489}
1490
1491
1492static void mmc_spi_remove(struct spi_device *spi)
1493{
1494 struct mmc_host *mmc = dev_get_drvdata(&spi->dev);
1495 struct mmc_spi_host *host = mmc_priv(mmc);
1496
1497
1498 if (host->pdata && host->pdata->exit)
1499 host->pdata->exit(&spi->dev, mmc);
1500
1501 mmc_remove_host(mmc);
1502
1503 mmc_spi_dma_free(host);
1504 kfree(host->data);
1505 kfree(host->ones);
1506
1507 spi->max_speed_hz = mmc->f_max;
1508 mmc_spi_put_pdata(spi);
1509 mmc_free_host(mmc);
1510}
1511
1512static const struct spi_device_id mmc_spi_dev_ids[] = {
1513 { "mmc-spi-slot"},
1514 { },
1515};
1516MODULE_DEVICE_TABLE(spi, mmc_spi_dev_ids);
1517
1518static const struct of_device_id mmc_spi_of_match_table[] = {
1519 { .compatible = "mmc-spi-slot", },
1520 {},
1521};
1522MODULE_DEVICE_TABLE(of, mmc_spi_of_match_table);
1523
1524static struct spi_driver mmc_spi_driver = {
1525 .driver = {
1526 .name = "mmc_spi",
1527 .of_match_table = mmc_spi_of_match_table,
1528 },
1529 .id_table = mmc_spi_dev_ids,
1530 .probe = mmc_spi_probe,
1531 .remove = mmc_spi_remove,
1532};
1533
1534module_spi_driver(mmc_spi_driver);
1535
1536MODULE_AUTHOR("Mike Lavender, David Brownell, Hans-Peter Nilsson, Jan Nikitenko");
1537MODULE_DESCRIPTION("SPI SD/MMC host driver");
1538MODULE_LICENSE("GPL");
1539MODULE_ALIAS("spi:mmc_spi");
1540