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9#ifndef __SDHCI_HW_H
10#define __SDHCI_HW_H
11
12#include <linux/bits.h>
13#include <linux/scatterlist.h>
14#include <linux/compiler.h>
15#include <linux/types.h>
16#include <linux/io.h>
17#include <linux/leds.h>
18#include <linux/interrupt.h>
19
20#include <linux/mmc/host.h>
21
22
23
24
25
26#define SDHCI_DMA_ADDRESS 0x00
27#define SDHCI_ARGUMENT2 SDHCI_DMA_ADDRESS
28#define SDHCI_32BIT_BLK_CNT SDHCI_DMA_ADDRESS
29
30#define SDHCI_BLOCK_SIZE 0x04
31#define SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF))
32
33#define SDHCI_BLOCK_COUNT 0x06
34
35#define SDHCI_ARGUMENT 0x08
36
37#define SDHCI_TRANSFER_MODE 0x0C
38#define SDHCI_TRNS_DMA 0x01
39#define SDHCI_TRNS_BLK_CNT_EN 0x02
40#define SDHCI_TRNS_AUTO_CMD12 0x04
41#define SDHCI_TRNS_AUTO_CMD23 0x08
42#define SDHCI_TRNS_AUTO_SEL 0x0C
43#define SDHCI_TRNS_READ 0x10
44#define SDHCI_TRNS_MULTI 0x20
45
46#define SDHCI_COMMAND 0x0E
47#define SDHCI_CMD_RESP_MASK 0x03
48#define SDHCI_CMD_CRC 0x08
49#define SDHCI_CMD_INDEX 0x10
50#define SDHCI_CMD_DATA 0x20
51#define SDHCI_CMD_ABORTCMD 0xC0
52
53#define SDHCI_CMD_RESP_NONE 0x00
54#define SDHCI_CMD_RESP_LONG 0x01
55#define SDHCI_CMD_RESP_SHORT 0x02
56#define SDHCI_CMD_RESP_SHORT_BUSY 0x03
57
58#define SDHCI_MAKE_CMD(c, f) (((c & 0xff) << 8) | (f & 0xff))
59#define SDHCI_GET_CMD(c) ((c>>8) & 0x3f)
60
61#define SDHCI_RESPONSE 0x10
62
63#define SDHCI_BUFFER 0x20
64
65#define SDHCI_PRESENT_STATE 0x24
66#define SDHCI_CMD_INHIBIT 0x00000001
67#define SDHCI_DATA_INHIBIT 0x00000002
68#define SDHCI_DOING_WRITE 0x00000100
69#define SDHCI_DOING_READ 0x00000200
70#define SDHCI_SPACE_AVAILABLE 0x00000400
71#define SDHCI_DATA_AVAILABLE 0x00000800
72#define SDHCI_CARD_PRESENT 0x00010000
73#define SDHCI_CARD_PRES_SHIFT 16
74#define SDHCI_CD_STABLE 0x00020000
75#define SDHCI_CD_LVL 0x00040000
76#define SDHCI_CD_LVL_SHIFT 18
77#define SDHCI_WRITE_PROTECT 0x00080000
78#define SDHCI_DATA_LVL_MASK 0x00F00000
79#define SDHCI_DATA_LVL_SHIFT 20
80#define SDHCI_DATA_0_LVL_MASK 0x00100000
81#define SDHCI_CMD_LVL 0x01000000
82
83#define SDHCI_HOST_CONTROL 0x28
84#define SDHCI_CTRL_LED 0x01
85#define SDHCI_CTRL_4BITBUS 0x02
86#define SDHCI_CTRL_HISPD 0x04
87#define SDHCI_CTRL_DMA_MASK 0x18
88#define SDHCI_CTRL_SDMA 0x00
89#define SDHCI_CTRL_ADMA1 0x08
90#define SDHCI_CTRL_ADMA32 0x10
91#define SDHCI_CTRL_ADMA64 0x18
92#define SDHCI_CTRL_ADMA3 0x18
93#define SDHCI_CTRL_8BITBUS 0x20
94#define SDHCI_CTRL_CDTEST_INS 0x40
95#define SDHCI_CTRL_CDTEST_EN 0x80
96
97#define SDHCI_POWER_CONTROL 0x29
98#define SDHCI_POWER_ON 0x01
99#define SDHCI_POWER_180 0x0A
100#define SDHCI_POWER_300 0x0C
101#define SDHCI_POWER_330 0x0E
102
103#define SDHCI_BLOCK_GAP_CONTROL 0x2A
104
105#define SDHCI_WAKE_UP_CONTROL 0x2B
106#define SDHCI_WAKE_ON_INT 0x01
107#define SDHCI_WAKE_ON_INSERT 0x02
108#define SDHCI_WAKE_ON_REMOVE 0x04
109
110#define SDHCI_CLOCK_CONTROL 0x2C
111#define SDHCI_DIVIDER_SHIFT 8
112#define SDHCI_DIVIDER_HI_SHIFT 6
113#define SDHCI_DIV_MASK 0xFF
114#define SDHCI_DIV_MASK_LEN 8
115#define SDHCI_DIV_HI_MASK 0x300
116#define SDHCI_PROG_CLOCK_MODE 0x0020
117#define SDHCI_CLOCK_CARD_EN 0x0004
118#define SDHCI_CLOCK_PLL_EN 0x0008
119#define SDHCI_CLOCK_INT_STABLE 0x0002
120#define SDHCI_CLOCK_INT_EN 0x0001
121
122#define SDHCI_TIMEOUT_CONTROL 0x2E
123
124#define SDHCI_SOFTWARE_RESET 0x2F
125#define SDHCI_RESET_ALL 0x01
126#define SDHCI_RESET_CMD 0x02
127#define SDHCI_RESET_DATA 0x04
128
129#define SDHCI_INT_STATUS 0x30
130#define SDHCI_INT_ENABLE 0x34
131#define SDHCI_SIGNAL_ENABLE 0x38
132#define SDHCI_INT_RESPONSE 0x00000001
133#define SDHCI_INT_DATA_END 0x00000002
134#define SDHCI_INT_BLK_GAP 0x00000004
135#define SDHCI_INT_DMA_END 0x00000008
136#define SDHCI_INT_SPACE_AVAIL 0x00000010
137#define SDHCI_INT_DATA_AVAIL 0x00000020
138#define SDHCI_INT_CARD_INSERT 0x00000040
139#define SDHCI_INT_CARD_REMOVE 0x00000080
140#define SDHCI_INT_CARD_INT 0x00000100
141#define SDHCI_INT_RETUNE 0x00001000
142#define SDHCI_INT_CQE 0x00004000
143#define SDHCI_INT_ERROR 0x00008000
144#define SDHCI_INT_TIMEOUT 0x00010000
145#define SDHCI_INT_CRC 0x00020000
146#define SDHCI_INT_END_BIT 0x00040000
147#define SDHCI_INT_INDEX 0x00080000
148#define SDHCI_INT_DATA_TIMEOUT 0x00100000
149#define SDHCI_INT_DATA_CRC 0x00200000
150#define SDHCI_INT_DATA_END_BIT 0x00400000
151#define SDHCI_INT_BUS_POWER 0x00800000
152#define SDHCI_INT_AUTO_CMD_ERR 0x01000000
153#define SDHCI_INT_ADMA_ERROR 0x02000000
154
155#define SDHCI_INT_NORMAL_MASK 0x00007FFF
156#define SDHCI_INT_ERROR_MASK 0xFFFF8000
157
158#define SDHCI_INT_CMD_MASK (SDHCI_INT_RESPONSE | SDHCI_INT_TIMEOUT | \
159 SDHCI_INT_CRC | SDHCI_INT_END_BIT | SDHCI_INT_INDEX | \
160 SDHCI_INT_AUTO_CMD_ERR)
161#define SDHCI_INT_DATA_MASK (SDHCI_INT_DATA_END | SDHCI_INT_DMA_END | \
162 SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | \
163 SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_DATA_CRC | \
164 SDHCI_INT_DATA_END_BIT | SDHCI_INT_ADMA_ERROR | \
165 SDHCI_INT_BLK_GAP)
166#define SDHCI_INT_ALL_MASK ((unsigned int)-1)
167
168#define SDHCI_CQE_INT_ERR_MASK ( \
169 SDHCI_INT_ADMA_ERROR | SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT | \
170 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX | \
171 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT)
172
173#define SDHCI_CQE_INT_MASK (SDHCI_CQE_INT_ERR_MASK | SDHCI_INT_CQE)
174
175#define SDHCI_AUTO_CMD_STATUS 0x3C
176#define SDHCI_AUTO_CMD_TIMEOUT 0x00000002
177#define SDHCI_AUTO_CMD_CRC 0x00000004
178#define SDHCI_AUTO_CMD_END_BIT 0x00000008
179#define SDHCI_AUTO_CMD_INDEX 0x00000010
180
181#define SDHCI_HOST_CONTROL2 0x3E
182#define SDHCI_CTRL_UHS_MASK 0x0007
183#define SDHCI_CTRL_UHS_SDR12 0x0000
184#define SDHCI_CTRL_UHS_SDR25 0x0001
185#define SDHCI_CTRL_UHS_SDR50 0x0002
186#define SDHCI_CTRL_UHS_SDR104 0x0003
187#define SDHCI_CTRL_UHS_DDR50 0x0004
188#define SDHCI_CTRL_HS400 0x0005
189#define SDHCI_CTRL_VDD_180 0x0008
190#define SDHCI_CTRL_DRV_TYPE_MASK 0x0030
191#define SDHCI_CTRL_DRV_TYPE_B 0x0000
192#define SDHCI_CTRL_DRV_TYPE_A 0x0010
193#define SDHCI_CTRL_DRV_TYPE_C 0x0020
194#define SDHCI_CTRL_DRV_TYPE_D 0x0030
195#define SDHCI_CTRL_EXEC_TUNING 0x0040
196#define SDHCI_CTRL_TUNED_CLK 0x0080
197#define SDHCI_CMD23_ENABLE 0x0800
198#define SDHCI_CTRL_V4_MODE 0x1000
199#define SDHCI_CTRL_64BIT_ADDR 0x2000
200#define SDHCI_CTRL_PRESET_VAL_ENABLE 0x8000
201
202#define SDHCI_CAPABILITIES 0x40
203#define SDHCI_TIMEOUT_CLK_MASK GENMASK(5, 0)
204#define SDHCI_TIMEOUT_CLK_SHIFT 0
205#define SDHCI_TIMEOUT_CLK_UNIT 0x00000080
206#define SDHCI_CLOCK_BASE_MASK GENMASK(13, 8)
207#define SDHCI_CLOCK_BASE_SHIFT 8
208#define SDHCI_CLOCK_V3_BASE_MASK GENMASK(15, 8)
209#define SDHCI_MAX_BLOCK_MASK 0x00030000
210#define SDHCI_MAX_BLOCK_SHIFT 16
211#define SDHCI_CAN_DO_8BIT 0x00040000
212#define SDHCI_CAN_DO_ADMA2 0x00080000
213#define SDHCI_CAN_DO_ADMA1 0x00100000
214#define SDHCI_CAN_DO_HISPD 0x00200000
215#define SDHCI_CAN_DO_SDMA 0x00400000
216#define SDHCI_CAN_DO_SUSPEND 0x00800000
217#define SDHCI_CAN_VDD_330 0x01000000
218#define SDHCI_CAN_VDD_300 0x02000000
219#define SDHCI_CAN_VDD_180 0x04000000
220#define SDHCI_CAN_64BIT_V4 0x08000000
221#define SDHCI_CAN_64BIT 0x10000000
222
223#define SDHCI_CAPABILITIES_1 0x44
224#define SDHCI_SUPPORT_SDR50 0x00000001
225#define SDHCI_SUPPORT_SDR104 0x00000002
226#define SDHCI_SUPPORT_DDR50 0x00000004
227#define SDHCI_DRIVER_TYPE_A 0x00000010
228#define SDHCI_DRIVER_TYPE_C 0x00000020
229#define SDHCI_DRIVER_TYPE_D 0x00000040
230#define SDHCI_RETUNING_TIMER_COUNT_MASK GENMASK(11, 8)
231#define SDHCI_USE_SDR50_TUNING 0x00002000
232#define SDHCI_RETUNING_MODE_MASK GENMASK(15, 14)
233#define SDHCI_CLOCK_MUL_MASK GENMASK(23, 16)
234#define SDHCI_CAN_DO_ADMA3 0x08000000
235#define SDHCI_SUPPORT_HS400 0x80000000
236
237#define SDHCI_MAX_CURRENT 0x48
238#define SDHCI_MAX_CURRENT_LIMIT GENMASK(7, 0)
239#define SDHCI_MAX_CURRENT_330_MASK GENMASK(7, 0)
240#define SDHCI_MAX_CURRENT_300_MASK GENMASK(15, 8)
241#define SDHCI_MAX_CURRENT_180_MASK GENMASK(23, 16)
242#define SDHCI_MAX_CURRENT_MULTIPLIER 4
243
244
245
246#define SDHCI_SET_ACMD12_ERROR 0x50
247#define SDHCI_SET_INT_ERROR 0x52
248
249#define SDHCI_ADMA_ERROR 0x54
250
251
252
253#define SDHCI_ADMA_ADDRESS 0x58
254#define SDHCI_ADMA_ADDRESS_HI 0x5C
255
256
257
258#define SDHCI_PRESET_FOR_HIGH_SPEED 0x64
259#define SDHCI_PRESET_FOR_SDR12 0x66
260#define SDHCI_PRESET_FOR_SDR25 0x68
261#define SDHCI_PRESET_FOR_SDR50 0x6A
262#define SDHCI_PRESET_FOR_SDR104 0x6C
263#define SDHCI_PRESET_FOR_DDR50 0x6E
264#define SDHCI_PRESET_FOR_HS400 0x74
265#define SDHCI_PRESET_DRV_MASK GENMASK(15, 14)
266#define SDHCI_PRESET_CLKGEN_SEL BIT(10)
267#define SDHCI_PRESET_SDCLK_FREQ_MASK GENMASK(9, 0)
268
269#define SDHCI_SLOT_INT_STATUS 0xFC
270
271#define SDHCI_HOST_VERSION 0xFE
272#define SDHCI_VENDOR_VER_MASK 0xFF00
273#define SDHCI_VENDOR_VER_SHIFT 8
274#define SDHCI_SPEC_VER_MASK 0x00FF
275#define SDHCI_SPEC_VER_SHIFT 0
276#define SDHCI_SPEC_100 0
277#define SDHCI_SPEC_200 1
278#define SDHCI_SPEC_300 2
279#define SDHCI_SPEC_400 3
280#define SDHCI_SPEC_410 4
281#define SDHCI_SPEC_420 5
282
283
284
285
286
287#define SDHCI_MAX_DIV_SPEC_200 256
288#define SDHCI_MAX_DIV_SPEC_300 2046
289
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291
292
293#define SDHCI_DEFAULT_BOUNDARY_SIZE (512 * 1024)
294#define SDHCI_DEFAULT_BOUNDARY_ARG (ilog2(SDHCI_DEFAULT_BOUNDARY_SIZE) - 12)
295
296
297#define SDHCI_ADMA2_32_DESC_SZ 8
298
299
300struct sdhci_adma2_32_desc {
301 __le16 cmd;
302 __le16 len;
303 __le32 addr;
304} __packed __aligned(4);
305
306
307#define SDHCI_ADMA2_ALIGN 4
308#define SDHCI_ADMA2_MASK (SDHCI_ADMA2_ALIGN - 1)
309
310
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313
314
315#define SDHCI_ADMA2_DESC_ALIGN 8
316
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323
324#define SDHCI_ADMA2_64_DESC_SZ(host) ((host)->v4_mode ? 16 : 12)
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329
330struct sdhci_adma2_64_desc {
331 __le16 cmd;
332 __le16 len;
333 __le32 addr_lo;
334 __le32 addr_hi;
335} __packed __aligned(4);
336
337#define ADMA2_TRAN_VALID 0x21
338#define ADMA2_NOP_END_VALID 0x3
339#define ADMA2_END 0x2
340
341
342
343
344
345
346#define SDHCI_MAX_SEGS 128
347
348
349#define SDHCI_MAX_MRQS 2
350
351
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353
354
355
356
357#define MMC_CMD_TRANSFER_TIME (10 * NSEC_PER_MSEC)
358
359enum sdhci_cookie {
360 COOKIE_UNMAPPED,
361 COOKIE_PRE_MAPPED,
362 COOKIE_MAPPED,
363};
364
365struct sdhci_host {
366
367 const char *hw_name;
368
369 unsigned int quirks;
370
371
372#define SDHCI_QUIRK_CLOCK_BEFORE_RESET (1<<0)
373
374#define SDHCI_QUIRK_FORCE_DMA (1<<1)
375
376#define SDHCI_QUIRK_NO_CARD_NO_RESET (1<<2)
377
378#define SDHCI_QUIRK_SINGLE_POWER_WRITE (1<<3)
379
380#define SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS (1<<4)
381
382#define SDHCI_QUIRK_BROKEN_DMA (1<<5)
383
384#define SDHCI_QUIRK_BROKEN_ADMA (1<<6)
385
386#define SDHCI_QUIRK_32BIT_DMA_ADDR (1<<7)
387
388#define SDHCI_QUIRK_32BIT_DMA_SIZE (1<<8)
389
390#define SDHCI_QUIRK_32BIT_ADMA_SIZE (1<<9)
391
392#define SDHCI_QUIRK_RESET_AFTER_REQUEST (1<<10)
393
394#define SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER (1<<11)
395
396#define SDHCI_QUIRK_BROKEN_TIMEOUT_VAL (1<<12)
397
398#define SDHCI_QUIRK_BROKEN_SMALL_PIO (1<<13)
399
400#define SDHCI_QUIRK_NO_BUSY_IRQ (1<<14)
401
402#define SDHCI_QUIRK_BROKEN_CARD_DETECTION (1<<15)
403
404#define SDHCI_QUIRK_INVERTED_WRITE_PROTECT (1<<16)
405
406#define SDHCI_QUIRK_BROKEN_CQE (1<<17)
407
408#define SDHCI_QUIRK_PIO_NEEDS_DELAY (1<<18)
409
410#define SDHCI_QUIRK_NO_LED (1<<19)
411
412#define SDHCI_QUIRK_FORCE_BLK_SZ_2048 (1<<20)
413
414#define SDHCI_QUIRK_NO_MULTIBLOCK (1<<21)
415
416#define SDHCI_QUIRK_FORCE_1_BIT_DATA (1<<22)
417
418#define SDHCI_QUIRK_DELAY_AFTER_POWER (1<<23)
419
420#define SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK (1<<24)
421
422#define SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN (1<<25)
423
424#define SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC (1<<26)
425
426#define SDHCI_QUIRK_MISSING_CAPS (1<<27)
427
428#define SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12 (1<<28)
429
430#define SDHCI_QUIRK_NO_HISPD_BIT (1<<29)
431
432#define SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC (1<<30)
433
434#define SDHCI_QUIRK_UNSTABLE_RO_DETECT (1<<31)
435
436 unsigned int quirks2;
437
438#define SDHCI_QUIRK2_HOST_OFF_CARD_ON (1<<0)
439#define SDHCI_QUIRK2_HOST_NO_CMD23 (1<<1)
440
441#define SDHCI_QUIRK2_NO_1_8_V (1<<2)
442#define SDHCI_QUIRK2_PRESET_VALUE_BROKEN (1<<3)
443#define SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON (1<<4)
444
445#define SDHCI_QUIRK2_BROKEN_HOST_CONTROL (1<<5)
446
447#define SDHCI_QUIRK2_BROKEN_HS200 (1<<6)
448
449#define SDHCI_QUIRK2_BROKEN_DDR50 (1<<7)
450
451#define SDHCI_QUIRK2_STOP_WITH_TC (1<<8)
452
453#define SDHCI_QUIRK2_BROKEN_64_BIT_DMA (1<<9)
454
455#define SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD (1<<10)
456
457#define SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 (1<<11)
458
459#define SDHCI_QUIRK2_TUNING_WORK_AROUND (1<<12)
460
461#define SDHCI_QUIRK2_SUPPORT_SINGLE (1<<13)
462
463#define SDHCI_QUIRK2_ACMD23_BROKEN (1<<14)
464
465#define SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN (1<<15)
466
467#define SDHCI_QUIRK2_RSP_136_HAS_CRC (1<<16)
468
469
470
471
472#define SDHCI_QUIRK2_DISABLE_HW_TIMEOUT (1<<17)
473
474
475
476
477
478
479#define SDHCI_QUIRK2_USE_32BIT_BLK_CNT (1<<18)
480
481 int irq;
482 void __iomem *ioaddr;
483 phys_addr_t mapbase;
484 char *bounce_buffer;
485 dma_addr_t bounce_addr;
486 unsigned int bounce_buffer_size;
487
488 const struct sdhci_ops *ops;
489
490
491 struct mmc_host *mmc;
492 struct mmc_host_ops mmc_host_ops;
493 u64 dma_mask;
494
495#if IS_ENABLED(CONFIG_LEDS_CLASS)
496 struct led_classdev led;
497 char led_name[32];
498#endif
499
500 spinlock_t lock;
501
502 int flags;
503#define SDHCI_USE_SDMA (1<<0)
504#define SDHCI_USE_ADMA (1<<1)
505#define SDHCI_REQ_USE_DMA (1<<2)
506#define SDHCI_DEVICE_DEAD (1<<3)
507#define SDHCI_SDR50_NEEDS_TUNING (1<<4)
508#define SDHCI_AUTO_CMD12 (1<<6)
509#define SDHCI_AUTO_CMD23 (1<<7)
510#define SDHCI_PV_ENABLED (1<<8)
511#define SDHCI_USE_64_BIT_DMA (1<<12)
512#define SDHCI_HS400_TUNING (1<<13)
513#define SDHCI_SIGNALING_330 (1<<14)
514#define SDHCI_SIGNALING_180 (1<<15)
515#define SDHCI_SIGNALING_120 (1<<16)
516
517 unsigned int version;
518
519 unsigned int max_clk;
520 unsigned int timeout_clk;
521 u8 max_timeout_count;
522 unsigned int clk_mul;
523
524 unsigned int clock;
525 u8 pwr;
526
527 bool runtime_suspended;
528 bool bus_on;
529 bool preset_enabled;
530 bool pending_reset;
531 bool irq_wake_enabled;
532 bool v4_mode;
533 bool use_external_dma;
534 bool always_defer_done;
535
536 struct mmc_request *mrqs_done[SDHCI_MAX_MRQS];
537 struct mmc_command *cmd;
538 struct mmc_command *data_cmd;
539 struct mmc_command *deferred_cmd;
540 struct mmc_data *data;
541 unsigned int data_early:1;
542
543 struct sg_mapping_iter sg_miter;
544 unsigned int blocks;
545
546 int sg_count;
547 int max_adma;
548
549 void *adma_table;
550 void *align_buffer;
551
552 size_t adma_table_sz;
553 size_t align_buffer_sz;
554
555 dma_addr_t adma_addr;
556 dma_addr_t align_addr;
557
558 unsigned int desc_sz;
559 unsigned int alloc_desc_sz;
560
561 struct workqueue_struct *complete_wq;
562 struct work_struct complete_work;
563
564 struct timer_list timer;
565 struct timer_list data_timer;
566
567#if IS_ENABLED(CONFIG_MMC_SDHCI_EXTERNAL_DMA)
568 struct dma_chan *rx_chan;
569 struct dma_chan *tx_chan;
570#endif
571
572 u32 caps;
573 u32 caps1;
574 bool read_caps;
575
576 bool sdhci_core_to_disable_vqmmc;
577 unsigned int ocr_avail_sdio;
578 unsigned int ocr_avail_sd;
579 unsigned int ocr_avail_mmc;
580 u32 ocr_mask;
581
582 unsigned timing;
583
584 u32 thread_isr;
585
586
587 u32 ier;
588
589 bool cqe_on;
590 u32 cqe_ier;
591 u32 cqe_err_ier;
592
593 wait_queue_head_t buf_ready_int;
594 unsigned int tuning_done;
595
596 unsigned int tuning_count;
597 unsigned int tuning_mode;
598 unsigned int tuning_err;
599#define SDHCI_TUNING_MODE_1 0
600#define SDHCI_TUNING_MODE_2 1
601#define SDHCI_TUNING_MODE_3 2
602
603 int tuning_delay;
604 int tuning_loop_count;
605
606
607 u32 sdma_boundary;
608
609
610 u32 adma_table_cnt;
611
612 u64 data_timeout;
613
614 unsigned long private[] ____cacheline_aligned;
615};
616
617struct sdhci_ops {
618#ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
619 u32 (*read_l)(struct sdhci_host *host, int reg);
620 u16 (*read_w)(struct sdhci_host *host, int reg);
621 u8 (*read_b)(struct sdhci_host *host, int reg);
622 void (*write_l)(struct sdhci_host *host, u32 val, int reg);
623 void (*write_w)(struct sdhci_host *host, u16 val, int reg);
624 void (*write_b)(struct sdhci_host *host, u8 val, int reg);
625#endif
626
627 void (*set_clock)(struct sdhci_host *host, unsigned int clock);
628 void (*set_power)(struct sdhci_host *host, unsigned char mode,
629 unsigned short vdd);
630
631 u32 (*irq)(struct sdhci_host *host, u32 intmask);
632
633 int (*set_dma_mask)(struct sdhci_host *host);
634 int (*enable_dma)(struct sdhci_host *host);
635 unsigned int (*get_max_clock)(struct sdhci_host *host);
636 unsigned int (*get_min_clock)(struct sdhci_host *host);
637
638 unsigned int (*get_timeout_clock)(struct sdhci_host *host);
639 unsigned int (*get_max_timeout_count)(struct sdhci_host *host);
640 void (*set_timeout)(struct sdhci_host *host,
641 struct mmc_command *cmd);
642 void (*set_bus_width)(struct sdhci_host *host, int width);
643 void (*platform_send_init_74_clocks)(struct sdhci_host *host,
644 u8 power_mode);
645 unsigned int (*get_ro)(struct sdhci_host *host);
646 void (*reset)(struct sdhci_host *host, u8 mask);
647 int (*platform_execute_tuning)(struct sdhci_host *host, u32 opcode);
648 void (*set_uhs_signaling)(struct sdhci_host *host, unsigned int uhs);
649 void (*hw_reset)(struct sdhci_host *host);
650 void (*adma_workaround)(struct sdhci_host *host, u32 intmask);
651 void (*card_event)(struct sdhci_host *host);
652 void (*voltage_switch)(struct sdhci_host *host);
653 void (*adma_write_desc)(struct sdhci_host *host, void **desc,
654 dma_addr_t addr, int len, unsigned int cmd);
655 void (*copy_to_bounce_buffer)(struct sdhci_host *host,
656 struct mmc_data *data,
657 unsigned int length);
658 void (*request_done)(struct sdhci_host *host,
659 struct mmc_request *mrq);
660 void (*dump_vendor_regs)(struct sdhci_host *host);
661};
662
663#ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
664
665static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg)
666{
667 if (unlikely(host->ops->write_l))
668 host->ops->write_l(host, val, reg);
669 else
670 writel(val, host->ioaddr + reg);
671}
672
673static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg)
674{
675 if (unlikely(host->ops->write_w))
676 host->ops->write_w(host, val, reg);
677 else
678 writew(val, host->ioaddr + reg);
679}
680
681static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg)
682{
683 if (unlikely(host->ops->write_b))
684 host->ops->write_b(host, val, reg);
685 else
686 writeb(val, host->ioaddr + reg);
687}
688
689static inline u32 sdhci_readl(struct sdhci_host *host, int reg)
690{
691 if (unlikely(host->ops->read_l))
692 return host->ops->read_l(host, reg);
693 else
694 return readl(host->ioaddr + reg);
695}
696
697static inline u16 sdhci_readw(struct sdhci_host *host, int reg)
698{
699 if (unlikely(host->ops->read_w))
700 return host->ops->read_w(host, reg);
701 else
702 return readw(host->ioaddr + reg);
703}
704
705static inline u8 sdhci_readb(struct sdhci_host *host, int reg)
706{
707 if (unlikely(host->ops->read_b))
708 return host->ops->read_b(host, reg);
709 else
710 return readb(host->ioaddr + reg);
711}
712
713#else
714
715static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg)
716{
717 writel(val, host->ioaddr + reg);
718}
719
720static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg)
721{
722 writew(val, host->ioaddr + reg);
723}
724
725static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg)
726{
727 writeb(val, host->ioaddr + reg);
728}
729
730static inline u32 sdhci_readl(struct sdhci_host *host, int reg)
731{
732 return readl(host->ioaddr + reg);
733}
734
735static inline u16 sdhci_readw(struct sdhci_host *host, int reg)
736{
737 return readw(host->ioaddr + reg);
738}
739
740static inline u8 sdhci_readb(struct sdhci_host *host, int reg)
741{
742 return readb(host->ioaddr + reg);
743}
744
745#endif
746
747struct sdhci_host *sdhci_alloc_host(struct device *dev, size_t priv_size);
748void sdhci_free_host(struct sdhci_host *host);
749
750static inline void *sdhci_priv(struct sdhci_host *host)
751{
752 return host->private;
753}
754
755void __sdhci_read_caps(struct sdhci_host *host, const u16 *ver,
756 const u32 *caps, const u32 *caps1);
757int sdhci_setup_host(struct sdhci_host *host);
758void sdhci_cleanup_host(struct sdhci_host *host);
759int __sdhci_add_host(struct sdhci_host *host);
760int sdhci_add_host(struct sdhci_host *host);
761void sdhci_remove_host(struct sdhci_host *host, int dead);
762
763static inline void sdhci_read_caps(struct sdhci_host *host)
764{
765 __sdhci_read_caps(host, NULL, NULL, NULL);
766}
767
768u16 sdhci_calc_clk(struct sdhci_host *host, unsigned int clock,
769 unsigned int *actual_clock);
770void sdhci_set_clock(struct sdhci_host *host, unsigned int clock);
771void sdhci_enable_clk(struct sdhci_host *host, u16 clk);
772void sdhci_set_power(struct sdhci_host *host, unsigned char mode,
773 unsigned short vdd);
774void sdhci_set_power_and_bus_voltage(struct sdhci_host *host,
775 unsigned char mode,
776 unsigned short vdd);
777void sdhci_set_power_noreg(struct sdhci_host *host, unsigned char mode,
778 unsigned short vdd);
779int sdhci_get_cd_nogpio(struct mmc_host *mmc);
780void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq);
781int sdhci_request_atomic(struct mmc_host *mmc, struct mmc_request *mrq);
782void sdhci_set_bus_width(struct sdhci_host *host, int width);
783void sdhci_reset(struct sdhci_host *host, u8 mask);
784void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing);
785int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode);
786void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
787int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
788 struct mmc_ios *ios);
789void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable);
790void sdhci_adma_write_desc(struct sdhci_host *host, void **desc,
791 dma_addr_t addr, int len, unsigned int cmd);
792
793#ifdef CONFIG_PM
794int sdhci_suspend_host(struct sdhci_host *host);
795int sdhci_resume_host(struct sdhci_host *host);
796int sdhci_runtime_suspend_host(struct sdhci_host *host);
797int sdhci_runtime_resume_host(struct sdhci_host *host, int soft_reset);
798#endif
799
800void sdhci_cqe_enable(struct mmc_host *mmc);
801void sdhci_cqe_disable(struct mmc_host *mmc, bool recovery);
802bool sdhci_cqe_irq(struct sdhci_host *host, u32 intmask, int *cmd_error,
803 int *data_error);
804
805void sdhci_dumpregs(struct sdhci_host *host);
806void sdhci_enable_v4_mode(struct sdhci_host *host);
807
808void sdhci_start_tuning(struct sdhci_host *host);
809void sdhci_end_tuning(struct sdhci_host *host);
810void sdhci_reset_tuning(struct sdhci_host *host);
811void sdhci_send_tuning(struct sdhci_host *host, u32 opcode);
812void sdhci_abort_tuning(struct sdhci_host *host, u32 opcode);
813void sdhci_switch_external_dma(struct sdhci_host *host, bool en);
814void sdhci_set_data_timeout_irq(struct sdhci_host *host, bool enable);
815void __sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd);
816
817#endif
818