LXR linux/drivers/net/dsa/mv88e6xxx/global2.h

   1/* SPDX-License-Identifier: GPL-2.0-or-later */
   2/*
   3 * Marvell 88E6xxx Switch Global 2 Registers support
   4 *
   5 * Copyright (c) 2008 Marvell Semiconductor
   6 *
   7 * Copyright (c) 2016-2017 Savoir-faire Linux Inc.
   8 *      Vivien Didelot <vivien.didelot@savoirfairelinux.com>
   9 */
  10
  11#ifndef _MV88E6XXX_GLOBAL2_H
  12#define _MV88E6XXX_GLOBAL2_H
  13
  14#include "chip.h"
  15
  16/* Offset 0x00: Interrupt Source Register */
  17#define MV88E6XXX_G2_INT_SRC                    0x00
  18#define MV88E6XXX_G2_INT_SRC_WDOG               0x8000
  19#define MV88E6XXX_G2_INT_SRC_JAM_LIMIT          0x4000
  20#define MV88E6XXX_G2_INT_SRC_DUPLEX_MISMATCH    0x2000
  21#define MV88E6XXX_G2_INT_SRC_WAKE_EVENT         0x1000
  22#define MV88E6352_G2_INT_SRC_SERDES             0x0800
  23#define MV88E6352_G2_INT_SRC_PHY                0x001f
  24#define MV88E6390_G2_INT_SRC_PHY                0x07fe
  25
  26#define MV88E6XXX_G2_INT_SOURCE_WATCHDOG        15
  27
  28/* Offset 0x01: Interrupt Mask Register */
  29#define MV88E6XXX_G2_INT_MASK                   0x01
  30#define MV88E6XXX_G2_INT_MASK_WDOG              0x8000
  31#define MV88E6XXX_G2_INT_MASK_JAM_LIMIT         0x4000
  32#define MV88E6XXX_G2_INT_MASK_DUPLEX_MISMATCH   0x2000
  33#define MV88E6XXX_G2_INT_MASK_WAKE_EVENT        0x1000
  34#define MV88E6352_G2_INT_MASK_SERDES            0x0800
  35#define MV88E6352_G2_INT_MASK_PHY               0x001f
  36#define MV88E6390_G2_INT_MASK_PHY               0x07fe
  37
  38/* Offset 0x02: MGMT Enable Register 2x */
  39#define MV88E6XXX_G2_MGMT_EN_2X         0x02
  40
  41/* Offset 0x02: MAC LINK change IRQ Register for MV88E6393X */
  42#define MV88E6393X_G2_MACLINK_INT_SRC           0x02
  43
  44/* Offset 0x03: MGMT Enable Register 0x */
  45#define MV88E6XXX_G2_MGMT_EN_0X         0x03
  46
  47/* Offset 0x03: MAC LINK change IRQ Mask Register for MV88E6393X */
  48#define MV88E6393X_G2_MACLINK_INT_MASK          0x03
  49
  50/* Offset 0x04: Flow Control Delay Register */
  51#define MV88E6XXX_G2_FLOW_CTL   0x04
  52
  53/* Offset 0x05: Switch Management Register */
  54#define MV88E6XXX_G2_SWITCH_MGMT                        0x05
  55#define MV88E6XXX_G2_SWITCH_MGMT_USE_DOUBLE_TAG_DATA    0x8000
  56#define MV88E6XXX_G2_SWITCH_MGMT_PREVENT_LOOPS          0x4000
  57#define MV88E6XXX_G2_SWITCH_MGMT_FLOW_CTL_MSG           0x2000
  58#define MV88E6XXX_G2_SWITCH_MGMT_FORCE_FLOW_CTL_PRI     0x0080
  59#define MV88E6XXX_G2_SWITCH_MGMT_RSVD2CPU               0x0008
  60
  61#define MV88E6393X_G2_EGRESS_MONITOR_DEST               0x05
  62
  63/* Offset 0x06: Device Mapping Table Register */
  64#define MV88E6XXX_G2_DEVICE_MAPPING             0x06
  65#define MV88E6XXX_G2_DEVICE_MAPPING_UPDATE      0x8000
  66#define MV88E6XXX_G2_DEVICE_MAPPING_DEV_MASK    0x1f00
  67#define MV88E6352_G2_DEVICE_MAPPING_PORT_MASK   0x000f
  68#define MV88E6390_G2_DEVICE_MAPPING_PORT_MASK   0x001f
  69
  70/* Offset 0x07: Trunk Mask Table Register */
  71#define MV88E6XXX_G2_TRUNK_MASK                 0x07
  72#define MV88E6XXX_G2_TRUNK_MASK_UPDATE          0x8000
  73#define MV88E6XXX_G2_TRUNK_MASK_NUM_MASK        0x7000
  74#define MV88E6XXX_G2_TRUNK_MASK_HASH            0x0800
  75
  76/* Offset 0x08: Trunk Mapping Table Register */
  77#define MV88E6XXX_G2_TRUNK_MAPPING              0x08
  78#define MV88E6XXX_G2_TRUNK_MAPPING_UPDATE       0x8000
  79#define MV88E6XXX_G2_TRUNK_MAPPING_ID_MASK      0x7800
  80
  81/* Offset 0x09: Ingress Rate Command Register */
  82#define MV88E6XXX_G2_IRL_CMD                    0x09
  83#define MV88E6XXX_G2_IRL_CMD_BUSY               0x8000
  84#define MV88E6352_G2_IRL_CMD_OP_MASK            0x7000
  85#define MV88E6352_G2_IRL_CMD_OP_NOOP            0x0000
  86#define MV88E6352_G2_IRL_CMD_OP_INIT_ALL        0x1000
  87#define MV88E6352_G2_IRL_CMD_OP_INIT_RES        0x2000
  88#define MV88E6352_G2_IRL_CMD_OP_WRITE_REG       0x3000
  89#define MV88E6352_G2_IRL_CMD_OP_READ_REG        0x4000
  90#define MV88E6390_G2_IRL_CMD_OP_MASK            0x6000
  91#define MV88E6390_G2_IRL_CMD_OP_READ_REG        0x0000
  92#define MV88E6390_G2_IRL_CMD_OP_INIT_ALL        0x2000
  93#define MV88E6390_G2_IRL_CMD_OP_INIT_RES        0x4000
  94#define MV88E6390_G2_IRL_CMD_OP_WRITE_REG       0x6000
  95#define MV88E6352_G2_IRL_CMD_PORT_MASK          0x0f00
  96#define MV88E6390_G2_IRL_CMD_PORT_MASK          0x1f00
  97#define MV88E6XXX_G2_IRL_CMD_RES_MASK           0x00e0
  98#define MV88E6XXX_G2_IRL_CMD_REG_MASK           0x000f
  99
 100/* Offset 0x0A: Ingress Rate Data Register */
 101#define MV88E6XXX_G2_IRL_DATA           0x0a
 102#define MV88E6XXX_G2_IRL_DATA_MASK      0xffff
 103
 104/* Offset 0x0B: Cross-chip Port VLAN Register */
 105#define MV88E6XXX_G2_PVT_ADDR                   0x0b
 106#define MV88E6XXX_G2_PVT_ADDR_BUSY              0x8000
 107#define MV88E6XXX_G2_PVT_ADDR_OP_MASK           0x7000
 108#define MV88E6XXX_G2_PVT_ADDR_OP_INIT_ONES      0x1000
 109#define MV88E6XXX_G2_PVT_ADDR_OP_WRITE_PVLAN    0x3000
 110#define MV88E6XXX_G2_PVT_ADDR_OP_READ           0x4000
 111#define MV88E6XXX_G2_PVT_ADDR_PTR_MASK          0x01ff
 112#define MV88E6XXX_G2_PVT_ADDR_DEV_TRUNK         0x1f
 113
 114/* Offset 0x0C: Cross-chip Port VLAN Data Register */
 115#define MV88E6XXX_G2_PVT_DATA           0x0c
 116#define MV88E6XXX_G2_PVT_DATA_MASK      0x7f
 117
 118/* Offset 0x0D: Switch MAC/WoL/WoF Register */
 119#define MV88E6XXX_G2_SWITCH_MAC                 0x0d
 120#define MV88E6XXX_G2_SWITCH_MAC_UPDATE          0x8000
 121#define MV88E6XXX_G2_SWITCH_MAC_PTR_MASK        0x1f00
 122#define MV88E6XXX_G2_SWITCH_MAC_DATA_MASK       0x00ff
 123
 124/* Offset 0x0E: ATU Stats Register */
 125#define MV88E6XXX_G2_ATU_STATS                          0x0e
 126#define MV88E6XXX_G2_ATU_STATS_BIN_0                    (0x0 << 14)
 127#define MV88E6XXX_G2_ATU_STATS_BIN_1                    (0x1 << 14)
 128#define MV88E6XXX_G2_ATU_STATS_BIN_2                    (0x2 << 14)
 129#define MV88E6XXX_G2_ATU_STATS_BIN_3                    (0x3 << 14)
 130#define MV88E6XXX_G2_ATU_STATS_MODE_ALL                 (0x0 << 12)
 131#define MV88E6XXX_G2_ATU_STATS_MODE_ALL_DYNAMIC         (0x1 << 12)
 132#define MV88E6XXX_G2_ATU_STATS_MODE_FID_ALL             (0x2 << 12)
 133#define MV88E6XXX_G2_ATU_STATS_MODE_FID_ALL_DYNAMIC     (0x3 << 12)
 134#define MV88E6XXX_G2_ATU_STATS_MASK                     0x0fff
 135
 136/* Offset 0x0F: Priority Override Table */
 137#define MV88E6XXX_G2_PRIO_OVERRIDE              0x0f
 138#define MV88E6XXX_G2_PRIO_OVERRIDE_UPDATE       0x8000
 139#define MV88E6XXX_G2_PRIO_OVERRIDE_FPRISET      0x1000
 140#define MV88E6XXX_G2_PRIO_OVERRIDE_PTR_MASK     0x0f00
 141#define MV88E6352_G2_PRIO_OVERRIDE_QPRIAVBEN    0x0080
 142#define MV88E6352_G2_PRIO_OVERRIDE_DATAAVB_MASK 0x0030
 143#define MV88E6XXX_G2_PRIO_OVERRIDE_QFPRIEN      0x0008
 144#define MV88E6XXX_G2_PRIO_OVERRIDE_DATA_MASK    0x0007
 145
 146/* Offset 0x14: EEPROM Command */
 147#define MV88E6XXX_G2_EEPROM_CMD                 0x14
 148#define MV88E6XXX_G2_EEPROM_CMD_BUSY            0x8000
 149#define MV88E6XXX_G2_EEPROM_CMD_OP_MASK         0x7000
 150#define MV88E6XXX_G2_EEPROM_CMD_OP_WRITE        0x3000
 151#define MV88E6XXX_G2_EEPROM_CMD_OP_READ         0x4000
 152#define MV88E6XXX_G2_EEPROM_CMD_OP_LOAD         0x6000
 153#define MV88E6XXX_G2_EEPROM_CMD_RUNNING         0x0800
 154#define MV88E6XXX_G2_EEPROM_CMD_WRITE_EN        0x0400
 155#define MV88E6352_G2_EEPROM_CMD_ADDR_MASK       0x00ff
 156#define MV88E6390_G2_EEPROM_CMD_DATA_MASK       0x00ff
 157
 158/* Offset 0x15: EEPROM Data */
 159#define MV88E6352_G2_EEPROM_DATA        0x15
 160#define MV88E6352_G2_EEPROM_DATA_MASK   0xffff
 161
 162/* Offset 0x15: EEPROM Addr */
 163#define MV88E6390_G2_EEPROM_ADDR        0x15
 164#define MV88E6390_G2_EEPROM_ADDR_MASK   0xffff
 165
 166/* Offset 0x16: AVB Command Register */
 167#define MV88E6352_G2_AVB_CMD                    0x16
 168#define MV88E6352_G2_AVB_CMD_BUSY               0x8000
 169#define MV88E6352_G2_AVB_CMD_OP_READ            0x4000
 170#define MV88E6352_G2_AVB_CMD_OP_READ_INCR       0x6000
 171#define MV88E6352_G2_AVB_CMD_OP_WRITE           0x3000
 172#define MV88E6390_G2_AVB_CMD_OP_READ            0x0000
 173#define MV88E6390_G2_AVB_CMD_OP_READ_INCR       0x4000
 174#define MV88E6390_G2_AVB_CMD_OP_WRITE           0x6000
 175#define MV88E6352_G2_AVB_CMD_PORT_MASK          0x0f00
 176#define MV88E6352_G2_AVB_CMD_PORT_TAIGLOBAL     0xe
 177#define MV88E6165_G2_AVB_CMD_PORT_PTPGLOBAL     0xf
 178#define MV88E6352_G2_AVB_CMD_PORT_PTPGLOBAL     0xf
 179#define MV88E6390_G2_AVB_CMD_PORT_MASK          0x1f00
 180#define MV88E6390_G2_AVB_CMD_PORT_TAIGLOBAL     0x1e
 181#define MV88E6390_G2_AVB_CMD_PORT_PTPGLOBAL     0x1f
 182#define MV88E6352_G2_AVB_CMD_BLOCK_PTP          0
 183#define MV88E6352_G2_AVB_CMD_BLOCK_AVB          1
 184#define MV88E6352_G2_AVB_CMD_BLOCK_QAV          2
 185#define MV88E6352_G2_AVB_CMD_BLOCK_QVB          3
 186#define MV88E6352_G2_AVB_CMD_BLOCK_MASK         0x00e0
 187#define MV88E6352_G2_AVB_CMD_ADDR_MASK          0x001f
 188
 189/* Offset 0x17: AVB Data Register */
 190#define MV88E6352_G2_AVB_DATA           0x17
 191
 192/* Offset 0x18: SMI PHY Command Register */
 193#define MV88E6XXX_G2_SMI_PHY_CMD                        0x18
 194#define MV88E6XXX_G2_SMI_PHY_CMD_BUSY                   0x8000
 195#define MV88E6390_G2_SMI_PHY_CMD_FUNC_MASK              0x6000
 196#define MV88E6390_G2_SMI_PHY_CMD_FUNC_INTERNAL          0x0000
 197#define MV88E6390_G2_SMI_PHY_CMD_FUNC_EXTERNAL          0x2000
 198#define MV88E6390_G2_SMI_PHY_CMD_FUNC_SETUP             0x4000
 199#define MV88E6XXX_G2_SMI_PHY_CMD_MODE_MASK              0x1000
 200#define MV88E6XXX_G2_SMI_PHY_CMD_MODE_45                0x0000
 201#define MV88E6XXX_G2_SMI_PHY_CMD_MODE_22                0x1000
 202#define MV88E6XXX_G2_SMI_PHY_CMD_OP_MASK                0x0c00
 203#define MV88E6XXX_G2_SMI_PHY_CMD_OP_22_WRITE_DATA       0x0400
 204#define MV88E6XXX_G2_SMI_PHY_CMD_OP_22_READ_DATA        0x0800
 205#define MV88E6XXX_G2_SMI_PHY_CMD_OP_45_WRITE_ADDR       0x0000
 206#define MV88E6XXX_G2_SMI_PHY_CMD_OP_45_WRITE_DATA       0x0400
 207#define MV88E6XXX_G2_SMI_PHY_CMD_OP_45_READ_DATA_INC    0x0800
 208#define MV88E6XXX_G2_SMI_PHY_CMD_OP_45_READ_DATA        0x0c00
 209#define MV88E6XXX_G2_SMI_PHY_CMD_DEV_ADDR_MASK          0x03e0
 210#define MV88E6XXX_G2_SMI_PHY_CMD_REG_ADDR_MASK          0x001f
 211#define MV88E6XXX_G2_SMI_PHY_CMD_SETUP_PTR_MASK         0x03ff
 212
 213/* Offset 0x19: SMI PHY Data Register */
 214#define MV88E6XXX_G2_SMI_PHY_DATA       0x19
 215
 216/* Offset 0x1A: Scratch and Misc. Register */
 217#define MV88E6XXX_G2_SCRATCH_MISC_MISC          0x1a
 218#define MV88E6XXX_G2_SCRATCH_MISC_UPDATE        0x8000
 219#define MV88E6XXX_G2_SCRATCH_MISC_PTR_MASK      0x7f00
 220#define MV88E6XXX_G2_SCRATCH_MISC_DATA_MASK     0x00ff
 221
 222/* Offset 0x1B: Watch Dog Control Register */
 223#define MV88E6250_G2_WDOG_CTL                   0x1b
 224#define MV88E6250_G2_WDOG_CTL_QC_HISTORY        0x0100
 225#define MV88E6250_G2_WDOG_CTL_QC_EVENT          0x0080
 226#define MV88E6250_G2_WDOG_CTL_QC_ENABLE         0x0040
 227#define MV88E6250_G2_WDOG_CTL_EGRESS_HISTORY    0x0020
 228#define MV88E6250_G2_WDOG_CTL_EGRESS_EVENT      0x0010
 229#define MV88E6250_G2_WDOG_CTL_EGRESS_ENABLE     0x0008
 230#define MV88E6250_G2_WDOG_CTL_FORCE_IRQ         0x0004
 231#define MV88E6250_G2_WDOG_CTL_HISTORY           0x0002
 232#define MV88E6250_G2_WDOG_CTL_SWRESET           0x0001
 233
 234/* Offset 0x1B: Watch Dog Control Register */
 235#define MV88E6352_G2_WDOG_CTL                   0x1b
 236#define MV88E6352_G2_WDOG_CTL_EGRESS_EVENT      0x0080
 237#define MV88E6352_G2_WDOG_CTL_RMU_TIMEOUT       0x0040
 238#define MV88E6352_G2_WDOG_CTL_QC_ENABLE         0x0020
 239#define MV88E6352_G2_WDOG_CTL_EGRESS_HISTORY    0x0010
 240#define MV88E6352_G2_WDOG_CTL_EGRESS_ENABLE     0x0008
 241#define MV88E6352_G2_WDOG_CTL_FORCE_IRQ         0x0004
 242#define MV88E6352_G2_WDOG_CTL_HISTORY           0x0002
 243#define MV88E6352_G2_WDOG_CTL_SWRESET           0x0001
 244
 245/* Offset 0x1B: Watch Dog Control Register */
 246#define MV88E6390_G2_WDOG_CTL                           0x1b
 247#define MV88E6390_G2_WDOG_CTL_UPDATE                    0x8000
 248#define MV88E6390_G2_WDOG_CTL_PTR_MASK                  0x7f00
 249#define MV88E6390_G2_WDOG_CTL_PTR_INT_SOURCE            0x0000
 250#define MV88E6390_G2_WDOG_CTL_PTR_INT_STS               0x1000
 251#define MV88E6390_G2_WDOG_CTL_PTR_INT_ENABLE            0x1100
 252#define MV88E6390_G2_WDOG_CTL_PTR_EVENT                 0x1200
 253#define MV88E6390_G2_WDOG_CTL_PTR_HISTORY               0x1300
 254#define MV88E6390_G2_WDOG_CTL_DATA_MASK                 0x00ff
 255#define MV88E6390_G2_WDOG_CTL_CUT_THROUGH               0x0008
 256#define MV88E6390_G2_WDOG_CTL_QUEUE_CONTROLLER          0x0004
 257#define MV88E6390_G2_WDOG_CTL_EGRESS                    0x0002
 258#define MV88E6390_G2_WDOG_CTL_FORCE_IRQ                 0x0001
 259
 260/* Offset 0x1C: QoS Weights Register */
 261#define MV88E6XXX_G2_QOS_WEIGHTS                0x1c
 262#define MV88E6XXX_G2_QOS_WEIGHTS_UPDATE         0x8000
 263#define MV88E6352_G2_QOS_WEIGHTS_PTR_MASK       0x3f00
 264#define MV88E6390_G2_QOS_WEIGHTS_PTR_MASK       0x7f00
 265#define MV88E6XXX_G2_QOS_WEIGHTS_DATA_MASK      0x00ff
 266
 267/* Offset 0x1D: Misc Register */
 268#define MV88E6XXX_G2_MISC               0x1d
 269#define MV88E6XXX_G2_MISC_5_BIT_PORT    0x4000
 270#define MV88E6352_G2_NOEGR_POLICY       0x2000
 271#define MV88E6390_G2_LAG_ID_4           0x2000
 272
 273/* Scratch/Misc registers accessed through MV88E6XXX_G2_SCRATCH_MISC */
 274/* Offset 0x02: Misc Configuration */
 275#define MV88E6352_G2_SCRATCH_MISC_CFG           0x02
 276#define MV88E6352_G2_SCRATCH_MISC_CFG_NORMALSMI 0x80
 277/* Offset 0x60-0x61: GPIO Configuration */
 278#define MV88E6352_G2_SCRATCH_GPIO_CFG0          0x60
 279#define MV88E6352_G2_SCRATCH_GPIO_CFG1          0x61
 280/* Offset 0x62-0x63: GPIO Direction */
 281#define MV88E6352_G2_SCRATCH_GPIO_DIR0          0x62
 282#define MV88E6352_G2_SCRATCH_GPIO_DIR1          0x63
 283#define MV88E6352_G2_SCRATCH_GPIO_DIR_OUT       0
 284#define MV88E6352_G2_SCRATCH_GPIO_DIR_IN        1
 285/* Offset 0x64-0x65: GPIO Data */
 286#define MV88E6352_G2_SCRATCH_GPIO_DATA0         0x64
 287#define MV88E6352_G2_SCRATCH_GPIO_DATA1         0x65
 288/* Offset 0x68-0x6F: GPIO Pin Control */
 289#define MV88E6352_G2_SCRATCH_GPIO_PCTL0         0x68
 290#define MV88E6352_G2_SCRATCH_GPIO_PCTL1         0x69
 291#define MV88E6352_G2_SCRATCH_GPIO_PCTL2         0x6A
 292#define MV88E6352_G2_SCRATCH_GPIO_PCTL3         0x6B
 293#define MV88E6352_G2_SCRATCH_GPIO_PCTL4         0x6C
 294#define MV88E6352_G2_SCRATCH_GPIO_PCTL5         0x6D
 295#define MV88E6352_G2_SCRATCH_GPIO_PCTL6         0x6E
 296#define MV88E6352_G2_SCRATCH_GPIO_PCTL7         0x6F
 297#define MV88E6352_G2_SCRATCH_CONFIG_DATA0       0x70
 298#define MV88E6352_G2_SCRATCH_CONFIG_DATA1       0x71
 299#define MV88E6352_G2_SCRATCH_CONFIG_DATA1_NO_CPU        BIT(2)
 300#define MV88E6352_G2_SCRATCH_CONFIG_DATA2       0x72
 301#define MV88E6352_G2_SCRATCH_CONFIG_DATA2_P0_MODE_MASK  0x3
 302#define MV88E6352_G2_SCRATCH_CONFIG_DATA3       0x73
 303#define MV88E6352_G2_SCRATCH_CONFIG_DATA3_S_SEL         BIT(1)
 304
 305#define MV88E6352_G2_SCRATCH_GPIO_PCTL_GPIO     0
 306#define MV88E6352_G2_SCRATCH_GPIO_PCTL_TRIG     1
 307#define MV88E6352_G2_SCRATCH_GPIO_PCTL_EVREQ    2
 308
 309int mv88e6xxx_g2_read(struct mv88e6xxx_chip *chip, int reg, u16 *val);
 310int mv88e6xxx_g2_write(struct mv88e6xxx_chip *chip, int reg, u16 val);
 311int mv88e6xxx_g2_wait_bit(struct mv88e6xxx_chip *chip, int reg,
 312                          int bit, int val);
 313
 314int mv88e6352_g2_irl_init_all(struct mv88e6xxx_chip *chip, int port);
 315int mv88e6390_g2_irl_init_all(struct mv88e6xxx_chip *chip, int port);
 316
 317int mv88e6xxx_g2_smi_phy_read(struct mv88e6xxx_chip *chip,
 318                              struct mii_bus *bus,
 319                              int addr, int reg, u16 *val);
 320int mv88e6xxx_g2_smi_phy_write(struct mv88e6xxx_chip *chip,
 321                               struct mii_bus *bus,
 322                               int addr, int reg, u16 val);
 323int mv88e6xxx_g2_set_switch_mac(struct mv88e6xxx_chip *chip, u8 *addr);
 324
 325int mv88e6xxx_g2_get_eeprom8(struct mv88e6xxx_chip *chip,
 326                             struct ethtool_eeprom *eeprom, u8 *data);
 327int mv88e6xxx_g2_set_eeprom8(struct mv88e6xxx_chip *chip,
 328                             struct ethtool_eeprom *eeprom, u8 *data);
 329
 330int mv88e6xxx_g2_get_eeprom16(struct mv88e6xxx_chip *chip,
 331                              struct ethtool_eeprom *eeprom, u8 *data);
 332int mv88e6xxx_g2_set_eeprom16(struct mv88e6xxx_chip *chip,
 333                              struct ethtool_eeprom *eeprom, u8 *data);
 334
 335int mv88e6xxx_g2_pvt_read(struct mv88e6xxx_chip *chip, int src_dev,
 336                          int src_port, u16 *data);
 337int mv88e6xxx_g2_pvt_write(struct mv88e6xxx_chip *chip, int src_dev,
 338                           int src_port, u16 data);
 339int mv88e6xxx_g2_misc_4_bit_port(struct mv88e6xxx_chip *chip);
 340
 341int mv88e6xxx_g2_irq_setup(struct mv88e6xxx_chip *chip);
 342void mv88e6xxx_g2_irq_free(struct mv88e6xxx_chip *chip);
 343
 344int mv88e6xxx_g2_irq_mdio_setup(struct mv88e6xxx_chip *chip,
 345                                struct mii_bus *bus);
 346void mv88e6xxx_g2_irq_mdio_free(struct mv88e6xxx_chip *chip,
 347                                struct mii_bus *bus);
 348
 349int mv88e6185_g2_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip);
 350int mv88e6352_g2_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip);
 351
 352int mv88e6xxx_g2_pot_clear(struct mv88e6xxx_chip *chip);
 353
 354int mv88e6xxx_g2_trunk_mask_write(struct mv88e6xxx_chip *chip, int num,
 355                                  bool hash, u16 mask);
 356int mv88e6xxx_g2_trunk_mapping_write(struct mv88e6xxx_chip *chip, int id,
 357                                     u16 map);
 358int mv88e6xxx_g2_trunk_clear(struct mv88e6xxx_chip *chip);
 359
 360int mv88e6xxx_g2_device_mapping_write(struct mv88e6xxx_chip *chip, int target,
 361                                      int port);
 362
 363extern const struct mv88e6xxx_irq_ops mv88e6097_watchdog_ops;
 364extern const struct mv88e6xxx_irq_ops mv88e6250_watchdog_ops;
 365extern const struct mv88e6xxx_irq_ops mv88e6390_watchdog_ops;
 366
 367extern const struct mv88e6xxx_avb_ops mv88e6165_avb_ops;
 368extern const struct mv88e6xxx_avb_ops mv88e6352_avb_ops;
 369extern const struct mv88e6xxx_avb_ops mv88e6390_avb_ops;
 370
 371extern const struct mv88e6xxx_gpio_ops mv88e6352_gpio_ops;
 372
 373int mv88e6xxx_g2_scratch_gpio_set_smi(struct mv88e6xxx_chip *chip,
 374                                      bool external);
 375int mv88e6352_g2_scratch_port_has_serdes(struct mv88e6xxx_chip *chip, int port);
 376int mv88e6xxx_g2_atu_stats_set(struct mv88e6xxx_chip *chip, u16 kind, u16 bin);
 377int mv88e6xxx_g2_atu_stats_get(struct mv88e6xxx_chip *chip, u16 *stats);
 378
 379#endif /* _MV88E6XXX_GLOBAL2_H */
 380