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42#include <linux/bitfield.h>
43#include <linux/module.h>
44#include <linux/of_irq.h>
45#include <linux/of_mdio.h>
46#include <linux/regmap.h>
47#include <linux/reset.h>
48#include <net/dsa.h>
49
50#define AR9331_SW_NAME "ar9331_switch"
51#define AR9331_SW_PORTS 6
52
53
54#define AR9331_SW_REG_PAGE 0x40000
55
56
57#define AR9331_SW_REG_GINT 0x10
58#define AR9331_SW_REG_GINT_MASK 0x14
59#define AR9331_SW_GINT_PHY_INT BIT(2)
60
61#define AR9331_SW_REG_FLOOD_MASK 0x2c
62#define AR9331_SW_FLOOD_MASK_BROAD_TO_CPU BIT(26)
63
64#define AR9331_SW_REG_GLOBAL_CTRL 0x30
65#define AR9331_SW_GLOBAL_CTRL_MFS_M GENMASK(13, 0)
66
67#define AR9331_SW_REG_MDIO_CTRL 0x98
68#define AR9331_SW_MDIO_CTRL_BUSY BIT(31)
69#define AR9331_SW_MDIO_CTRL_MASTER_EN BIT(30)
70#define AR9331_SW_MDIO_CTRL_CMD_READ BIT(27)
71#define AR9331_SW_MDIO_CTRL_PHY_ADDR_M GENMASK(25, 21)
72#define AR9331_SW_MDIO_CTRL_REG_ADDR_M GENMASK(20, 16)
73#define AR9331_SW_MDIO_CTRL_DATA_M GENMASK(16, 0)
74
75#define AR9331_SW_REG_PORT_STATUS(_port) (0x100 + (_port) * 0x100)
76
77
78
79
80#define AR9331_SW_PORT_STATUS_FLOW_LINK_EN BIT(12)
81
82
83
84
85#define AR9331_SW_PORT_STATUS_LINK_EN BIT(9)
86#define AR9331_SW_PORT_STATUS_DUPLEX_MODE BIT(6)
87#define AR9331_SW_PORT_STATUS_RX_FLOW_EN BIT(5)
88#define AR9331_SW_PORT_STATUS_TX_FLOW_EN BIT(4)
89#define AR9331_SW_PORT_STATUS_RXMAC BIT(3)
90#define AR9331_SW_PORT_STATUS_TXMAC BIT(2)
91#define AR9331_SW_PORT_STATUS_SPEED_M GENMASK(1, 0)
92#define AR9331_SW_PORT_STATUS_SPEED_1000 2
93#define AR9331_SW_PORT_STATUS_SPEED_100 1
94#define AR9331_SW_PORT_STATUS_SPEED_10 0
95
96#define AR9331_SW_PORT_STATUS_MAC_MASK \
97 (AR9331_SW_PORT_STATUS_TXMAC | AR9331_SW_PORT_STATUS_RXMAC)
98
99#define AR9331_SW_PORT_STATUS_LINK_MASK \
100 (AR9331_SW_PORT_STATUS_DUPLEX_MODE | \
101 AR9331_SW_PORT_STATUS_RX_FLOW_EN | AR9331_SW_PORT_STATUS_TX_FLOW_EN | \
102 AR9331_SW_PORT_STATUS_SPEED_M)
103
104#define AR9331_SW_REG_PORT_CTRL(_port) (0x104 + (_port) * 0x100)
105#define AR9331_SW_PORT_CTRL_HEAD_EN BIT(11)
106#define AR9331_SW_PORT_CTRL_PORT_STATE GENMASK(2, 0)
107#define AR9331_SW_PORT_CTRL_PORT_STATE_DISABLED 0
108#define AR9331_SW_PORT_CTRL_PORT_STATE_BLOCKING 1
109#define AR9331_SW_PORT_CTRL_PORT_STATE_LISTENING 2
110#define AR9331_SW_PORT_CTRL_PORT_STATE_LEARNING 3
111#define AR9331_SW_PORT_CTRL_PORT_STATE_FORWARD 4
112
113#define AR9331_SW_REG_PORT_VLAN(_port) (0x108 + (_port) * 0x100)
114#define AR9331_SW_PORT_VLAN_8021Q_MODE GENMASK(31, 30)
115#define AR9331_SW_8021Q_MODE_SECURE 3
116#define AR9331_SW_8021Q_MODE_CHECK 2
117#define AR9331_SW_8021Q_MODE_FALLBACK 1
118#define AR9331_SW_8021Q_MODE_NONE 0
119#define AR9331_SW_PORT_VLAN_PORT_VID_MEMBER GENMASK(25, 16)
120
121
122#define AR9331_MIB_COUNTER(x) (0x20000 + ((x) * 0x100))
123
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149
150#define AR9331_SW_ADDR_PAGE GENMASK(18, 9)
151
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162
163
164#define AR9331_SW_LOW_ADDR_PHY GENMASK(8, 6)
165#define AR9331_SW_LOW_ADDR_REG GENMASK(5, 1)
166
167#define AR9331_SW_MDIO_PHY_MODE_M GENMASK(4, 3)
168#define AR9331_SW_MDIO_PHY_MODE_PAGE 3
169#define AR9331_SW_MDIO_PHY_MODE_REG 2
170#define AR9331_SW_MDIO_PHY_MODE_BYPASS 0
171#define AR9331_SW_MDIO_PHY_ADDR_M GENMASK(2, 0)
172
173
174#define AR9331_SW_MDIO_POLL_SLEEP_US 1
175#define AR9331_SW_MDIO_POLL_TIMEOUT_US 20
176
177
178
179
180
181
182
183#define STATS_INTERVAL_JIFFIES (3 * HZ)
184
185struct ar9331_sw_stats_raw {
186 u32 rxbroad;
187 u32 rxpause;
188 u32 rxmulti;
189 u32 rxfcserr;
190 u32 rxalignerr;
191 u32 rxrunt;
192 u32 rxfragment;
193 u32 rx64byte;
194 u32 rx128byte;
195 u32 rx256byte;
196 u32 rx512byte;
197 u32 rx1024byte;
198 u32 rx1518byte;
199 u32 rxmaxbyte;
200 u32 rxtoolong;
201 u32 rxgoodbyte;
202 u32 rxgoodbyte_hi;
203 u32 rxbadbyte;
204 u32 rxbadbyte_hi;
205 u32 rxoverflow;
206 u32 filtered;
207 u32 txbroad;
208 u32 txpause;
209 u32 txmulti;
210 u32 txunderrun;
211 u32 tx64byte;
212 u32 tx128byte;
213 u32 tx256byte;
214 u32 tx512byte;
215 u32 tx1024byte;
216 u32 tx1518byte;
217 u32 txmaxbyte;
218 u32 txoversize;
219 u32 txbyte;
220 u32 txbyte_hi;
221 u32 txcollision;
222 u32 txabortcol;
223 u32 txmulticol;
224 u32 txsinglecol;
225 u32 txexcdefer;
226 u32 txdefer;
227 u32 txlatecol;
228};
229
230struct ar9331_sw_port {
231 int idx;
232 struct delayed_work mib_read;
233 struct rtnl_link_stats64 stats;
234 struct spinlock stats_lock;
235};
236
237struct ar9331_sw_priv {
238 struct device *dev;
239 struct dsa_switch ds;
240 struct dsa_switch_ops ops;
241 struct irq_domain *irqdomain;
242 u32 irq_mask;
243 struct mutex lock_irq;
244 struct mii_bus *mbus;
245 struct mii_bus *sbus;
246 struct regmap *regmap;
247 struct reset_control *sw_reset;
248 struct ar9331_sw_port port[AR9331_SW_PORTS];
249};
250
251static struct ar9331_sw_priv *ar9331_sw_port_to_priv(struct ar9331_sw_port *port)
252{
253 struct ar9331_sw_port *p = port - port->idx;
254
255 return (struct ar9331_sw_priv *)((void *)p -
256 offsetof(struct ar9331_sw_priv, port));
257}
258
259
260
261
262static int ar9331_sw_reset(struct ar9331_sw_priv *priv)
263{
264 int ret;
265
266 ret = reset_control_assert(priv->sw_reset);
267 if (ret)
268 goto error;
269
270
271
272
273
274
275 usleep_range(10000, 15000);
276 ret = reset_control_deassert(priv->sw_reset);
277 if (ret)
278 goto error;
279
280
281
282
283
284
285
286 return 0;
287error:
288 dev_err_ratelimited(priv->dev, "%s: %i\n", __func__, ret);
289 return ret;
290}
291
292static int ar9331_sw_mbus_write(struct mii_bus *mbus, int port, int regnum,
293 u16 data)
294{
295 struct ar9331_sw_priv *priv = mbus->priv;
296 struct regmap *regmap = priv->regmap;
297 u32 val;
298 int ret;
299
300 ret = regmap_write(regmap, AR9331_SW_REG_MDIO_CTRL,
301 AR9331_SW_MDIO_CTRL_BUSY |
302 AR9331_SW_MDIO_CTRL_MASTER_EN |
303 FIELD_PREP(AR9331_SW_MDIO_CTRL_PHY_ADDR_M, port) |
304 FIELD_PREP(AR9331_SW_MDIO_CTRL_REG_ADDR_M, regnum) |
305 FIELD_PREP(AR9331_SW_MDIO_CTRL_DATA_M, data));
306 if (ret)
307 goto error;
308
309 ret = regmap_read_poll_timeout(regmap, AR9331_SW_REG_MDIO_CTRL, val,
310 !(val & AR9331_SW_MDIO_CTRL_BUSY),
311 AR9331_SW_MDIO_POLL_SLEEP_US,
312 AR9331_SW_MDIO_POLL_TIMEOUT_US);
313 if (ret)
314 goto error;
315
316 return 0;
317error:
318 dev_err_ratelimited(priv->dev, "PHY write error: %i\n", ret);
319 return ret;
320}
321
322static int ar9331_sw_mbus_read(struct mii_bus *mbus, int port, int regnum)
323{
324 struct ar9331_sw_priv *priv = mbus->priv;
325 struct regmap *regmap = priv->regmap;
326 u32 val;
327 int ret;
328
329 ret = regmap_write(regmap, AR9331_SW_REG_MDIO_CTRL,
330 AR9331_SW_MDIO_CTRL_BUSY |
331 AR9331_SW_MDIO_CTRL_MASTER_EN |
332 AR9331_SW_MDIO_CTRL_CMD_READ |
333 FIELD_PREP(AR9331_SW_MDIO_CTRL_PHY_ADDR_M, port) |
334 FIELD_PREP(AR9331_SW_MDIO_CTRL_REG_ADDR_M, regnum));
335 if (ret)
336 goto error;
337
338 ret = regmap_read_poll_timeout(regmap, AR9331_SW_REG_MDIO_CTRL, val,
339 !(val & AR9331_SW_MDIO_CTRL_BUSY),
340 AR9331_SW_MDIO_POLL_SLEEP_US,
341 AR9331_SW_MDIO_POLL_TIMEOUT_US);
342 if (ret)
343 goto error;
344
345 ret = regmap_read(regmap, AR9331_SW_REG_MDIO_CTRL, &val);
346 if (ret)
347 goto error;
348
349 return FIELD_GET(AR9331_SW_MDIO_CTRL_DATA_M, val);
350
351error:
352 dev_err_ratelimited(priv->dev, "PHY read error: %i\n", ret);
353 return ret;
354}
355
356static int ar9331_sw_mbus_init(struct ar9331_sw_priv *priv)
357{
358 struct device *dev = priv->dev;
359 struct mii_bus *mbus;
360 struct device_node *np, *mnp;
361 int ret;
362
363 np = dev->of_node;
364
365 mbus = devm_mdiobus_alloc(dev);
366 if (!mbus)
367 return -ENOMEM;
368
369 mbus->name = np->full_name;
370 snprintf(mbus->id, MII_BUS_ID_SIZE, "%pOF", np);
371
372 mbus->read = ar9331_sw_mbus_read;
373 mbus->write = ar9331_sw_mbus_write;
374 mbus->priv = priv;
375 mbus->parent = dev;
376
377 mnp = of_get_child_by_name(np, "mdio");
378 if (!mnp)
379 return -ENODEV;
380
381 ret = devm_of_mdiobus_register(dev, mbus, mnp);
382 of_node_put(mnp);
383 if (ret)
384 return ret;
385
386 priv->mbus = mbus;
387
388 return 0;
389}
390
391static int ar9331_sw_setup_port(struct dsa_switch *ds, int port)
392{
393 struct ar9331_sw_priv *priv = (struct ar9331_sw_priv *)ds->priv;
394 struct regmap *regmap = priv->regmap;
395 u32 port_mask, port_ctrl, val;
396 int ret;
397
398
399 port_ctrl = FIELD_PREP(AR9331_SW_PORT_CTRL_PORT_STATE,
400 AR9331_SW_PORT_CTRL_PORT_STATE_FORWARD);
401
402 if (dsa_is_cpu_port(ds, port)) {
403
404
405
406 port_mask = dsa_user_ports(ds);
407
408
409
410 port_ctrl |= AR9331_SW_PORT_CTRL_HEAD_EN;
411 } else if (dsa_is_user_port(ds, port)) {
412
413
414 port_mask = BIT(dsa_upstream_port(ds, port));
415 } else {
416
417 port_mask = 0;
418 }
419
420 val = FIELD_PREP(AR9331_SW_PORT_VLAN_8021Q_MODE,
421 AR9331_SW_8021Q_MODE_NONE) |
422 FIELD_PREP(AR9331_SW_PORT_VLAN_PORT_VID_MEMBER, port_mask);
423
424 ret = regmap_write(regmap, AR9331_SW_REG_PORT_VLAN(port), val);
425 if (ret)
426 goto error;
427
428 ret = regmap_write(regmap, AR9331_SW_REG_PORT_CTRL(port), port_ctrl);
429 if (ret)
430 goto error;
431
432 return 0;
433error:
434 dev_err(priv->dev, "%s: error: %i\n", __func__, ret);
435
436 return ret;
437}
438
439static int ar9331_sw_setup(struct dsa_switch *ds)
440{
441 struct ar9331_sw_priv *priv = (struct ar9331_sw_priv *)ds->priv;
442 struct regmap *regmap = priv->regmap;
443 int ret, i;
444
445 ret = ar9331_sw_reset(priv);
446 if (ret)
447 return ret;
448
449
450
451
452 ret = ar9331_sw_mbus_init(priv);
453 if (ret)
454 return ret;
455
456
457 ret = regmap_write_bits(regmap, AR9331_SW_REG_FLOOD_MASK,
458 AR9331_SW_FLOOD_MASK_BROAD_TO_CPU,
459 AR9331_SW_FLOOD_MASK_BROAD_TO_CPU);
460 if (ret)
461 goto error;
462
463
464 ret = regmap_write_bits(regmap, AR9331_SW_REG_GLOBAL_CTRL,
465 AR9331_SW_GLOBAL_CTRL_MFS_M,
466 AR9331_SW_GLOBAL_CTRL_MFS_M);
467 if (ret)
468 goto error;
469
470 for (i = 0; i < ds->num_ports; i++) {
471 ret = ar9331_sw_setup_port(ds, i);
472 if (ret)
473 goto error;
474 }
475
476 ds->configure_vlan_while_not_filtering = false;
477
478 return 0;
479error:
480 dev_err_ratelimited(priv->dev, "%s: %i\n", __func__, ret);
481 return ret;
482}
483
484static void ar9331_sw_port_disable(struct dsa_switch *ds, int port)
485{
486 struct ar9331_sw_priv *priv = (struct ar9331_sw_priv *)ds->priv;
487 struct regmap *regmap = priv->regmap;
488 int ret;
489
490 ret = regmap_write(regmap, AR9331_SW_REG_PORT_STATUS(port), 0);
491 if (ret)
492 dev_err_ratelimited(priv->dev, "%s: %i\n", __func__, ret);
493}
494
495static enum dsa_tag_protocol ar9331_sw_get_tag_protocol(struct dsa_switch *ds,
496 int port,
497 enum dsa_tag_protocol m)
498{
499 return DSA_TAG_PROTO_AR9331;
500}
501
502static void ar9331_sw_phylink_get_caps(struct dsa_switch *ds, int port,
503 struct phylink_config *config)
504{
505 config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE |
506 MAC_10 | MAC_100;
507
508 switch (port) {
509 case 0:
510 __set_bit(PHY_INTERFACE_MODE_GMII,
511 config->supported_interfaces);
512 config->mac_capabilities |= MAC_1000;
513 break;
514 case 1:
515 case 2:
516 case 3:
517 case 4:
518 case 5:
519 __set_bit(PHY_INTERFACE_MODE_INTERNAL,
520 config->supported_interfaces);
521 break;
522 }
523}
524
525static void ar9331_sw_phylink_mac_config(struct dsa_switch *ds, int port,
526 unsigned int mode,
527 const struct phylink_link_state *state)
528{
529 struct ar9331_sw_priv *priv = (struct ar9331_sw_priv *)ds->priv;
530 struct regmap *regmap = priv->regmap;
531 int ret;
532
533 ret = regmap_update_bits(regmap, AR9331_SW_REG_PORT_STATUS(port),
534 AR9331_SW_PORT_STATUS_LINK_EN |
535 AR9331_SW_PORT_STATUS_FLOW_LINK_EN, 0);
536 if (ret)
537 dev_err_ratelimited(priv->dev, "%s: %i\n", __func__, ret);
538}
539
540static void ar9331_sw_phylink_mac_link_down(struct dsa_switch *ds, int port,
541 unsigned int mode,
542 phy_interface_t interface)
543{
544 struct ar9331_sw_priv *priv = (struct ar9331_sw_priv *)ds->priv;
545 struct ar9331_sw_port *p = &priv->port[port];
546 struct regmap *regmap = priv->regmap;
547 int ret;
548
549 ret = regmap_update_bits(regmap, AR9331_SW_REG_PORT_STATUS(port),
550 AR9331_SW_PORT_STATUS_MAC_MASK, 0);
551 if (ret)
552 dev_err_ratelimited(priv->dev, "%s: %i\n", __func__, ret);
553
554 cancel_delayed_work_sync(&p->mib_read);
555}
556
557static void ar9331_sw_phylink_mac_link_up(struct dsa_switch *ds, int port,
558 unsigned int mode,
559 phy_interface_t interface,
560 struct phy_device *phydev,
561 int speed, int duplex,
562 bool tx_pause, bool rx_pause)
563{
564 struct ar9331_sw_priv *priv = (struct ar9331_sw_priv *)ds->priv;
565 struct ar9331_sw_port *p = &priv->port[port];
566 struct regmap *regmap = priv->regmap;
567 u32 val;
568 int ret;
569
570 schedule_delayed_work(&p->mib_read, 0);
571
572 val = AR9331_SW_PORT_STATUS_MAC_MASK;
573 switch (speed) {
574 case SPEED_1000:
575 val |= AR9331_SW_PORT_STATUS_SPEED_1000;
576 break;
577 case SPEED_100:
578 val |= AR9331_SW_PORT_STATUS_SPEED_100;
579 break;
580 case SPEED_10:
581 val |= AR9331_SW_PORT_STATUS_SPEED_10;
582 break;
583 default:
584 return;
585 }
586
587 if (duplex)
588 val |= AR9331_SW_PORT_STATUS_DUPLEX_MODE;
589
590 if (tx_pause)
591 val |= AR9331_SW_PORT_STATUS_TX_FLOW_EN;
592
593 if (rx_pause)
594 val |= AR9331_SW_PORT_STATUS_RX_FLOW_EN;
595
596 ret = regmap_update_bits(regmap, AR9331_SW_REG_PORT_STATUS(port),
597 AR9331_SW_PORT_STATUS_MAC_MASK |
598 AR9331_SW_PORT_STATUS_LINK_MASK,
599 val);
600 if (ret)
601 dev_err_ratelimited(priv->dev, "%s: %i\n", __func__, ret);
602}
603
604static void ar9331_read_stats(struct ar9331_sw_port *port)
605{
606 struct ar9331_sw_priv *priv = ar9331_sw_port_to_priv(port);
607 struct rtnl_link_stats64 *stats = &port->stats;
608 struct ar9331_sw_stats_raw raw;
609 int ret;
610
611
612 ret = regmap_bulk_read(priv->regmap, AR9331_MIB_COUNTER(port->idx),
613 &raw, sizeof(raw) / sizeof(u32));
614 if (ret) {
615 dev_err_ratelimited(priv->dev, "%s: %i\n", __func__, ret);
616 return;
617 }
618
619
620 spin_lock(&port->stats_lock);
621
622 stats->rx_bytes += raw.rxgoodbyte;
623 stats->tx_bytes += raw.txbyte;
624
625 stats->rx_packets += raw.rx64byte + raw.rx128byte + raw.rx256byte +
626 raw.rx512byte + raw.rx1024byte + raw.rx1518byte + raw.rxmaxbyte;
627 stats->tx_packets += raw.tx64byte + raw.tx128byte + raw.tx256byte +
628 raw.tx512byte + raw.tx1024byte + raw.tx1518byte + raw.txmaxbyte;
629
630 stats->rx_length_errors += raw.rxrunt + raw.rxfragment + raw.rxtoolong;
631 stats->rx_crc_errors += raw.rxfcserr;
632 stats->rx_frame_errors += raw.rxalignerr;
633 stats->rx_missed_errors += raw.rxoverflow;
634 stats->rx_dropped += raw.filtered;
635 stats->rx_errors += raw.rxfcserr + raw.rxalignerr + raw.rxrunt +
636 raw.rxfragment + raw.rxoverflow + raw.rxtoolong;
637
638 stats->tx_window_errors += raw.txlatecol;
639 stats->tx_fifo_errors += raw.txunderrun;
640 stats->tx_aborted_errors += raw.txabortcol;
641 stats->tx_errors += raw.txoversize + raw.txabortcol + raw.txunderrun +
642 raw.txlatecol;
643
644 stats->multicast += raw.rxmulti;
645 stats->collisions += raw.txcollision;
646
647 spin_unlock(&port->stats_lock);
648}
649
650static void ar9331_do_stats_poll(struct work_struct *work)
651{
652 struct ar9331_sw_port *port = container_of(work, struct ar9331_sw_port,
653 mib_read.work);
654
655 ar9331_read_stats(port);
656
657 schedule_delayed_work(&port->mib_read, STATS_INTERVAL_JIFFIES);
658}
659
660static void ar9331_get_stats64(struct dsa_switch *ds, int port,
661 struct rtnl_link_stats64 *s)
662{
663 struct ar9331_sw_priv *priv = (struct ar9331_sw_priv *)ds->priv;
664 struct ar9331_sw_port *p = &priv->port[port];
665
666 spin_lock(&p->stats_lock);
667 memcpy(s, &p->stats, sizeof(*s));
668 spin_unlock(&p->stats_lock);
669}
670
671static const struct dsa_switch_ops ar9331_sw_ops = {
672 .get_tag_protocol = ar9331_sw_get_tag_protocol,
673 .setup = ar9331_sw_setup,
674 .port_disable = ar9331_sw_port_disable,
675 .phylink_get_caps = ar9331_sw_phylink_get_caps,
676 .phylink_mac_config = ar9331_sw_phylink_mac_config,
677 .phylink_mac_link_down = ar9331_sw_phylink_mac_link_down,
678 .phylink_mac_link_up = ar9331_sw_phylink_mac_link_up,
679 .get_stats64 = ar9331_get_stats64,
680};
681
682static irqreturn_t ar9331_sw_irq(int irq, void *data)
683{
684 struct ar9331_sw_priv *priv = data;
685 struct regmap *regmap = priv->regmap;
686 u32 stat;
687 int ret;
688
689 ret = regmap_read(regmap, AR9331_SW_REG_GINT, &stat);
690 if (ret) {
691 dev_err(priv->dev, "can't read interrupt status\n");
692 return IRQ_NONE;
693 }
694
695 if (!stat)
696 return IRQ_NONE;
697
698 if (stat & AR9331_SW_GINT_PHY_INT) {
699 int child_irq;
700
701 child_irq = irq_find_mapping(priv->irqdomain, 0);
702 handle_nested_irq(child_irq);
703 }
704
705 ret = regmap_write(regmap, AR9331_SW_REG_GINT, stat);
706 if (ret) {
707 dev_err(priv->dev, "can't write interrupt status\n");
708 return IRQ_NONE;
709 }
710
711 return IRQ_HANDLED;
712}
713
714static void ar9331_sw_mask_irq(struct irq_data *d)
715{
716 struct ar9331_sw_priv *priv = irq_data_get_irq_chip_data(d);
717
718 priv->irq_mask = 0;
719}
720
721static void ar9331_sw_unmask_irq(struct irq_data *d)
722{
723 struct ar9331_sw_priv *priv = irq_data_get_irq_chip_data(d);
724
725 priv->irq_mask = AR9331_SW_GINT_PHY_INT;
726}
727
728static void ar9331_sw_irq_bus_lock(struct irq_data *d)
729{
730 struct ar9331_sw_priv *priv = irq_data_get_irq_chip_data(d);
731
732 mutex_lock(&priv->lock_irq);
733}
734
735static void ar9331_sw_irq_bus_sync_unlock(struct irq_data *d)
736{
737 struct ar9331_sw_priv *priv = irq_data_get_irq_chip_data(d);
738 struct regmap *regmap = priv->regmap;
739 int ret;
740
741 ret = regmap_update_bits(regmap, AR9331_SW_REG_GINT_MASK,
742 AR9331_SW_GINT_PHY_INT, priv->irq_mask);
743 if (ret)
744 dev_err(priv->dev, "failed to change IRQ mask\n");
745
746 mutex_unlock(&priv->lock_irq);
747}
748
749static struct irq_chip ar9331_sw_irq_chip = {
750 .name = AR9331_SW_NAME,
751 .irq_mask = ar9331_sw_mask_irq,
752 .irq_unmask = ar9331_sw_unmask_irq,
753 .irq_bus_lock = ar9331_sw_irq_bus_lock,
754 .irq_bus_sync_unlock = ar9331_sw_irq_bus_sync_unlock,
755};
756
757static int ar9331_sw_irq_map(struct irq_domain *domain, unsigned int irq,
758 irq_hw_number_t hwirq)
759{
760 irq_set_chip_data(irq, domain->host_data);
761 irq_set_chip_and_handler(irq, &ar9331_sw_irq_chip, handle_simple_irq);
762 irq_set_nested_thread(irq, 1);
763 irq_set_noprobe(irq);
764
765 return 0;
766}
767
768static void ar9331_sw_irq_unmap(struct irq_domain *d, unsigned int irq)
769{
770 irq_set_nested_thread(irq, 0);
771 irq_set_chip_and_handler(irq, NULL, NULL);
772 irq_set_chip_data(irq, NULL);
773}
774
775static const struct irq_domain_ops ar9331_sw_irqdomain_ops = {
776 .map = ar9331_sw_irq_map,
777 .unmap = ar9331_sw_irq_unmap,
778 .xlate = irq_domain_xlate_onecell,
779};
780
781static int ar9331_sw_irq_init(struct ar9331_sw_priv *priv)
782{
783 struct device_node *np = priv->dev->of_node;
784 struct device *dev = priv->dev;
785 int ret, irq;
786
787 irq = of_irq_get(np, 0);
788 if (irq <= 0) {
789 dev_err(dev, "failed to get parent IRQ\n");
790 return irq ? irq : -EINVAL;
791 }
792
793 mutex_init(&priv->lock_irq);
794 ret = devm_request_threaded_irq(dev, irq, NULL, ar9331_sw_irq,
795 IRQF_ONESHOT, AR9331_SW_NAME, priv);
796 if (ret) {
797 dev_err(dev, "unable to request irq: %d\n", ret);
798 return ret;
799 }
800
801 priv->irqdomain = irq_domain_add_linear(np, 1, &ar9331_sw_irqdomain_ops,
802 priv);
803 if (!priv->irqdomain) {
804 dev_err(dev, "failed to create IRQ domain\n");
805 return -EINVAL;
806 }
807
808 irq_set_parent(irq_create_mapping(priv->irqdomain, 0), irq);
809
810 return 0;
811}
812
813static int __ar9331_mdio_write(struct mii_bus *sbus, u8 mode, u16 reg, u16 val)
814{
815 u8 r, p;
816
817 p = FIELD_PREP(AR9331_SW_MDIO_PHY_MODE_M, mode) |
818 FIELD_GET(AR9331_SW_LOW_ADDR_PHY, reg);
819 r = FIELD_GET(AR9331_SW_LOW_ADDR_REG, reg);
820
821 return mdiobus_write(sbus, p, r, val);
822}
823
824static int __ar9331_mdio_read(struct mii_bus *sbus, u16 reg)
825{
826 u8 r, p;
827
828 p = FIELD_PREP(AR9331_SW_MDIO_PHY_MODE_M, AR9331_SW_MDIO_PHY_MODE_REG) |
829 FIELD_GET(AR9331_SW_LOW_ADDR_PHY, reg);
830 r = FIELD_GET(AR9331_SW_LOW_ADDR_REG, reg);
831
832 return mdiobus_read(sbus, p, r);
833}
834
835static int ar9331_mdio_read(void *ctx, const void *reg_buf, size_t reg_len,
836 void *val_buf, size_t val_len)
837{
838 struct ar9331_sw_priv *priv = ctx;
839 struct mii_bus *sbus = priv->sbus;
840 u32 reg = *(u32 *)reg_buf;
841 int ret;
842
843 if (reg == AR9331_SW_REG_PAGE) {
844
845
846
847
848 *(u32 *)val_buf = GENMASK(9, 0);
849 return 0;
850 }
851
852 ret = __ar9331_mdio_read(sbus, reg);
853 if (ret < 0)
854 goto error;
855
856 *(u32 *)val_buf = ret;
857 ret = __ar9331_mdio_read(sbus, reg + 2);
858 if (ret < 0)
859 goto error;
860
861 *(u32 *)val_buf |= ret << 16;
862
863 return 0;
864error:
865 dev_err_ratelimited(&sbus->dev, "Bus error. Failed to read register.\n");
866 return ret;
867}
868
869static int ar9331_mdio_write(void *ctx, u32 reg, u32 val)
870{
871 struct ar9331_sw_priv *priv = (struct ar9331_sw_priv *)ctx;
872 struct mii_bus *sbus = priv->sbus;
873 int ret;
874
875 if (reg == AR9331_SW_REG_PAGE) {
876 ret = __ar9331_mdio_write(sbus, AR9331_SW_MDIO_PHY_MODE_PAGE,
877 0, val);
878 if (ret < 0)
879 goto error;
880
881 return 0;
882 }
883
884
885
886
887
888
889
890
891 ret = __ar9331_mdio_write(sbus, AR9331_SW_MDIO_PHY_MODE_REG, reg + 2,
892 val >> 16);
893 if (ret < 0)
894 goto error;
895
896 ret = __ar9331_mdio_write(sbus, AR9331_SW_MDIO_PHY_MODE_REG, reg, val);
897 if (ret < 0)
898 goto error;
899
900 return 0;
901
902error:
903 dev_err_ratelimited(&sbus->dev, "Bus error. Failed to write register.\n");
904 return ret;
905}
906
907static int ar9331_sw_bus_write(void *context, const void *data, size_t count)
908{
909 u32 reg = *(u32 *)data;
910 u32 val = *((u32 *)data + 1);
911
912 return ar9331_mdio_write(context, reg, val);
913}
914
915static const struct regmap_range ar9331_valid_regs[] = {
916 regmap_reg_range(0x0, 0x0),
917 regmap_reg_range(0x10, 0x14),
918 regmap_reg_range(0x20, 0x24),
919 regmap_reg_range(0x2c, 0x30),
920 regmap_reg_range(0x40, 0x44),
921 regmap_reg_range(0x50, 0x78),
922 regmap_reg_range(0x80, 0x98),
923
924 regmap_reg_range(0x100, 0x120),
925 regmap_reg_range(0x200, 0x220),
926 regmap_reg_range(0x300, 0x320),
927 regmap_reg_range(0x400, 0x420),
928 regmap_reg_range(0x500, 0x520),
929 regmap_reg_range(0x600, 0x620),
930
931 regmap_reg_range(0x20000, 0x200a4),
932 regmap_reg_range(0x20100, 0x201a4),
933 regmap_reg_range(0x20200, 0x202a4),
934 regmap_reg_range(0x20300, 0x203a4),
935 regmap_reg_range(0x20400, 0x204a4),
936 regmap_reg_range(0x20500, 0x205a4),
937
938
939 regmap_reg_range(AR9331_SW_REG_PAGE, AR9331_SW_REG_PAGE),
940};
941
942static const struct regmap_range ar9331_nonvolatile_regs[] = {
943 regmap_reg_range(AR9331_SW_REG_PAGE, AR9331_SW_REG_PAGE),
944};
945
946static const struct regmap_range_cfg ar9331_regmap_range[] = {
947 {
948 .selector_reg = AR9331_SW_REG_PAGE,
949 .selector_mask = GENMASK(9, 0),
950 .selector_shift = 0,
951
952 .window_start = 0,
953 .window_len = 512,
954
955 .range_min = 0,
956 .range_max = AR9331_SW_REG_PAGE - 4,
957 },
958};
959
960static const struct regmap_access_table ar9331_register_set = {
961 .yes_ranges = ar9331_valid_regs,
962 .n_yes_ranges = ARRAY_SIZE(ar9331_valid_regs),
963};
964
965static const struct regmap_access_table ar9331_volatile_set = {
966 .no_ranges = ar9331_nonvolatile_regs,
967 .n_no_ranges = ARRAY_SIZE(ar9331_nonvolatile_regs),
968};
969
970static const struct regmap_config ar9331_mdio_regmap_config = {
971 .reg_bits = 32,
972 .val_bits = 32,
973 .reg_stride = 4,
974 .max_register = AR9331_SW_REG_PAGE,
975
976 .ranges = ar9331_regmap_range,
977 .num_ranges = ARRAY_SIZE(ar9331_regmap_range),
978
979 .volatile_table = &ar9331_volatile_set,
980 .wr_table = &ar9331_register_set,
981 .rd_table = &ar9331_register_set,
982
983 .cache_type = REGCACHE_RBTREE,
984};
985
986static struct regmap_bus ar9331_sw_bus = {
987 .reg_format_endian_default = REGMAP_ENDIAN_NATIVE,
988 .val_format_endian_default = REGMAP_ENDIAN_NATIVE,
989 .read = ar9331_mdio_read,
990 .write = ar9331_sw_bus_write,
991 .max_raw_read = 4,
992 .max_raw_write = 4,
993};
994
995static int ar9331_sw_probe(struct mdio_device *mdiodev)
996{
997 struct ar9331_sw_priv *priv;
998 struct dsa_switch *ds;
999 int ret, i;
1000
1001 priv = devm_kzalloc(&mdiodev->dev, sizeof(*priv), GFP_KERNEL);
1002 if (!priv)
1003 return -ENOMEM;
1004
1005 priv->regmap = devm_regmap_init(&mdiodev->dev, &ar9331_sw_bus, priv,
1006 &ar9331_mdio_regmap_config);
1007 if (IS_ERR(priv->regmap)) {
1008 ret = PTR_ERR(priv->regmap);
1009 dev_err(&mdiodev->dev, "regmap init failed: %d\n", ret);
1010 return ret;
1011 }
1012
1013 priv->sw_reset = devm_reset_control_get(&mdiodev->dev, "switch");
1014 if (IS_ERR(priv->sw_reset)) {
1015 dev_err(&mdiodev->dev, "missing switch reset\n");
1016 return PTR_ERR(priv->sw_reset);
1017 }
1018
1019 priv->sbus = mdiodev->bus;
1020 priv->dev = &mdiodev->dev;
1021
1022 ret = ar9331_sw_irq_init(priv);
1023 if (ret)
1024 return ret;
1025
1026 ds = &priv->ds;
1027 ds->dev = &mdiodev->dev;
1028 ds->num_ports = AR9331_SW_PORTS;
1029 ds->priv = priv;
1030 priv->ops = ar9331_sw_ops;
1031 ds->ops = &priv->ops;
1032 dev_set_drvdata(&mdiodev->dev, priv);
1033
1034 for (i = 0; i < ARRAY_SIZE(priv->port); i++) {
1035 struct ar9331_sw_port *port = &priv->port[i];
1036
1037 port->idx = i;
1038 spin_lock_init(&port->stats_lock);
1039 INIT_DELAYED_WORK(&port->mib_read, ar9331_do_stats_poll);
1040 }
1041
1042 ret = dsa_register_switch(ds);
1043 if (ret)
1044 goto err_remove_irq;
1045
1046 return 0;
1047
1048err_remove_irq:
1049 irq_domain_remove(priv->irqdomain);
1050
1051 return ret;
1052}
1053
1054static void ar9331_sw_remove(struct mdio_device *mdiodev)
1055{
1056 struct ar9331_sw_priv *priv = dev_get_drvdata(&mdiodev->dev);
1057 unsigned int i;
1058
1059 if (!priv)
1060 return;
1061
1062 for (i = 0; i < ARRAY_SIZE(priv->port); i++) {
1063 struct ar9331_sw_port *port = &priv->port[i];
1064
1065 cancel_delayed_work_sync(&port->mib_read);
1066 }
1067
1068 irq_domain_remove(priv->irqdomain);
1069 dsa_unregister_switch(&priv->ds);
1070
1071 reset_control_assert(priv->sw_reset);
1072
1073 dev_set_drvdata(&mdiodev->dev, NULL);
1074}
1075
1076static void ar9331_sw_shutdown(struct mdio_device *mdiodev)
1077{
1078 struct ar9331_sw_priv *priv = dev_get_drvdata(&mdiodev->dev);
1079
1080 if (!priv)
1081 return;
1082
1083 dsa_switch_shutdown(&priv->ds);
1084
1085 dev_set_drvdata(&mdiodev->dev, NULL);
1086}
1087
1088static const struct of_device_id ar9331_sw_of_match[] = {
1089 { .compatible = "qca,ar9331-switch" },
1090 { },
1091};
1092
1093static struct mdio_driver ar9331_sw_mdio_driver = {
1094 .probe = ar9331_sw_probe,
1095 .remove = ar9331_sw_remove,
1096 .shutdown = ar9331_sw_shutdown,
1097 .mdiodrv.driver = {
1098 .name = AR9331_SW_NAME,
1099 .of_match_table = ar9331_sw_of_match,
1100 },
1101};
1102
1103mdio_module_driver(ar9331_sw_mdio_driver);
1104
1105MODULE_AUTHOR("Oleksij Rempel <kernel@pengutronix.de>");
1106MODULE_DESCRIPTION("Driver for Atheros AR9331 switch");
1107MODULE_LICENSE("GPL v2");
1108