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11#include <linux/ctype.h>
12#include <linux/stringify.h>
13#include <linux/ethtool.h>
14#include <linux/ethtool_netlink.h>
15#include <linux/linkmode.h>
16#include <linux/interrupt.h>
17#include <linux/pci.h>
18#include <linux/etherdevice.h>
19#include <linux/crc32.h>
20#include <linux/firmware.h>
21#include <linux/utsname.h>
22#include <linux/time.h>
23#include <linux/ptp_clock_kernel.h>
24#include <linux/net_tstamp.h>
25#include <linux/timecounter.h>
26#include <net/netlink.h>
27#include "bnxt_hsi.h"
28#include "bnxt.h"
29#include "bnxt_hwrm.h"
30#include "bnxt_ulp.h"
31#include "bnxt_xdp.h"
32#include "bnxt_ptp.h"
33#include "bnxt_ethtool.h"
34#include "bnxt_nvm_defs.h"
35#include "bnxt_fw_hdr.h"
36#include "bnxt_coredump.h"
37
38#define BNXT_NVM_ERR_MSG(dev, extack, msg) \
39 do { \
40 if (extack) \
41 NL_SET_ERR_MSG_MOD(extack, msg); \
42 netdev_err(dev, "%s\n", msg); \
43 } while (0)
44
45static u32 bnxt_get_msglevel(struct net_device *dev)
46{
47 struct bnxt *bp = netdev_priv(dev);
48
49 return bp->msg_enable;
50}
51
52static void bnxt_set_msglevel(struct net_device *dev, u32 value)
53{
54 struct bnxt *bp = netdev_priv(dev);
55
56 bp->msg_enable = value;
57}
58
59static int bnxt_get_coalesce(struct net_device *dev,
60 struct ethtool_coalesce *coal,
61 struct kernel_ethtool_coalesce *kernel_coal,
62 struct netlink_ext_ack *extack)
63{
64 struct bnxt *bp = netdev_priv(dev);
65 struct bnxt_coal *hw_coal;
66 u16 mult;
67
68 memset(coal, 0, sizeof(*coal));
69
70 coal->use_adaptive_rx_coalesce = bp->flags & BNXT_FLAG_DIM;
71
72 hw_coal = &bp->rx_coal;
73 mult = hw_coal->bufs_per_record;
74 coal->rx_coalesce_usecs = hw_coal->coal_ticks;
75 coal->rx_max_coalesced_frames = hw_coal->coal_bufs / mult;
76 coal->rx_coalesce_usecs_irq = hw_coal->coal_ticks_irq;
77 coal->rx_max_coalesced_frames_irq = hw_coal->coal_bufs_irq / mult;
78 if (hw_coal->flags &
79 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET)
80 kernel_coal->use_cqe_mode_rx = true;
81
82 hw_coal = &bp->tx_coal;
83 mult = hw_coal->bufs_per_record;
84 coal->tx_coalesce_usecs = hw_coal->coal_ticks;
85 coal->tx_max_coalesced_frames = hw_coal->coal_bufs / mult;
86 coal->tx_coalesce_usecs_irq = hw_coal->coal_ticks_irq;
87 coal->tx_max_coalesced_frames_irq = hw_coal->coal_bufs_irq / mult;
88 if (hw_coal->flags &
89 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET)
90 kernel_coal->use_cqe_mode_tx = true;
91
92 coal->stats_block_coalesce_usecs = bp->stats_coal_ticks;
93
94 return 0;
95}
96
97static int bnxt_set_coalesce(struct net_device *dev,
98 struct ethtool_coalesce *coal,
99 struct kernel_ethtool_coalesce *kernel_coal,
100 struct netlink_ext_ack *extack)
101{
102 struct bnxt *bp = netdev_priv(dev);
103 bool update_stats = false;
104 struct bnxt_coal *hw_coal;
105 int rc = 0;
106 u16 mult;
107
108 if (coal->use_adaptive_rx_coalesce) {
109 bp->flags |= BNXT_FLAG_DIM;
110 } else {
111 if (bp->flags & BNXT_FLAG_DIM) {
112 bp->flags &= ~(BNXT_FLAG_DIM);
113 goto reset_coalesce;
114 }
115 }
116
117 if ((kernel_coal->use_cqe_mode_rx || kernel_coal->use_cqe_mode_tx) &&
118 !(bp->coal_cap.cmpl_params &
119 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_TIMER_RESET))
120 return -EOPNOTSUPP;
121
122 hw_coal = &bp->rx_coal;
123 mult = hw_coal->bufs_per_record;
124 hw_coal->coal_ticks = coal->rx_coalesce_usecs;
125 hw_coal->coal_bufs = coal->rx_max_coalesced_frames * mult;
126 hw_coal->coal_ticks_irq = coal->rx_coalesce_usecs_irq;
127 hw_coal->coal_bufs_irq = coal->rx_max_coalesced_frames_irq * mult;
128 hw_coal->flags &=
129 ~RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET;
130 if (kernel_coal->use_cqe_mode_rx)
131 hw_coal->flags |=
132 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET;
133
134 hw_coal = &bp->tx_coal;
135 mult = hw_coal->bufs_per_record;
136 hw_coal->coal_ticks = coal->tx_coalesce_usecs;
137 hw_coal->coal_bufs = coal->tx_max_coalesced_frames * mult;
138 hw_coal->coal_ticks_irq = coal->tx_coalesce_usecs_irq;
139 hw_coal->coal_bufs_irq = coal->tx_max_coalesced_frames_irq * mult;
140 hw_coal->flags &=
141 ~RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET;
142 if (kernel_coal->use_cqe_mode_tx)
143 hw_coal->flags |=
144 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET;
145
146 if (bp->stats_coal_ticks != coal->stats_block_coalesce_usecs) {
147 u32 stats_ticks = coal->stats_block_coalesce_usecs;
148
149
150 if (stats_ticks)
151 stats_ticks = clamp_t(u32, stats_ticks,
152 BNXT_MIN_STATS_COAL_TICKS,
153 BNXT_MAX_STATS_COAL_TICKS);
154 stats_ticks = rounddown(stats_ticks, BNXT_MIN_STATS_COAL_TICKS);
155 bp->stats_coal_ticks = stats_ticks;
156 if (bp->stats_coal_ticks)
157 bp->current_interval =
158 bp->stats_coal_ticks * HZ / 1000000;
159 else
160 bp->current_interval = BNXT_TIMER_INTERVAL;
161 update_stats = true;
162 }
163
164reset_coalesce:
165 if (netif_running(dev)) {
166 if (update_stats) {
167 rc = bnxt_close_nic(bp, true, false);
168 if (!rc)
169 rc = bnxt_open_nic(bp, true, false);
170 } else {
171 rc = bnxt_hwrm_set_coal(bp);
172 }
173 }
174
175 return rc;
176}
177
178static const char * const bnxt_ring_rx_stats_str[] = {
179 "rx_ucast_packets",
180 "rx_mcast_packets",
181 "rx_bcast_packets",
182 "rx_discards",
183 "rx_errors",
184 "rx_ucast_bytes",
185 "rx_mcast_bytes",
186 "rx_bcast_bytes",
187};
188
189static const char * const bnxt_ring_tx_stats_str[] = {
190 "tx_ucast_packets",
191 "tx_mcast_packets",
192 "tx_bcast_packets",
193 "tx_errors",
194 "tx_discards",
195 "tx_ucast_bytes",
196 "tx_mcast_bytes",
197 "tx_bcast_bytes",
198};
199
200static const char * const bnxt_ring_tpa_stats_str[] = {
201 "tpa_packets",
202 "tpa_bytes",
203 "tpa_events",
204 "tpa_aborts",
205};
206
207static const char * const bnxt_ring_tpa2_stats_str[] = {
208 "rx_tpa_eligible_pkt",
209 "rx_tpa_eligible_bytes",
210 "rx_tpa_pkt",
211 "rx_tpa_bytes",
212 "rx_tpa_errors",
213 "rx_tpa_events",
214};
215
216static const char * const bnxt_rx_sw_stats_str[] = {
217 "rx_l4_csum_errors",
218 "rx_resets",
219 "rx_buf_errors",
220};
221
222static const char * const bnxt_cmn_sw_stats_str[] = {
223 "missed_irqs",
224};
225
226#define BNXT_RX_STATS_ENTRY(counter) \
227 { BNXT_RX_STATS_OFFSET(counter), __stringify(counter) }
228
229#define BNXT_TX_STATS_ENTRY(counter) \
230 { BNXT_TX_STATS_OFFSET(counter), __stringify(counter) }
231
232#define BNXT_RX_STATS_EXT_ENTRY(counter) \
233 { BNXT_RX_STATS_EXT_OFFSET(counter), __stringify(counter) }
234
235#define BNXT_TX_STATS_EXT_ENTRY(counter) \
236 { BNXT_TX_STATS_EXT_OFFSET(counter), __stringify(counter) }
237
238#define BNXT_RX_STATS_EXT_PFC_ENTRY(n) \
239 BNXT_RX_STATS_EXT_ENTRY(pfc_pri##n##_rx_duration_us), \
240 BNXT_RX_STATS_EXT_ENTRY(pfc_pri##n##_rx_transitions)
241
242#define BNXT_TX_STATS_EXT_PFC_ENTRY(n) \
243 BNXT_TX_STATS_EXT_ENTRY(pfc_pri##n##_tx_duration_us), \
244 BNXT_TX_STATS_EXT_ENTRY(pfc_pri##n##_tx_transitions)
245
246#define BNXT_RX_STATS_EXT_PFC_ENTRIES \
247 BNXT_RX_STATS_EXT_PFC_ENTRY(0), \
248 BNXT_RX_STATS_EXT_PFC_ENTRY(1), \
249 BNXT_RX_STATS_EXT_PFC_ENTRY(2), \
250 BNXT_RX_STATS_EXT_PFC_ENTRY(3), \
251 BNXT_RX_STATS_EXT_PFC_ENTRY(4), \
252 BNXT_RX_STATS_EXT_PFC_ENTRY(5), \
253 BNXT_RX_STATS_EXT_PFC_ENTRY(6), \
254 BNXT_RX_STATS_EXT_PFC_ENTRY(7)
255
256#define BNXT_TX_STATS_EXT_PFC_ENTRIES \
257 BNXT_TX_STATS_EXT_PFC_ENTRY(0), \
258 BNXT_TX_STATS_EXT_PFC_ENTRY(1), \
259 BNXT_TX_STATS_EXT_PFC_ENTRY(2), \
260 BNXT_TX_STATS_EXT_PFC_ENTRY(3), \
261 BNXT_TX_STATS_EXT_PFC_ENTRY(4), \
262 BNXT_TX_STATS_EXT_PFC_ENTRY(5), \
263 BNXT_TX_STATS_EXT_PFC_ENTRY(6), \
264 BNXT_TX_STATS_EXT_PFC_ENTRY(7)
265
266#define BNXT_RX_STATS_EXT_COS_ENTRY(n) \
267 BNXT_RX_STATS_EXT_ENTRY(rx_bytes_cos##n), \
268 BNXT_RX_STATS_EXT_ENTRY(rx_packets_cos##n)
269
270#define BNXT_TX_STATS_EXT_COS_ENTRY(n) \
271 BNXT_TX_STATS_EXT_ENTRY(tx_bytes_cos##n), \
272 BNXT_TX_STATS_EXT_ENTRY(tx_packets_cos##n)
273
274#define BNXT_RX_STATS_EXT_COS_ENTRIES \
275 BNXT_RX_STATS_EXT_COS_ENTRY(0), \
276 BNXT_RX_STATS_EXT_COS_ENTRY(1), \
277 BNXT_RX_STATS_EXT_COS_ENTRY(2), \
278 BNXT_RX_STATS_EXT_COS_ENTRY(3), \
279 BNXT_RX_STATS_EXT_COS_ENTRY(4), \
280 BNXT_RX_STATS_EXT_COS_ENTRY(5), \
281 BNXT_RX_STATS_EXT_COS_ENTRY(6), \
282 BNXT_RX_STATS_EXT_COS_ENTRY(7) \
283
284#define BNXT_TX_STATS_EXT_COS_ENTRIES \
285 BNXT_TX_STATS_EXT_COS_ENTRY(0), \
286 BNXT_TX_STATS_EXT_COS_ENTRY(1), \
287 BNXT_TX_STATS_EXT_COS_ENTRY(2), \
288 BNXT_TX_STATS_EXT_COS_ENTRY(3), \
289 BNXT_TX_STATS_EXT_COS_ENTRY(4), \
290 BNXT_TX_STATS_EXT_COS_ENTRY(5), \
291 BNXT_TX_STATS_EXT_COS_ENTRY(6), \
292 BNXT_TX_STATS_EXT_COS_ENTRY(7) \
293
294#define BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(n) \
295 BNXT_RX_STATS_EXT_ENTRY(rx_discard_bytes_cos##n), \
296 BNXT_RX_STATS_EXT_ENTRY(rx_discard_packets_cos##n)
297
298#define BNXT_RX_STATS_EXT_DISCARD_COS_ENTRIES \
299 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(0), \
300 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(1), \
301 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(2), \
302 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(3), \
303 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(4), \
304 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(5), \
305 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(6), \
306 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(7)
307
308#define BNXT_RX_STATS_PRI_ENTRY(counter, n) \
309 { BNXT_RX_STATS_EXT_OFFSET(counter##_cos0), \
310 __stringify(counter##_pri##n) }
311
312#define BNXT_TX_STATS_PRI_ENTRY(counter, n) \
313 { BNXT_TX_STATS_EXT_OFFSET(counter##_cos0), \
314 __stringify(counter##_pri##n) }
315
316#define BNXT_RX_STATS_PRI_ENTRIES(counter) \
317 BNXT_RX_STATS_PRI_ENTRY(counter, 0), \
318 BNXT_RX_STATS_PRI_ENTRY(counter, 1), \
319 BNXT_RX_STATS_PRI_ENTRY(counter, 2), \
320 BNXT_RX_STATS_PRI_ENTRY(counter, 3), \
321 BNXT_RX_STATS_PRI_ENTRY(counter, 4), \
322 BNXT_RX_STATS_PRI_ENTRY(counter, 5), \
323 BNXT_RX_STATS_PRI_ENTRY(counter, 6), \
324 BNXT_RX_STATS_PRI_ENTRY(counter, 7)
325
326#define BNXT_TX_STATS_PRI_ENTRIES(counter) \
327 BNXT_TX_STATS_PRI_ENTRY(counter, 0), \
328 BNXT_TX_STATS_PRI_ENTRY(counter, 1), \
329 BNXT_TX_STATS_PRI_ENTRY(counter, 2), \
330 BNXT_TX_STATS_PRI_ENTRY(counter, 3), \
331 BNXT_TX_STATS_PRI_ENTRY(counter, 4), \
332 BNXT_TX_STATS_PRI_ENTRY(counter, 5), \
333 BNXT_TX_STATS_PRI_ENTRY(counter, 6), \
334 BNXT_TX_STATS_PRI_ENTRY(counter, 7)
335
336enum {
337 RX_TOTAL_DISCARDS,
338 TX_TOTAL_DISCARDS,
339 RX_NETPOLL_DISCARDS,
340};
341
342static struct {
343 u64 counter;
344 char string[ETH_GSTRING_LEN];
345} bnxt_sw_func_stats[] = {
346 {0, "rx_total_discard_pkts"},
347 {0, "tx_total_discard_pkts"},
348 {0, "rx_total_netpoll_discards"},
349};
350
351#define NUM_RING_RX_SW_STATS ARRAY_SIZE(bnxt_rx_sw_stats_str)
352#define NUM_RING_CMN_SW_STATS ARRAY_SIZE(bnxt_cmn_sw_stats_str)
353#define NUM_RING_RX_HW_STATS ARRAY_SIZE(bnxt_ring_rx_stats_str)
354#define NUM_RING_TX_HW_STATS ARRAY_SIZE(bnxt_ring_tx_stats_str)
355
356static const struct {
357 long offset;
358 char string[ETH_GSTRING_LEN];
359} bnxt_port_stats_arr[] = {
360 BNXT_RX_STATS_ENTRY(rx_64b_frames),
361 BNXT_RX_STATS_ENTRY(rx_65b_127b_frames),
362 BNXT_RX_STATS_ENTRY(rx_128b_255b_frames),
363 BNXT_RX_STATS_ENTRY(rx_256b_511b_frames),
364 BNXT_RX_STATS_ENTRY(rx_512b_1023b_frames),
365 BNXT_RX_STATS_ENTRY(rx_1024b_1518b_frames),
366 BNXT_RX_STATS_ENTRY(rx_good_vlan_frames),
367 BNXT_RX_STATS_ENTRY(rx_1519b_2047b_frames),
368 BNXT_RX_STATS_ENTRY(rx_2048b_4095b_frames),
369 BNXT_RX_STATS_ENTRY(rx_4096b_9216b_frames),
370 BNXT_RX_STATS_ENTRY(rx_9217b_16383b_frames),
371 BNXT_RX_STATS_ENTRY(rx_total_frames),
372 BNXT_RX_STATS_ENTRY(rx_ucast_frames),
373 BNXT_RX_STATS_ENTRY(rx_mcast_frames),
374 BNXT_RX_STATS_ENTRY(rx_bcast_frames),
375 BNXT_RX_STATS_ENTRY(rx_fcs_err_frames),
376 BNXT_RX_STATS_ENTRY(rx_ctrl_frames),
377 BNXT_RX_STATS_ENTRY(rx_pause_frames),
378 BNXT_RX_STATS_ENTRY(rx_pfc_frames),
379 BNXT_RX_STATS_ENTRY(rx_align_err_frames),
380 BNXT_RX_STATS_ENTRY(rx_ovrsz_frames),
381 BNXT_RX_STATS_ENTRY(rx_jbr_frames),
382 BNXT_RX_STATS_ENTRY(rx_mtu_err_frames),
383 BNXT_RX_STATS_ENTRY(rx_tagged_frames),
384 BNXT_RX_STATS_ENTRY(rx_double_tagged_frames),
385 BNXT_RX_STATS_ENTRY(rx_good_frames),
386 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri0),
387 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri1),
388 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri2),
389 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri3),
390 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri4),
391 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri5),
392 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri6),
393 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri7),
394 BNXT_RX_STATS_ENTRY(rx_undrsz_frames),
395 BNXT_RX_STATS_ENTRY(rx_eee_lpi_events),
396 BNXT_RX_STATS_ENTRY(rx_eee_lpi_duration),
397 BNXT_RX_STATS_ENTRY(rx_bytes),
398 BNXT_RX_STATS_ENTRY(rx_runt_bytes),
399 BNXT_RX_STATS_ENTRY(rx_runt_frames),
400 BNXT_RX_STATS_ENTRY(rx_stat_discard),
401 BNXT_RX_STATS_ENTRY(rx_stat_err),
402
403 BNXT_TX_STATS_ENTRY(tx_64b_frames),
404 BNXT_TX_STATS_ENTRY(tx_65b_127b_frames),
405 BNXT_TX_STATS_ENTRY(tx_128b_255b_frames),
406 BNXT_TX_STATS_ENTRY(tx_256b_511b_frames),
407 BNXT_TX_STATS_ENTRY(tx_512b_1023b_frames),
408 BNXT_TX_STATS_ENTRY(tx_1024b_1518b_frames),
409 BNXT_TX_STATS_ENTRY(tx_good_vlan_frames),
410 BNXT_TX_STATS_ENTRY(tx_1519b_2047b_frames),
411 BNXT_TX_STATS_ENTRY(tx_2048b_4095b_frames),
412 BNXT_TX_STATS_ENTRY(tx_4096b_9216b_frames),
413 BNXT_TX_STATS_ENTRY(tx_9217b_16383b_frames),
414 BNXT_TX_STATS_ENTRY(tx_good_frames),
415 BNXT_TX_STATS_ENTRY(tx_total_frames),
416 BNXT_TX_STATS_ENTRY(tx_ucast_frames),
417 BNXT_TX_STATS_ENTRY(tx_mcast_frames),
418 BNXT_TX_STATS_ENTRY(tx_bcast_frames),
419 BNXT_TX_STATS_ENTRY(tx_pause_frames),
420 BNXT_TX_STATS_ENTRY(tx_pfc_frames),
421 BNXT_TX_STATS_ENTRY(tx_jabber_frames),
422 BNXT_TX_STATS_ENTRY(tx_fcs_err_frames),
423 BNXT_TX_STATS_ENTRY(tx_err),
424 BNXT_TX_STATS_ENTRY(tx_fifo_underruns),
425 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri0),
426 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri1),
427 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri2),
428 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri3),
429 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri4),
430 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri5),
431 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri6),
432 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri7),
433 BNXT_TX_STATS_ENTRY(tx_eee_lpi_events),
434 BNXT_TX_STATS_ENTRY(tx_eee_lpi_duration),
435 BNXT_TX_STATS_ENTRY(tx_total_collisions),
436 BNXT_TX_STATS_ENTRY(tx_bytes),
437 BNXT_TX_STATS_ENTRY(tx_xthol_frames),
438 BNXT_TX_STATS_ENTRY(tx_stat_discard),
439 BNXT_TX_STATS_ENTRY(tx_stat_error),
440};
441
442static const struct {
443 long offset;
444 char string[ETH_GSTRING_LEN];
445} bnxt_port_stats_ext_arr[] = {
446 BNXT_RX_STATS_EXT_ENTRY(link_down_events),
447 BNXT_RX_STATS_EXT_ENTRY(continuous_pause_events),
448 BNXT_RX_STATS_EXT_ENTRY(resume_pause_events),
449 BNXT_RX_STATS_EXT_ENTRY(continuous_roce_pause_events),
450 BNXT_RX_STATS_EXT_ENTRY(resume_roce_pause_events),
451 BNXT_RX_STATS_EXT_COS_ENTRIES,
452 BNXT_RX_STATS_EXT_PFC_ENTRIES,
453 BNXT_RX_STATS_EXT_ENTRY(rx_bits),
454 BNXT_RX_STATS_EXT_ENTRY(rx_buffer_passed_threshold),
455 BNXT_RX_STATS_EXT_ENTRY(rx_pcs_symbol_err),
456 BNXT_RX_STATS_EXT_ENTRY(rx_corrected_bits),
457 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRIES,
458 BNXT_RX_STATS_EXT_ENTRY(rx_fec_corrected_blocks),
459 BNXT_RX_STATS_EXT_ENTRY(rx_fec_uncorrectable_blocks),
460};
461
462static const struct {
463 long offset;
464 char string[ETH_GSTRING_LEN];
465} bnxt_tx_port_stats_ext_arr[] = {
466 BNXT_TX_STATS_EXT_COS_ENTRIES,
467 BNXT_TX_STATS_EXT_PFC_ENTRIES,
468};
469
470static const struct {
471 long base_off;
472 char string[ETH_GSTRING_LEN];
473} bnxt_rx_bytes_pri_arr[] = {
474 BNXT_RX_STATS_PRI_ENTRIES(rx_bytes),
475};
476
477static const struct {
478 long base_off;
479 char string[ETH_GSTRING_LEN];
480} bnxt_rx_pkts_pri_arr[] = {
481 BNXT_RX_STATS_PRI_ENTRIES(rx_packets),
482};
483
484static const struct {
485 long base_off;
486 char string[ETH_GSTRING_LEN];
487} bnxt_tx_bytes_pri_arr[] = {
488 BNXT_TX_STATS_PRI_ENTRIES(tx_bytes),
489};
490
491static const struct {
492 long base_off;
493 char string[ETH_GSTRING_LEN];
494} bnxt_tx_pkts_pri_arr[] = {
495 BNXT_TX_STATS_PRI_ENTRIES(tx_packets),
496};
497
498#define BNXT_NUM_SW_FUNC_STATS ARRAY_SIZE(bnxt_sw_func_stats)
499#define BNXT_NUM_PORT_STATS ARRAY_SIZE(bnxt_port_stats_arr)
500#define BNXT_NUM_STATS_PRI \
501 (ARRAY_SIZE(bnxt_rx_bytes_pri_arr) + \
502 ARRAY_SIZE(bnxt_rx_pkts_pri_arr) + \
503 ARRAY_SIZE(bnxt_tx_bytes_pri_arr) + \
504 ARRAY_SIZE(bnxt_tx_pkts_pri_arr))
505
506static int bnxt_get_num_tpa_ring_stats(struct bnxt *bp)
507{
508 if (BNXT_SUPPORTS_TPA(bp)) {
509 if (bp->max_tpa_v2) {
510 if (BNXT_CHIP_P5_THOR(bp))
511 return BNXT_NUM_TPA_RING_STATS_P5;
512 return BNXT_NUM_TPA_RING_STATS_P5_SR2;
513 }
514 return BNXT_NUM_TPA_RING_STATS;
515 }
516 return 0;
517}
518
519static int bnxt_get_num_ring_stats(struct bnxt *bp)
520{
521 int rx, tx, cmn;
522
523 rx = NUM_RING_RX_HW_STATS + NUM_RING_RX_SW_STATS +
524 bnxt_get_num_tpa_ring_stats(bp);
525 tx = NUM_RING_TX_HW_STATS;
526 cmn = NUM_RING_CMN_SW_STATS;
527 return rx * bp->rx_nr_rings + tx * bp->tx_nr_rings +
528 cmn * bp->cp_nr_rings;
529}
530
531static int bnxt_get_num_stats(struct bnxt *bp)
532{
533 int num_stats = bnxt_get_num_ring_stats(bp);
534
535 num_stats += BNXT_NUM_SW_FUNC_STATS;
536
537 if (bp->flags & BNXT_FLAG_PORT_STATS)
538 num_stats += BNXT_NUM_PORT_STATS;
539
540 if (bp->flags & BNXT_FLAG_PORT_STATS_EXT) {
541 num_stats += bp->fw_rx_stats_ext_size +
542 bp->fw_tx_stats_ext_size;
543 if (bp->pri2cos_valid)
544 num_stats += BNXT_NUM_STATS_PRI;
545 }
546
547 return num_stats;
548}
549
550static int bnxt_get_sset_count(struct net_device *dev, int sset)
551{
552 struct bnxt *bp = netdev_priv(dev);
553
554 switch (sset) {
555 case ETH_SS_STATS:
556 return bnxt_get_num_stats(bp);
557 case ETH_SS_TEST:
558 if (!bp->num_tests)
559 return -EOPNOTSUPP;
560 return bp->num_tests;
561 default:
562 return -EOPNOTSUPP;
563 }
564}
565
566static bool is_rx_ring(struct bnxt *bp, int ring_num)
567{
568 return ring_num < bp->rx_nr_rings;
569}
570
571static bool is_tx_ring(struct bnxt *bp, int ring_num)
572{
573 int tx_base = 0;
574
575 if (!(bp->flags & BNXT_FLAG_SHARED_RINGS))
576 tx_base = bp->rx_nr_rings;
577
578 if (ring_num >= tx_base && ring_num < (tx_base + bp->tx_nr_rings))
579 return true;
580 return false;
581}
582
583static void bnxt_get_ethtool_stats(struct net_device *dev,
584 struct ethtool_stats *stats, u64 *buf)
585{
586 u32 i, j = 0;
587 struct bnxt *bp = netdev_priv(dev);
588 u32 tpa_stats;
589
590 if (!bp->bnapi) {
591 j += bnxt_get_num_ring_stats(bp) + BNXT_NUM_SW_FUNC_STATS;
592 goto skip_ring_stats;
593 }
594
595 for (i = 0; i < BNXT_NUM_SW_FUNC_STATS; i++)
596 bnxt_sw_func_stats[i].counter = 0;
597
598 tpa_stats = bnxt_get_num_tpa_ring_stats(bp);
599 for (i = 0; i < bp->cp_nr_rings; i++) {
600 struct bnxt_napi *bnapi = bp->bnapi[i];
601 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
602 u64 *sw_stats = cpr->stats.sw_stats;
603 u64 *sw;
604 int k;
605
606 if (is_rx_ring(bp, i)) {
607 for (k = 0; k < NUM_RING_RX_HW_STATS; j++, k++)
608 buf[j] = sw_stats[k];
609 }
610 if (is_tx_ring(bp, i)) {
611 k = NUM_RING_RX_HW_STATS;
612 for (; k < NUM_RING_RX_HW_STATS + NUM_RING_TX_HW_STATS;
613 j++, k++)
614 buf[j] = sw_stats[k];
615 }
616 if (!tpa_stats || !is_rx_ring(bp, i))
617 goto skip_tpa_ring_stats;
618
619 k = NUM_RING_RX_HW_STATS + NUM_RING_TX_HW_STATS;
620 for (; k < NUM_RING_RX_HW_STATS + NUM_RING_TX_HW_STATS +
621 tpa_stats; j++, k++)
622 buf[j] = sw_stats[k];
623
624skip_tpa_ring_stats:
625 sw = (u64 *)&cpr->sw_stats.rx;
626 if (is_rx_ring(bp, i)) {
627 for (k = 0; k < NUM_RING_RX_SW_STATS; j++, k++)
628 buf[j] = sw[k];
629 }
630
631 sw = (u64 *)&cpr->sw_stats.cmn;
632 for (k = 0; k < NUM_RING_CMN_SW_STATS; j++, k++)
633 buf[j] = sw[k];
634
635 bnxt_sw_func_stats[RX_TOTAL_DISCARDS].counter +=
636 BNXT_GET_RING_STATS64(sw_stats, rx_discard_pkts);
637 bnxt_sw_func_stats[TX_TOTAL_DISCARDS].counter +=
638 BNXT_GET_RING_STATS64(sw_stats, tx_discard_pkts);
639 bnxt_sw_func_stats[RX_NETPOLL_DISCARDS].counter +=
640 cpr->sw_stats.rx.rx_netpoll_discards;
641 }
642
643 for (i = 0; i < BNXT_NUM_SW_FUNC_STATS; i++, j++)
644 buf[j] = bnxt_sw_func_stats[i].counter;
645
646skip_ring_stats:
647 if (bp->flags & BNXT_FLAG_PORT_STATS) {
648 u64 *port_stats = bp->port_stats.sw_stats;
649
650 for (i = 0; i < BNXT_NUM_PORT_STATS; i++, j++)
651 buf[j] = *(port_stats + bnxt_port_stats_arr[i].offset);
652 }
653 if (bp->flags & BNXT_FLAG_PORT_STATS_EXT) {
654 u64 *rx_port_stats_ext = bp->rx_port_stats_ext.sw_stats;
655 u64 *tx_port_stats_ext = bp->tx_port_stats_ext.sw_stats;
656
657 for (i = 0; i < bp->fw_rx_stats_ext_size; i++, j++) {
658 buf[j] = *(rx_port_stats_ext +
659 bnxt_port_stats_ext_arr[i].offset);
660 }
661 for (i = 0; i < bp->fw_tx_stats_ext_size; i++, j++) {
662 buf[j] = *(tx_port_stats_ext +
663 bnxt_tx_port_stats_ext_arr[i].offset);
664 }
665 if (bp->pri2cos_valid) {
666 for (i = 0; i < 8; i++, j++) {
667 long n = bnxt_rx_bytes_pri_arr[i].base_off +
668 bp->pri2cos_idx[i];
669
670 buf[j] = *(rx_port_stats_ext + n);
671 }
672 for (i = 0; i < 8; i++, j++) {
673 long n = bnxt_rx_pkts_pri_arr[i].base_off +
674 bp->pri2cos_idx[i];
675
676 buf[j] = *(rx_port_stats_ext + n);
677 }
678 for (i = 0; i < 8; i++, j++) {
679 long n = bnxt_tx_bytes_pri_arr[i].base_off +
680 bp->pri2cos_idx[i];
681
682 buf[j] = *(tx_port_stats_ext + n);
683 }
684 for (i = 0; i < 8; i++, j++) {
685 long n = bnxt_tx_pkts_pri_arr[i].base_off +
686 bp->pri2cos_idx[i];
687
688 buf[j] = *(tx_port_stats_ext + n);
689 }
690 }
691 }
692}
693
694static void bnxt_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
695{
696 struct bnxt *bp = netdev_priv(dev);
697 static const char * const *str;
698 u32 i, j, num_str;
699
700 switch (stringset) {
701 case ETH_SS_STATS:
702 for (i = 0; i < bp->cp_nr_rings; i++) {
703 if (is_rx_ring(bp, i)) {
704 num_str = NUM_RING_RX_HW_STATS;
705 for (j = 0; j < num_str; j++) {
706 sprintf(buf, "[%d]: %s", i,
707 bnxt_ring_rx_stats_str[j]);
708 buf += ETH_GSTRING_LEN;
709 }
710 }
711 if (is_tx_ring(bp, i)) {
712 num_str = NUM_RING_TX_HW_STATS;
713 for (j = 0; j < num_str; j++) {
714 sprintf(buf, "[%d]: %s", i,
715 bnxt_ring_tx_stats_str[j]);
716 buf += ETH_GSTRING_LEN;
717 }
718 }
719 num_str = bnxt_get_num_tpa_ring_stats(bp);
720 if (!num_str || !is_rx_ring(bp, i))
721 goto skip_tpa_stats;
722
723 if (bp->max_tpa_v2)
724 str = bnxt_ring_tpa2_stats_str;
725 else
726 str = bnxt_ring_tpa_stats_str;
727
728 for (j = 0; j < num_str; j++) {
729 sprintf(buf, "[%d]: %s", i, str[j]);
730 buf += ETH_GSTRING_LEN;
731 }
732skip_tpa_stats:
733 if (is_rx_ring(bp, i)) {
734 num_str = NUM_RING_RX_SW_STATS;
735 for (j = 0; j < num_str; j++) {
736 sprintf(buf, "[%d]: %s", i,
737 bnxt_rx_sw_stats_str[j]);
738 buf += ETH_GSTRING_LEN;
739 }
740 }
741 num_str = NUM_RING_CMN_SW_STATS;
742 for (j = 0; j < num_str; j++) {
743 sprintf(buf, "[%d]: %s", i,
744 bnxt_cmn_sw_stats_str[j]);
745 buf += ETH_GSTRING_LEN;
746 }
747 }
748 for (i = 0; i < BNXT_NUM_SW_FUNC_STATS; i++) {
749 strcpy(buf, bnxt_sw_func_stats[i].string);
750 buf += ETH_GSTRING_LEN;
751 }
752
753 if (bp->flags & BNXT_FLAG_PORT_STATS) {
754 for (i = 0; i < BNXT_NUM_PORT_STATS; i++) {
755 strcpy(buf, bnxt_port_stats_arr[i].string);
756 buf += ETH_GSTRING_LEN;
757 }
758 }
759 if (bp->flags & BNXT_FLAG_PORT_STATS_EXT) {
760 for (i = 0; i < bp->fw_rx_stats_ext_size; i++) {
761 strcpy(buf, bnxt_port_stats_ext_arr[i].string);
762 buf += ETH_GSTRING_LEN;
763 }
764 for (i = 0; i < bp->fw_tx_stats_ext_size; i++) {
765 strcpy(buf,
766 bnxt_tx_port_stats_ext_arr[i].string);
767 buf += ETH_GSTRING_LEN;
768 }
769 if (bp->pri2cos_valid) {
770 for (i = 0; i < 8; i++) {
771 strcpy(buf,
772 bnxt_rx_bytes_pri_arr[i].string);
773 buf += ETH_GSTRING_LEN;
774 }
775 for (i = 0; i < 8; i++) {
776 strcpy(buf,
777 bnxt_rx_pkts_pri_arr[i].string);
778 buf += ETH_GSTRING_LEN;
779 }
780 for (i = 0; i < 8; i++) {
781 strcpy(buf,
782 bnxt_tx_bytes_pri_arr[i].string);
783 buf += ETH_GSTRING_LEN;
784 }
785 for (i = 0; i < 8; i++) {
786 strcpy(buf,
787 bnxt_tx_pkts_pri_arr[i].string);
788 buf += ETH_GSTRING_LEN;
789 }
790 }
791 }
792 break;
793 case ETH_SS_TEST:
794 if (bp->num_tests)
795 memcpy(buf, bp->test_info->string,
796 bp->num_tests * ETH_GSTRING_LEN);
797 break;
798 default:
799 netdev_err(bp->dev, "bnxt_get_strings invalid request %x\n",
800 stringset);
801 break;
802 }
803}
804
805static void bnxt_get_ringparam(struct net_device *dev,
806 struct ethtool_ringparam *ering,
807 struct kernel_ethtool_ringparam *kernel_ering,
808 struct netlink_ext_ack *extack)
809{
810 struct bnxt *bp = netdev_priv(dev);
811
812 if (bp->flags & BNXT_FLAG_AGG_RINGS) {
813 ering->rx_max_pending = BNXT_MAX_RX_DESC_CNT_JUM_ENA;
814 ering->rx_jumbo_max_pending = BNXT_MAX_RX_JUM_DESC_CNT;
815 kernel_ering->tcp_data_split = ETHTOOL_TCP_DATA_SPLIT_ENABLED;
816 } else {
817 ering->rx_max_pending = BNXT_MAX_RX_DESC_CNT;
818 ering->rx_jumbo_max_pending = 0;
819 kernel_ering->tcp_data_split = ETHTOOL_TCP_DATA_SPLIT_DISABLED;
820 }
821 ering->tx_max_pending = BNXT_MAX_TX_DESC_CNT;
822
823 ering->rx_pending = bp->rx_ring_size;
824 ering->rx_jumbo_pending = bp->rx_agg_ring_size;
825 ering->tx_pending = bp->tx_ring_size;
826}
827
828static int bnxt_set_ringparam(struct net_device *dev,
829 struct ethtool_ringparam *ering,
830 struct kernel_ethtool_ringparam *kernel_ering,
831 struct netlink_ext_ack *extack)
832{
833 struct bnxt *bp = netdev_priv(dev);
834
835 if ((ering->rx_pending > BNXT_MAX_RX_DESC_CNT) ||
836 (ering->tx_pending > BNXT_MAX_TX_DESC_CNT) ||
837 (ering->tx_pending < BNXT_MIN_TX_DESC_CNT))
838 return -EINVAL;
839
840 if (netif_running(dev))
841 bnxt_close_nic(bp, false, false);
842
843 bp->rx_ring_size = ering->rx_pending;
844 bp->tx_ring_size = ering->tx_pending;
845 bnxt_set_ring_params(bp);
846
847 if (netif_running(dev))
848 return bnxt_open_nic(bp, false, false);
849
850 return 0;
851}
852
853static void bnxt_get_channels(struct net_device *dev,
854 struct ethtool_channels *channel)
855{
856 struct bnxt *bp = netdev_priv(dev);
857 struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
858 int max_rx_rings, max_tx_rings, tcs;
859 int max_tx_sch_inputs, tx_grps;
860
861
862 if (netif_running(dev) && BNXT_NEW_RM(bp))
863 bnxt_hwrm_func_resc_qcaps(bp, false);
864 max_tx_sch_inputs = hw_resc->max_tx_sch_inputs;
865
866 bnxt_get_max_rings(bp, &max_rx_rings, &max_tx_rings, true);
867 if (max_tx_sch_inputs)
868 max_tx_rings = min_t(int, max_tx_rings, max_tx_sch_inputs);
869
870 tcs = netdev_get_num_tc(dev);
871 tx_grps = max(tcs, 1);
872 if (bp->tx_nr_rings_xdp)
873 tx_grps++;
874 max_tx_rings /= tx_grps;
875 channel->max_combined = min_t(int, max_rx_rings, max_tx_rings);
876
877 if (bnxt_get_max_rings(bp, &max_rx_rings, &max_tx_rings, false)) {
878 max_rx_rings = 0;
879 max_tx_rings = 0;
880 }
881 if (max_tx_sch_inputs)
882 max_tx_rings = min_t(int, max_tx_rings, max_tx_sch_inputs);
883
884 if (tcs > 1)
885 max_tx_rings /= tcs;
886
887 channel->max_rx = max_rx_rings;
888 channel->max_tx = max_tx_rings;
889 channel->max_other = 0;
890 if (bp->flags & BNXT_FLAG_SHARED_RINGS) {
891 channel->combined_count = bp->rx_nr_rings;
892 if (BNXT_CHIP_TYPE_NITRO_A0(bp))
893 channel->combined_count--;
894 } else {
895 if (!BNXT_CHIP_TYPE_NITRO_A0(bp)) {
896 channel->rx_count = bp->rx_nr_rings;
897 channel->tx_count = bp->tx_nr_rings_per_tc;
898 }
899 }
900}
901
902static int bnxt_set_channels(struct net_device *dev,
903 struct ethtool_channels *channel)
904{
905 struct bnxt *bp = netdev_priv(dev);
906 int req_tx_rings, req_rx_rings, tcs;
907 bool sh = false;
908 int tx_xdp = 0;
909 int rc = 0;
910
911 if (channel->other_count)
912 return -EINVAL;
913
914 if (!channel->combined_count &&
915 (!channel->rx_count || !channel->tx_count))
916 return -EINVAL;
917
918 if (channel->combined_count &&
919 (channel->rx_count || channel->tx_count))
920 return -EINVAL;
921
922 if (BNXT_CHIP_TYPE_NITRO_A0(bp) && (channel->rx_count ||
923 channel->tx_count))
924 return -EINVAL;
925
926 if (channel->combined_count)
927 sh = true;
928
929 tcs = netdev_get_num_tc(dev);
930
931 req_tx_rings = sh ? channel->combined_count : channel->tx_count;
932 req_rx_rings = sh ? channel->combined_count : channel->rx_count;
933 if (bp->tx_nr_rings_xdp) {
934 if (!sh) {
935 netdev_err(dev, "Only combined mode supported when XDP is enabled.\n");
936 return -EINVAL;
937 }
938 tx_xdp = req_rx_rings;
939 }
940 rc = bnxt_check_rings(bp, req_tx_rings, req_rx_rings, sh, tcs, tx_xdp);
941 if (rc) {
942 netdev_warn(dev, "Unable to allocate the requested rings\n");
943 return rc;
944 }
945
946 if (bnxt_get_nr_rss_ctxs(bp, req_rx_rings) !=
947 bnxt_get_nr_rss_ctxs(bp, bp->rx_nr_rings) &&
948 netif_is_rxfh_configured(dev)) {
949 netdev_warn(dev, "RSS table size change required, RSS table entries must be default to proceed\n");
950 return -EINVAL;
951 }
952
953 if (netif_running(dev)) {
954 if (BNXT_PF(bp)) {
955
956
957
958 }
959 rc = bnxt_close_nic(bp, true, false);
960 if (rc) {
961 netdev_err(bp->dev, "Set channel failure rc :%x\n",
962 rc);
963 return rc;
964 }
965 }
966
967 if (sh) {
968 bp->flags |= BNXT_FLAG_SHARED_RINGS;
969 bp->rx_nr_rings = channel->combined_count;
970 bp->tx_nr_rings_per_tc = channel->combined_count;
971 } else {
972 bp->flags &= ~BNXT_FLAG_SHARED_RINGS;
973 bp->rx_nr_rings = channel->rx_count;
974 bp->tx_nr_rings_per_tc = channel->tx_count;
975 }
976 bp->tx_nr_rings_xdp = tx_xdp;
977 bp->tx_nr_rings = bp->tx_nr_rings_per_tc + tx_xdp;
978 if (tcs > 1)
979 bp->tx_nr_rings = bp->tx_nr_rings_per_tc * tcs + tx_xdp;
980
981 bp->cp_nr_rings = sh ? max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) :
982 bp->tx_nr_rings + bp->rx_nr_rings;
983
984
985 netdev_update_features(dev);
986 if (netif_running(dev)) {
987 rc = bnxt_open_nic(bp, true, false);
988 if ((!rc) && BNXT_PF(bp)) {
989
990
991
992 }
993 } else {
994 rc = bnxt_reserve_rings(bp, true);
995 }
996
997 return rc;
998}
999
1000#ifdef CONFIG_RFS_ACCEL
1001static int bnxt_grxclsrlall(struct bnxt *bp, struct ethtool_rxnfc *cmd,
1002 u32 *rule_locs)
1003{
1004 int i, j = 0;
1005
1006 cmd->data = bp->ntp_fltr_count;
1007 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) {
1008 struct hlist_head *head;
1009 struct bnxt_ntuple_filter *fltr;
1010
1011 head = &bp->ntp_fltr_hash_tbl[i];
1012 rcu_read_lock();
1013 hlist_for_each_entry_rcu(fltr, head, hash) {
1014 if (j == cmd->rule_cnt)
1015 break;
1016 rule_locs[j++] = fltr->sw_id;
1017 }
1018 rcu_read_unlock();
1019 if (j == cmd->rule_cnt)
1020 break;
1021 }
1022 cmd->rule_cnt = j;
1023 return 0;
1024}
1025
1026static int bnxt_grxclsrule(struct bnxt *bp, struct ethtool_rxnfc *cmd)
1027{
1028 struct ethtool_rx_flow_spec *fs =
1029 (struct ethtool_rx_flow_spec *)&cmd->fs;
1030 struct bnxt_ntuple_filter *fltr;
1031 struct flow_keys *fkeys;
1032 int i, rc = -EINVAL;
1033
1034 if (fs->location >= BNXT_NTP_FLTR_MAX_FLTR)
1035 return rc;
1036
1037 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) {
1038 struct hlist_head *head;
1039
1040 head = &bp->ntp_fltr_hash_tbl[i];
1041 rcu_read_lock();
1042 hlist_for_each_entry_rcu(fltr, head, hash) {
1043 if (fltr->sw_id == fs->location)
1044 goto fltr_found;
1045 }
1046 rcu_read_unlock();
1047 }
1048 return rc;
1049
1050fltr_found:
1051 fkeys = &fltr->fkeys;
1052 if (fkeys->basic.n_proto == htons(ETH_P_IP)) {
1053 if (fkeys->basic.ip_proto == IPPROTO_TCP)
1054 fs->flow_type = TCP_V4_FLOW;
1055 else if (fkeys->basic.ip_proto == IPPROTO_UDP)
1056 fs->flow_type = UDP_V4_FLOW;
1057 else
1058 goto fltr_err;
1059
1060 fs->h_u.tcp_ip4_spec.ip4src = fkeys->addrs.v4addrs.src;
1061 fs->m_u.tcp_ip4_spec.ip4src = cpu_to_be32(~0);
1062
1063 fs->h_u.tcp_ip4_spec.ip4dst = fkeys->addrs.v4addrs.dst;
1064 fs->m_u.tcp_ip4_spec.ip4dst = cpu_to_be32(~0);
1065
1066 fs->h_u.tcp_ip4_spec.psrc = fkeys->ports.src;
1067 fs->m_u.tcp_ip4_spec.psrc = cpu_to_be16(~0);
1068
1069 fs->h_u.tcp_ip4_spec.pdst = fkeys->ports.dst;
1070 fs->m_u.tcp_ip4_spec.pdst = cpu_to_be16(~0);
1071 } else {
1072 int i;
1073
1074 if (fkeys->basic.ip_proto == IPPROTO_TCP)
1075 fs->flow_type = TCP_V6_FLOW;
1076 else if (fkeys->basic.ip_proto == IPPROTO_UDP)
1077 fs->flow_type = UDP_V6_FLOW;
1078 else
1079 goto fltr_err;
1080
1081 *(struct in6_addr *)&fs->h_u.tcp_ip6_spec.ip6src[0] =
1082 fkeys->addrs.v6addrs.src;
1083 *(struct in6_addr *)&fs->h_u.tcp_ip6_spec.ip6dst[0] =
1084 fkeys->addrs.v6addrs.dst;
1085 for (i = 0; i < 4; i++) {
1086 fs->m_u.tcp_ip6_spec.ip6src[i] = cpu_to_be32(~0);
1087 fs->m_u.tcp_ip6_spec.ip6dst[i] = cpu_to_be32(~0);
1088 }
1089 fs->h_u.tcp_ip6_spec.psrc = fkeys->ports.src;
1090 fs->m_u.tcp_ip6_spec.psrc = cpu_to_be16(~0);
1091
1092 fs->h_u.tcp_ip6_spec.pdst = fkeys->ports.dst;
1093 fs->m_u.tcp_ip6_spec.pdst = cpu_to_be16(~0);
1094 }
1095
1096 fs->ring_cookie = fltr->rxq;
1097 rc = 0;
1098
1099fltr_err:
1100 rcu_read_unlock();
1101
1102 return rc;
1103}
1104#endif
1105
1106static u64 get_ethtool_ipv4_rss(struct bnxt *bp)
1107{
1108 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4)
1109 return RXH_IP_SRC | RXH_IP_DST;
1110 return 0;
1111}
1112
1113static u64 get_ethtool_ipv6_rss(struct bnxt *bp)
1114{
1115 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6)
1116 return RXH_IP_SRC | RXH_IP_DST;
1117 return 0;
1118}
1119
1120static int bnxt_grxfh(struct bnxt *bp, struct ethtool_rxnfc *cmd)
1121{
1122 cmd->data = 0;
1123 switch (cmd->flow_type) {
1124 case TCP_V4_FLOW:
1125 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4)
1126 cmd->data |= RXH_IP_SRC | RXH_IP_DST |
1127 RXH_L4_B_0_1 | RXH_L4_B_2_3;
1128 cmd->data |= get_ethtool_ipv4_rss(bp);
1129 break;
1130 case UDP_V4_FLOW:
1131 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4)
1132 cmd->data |= RXH_IP_SRC | RXH_IP_DST |
1133 RXH_L4_B_0_1 | RXH_L4_B_2_3;
1134 fallthrough;
1135 case SCTP_V4_FLOW:
1136 case AH_ESP_V4_FLOW:
1137 case AH_V4_FLOW:
1138 case ESP_V4_FLOW:
1139 case IPV4_FLOW:
1140 cmd->data |= get_ethtool_ipv4_rss(bp);
1141 break;
1142
1143 case TCP_V6_FLOW:
1144 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6)
1145 cmd->data |= RXH_IP_SRC | RXH_IP_DST |
1146 RXH_L4_B_0_1 | RXH_L4_B_2_3;
1147 cmd->data |= get_ethtool_ipv6_rss(bp);
1148 break;
1149 case UDP_V6_FLOW:
1150 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6)
1151 cmd->data |= RXH_IP_SRC | RXH_IP_DST |
1152 RXH_L4_B_0_1 | RXH_L4_B_2_3;
1153 fallthrough;
1154 case SCTP_V6_FLOW:
1155 case AH_ESP_V6_FLOW:
1156 case AH_V6_FLOW:
1157 case ESP_V6_FLOW:
1158 case IPV6_FLOW:
1159 cmd->data |= get_ethtool_ipv6_rss(bp);
1160 break;
1161 }
1162 return 0;
1163}
1164
1165#define RXH_4TUPLE (RXH_IP_SRC | RXH_IP_DST | RXH_L4_B_0_1 | RXH_L4_B_2_3)
1166#define RXH_2TUPLE (RXH_IP_SRC | RXH_IP_DST)
1167
1168static int bnxt_srxfh(struct bnxt *bp, struct ethtool_rxnfc *cmd)
1169{
1170 u32 rss_hash_cfg = bp->rss_hash_cfg;
1171 int tuple, rc = 0;
1172
1173 if (cmd->data == RXH_4TUPLE)
1174 tuple = 4;
1175 else if (cmd->data == RXH_2TUPLE)
1176 tuple = 2;
1177 else if (!cmd->data)
1178 tuple = 0;
1179 else
1180 return -EINVAL;
1181
1182 if (cmd->flow_type == TCP_V4_FLOW) {
1183 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4;
1184 if (tuple == 4)
1185 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4;
1186 } else if (cmd->flow_type == UDP_V4_FLOW) {
1187 if (tuple == 4 && !(bp->flags & BNXT_FLAG_UDP_RSS_CAP))
1188 return -EINVAL;
1189 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4;
1190 if (tuple == 4)
1191 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4;
1192 } else if (cmd->flow_type == TCP_V6_FLOW) {
1193 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6;
1194 if (tuple == 4)
1195 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6;
1196 } else if (cmd->flow_type == UDP_V6_FLOW) {
1197 if (tuple == 4 && !(bp->flags & BNXT_FLAG_UDP_RSS_CAP))
1198 return -EINVAL;
1199 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6;
1200 if (tuple == 4)
1201 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6;
1202 } else if (tuple == 4) {
1203 return -EINVAL;
1204 }
1205
1206 switch (cmd->flow_type) {
1207 case TCP_V4_FLOW:
1208 case UDP_V4_FLOW:
1209 case SCTP_V4_FLOW:
1210 case AH_ESP_V4_FLOW:
1211 case AH_V4_FLOW:
1212 case ESP_V4_FLOW:
1213 case IPV4_FLOW:
1214 if (tuple == 2)
1215 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4;
1216 else if (!tuple)
1217 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4;
1218 break;
1219
1220 case TCP_V6_FLOW:
1221 case UDP_V6_FLOW:
1222 case SCTP_V6_FLOW:
1223 case AH_ESP_V6_FLOW:
1224 case AH_V6_FLOW:
1225 case ESP_V6_FLOW:
1226 case IPV6_FLOW:
1227 if (tuple == 2)
1228 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6;
1229 else if (!tuple)
1230 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6;
1231 break;
1232 }
1233
1234 if (bp->rss_hash_cfg == rss_hash_cfg)
1235 return 0;
1236
1237 bp->rss_hash_cfg = rss_hash_cfg;
1238 if (netif_running(bp->dev)) {
1239 bnxt_close_nic(bp, false, false);
1240 rc = bnxt_open_nic(bp, false, false);
1241 }
1242 return rc;
1243}
1244
1245static int bnxt_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd,
1246 u32 *rule_locs)
1247{
1248 struct bnxt *bp = netdev_priv(dev);
1249 int rc = 0;
1250
1251 switch (cmd->cmd) {
1252#ifdef CONFIG_RFS_ACCEL
1253 case ETHTOOL_GRXRINGS:
1254 cmd->data = bp->rx_nr_rings;
1255 break;
1256
1257 case ETHTOOL_GRXCLSRLCNT:
1258 cmd->rule_cnt = bp->ntp_fltr_count;
1259 cmd->data = BNXT_NTP_FLTR_MAX_FLTR;
1260 break;
1261
1262 case ETHTOOL_GRXCLSRLALL:
1263 rc = bnxt_grxclsrlall(bp, cmd, (u32 *)rule_locs);
1264 break;
1265
1266 case ETHTOOL_GRXCLSRULE:
1267 rc = bnxt_grxclsrule(bp, cmd);
1268 break;
1269#endif
1270
1271 case ETHTOOL_GRXFH:
1272 rc = bnxt_grxfh(bp, cmd);
1273 break;
1274
1275 default:
1276 rc = -EOPNOTSUPP;
1277 break;
1278 }
1279
1280 return rc;
1281}
1282
1283static int bnxt_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd)
1284{
1285 struct bnxt *bp = netdev_priv(dev);
1286 int rc;
1287
1288 switch (cmd->cmd) {
1289 case ETHTOOL_SRXFH:
1290 rc = bnxt_srxfh(bp, cmd);
1291 break;
1292
1293 default:
1294 rc = -EOPNOTSUPP;
1295 break;
1296 }
1297 return rc;
1298}
1299
1300u32 bnxt_get_rxfh_indir_size(struct net_device *dev)
1301{
1302 struct bnxt *bp = netdev_priv(dev);
1303
1304 if (bp->flags & BNXT_FLAG_CHIP_P5)
1305 return ALIGN(bp->rx_nr_rings, BNXT_RSS_TABLE_ENTRIES_P5);
1306 return HW_HASH_INDEX_SIZE;
1307}
1308
1309static u32 bnxt_get_rxfh_key_size(struct net_device *dev)
1310{
1311 return HW_HASH_KEY_SIZE;
1312}
1313
1314static int bnxt_get_rxfh(struct net_device *dev, u32 *indir, u8 *key,
1315 u8 *hfunc)
1316{
1317 struct bnxt *bp = netdev_priv(dev);
1318 struct bnxt_vnic_info *vnic;
1319 u32 i, tbl_size;
1320
1321 if (hfunc)
1322 *hfunc = ETH_RSS_HASH_TOP;
1323
1324 if (!bp->vnic_info)
1325 return 0;
1326
1327 vnic = &bp->vnic_info[0];
1328 if (indir && bp->rss_indir_tbl) {
1329 tbl_size = bnxt_get_rxfh_indir_size(dev);
1330 for (i = 0; i < tbl_size; i++)
1331 indir[i] = bp->rss_indir_tbl[i];
1332 }
1333
1334 if (key && vnic->rss_hash_key)
1335 memcpy(key, vnic->rss_hash_key, HW_HASH_KEY_SIZE);
1336
1337 return 0;
1338}
1339
1340static int bnxt_set_rxfh(struct net_device *dev, const u32 *indir,
1341 const u8 *key, const u8 hfunc)
1342{
1343 struct bnxt *bp = netdev_priv(dev);
1344 int rc = 0;
1345
1346 if (hfunc && hfunc != ETH_RSS_HASH_TOP)
1347 return -EOPNOTSUPP;
1348
1349 if (key)
1350 return -EOPNOTSUPP;
1351
1352 if (indir) {
1353 u32 i, pad, tbl_size = bnxt_get_rxfh_indir_size(dev);
1354
1355 for (i = 0; i < tbl_size; i++)
1356 bp->rss_indir_tbl[i] = indir[i];
1357 pad = bp->rss_indir_tbl_entries - tbl_size;
1358 if (pad)
1359 memset(&bp->rss_indir_tbl[i], 0, pad * sizeof(u16));
1360 }
1361
1362 if (netif_running(bp->dev)) {
1363 bnxt_close_nic(bp, false, false);
1364 rc = bnxt_open_nic(bp, false, false);
1365 }
1366 return rc;
1367}
1368
1369static void bnxt_get_drvinfo(struct net_device *dev,
1370 struct ethtool_drvinfo *info)
1371{
1372 struct bnxt *bp = netdev_priv(dev);
1373
1374 strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver));
1375 strlcpy(info->fw_version, bp->fw_ver_str, sizeof(info->fw_version));
1376 strlcpy(info->bus_info, pci_name(bp->pdev), sizeof(info->bus_info));
1377 info->n_stats = bnxt_get_num_stats(bp);
1378 info->testinfo_len = bp->num_tests;
1379
1380 info->eedump_len = 0;
1381
1382 info->regdump_len = 0;
1383}
1384
1385static int bnxt_get_regs_len(struct net_device *dev)
1386{
1387 struct bnxt *bp = netdev_priv(dev);
1388 int reg_len;
1389
1390 if (!BNXT_PF(bp))
1391 return -EOPNOTSUPP;
1392
1393 reg_len = BNXT_PXP_REG_LEN;
1394
1395 if (bp->fw_cap & BNXT_FW_CAP_PCIE_STATS_SUPPORTED)
1396 reg_len += sizeof(struct pcie_ctx_hw_stats);
1397
1398 return reg_len;
1399}
1400
1401static void bnxt_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1402 void *_p)
1403{
1404 struct pcie_ctx_hw_stats *hw_pcie_stats;
1405 struct hwrm_pcie_qstats_input *req;
1406 struct bnxt *bp = netdev_priv(dev);
1407 dma_addr_t hw_pcie_stats_addr;
1408 int rc;
1409
1410 regs->version = 0;
1411 bnxt_dbg_hwrm_rd_reg(bp, 0, BNXT_PXP_REG_LEN / 4, _p);
1412
1413 if (!(bp->fw_cap & BNXT_FW_CAP_PCIE_STATS_SUPPORTED))
1414 return;
1415
1416 if (hwrm_req_init(bp, req, HWRM_PCIE_QSTATS))
1417 return;
1418
1419 hw_pcie_stats = hwrm_req_dma_slice(bp, req, sizeof(*hw_pcie_stats),
1420 &hw_pcie_stats_addr);
1421 if (!hw_pcie_stats) {
1422 hwrm_req_drop(bp, req);
1423 return;
1424 }
1425
1426 regs->version = 1;
1427 hwrm_req_hold(bp, req);
1428 req->pcie_stat_size = cpu_to_le16(sizeof(*hw_pcie_stats));
1429 req->pcie_stat_host_addr = cpu_to_le64(hw_pcie_stats_addr);
1430 rc = hwrm_req_send(bp, req);
1431 if (!rc) {
1432 __le64 *src = (__le64 *)hw_pcie_stats;
1433 u64 *dst = (u64 *)(_p + BNXT_PXP_REG_LEN);
1434 int i;
1435
1436 for (i = 0; i < sizeof(*hw_pcie_stats) / sizeof(__le64); i++)
1437 dst[i] = le64_to_cpu(src[i]);
1438 }
1439 hwrm_req_drop(bp, req);
1440}
1441
1442static void bnxt_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1443{
1444 struct bnxt *bp = netdev_priv(dev);
1445
1446 wol->supported = 0;
1447 wol->wolopts = 0;
1448 memset(&wol->sopass, 0, sizeof(wol->sopass));
1449 if (bp->flags & BNXT_FLAG_WOL_CAP) {
1450 wol->supported = WAKE_MAGIC;
1451 if (bp->wol)
1452 wol->wolopts = WAKE_MAGIC;
1453 }
1454}
1455
1456static int bnxt_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1457{
1458 struct bnxt *bp = netdev_priv(dev);
1459
1460 if (wol->wolopts & ~WAKE_MAGIC)
1461 return -EINVAL;
1462
1463 if (wol->wolopts & WAKE_MAGIC) {
1464 if (!(bp->flags & BNXT_FLAG_WOL_CAP))
1465 return -EINVAL;
1466 if (!bp->wol) {
1467 if (bnxt_hwrm_alloc_wol_fltr(bp))
1468 return -EBUSY;
1469 bp->wol = 1;
1470 }
1471 } else {
1472 if (bp->wol) {
1473 if (bnxt_hwrm_free_wol_fltr(bp))
1474 return -EBUSY;
1475 bp->wol = 0;
1476 }
1477 }
1478 return 0;
1479}
1480
1481u32 _bnxt_fw_to_ethtool_adv_spds(u16 fw_speeds, u8 fw_pause)
1482{
1483 u32 speed_mask = 0;
1484
1485
1486
1487 if (fw_speeds & BNXT_LINK_SPEED_MSK_100MB)
1488 speed_mask |= ADVERTISED_100baseT_Full;
1489 if (fw_speeds & BNXT_LINK_SPEED_MSK_1GB)
1490 speed_mask |= ADVERTISED_1000baseT_Full;
1491 if (fw_speeds & BNXT_LINK_SPEED_MSK_2_5GB)
1492 speed_mask |= ADVERTISED_2500baseX_Full;
1493 if (fw_speeds & BNXT_LINK_SPEED_MSK_10GB)
1494 speed_mask |= ADVERTISED_10000baseT_Full;
1495 if (fw_speeds & BNXT_LINK_SPEED_MSK_40GB)
1496 speed_mask |= ADVERTISED_40000baseCR4_Full;
1497
1498 if ((fw_pause & BNXT_LINK_PAUSE_BOTH) == BNXT_LINK_PAUSE_BOTH)
1499 speed_mask |= ADVERTISED_Pause;
1500 else if (fw_pause & BNXT_LINK_PAUSE_TX)
1501 speed_mask |= ADVERTISED_Asym_Pause;
1502 else if (fw_pause & BNXT_LINK_PAUSE_RX)
1503 speed_mask |= ADVERTISED_Pause | ADVERTISED_Asym_Pause;
1504
1505 return speed_mask;
1506}
1507
1508#define BNXT_FW_TO_ETHTOOL_SPDS(fw_speeds, fw_pause, lk_ksettings, name)\
1509{ \
1510 if ((fw_speeds) & BNXT_LINK_SPEED_MSK_100MB) \
1511 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\
1512 100baseT_Full); \
1513 if ((fw_speeds) & BNXT_LINK_SPEED_MSK_1GB) \
1514 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\
1515 1000baseT_Full); \
1516 if ((fw_speeds) & BNXT_LINK_SPEED_MSK_10GB) \
1517 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\
1518 10000baseT_Full); \
1519 if ((fw_speeds) & BNXT_LINK_SPEED_MSK_25GB) \
1520 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\
1521 25000baseCR_Full); \
1522 if ((fw_speeds) & BNXT_LINK_SPEED_MSK_40GB) \
1523 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\
1524 40000baseCR4_Full);\
1525 if ((fw_speeds) & BNXT_LINK_SPEED_MSK_50GB) \
1526 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\
1527 50000baseCR2_Full);\
1528 if ((fw_speeds) & BNXT_LINK_SPEED_MSK_100GB) \
1529 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\
1530 100000baseCR4_Full);\
1531 if ((fw_pause) & BNXT_LINK_PAUSE_RX) { \
1532 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\
1533 Pause); \
1534 if (!((fw_pause) & BNXT_LINK_PAUSE_TX)) \
1535 ethtool_link_ksettings_add_link_mode( \
1536 lk_ksettings, name, Asym_Pause);\
1537 } else if ((fw_pause) & BNXT_LINK_PAUSE_TX) { \
1538 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\
1539 Asym_Pause); \
1540 } \
1541}
1542
1543#define BNXT_ETHTOOL_TO_FW_SPDS(fw_speeds, lk_ksettings, name) \
1544{ \
1545 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \
1546 100baseT_Full) || \
1547 ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \
1548 100baseT_Half)) \
1549 (fw_speeds) |= BNXT_LINK_SPEED_MSK_100MB; \
1550 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \
1551 1000baseT_Full) || \
1552 ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \
1553 1000baseT_Half)) \
1554 (fw_speeds) |= BNXT_LINK_SPEED_MSK_1GB; \
1555 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \
1556 10000baseT_Full)) \
1557 (fw_speeds) |= BNXT_LINK_SPEED_MSK_10GB; \
1558 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \
1559 25000baseCR_Full)) \
1560 (fw_speeds) |= BNXT_LINK_SPEED_MSK_25GB; \
1561 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \
1562 40000baseCR4_Full)) \
1563 (fw_speeds) |= BNXT_LINK_SPEED_MSK_40GB; \
1564 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \
1565 50000baseCR2_Full)) \
1566 (fw_speeds) |= BNXT_LINK_SPEED_MSK_50GB; \
1567 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \
1568 100000baseCR4_Full)) \
1569 (fw_speeds) |= BNXT_LINK_SPEED_MSK_100GB; \
1570}
1571
1572#define BNXT_FW_TO_ETHTOOL_PAM4_SPDS(fw_speeds, lk_ksettings, name) \
1573{ \
1574 if ((fw_speeds) & BNXT_LINK_PAM4_SPEED_MSK_50GB) \
1575 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\
1576 50000baseCR_Full); \
1577 if ((fw_speeds) & BNXT_LINK_PAM4_SPEED_MSK_100GB) \
1578 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\
1579 100000baseCR2_Full);\
1580 if ((fw_speeds) & BNXT_LINK_PAM4_SPEED_MSK_200GB) \
1581 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\
1582 200000baseCR4_Full);\
1583}
1584
1585#define BNXT_ETHTOOL_TO_FW_PAM4_SPDS(fw_speeds, lk_ksettings, name) \
1586{ \
1587 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \
1588 50000baseCR_Full)) \
1589 (fw_speeds) |= BNXT_LINK_PAM4_SPEED_MSK_50GB; \
1590 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \
1591 100000baseCR2_Full)) \
1592 (fw_speeds) |= BNXT_LINK_PAM4_SPEED_MSK_100GB; \
1593 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \
1594 200000baseCR4_Full)) \
1595 (fw_speeds) |= BNXT_LINK_PAM4_SPEED_MSK_200GB; \
1596}
1597
1598static void bnxt_fw_to_ethtool_advertised_fec(struct bnxt_link_info *link_info,
1599 struct ethtool_link_ksettings *lk_ksettings)
1600{
1601 u16 fec_cfg = link_info->fec_cfg;
1602
1603 if ((fec_cfg & BNXT_FEC_NONE) || !(fec_cfg & BNXT_FEC_AUTONEG)) {
1604 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT,
1605 lk_ksettings->link_modes.advertising);
1606 return;
1607 }
1608 if (fec_cfg & BNXT_FEC_ENC_BASE_R)
1609 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_BASER_BIT,
1610 lk_ksettings->link_modes.advertising);
1611 if (fec_cfg & BNXT_FEC_ENC_RS)
1612 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_RS_BIT,
1613 lk_ksettings->link_modes.advertising);
1614 if (fec_cfg & BNXT_FEC_ENC_LLRS)
1615 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_LLRS_BIT,
1616 lk_ksettings->link_modes.advertising);
1617}
1618
1619static void bnxt_fw_to_ethtool_advertised_spds(struct bnxt_link_info *link_info,
1620 struct ethtool_link_ksettings *lk_ksettings)
1621{
1622 u16 fw_speeds = link_info->advertising;
1623 u8 fw_pause = 0;
1624
1625 if (link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL)
1626 fw_pause = link_info->auto_pause_setting;
1627
1628 BNXT_FW_TO_ETHTOOL_SPDS(fw_speeds, fw_pause, lk_ksettings, advertising);
1629 fw_speeds = link_info->advertising_pam4;
1630 BNXT_FW_TO_ETHTOOL_PAM4_SPDS(fw_speeds, lk_ksettings, advertising);
1631 bnxt_fw_to_ethtool_advertised_fec(link_info, lk_ksettings);
1632}
1633
1634static void bnxt_fw_to_ethtool_lp_adv(struct bnxt_link_info *link_info,
1635 struct ethtool_link_ksettings *lk_ksettings)
1636{
1637 u16 fw_speeds = link_info->lp_auto_link_speeds;
1638 u8 fw_pause = 0;
1639
1640 if (link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL)
1641 fw_pause = link_info->lp_pause;
1642
1643 BNXT_FW_TO_ETHTOOL_SPDS(fw_speeds, fw_pause, lk_ksettings,
1644 lp_advertising);
1645 fw_speeds = link_info->lp_auto_pam4_link_speeds;
1646 BNXT_FW_TO_ETHTOOL_PAM4_SPDS(fw_speeds, lk_ksettings, lp_advertising);
1647}
1648
1649static void bnxt_fw_to_ethtool_support_fec(struct bnxt_link_info *link_info,
1650 struct ethtool_link_ksettings *lk_ksettings)
1651{
1652 u16 fec_cfg = link_info->fec_cfg;
1653
1654 if (fec_cfg & BNXT_FEC_NONE) {
1655 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT,
1656 lk_ksettings->link_modes.supported);
1657 return;
1658 }
1659 if (fec_cfg & BNXT_FEC_ENC_BASE_R_CAP)
1660 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_BASER_BIT,
1661 lk_ksettings->link_modes.supported);
1662 if (fec_cfg & BNXT_FEC_ENC_RS_CAP)
1663 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_RS_BIT,
1664 lk_ksettings->link_modes.supported);
1665 if (fec_cfg & BNXT_FEC_ENC_LLRS_CAP)
1666 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_LLRS_BIT,
1667 lk_ksettings->link_modes.supported);
1668}
1669
1670static void bnxt_fw_to_ethtool_support_spds(struct bnxt_link_info *link_info,
1671 struct ethtool_link_ksettings *lk_ksettings)
1672{
1673 struct bnxt *bp = container_of(link_info, struct bnxt, link_info);
1674 u16 fw_speeds = link_info->support_speeds;
1675
1676 BNXT_FW_TO_ETHTOOL_SPDS(fw_speeds, 0, lk_ksettings, supported);
1677 fw_speeds = link_info->support_pam4_speeds;
1678 BNXT_FW_TO_ETHTOOL_PAM4_SPDS(fw_speeds, lk_ksettings, supported);
1679
1680 if (!(bp->phy_flags & BNXT_PHY_FL_NO_PAUSE)) {
1681 ethtool_link_ksettings_add_link_mode(lk_ksettings, supported,
1682 Pause);
1683 ethtool_link_ksettings_add_link_mode(lk_ksettings, supported,
1684 Asym_Pause);
1685 }
1686
1687 if (link_info->support_auto_speeds ||
1688 link_info->support_pam4_auto_speeds)
1689 ethtool_link_ksettings_add_link_mode(lk_ksettings, supported,
1690 Autoneg);
1691 bnxt_fw_to_ethtool_support_fec(link_info, lk_ksettings);
1692}
1693
1694u32 bnxt_fw_to_ethtool_speed(u16 fw_link_speed)
1695{
1696 switch (fw_link_speed) {
1697 case BNXT_LINK_SPEED_100MB:
1698 return SPEED_100;
1699 case BNXT_LINK_SPEED_1GB:
1700 return SPEED_1000;
1701 case BNXT_LINK_SPEED_2_5GB:
1702 return SPEED_2500;
1703 case BNXT_LINK_SPEED_10GB:
1704 return SPEED_10000;
1705 case BNXT_LINK_SPEED_20GB:
1706 return SPEED_20000;
1707 case BNXT_LINK_SPEED_25GB:
1708 return SPEED_25000;
1709 case BNXT_LINK_SPEED_40GB:
1710 return SPEED_40000;
1711 case BNXT_LINK_SPEED_50GB:
1712 return SPEED_50000;
1713 case BNXT_LINK_SPEED_100GB:
1714 return SPEED_100000;
1715 default:
1716 return SPEED_UNKNOWN;
1717 }
1718}
1719
1720static int bnxt_get_link_ksettings(struct net_device *dev,
1721 struct ethtool_link_ksettings *lk_ksettings)
1722{
1723 struct bnxt *bp = netdev_priv(dev);
1724 struct bnxt_link_info *link_info = &bp->link_info;
1725 struct ethtool_link_settings *base = &lk_ksettings->base;
1726 u32 ethtool_speed;
1727
1728 ethtool_link_ksettings_zero_link_mode(lk_ksettings, supported);
1729 mutex_lock(&bp->link_lock);
1730 bnxt_fw_to_ethtool_support_spds(link_info, lk_ksettings);
1731
1732 ethtool_link_ksettings_zero_link_mode(lk_ksettings, advertising);
1733 if (link_info->autoneg) {
1734 bnxt_fw_to_ethtool_advertised_spds(link_info, lk_ksettings);
1735 ethtool_link_ksettings_add_link_mode(lk_ksettings,
1736 advertising, Autoneg);
1737 base->autoneg = AUTONEG_ENABLE;
1738 base->duplex = DUPLEX_UNKNOWN;
1739 if (link_info->phy_link_status == BNXT_LINK_LINK) {
1740 bnxt_fw_to_ethtool_lp_adv(link_info, lk_ksettings);
1741 if (link_info->duplex & BNXT_LINK_DUPLEX_FULL)
1742 base->duplex = DUPLEX_FULL;
1743 else
1744 base->duplex = DUPLEX_HALF;
1745 }
1746 ethtool_speed = bnxt_fw_to_ethtool_speed(link_info->link_speed);
1747 } else {
1748 base->autoneg = AUTONEG_DISABLE;
1749 ethtool_speed =
1750 bnxt_fw_to_ethtool_speed(link_info->req_link_speed);
1751 base->duplex = DUPLEX_HALF;
1752 if (link_info->req_duplex == BNXT_LINK_DUPLEX_FULL)
1753 base->duplex = DUPLEX_FULL;
1754 }
1755 base->speed = ethtool_speed;
1756
1757 base->port = PORT_NONE;
1758 if (link_info->media_type == PORT_PHY_QCFG_RESP_MEDIA_TYPE_TP) {
1759 base->port = PORT_TP;
1760 ethtool_link_ksettings_add_link_mode(lk_ksettings, supported,
1761 TP);
1762 ethtool_link_ksettings_add_link_mode(lk_ksettings, advertising,
1763 TP);
1764 } else {
1765 ethtool_link_ksettings_add_link_mode(lk_ksettings, supported,
1766 FIBRE);
1767 ethtool_link_ksettings_add_link_mode(lk_ksettings, advertising,
1768 FIBRE);
1769
1770 if (link_info->media_type == PORT_PHY_QCFG_RESP_MEDIA_TYPE_DAC)
1771 base->port = PORT_DA;
1772 else if (link_info->media_type ==
1773 PORT_PHY_QCFG_RESP_MEDIA_TYPE_FIBRE)
1774 base->port = PORT_FIBRE;
1775 }
1776 base->phy_address = link_info->phy_addr;
1777 mutex_unlock(&bp->link_lock);
1778
1779 return 0;
1780}
1781
1782static int bnxt_force_link_speed(struct net_device *dev, u32 ethtool_speed)
1783{
1784 struct bnxt *bp = netdev_priv(dev);
1785 struct bnxt_link_info *link_info = &bp->link_info;
1786 u16 support_pam4_spds = link_info->support_pam4_speeds;
1787 u16 support_spds = link_info->support_speeds;
1788 u8 sig_mode = BNXT_SIG_MODE_NRZ;
1789 u16 fw_speed = 0;
1790
1791 switch (ethtool_speed) {
1792 case SPEED_100:
1793 if (support_spds & BNXT_LINK_SPEED_MSK_100MB)
1794 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100MB;
1795 break;
1796 case SPEED_1000:
1797 if (support_spds & BNXT_LINK_SPEED_MSK_1GB)
1798 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_1GB;
1799 break;
1800 case SPEED_2500:
1801 if (support_spds & BNXT_LINK_SPEED_MSK_2_5GB)
1802 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_2_5GB;
1803 break;
1804 case SPEED_10000:
1805 if (support_spds & BNXT_LINK_SPEED_MSK_10GB)
1806 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10GB;
1807 break;
1808 case SPEED_20000:
1809 if (support_spds & BNXT_LINK_SPEED_MSK_20GB)
1810 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_20GB;
1811 break;
1812 case SPEED_25000:
1813 if (support_spds & BNXT_LINK_SPEED_MSK_25GB)
1814 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_25GB;
1815 break;
1816 case SPEED_40000:
1817 if (support_spds & BNXT_LINK_SPEED_MSK_40GB)
1818 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_40GB;
1819 break;
1820 case SPEED_50000:
1821 if (support_spds & BNXT_LINK_SPEED_MSK_50GB) {
1822 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_50GB;
1823 } else if (support_pam4_spds & BNXT_LINK_PAM4_SPEED_MSK_50GB) {
1824 fw_speed = PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_50GB;
1825 sig_mode = BNXT_SIG_MODE_PAM4;
1826 }
1827 break;
1828 case SPEED_100000:
1829 if (support_spds & BNXT_LINK_SPEED_MSK_100GB) {
1830 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100GB;
1831 } else if (support_pam4_spds & BNXT_LINK_PAM4_SPEED_MSK_100GB) {
1832 fw_speed = PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_100GB;
1833 sig_mode = BNXT_SIG_MODE_PAM4;
1834 }
1835 break;
1836 case SPEED_200000:
1837 if (support_pam4_spds & BNXT_LINK_PAM4_SPEED_MSK_200GB) {
1838 fw_speed = PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_200GB;
1839 sig_mode = BNXT_SIG_MODE_PAM4;
1840 }
1841 break;
1842 }
1843
1844 if (!fw_speed) {
1845 netdev_err(dev, "unsupported speed!\n");
1846 return -EINVAL;
1847 }
1848
1849 if (link_info->req_link_speed == fw_speed &&
1850 link_info->req_signal_mode == sig_mode &&
1851 link_info->autoneg == 0)
1852 return -EALREADY;
1853
1854 link_info->req_link_speed = fw_speed;
1855 link_info->req_signal_mode = sig_mode;
1856 link_info->req_duplex = BNXT_LINK_DUPLEX_FULL;
1857 link_info->autoneg = 0;
1858 link_info->advertising = 0;
1859 link_info->advertising_pam4 = 0;
1860
1861 return 0;
1862}
1863
1864u16 bnxt_get_fw_auto_link_speeds(u32 advertising)
1865{
1866 u16 fw_speed_mask = 0;
1867
1868
1869 if (advertising & (ADVERTISED_100baseT_Full |
1870 ADVERTISED_100baseT_Half)) {
1871 fw_speed_mask |= BNXT_LINK_SPEED_MSK_100MB;
1872 }
1873 if (advertising & (ADVERTISED_1000baseT_Full |
1874 ADVERTISED_1000baseT_Half)) {
1875 fw_speed_mask |= BNXT_LINK_SPEED_MSK_1GB;
1876 }
1877 if (advertising & ADVERTISED_10000baseT_Full)
1878 fw_speed_mask |= BNXT_LINK_SPEED_MSK_10GB;
1879
1880 if (advertising & ADVERTISED_40000baseCR4_Full)
1881 fw_speed_mask |= BNXT_LINK_SPEED_MSK_40GB;
1882
1883 return fw_speed_mask;
1884}
1885
1886static int bnxt_set_link_ksettings(struct net_device *dev,
1887 const struct ethtool_link_ksettings *lk_ksettings)
1888{
1889 struct bnxt *bp = netdev_priv(dev);
1890 struct bnxt_link_info *link_info = &bp->link_info;
1891 const struct ethtool_link_settings *base = &lk_ksettings->base;
1892 bool set_pause = false;
1893 u32 speed;
1894 int rc = 0;
1895
1896 if (!BNXT_PHY_CFG_ABLE(bp))
1897 return -EOPNOTSUPP;
1898
1899 mutex_lock(&bp->link_lock);
1900 if (base->autoneg == AUTONEG_ENABLE) {
1901 link_info->advertising = 0;
1902 link_info->advertising_pam4 = 0;
1903 BNXT_ETHTOOL_TO_FW_SPDS(link_info->advertising, lk_ksettings,
1904 advertising);
1905 BNXT_ETHTOOL_TO_FW_PAM4_SPDS(link_info->advertising_pam4,
1906 lk_ksettings, advertising);
1907 link_info->autoneg |= BNXT_AUTONEG_SPEED;
1908 if (!link_info->advertising && !link_info->advertising_pam4) {
1909 link_info->advertising = link_info->support_auto_speeds;
1910 link_info->advertising_pam4 =
1911 link_info->support_pam4_auto_speeds;
1912 }
1913
1914
1915
1916 if (!(bp->phy_flags & BNXT_PHY_FL_NO_PAUSE))
1917 set_pause = true;
1918 } else {
1919 u8 phy_type = link_info->phy_type;
1920
1921 if (phy_type == PORT_PHY_QCFG_RESP_PHY_TYPE_BASET ||
1922 phy_type == PORT_PHY_QCFG_RESP_PHY_TYPE_BASETE ||
1923 link_info->media_type == PORT_PHY_QCFG_RESP_MEDIA_TYPE_TP) {
1924 netdev_err(dev, "10GBase-T devices must autoneg\n");
1925 rc = -EINVAL;
1926 goto set_setting_exit;
1927 }
1928 if (base->duplex == DUPLEX_HALF) {
1929 netdev_err(dev, "HALF DUPLEX is not supported!\n");
1930 rc = -EINVAL;
1931 goto set_setting_exit;
1932 }
1933 speed = base->speed;
1934 rc = bnxt_force_link_speed(dev, speed);
1935 if (rc) {
1936 if (rc == -EALREADY)
1937 rc = 0;
1938 goto set_setting_exit;
1939 }
1940 }
1941
1942 if (netif_running(dev))
1943 rc = bnxt_hwrm_set_link_setting(bp, set_pause, false);
1944
1945set_setting_exit:
1946 mutex_unlock(&bp->link_lock);
1947 return rc;
1948}
1949
1950static int bnxt_get_fecparam(struct net_device *dev,
1951 struct ethtool_fecparam *fec)
1952{
1953 struct bnxt *bp = netdev_priv(dev);
1954 struct bnxt_link_info *link_info;
1955 u8 active_fec;
1956 u16 fec_cfg;
1957
1958 link_info = &bp->link_info;
1959 fec_cfg = link_info->fec_cfg;
1960 active_fec = link_info->active_fec_sig_mode &
1961 PORT_PHY_QCFG_RESP_ACTIVE_FEC_MASK;
1962 if (fec_cfg & BNXT_FEC_NONE) {
1963 fec->fec = ETHTOOL_FEC_NONE;
1964 fec->active_fec = ETHTOOL_FEC_NONE;
1965 return 0;
1966 }
1967 if (fec_cfg & BNXT_FEC_AUTONEG)
1968 fec->fec |= ETHTOOL_FEC_AUTO;
1969 if (fec_cfg & BNXT_FEC_ENC_BASE_R)
1970 fec->fec |= ETHTOOL_FEC_BASER;
1971 if (fec_cfg & BNXT_FEC_ENC_RS)
1972 fec->fec |= ETHTOOL_FEC_RS;
1973 if (fec_cfg & BNXT_FEC_ENC_LLRS)
1974 fec->fec |= ETHTOOL_FEC_LLRS;
1975
1976 switch (active_fec) {
1977 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_CLAUSE74_ACTIVE:
1978 fec->active_fec |= ETHTOOL_FEC_BASER;
1979 break;
1980 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_CLAUSE91_ACTIVE:
1981 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS544_1XN_ACTIVE:
1982 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS544_IEEE_ACTIVE:
1983 fec->active_fec |= ETHTOOL_FEC_RS;
1984 break;
1985 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS272_1XN_ACTIVE:
1986 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS272_IEEE_ACTIVE:
1987 fec->active_fec |= ETHTOOL_FEC_LLRS;
1988 break;
1989 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_NONE_ACTIVE:
1990 fec->active_fec |= ETHTOOL_FEC_OFF;
1991 break;
1992 }
1993 return 0;
1994}
1995
1996static void bnxt_get_fec_stats(struct net_device *dev,
1997 struct ethtool_fec_stats *fec_stats)
1998{
1999 struct bnxt *bp = netdev_priv(dev);
2000 u64 *rx;
2001
2002 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS_EXT))
2003 return;
2004
2005 rx = bp->rx_port_stats_ext.sw_stats;
2006 fec_stats->corrected_bits.total =
2007 *(rx + BNXT_RX_STATS_EXT_OFFSET(rx_corrected_bits));
2008}
2009
2010static u32 bnxt_ethtool_forced_fec_to_fw(struct bnxt_link_info *link_info,
2011 u32 fec)
2012{
2013 u32 fw_fec = PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_DISABLE;
2014
2015 if (fec & ETHTOOL_FEC_BASER)
2016 fw_fec |= BNXT_FEC_BASE_R_ON(link_info);
2017 else if (fec & ETHTOOL_FEC_RS)
2018 fw_fec |= BNXT_FEC_RS_ON(link_info);
2019 else if (fec & ETHTOOL_FEC_LLRS)
2020 fw_fec |= BNXT_FEC_LLRS_ON;
2021 return fw_fec;
2022}
2023
2024static int bnxt_set_fecparam(struct net_device *dev,
2025 struct ethtool_fecparam *fecparam)
2026{
2027 struct hwrm_port_phy_cfg_input *req;
2028 struct bnxt *bp = netdev_priv(dev);
2029 struct bnxt_link_info *link_info;
2030 u32 new_cfg, fec = fecparam->fec;
2031 u16 fec_cfg;
2032 int rc;
2033
2034 link_info = &bp->link_info;
2035 fec_cfg = link_info->fec_cfg;
2036 if (fec_cfg & BNXT_FEC_NONE)
2037 return -EOPNOTSUPP;
2038
2039 if (fec & ETHTOOL_FEC_OFF) {
2040 new_cfg = PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_DISABLE |
2041 BNXT_FEC_ALL_OFF(link_info);
2042 goto apply_fec;
2043 }
2044 if (((fec & ETHTOOL_FEC_AUTO) && !(fec_cfg & BNXT_FEC_AUTONEG_CAP)) ||
2045 ((fec & ETHTOOL_FEC_RS) && !(fec_cfg & BNXT_FEC_ENC_RS_CAP)) ||
2046 ((fec & ETHTOOL_FEC_LLRS) && !(fec_cfg & BNXT_FEC_ENC_LLRS_CAP)) ||
2047 ((fec & ETHTOOL_FEC_BASER) && !(fec_cfg & BNXT_FEC_ENC_BASE_R_CAP)))
2048 return -EINVAL;
2049
2050 if (fec & ETHTOOL_FEC_AUTO) {
2051 if (!link_info->autoneg)
2052 return -EINVAL;
2053 new_cfg = PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_ENABLE;
2054 } else {
2055 new_cfg = bnxt_ethtool_forced_fec_to_fw(link_info, fec);
2056 }
2057
2058apply_fec:
2059 rc = hwrm_req_init(bp, req, HWRM_PORT_PHY_CFG);
2060 if (rc)
2061 return rc;
2062 req->flags = cpu_to_le32(new_cfg | PORT_PHY_CFG_REQ_FLAGS_RESET_PHY);
2063 rc = hwrm_req_send(bp, req);
2064
2065 if (!rc) {
2066 mutex_lock(&bp->link_lock);
2067 bnxt_update_link(bp, false);
2068 mutex_unlock(&bp->link_lock);
2069 }
2070 return rc;
2071}
2072
2073static void bnxt_get_pauseparam(struct net_device *dev,
2074 struct ethtool_pauseparam *epause)
2075{
2076 struct bnxt *bp = netdev_priv(dev);
2077 struct bnxt_link_info *link_info = &bp->link_info;
2078
2079 if (BNXT_VF(bp))
2080 return;
2081 epause->autoneg = !!(link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL);
2082 epause->rx_pause = !!(link_info->req_flow_ctrl & BNXT_LINK_PAUSE_RX);
2083 epause->tx_pause = !!(link_info->req_flow_ctrl & BNXT_LINK_PAUSE_TX);
2084}
2085
2086static void bnxt_get_pause_stats(struct net_device *dev,
2087 struct ethtool_pause_stats *epstat)
2088{
2089 struct bnxt *bp = netdev_priv(dev);
2090 u64 *rx, *tx;
2091
2092 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS))
2093 return;
2094
2095 rx = bp->port_stats.sw_stats;
2096 tx = bp->port_stats.sw_stats + BNXT_TX_PORT_STATS_BYTE_OFFSET / 8;
2097
2098 epstat->rx_pause_frames = BNXT_GET_RX_PORT_STATS64(rx, rx_pause_frames);
2099 epstat->tx_pause_frames = BNXT_GET_TX_PORT_STATS64(tx, tx_pause_frames);
2100}
2101
2102static int bnxt_set_pauseparam(struct net_device *dev,
2103 struct ethtool_pauseparam *epause)
2104{
2105 int rc = 0;
2106 struct bnxt *bp = netdev_priv(dev);
2107 struct bnxt_link_info *link_info = &bp->link_info;
2108
2109 if (!BNXT_PHY_CFG_ABLE(bp) || (bp->phy_flags & BNXT_PHY_FL_NO_PAUSE))
2110 return -EOPNOTSUPP;
2111
2112 mutex_lock(&bp->link_lock);
2113 if (epause->autoneg) {
2114 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) {
2115 rc = -EINVAL;
2116 goto pause_exit;
2117 }
2118
2119 link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL;
2120 link_info->req_flow_ctrl = 0;
2121 } else {
2122
2123
2124
2125 if (link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL)
2126 link_info->force_link_chng = true;
2127 link_info->autoneg &= ~BNXT_AUTONEG_FLOW_CTRL;
2128 link_info->req_flow_ctrl = 0;
2129 }
2130 if (epause->rx_pause)
2131 link_info->req_flow_ctrl |= BNXT_LINK_PAUSE_RX;
2132
2133 if (epause->tx_pause)
2134 link_info->req_flow_ctrl |= BNXT_LINK_PAUSE_TX;
2135
2136 if (netif_running(dev))
2137 rc = bnxt_hwrm_set_pause(bp);
2138
2139pause_exit:
2140 mutex_unlock(&bp->link_lock);
2141 return rc;
2142}
2143
2144static u32 bnxt_get_link(struct net_device *dev)
2145{
2146 struct bnxt *bp = netdev_priv(dev);
2147
2148
2149 return BNXT_LINK_IS_UP(bp);
2150}
2151
2152int bnxt_hwrm_nvm_get_dev_info(struct bnxt *bp,
2153 struct hwrm_nvm_get_dev_info_output *nvm_dev_info)
2154{
2155 struct hwrm_nvm_get_dev_info_output *resp;
2156 struct hwrm_nvm_get_dev_info_input *req;
2157 int rc;
2158
2159 if (BNXT_VF(bp))
2160 return -EOPNOTSUPP;
2161
2162 rc = hwrm_req_init(bp, req, HWRM_NVM_GET_DEV_INFO);
2163 if (rc)
2164 return rc;
2165
2166 resp = hwrm_req_hold(bp, req);
2167 rc = hwrm_req_send(bp, req);
2168 if (!rc)
2169 memcpy(nvm_dev_info, resp, sizeof(*resp));
2170 hwrm_req_drop(bp, req);
2171 return rc;
2172}
2173
2174static void bnxt_print_admin_err(struct bnxt *bp)
2175{
2176 netdev_info(bp->dev, "PF does not have admin privileges to flash or reset the device\n");
2177}
2178
2179static int bnxt_find_nvram_item(struct net_device *dev, u16 type, u16 ordinal,
2180 u16 ext, u16 *index, u32 *item_length,
2181 u32 *data_length);
2182
2183static int bnxt_flash_nvram(struct net_device *dev, u16 dir_type,
2184 u16 dir_ordinal, u16 dir_ext, u16 dir_attr,
2185 u32 dir_item_len, const u8 *data,
2186 size_t data_len)
2187{
2188 struct bnxt *bp = netdev_priv(dev);
2189 struct hwrm_nvm_write_input *req;
2190 int rc;
2191
2192 rc = hwrm_req_init(bp, req, HWRM_NVM_WRITE);
2193 if (rc)
2194 return rc;
2195
2196 if (data_len && data) {
2197 dma_addr_t dma_handle;
2198 u8 *kmem;
2199
2200 kmem = hwrm_req_dma_slice(bp, req, data_len, &dma_handle);
2201 if (!kmem) {
2202 hwrm_req_drop(bp, req);
2203 return -ENOMEM;
2204 }
2205
2206 req->dir_data_length = cpu_to_le32(data_len);
2207
2208 memcpy(kmem, data, data_len);
2209 req->host_src_addr = cpu_to_le64(dma_handle);
2210 }
2211
2212 hwrm_req_timeout(bp, req, bp->hwrm_cmd_max_timeout);
2213 req->dir_type = cpu_to_le16(dir_type);
2214 req->dir_ordinal = cpu_to_le16(dir_ordinal);
2215 req->dir_ext = cpu_to_le16(dir_ext);
2216 req->dir_attr = cpu_to_le16(dir_attr);
2217 req->dir_item_length = cpu_to_le32(dir_item_len);
2218 rc = hwrm_req_send(bp, req);
2219
2220 if (rc == -EACCES)
2221 bnxt_print_admin_err(bp);
2222 return rc;
2223}
2224
2225int bnxt_hwrm_firmware_reset(struct net_device *dev, u8 proc_type,
2226 u8 self_reset, u8 flags)
2227{
2228 struct bnxt *bp = netdev_priv(dev);
2229 struct hwrm_fw_reset_input *req;
2230 int rc;
2231
2232 if (!bnxt_hwrm_reset_permitted(bp)) {
2233 netdev_warn(bp->dev, "Reset denied by firmware, it may be inhibited by remote driver");
2234 return -EPERM;
2235 }
2236
2237 rc = hwrm_req_init(bp, req, HWRM_FW_RESET);
2238 if (rc)
2239 return rc;
2240
2241 req->embedded_proc_type = proc_type;
2242 req->selfrst_status = self_reset;
2243 req->flags = flags;
2244
2245 if (proc_type == FW_RESET_REQ_EMBEDDED_PROC_TYPE_AP) {
2246 rc = hwrm_req_send_silent(bp, req);
2247 } else {
2248 rc = hwrm_req_send(bp, req);
2249 if (rc == -EACCES)
2250 bnxt_print_admin_err(bp);
2251 }
2252 return rc;
2253}
2254
2255static int bnxt_firmware_reset(struct net_device *dev,
2256 enum bnxt_nvm_directory_type dir_type)
2257{
2258 u8 self_reset = FW_RESET_REQ_SELFRST_STATUS_SELFRSTNONE;
2259 u8 proc_type, flags = 0;
2260
2261
2262
2263 switch (dir_type) {
2264 case BNX_DIR_TYPE_CHIMP_PATCH:
2265 case BNX_DIR_TYPE_BOOTCODE:
2266 case BNX_DIR_TYPE_BOOTCODE_2:
2267 proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_BOOT;
2268
2269 self_reset = FW_RESET_REQ_SELFRST_STATUS_SELFRSTPCIERST;
2270 break;
2271 case BNX_DIR_TYPE_APE_FW:
2272 case BNX_DIR_TYPE_APE_PATCH:
2273 proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_MGMT;
2274
2275 self_reset = FW_RESET_REQ_SELFRST_STATUS_SELFRSTPCIERST;
2276 break;
2277 case BNX_DIR_TYPE_KONG_FW:
2278 case BNX_DIR_TYPE_KONG_PATCH:
2279 proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_NETCTRL;
2280 break;
2281 case BNX_DIR_TYPE_BONO_FW:
2282 case BNX_DIR_TYPE_BONO_PATCH:
2283 proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_ROCE;
2284 break;
2285 default:
2286 return -EINVAL;
2287 }
2288
2289 return bnxt_hwrm_firmware_reset(dev, proc_type, self_reset, flags);
2290}
2291
2292static int bnxt_firmware_reset_chip(struct net_device *dev)
2293{
2294 struct bnxt *bp = netdev_priv(dev);
2295 u8 flags = 0;
2296
2297 if (bp->fw_cap & BNXT_FW_CAP_HOT_RESET)
2298 flags = FW_RESET_REQ_FLAGS_RESET_GRACEFUL;
2299
2300 return bnxt_hwrm_firmware_reset(dev,
2301 FW_RESET_REQ_EMBEDDED_PROC_TYPE_CHIP,
2302 FW_RESET_REQ_SELFRST_STATUS_SELFRSTASAP,
2303 flags);
2304}
2305
2306static int bnxt_firmware_reset_ap(struct net_device *dev)
2307{
2308 return bnxt_hwrm_firmware_reset(dev, FW_RESET_REQ_EMBEDDED_PROC_TYPE_AP,
2309 FW_RESET_REQ_SELFRST_STATUS_SELFRSTNONE,
2310 0);
2311}
2312
2313static int bnxt_flash_firmware(struct net_device *dev,
2314 u16 dir_type,
2315 const u8 *fw_data,
2316 size_t fw_size)
2317{
2318 int rc = 0;
2319 u16 code_type;
2320 u32 stored_crc;
2321 u32 calculated_crc;
2322 struct bnxt_fw_header *header = (struct bnxt_fw_header *)fw_data;
2323
2324 switch (dir_type) {
2325 case BNX_DIR_TYPE_BOOTCODE:
2326 case BNX_DIR_TYPE_BOOTCODE_2:
2327 code_type = CODE_BOOT;
2328 break;
2329 case BNX_DIR_TYPE_CHIMP_PATCH:
2330 code_type = CODE_CHIMP_PATCH;
2331 break;
2332 case BNX_DIR_TYPE_APE_FW:
2333 code_type = CODE_MCTP_PASSTHRU;
2334 break;
2335 case BNX_DIR_TYPE_APE_PATCH:
2336 code_type = CODE_APE_PATCH;
2337 break;
2338 case BNX_DIR_TYPE_KONG_FW:
2339 code_type = CODE_KONG_FW;
2340 break;
2341 case BNX_DIR_TYPE_KONG_PATCH:
2342 code_type = CODE_KONG_PATCH;
2343 break;
2344 case BNX_DIR_TYPE_BONO_FW:
2345 code_type = CODE_BONO_FW;
2346 break;
2347 case BNX_DIR_TYPE_BONO_PATCH:
2348 code_type = CODE_BONO_PATCH;
2349 break;
2350 default:
2351 netdev_err(dev, "Unsupported directory entry type: %u\n",
2352 dir_type);
2353 return -EINVAL;
2354 }
2355 if (fw_size < sizeof(struct bnxt_fw_header)) {
2356 netdev_err(dev, "Invalid firmware file size: %u\n",
2357 (unsigned int)fw_size);
2358 return -EINVAL;
2359 }
2360 if (header->signature != cpu_to_le32(BNXT_FIRMWARE_BIN_SIGNATURE)) {
2361 netdev_err(dev, "Invalid firmware signature: %08X\n",
2362 le32_to_cpu(header->signature));
2363 return -EINVAL;
2364 }
2365 if (header->code_type != code_type) {
2366 netdev_err(dev, "Expected firmware type: %d, read: %d\n",
2367 code_type, header->code_type);
2368 return -EINVAL;
2369 }
2370 if (header->device != DEVICE_CUMULUS_FAMILY) {
2371 netdev_err(dev, "Expected firmware device family %d, read: %d\n",
2372 DEVICE_CUMULUS_FAMILY, header->device);
2373 return -EINVAL;
2374 }
2375
2376 stored_crc = le32_to_cpu(*(__le32 *)(fw_data + fw_size -
2377 sizeof(stored_crc)));
2378 calculated_crc = ~crc32(~0, fw_data, fw_size - sizeof(stored_crc));
2379 if (calculated_crc != stored_crc) {
2380 netdev_err(dev, "Firmware file CRC32 checksum (%08lX) does not match calculated checksum (%08lX)\n",
2381 (unsigned long)stored_crc,
2382 (unsigned long)calculated_crc);
2383 return -EINVAL;
2384 }
2385 rc = bnxt_flash_nvram(dev, dir_type, BNX_DIR_ORDINAL_FIRST,
2386 0, 0, 0, fw_data, fw_size);
2387 if (rc == 0)
2388 rc = bnxt_firmware_reset(dev, dir_type);
2389
2390 return rc;
2391}
2392
2393static int bnxt_flash_microcode(struct net_device *dev,
2394 u16 dir_type,
2395 const u8 *fw_data,
2396 size_t fw_size)
2397{
2398 struct bnxt_ucode_trailer *trailer;
2399 u32 calculated_crc;
2400 u32 stored_crc;
2401 int rc = 0;
2402
2403 if (fw_size < sizeof(struct bnxt_ucode_trailer)) {
2404 netdev_err(dev, "Invalid microcode file size: %u\n",
2405 (unsigned int)fw_size);
2406 return -EINVAL;
2407 }
2408 trailer = (struct bnxt_ucode_trailer *)(fw_data + (fw_size -
2409 sizeof(*trailer)));
2410 if (trailer->sig != cpu_to_le32(BNXT_UCODE_TRAILER_SIGNATURE)) {
2411 netdev_err(dev, "Invalid microcode trailer signature: %08X\n",
2412 le32_to_cpu(trailer->sig));
2413 return -EINVAL;
2414 }
2415 if (le16_to_cpu(trailer->dir_type) != dir_type) {
2416 netdev_err(dev, "Expected microcode type: %d, read: %d\n",
2417 dir_type, le16_to_cpu(trailer->dir_type));
2418 return -EINVAL;
2419 }
2420 if (le16_to_cpu(trailer->trailer_length) <
2421 sizeof(struct bnxt_ucode_trailer)) {
2422 netdev_err(dev, "Invalid microcode trailer length: %d\n",
2423 le16_to_cpu(trailer->trailer_length));
2424 return -EINVAL;
2425 }
2426
2427
2428 stored_crc = le32_to_cpu(*(__le32 *)(fw_data + fw_size -
2429 sizeof(stored_crc)));
2430 calculated_crc = ~crc32(~0, fw_data, fw_size - sizeof(stored_crc));
2431 if (calculated_crc != stored_crc) {
2432 netdev_err(dev,
2433 "CRC32 (%08lX) does not match calculated: %08lX\n",
2434 (unsigned long)stored_crc,
2435 (unsigned long)calculated_crc);
2436 return -EINVAL;
2437 }
2438 rc = bnxt_flash_nvram(dev, dir_type, BNX_DIR_ORDINAL_FIRST,
2439 0, 0, 0, fw_data, fw_size);
2440
2441 return rc;
2442}
2443
2444static bool bnxt_dir_type_is_ape_bin_format(u16 dir_type)
2445{
2446 switch (dir_type) {
2447 case BNX_DIR_TYPE_CHIMP_PATCH:
2448 case BNX_DIR_TYPE_BOOTCODE:
2449 case BNX_DIR_TYPE_BOOTCODE_2:
2450 case BNX_DIR_TYPE_APE_FW:
2451 case BNX_DIR_TYPE_APE_PATCH:
2452 case BNX_DIR_TYPE_KONG_FW:
2453 case BNX_DIR_TYPE_KONG_PATCH:
2454 case BNX_DIR_TYPE_BONO_FW:
2455 case BNX_DIR_TYPE_BONO_PATCH:
2456 return true;
2457 }
2458
2459 return false;
2460}
2461
2462static bool bnxt_dir_type_is_other_exec_format(u16 dir_type)
2463{
2464 switch (dir_type) {
2465 case BNX_DIR_TYPE_AVS:
2466 case BNX_DIR_TYPE_EXP_ROM_MBA:
2467 case BNX_DIR_TYPE_PCIE:
2468 case BNX_DIR_TYPE_TSCF_UCODE:
2469 case BNX_DIR_TYPE_EXT_PHY:
2470 case BNX_DIR_TYPE_CCM:
2471 case BNX_DIR_TYPE_ISCSI_BOOT:
2472 case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
2473 case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
2474 return true;
2475 }
2476
2477 return false;
2478}
2479
2480static bool bnxt_dir_type_is_executable(u16 dir_type)
2481{
2482 return bnxt_dir_type_is_ape_bin_format(dir_type) ||
2483 bnxt_dir_type_is_other_exec_format(dir_type);
2484}
2485
2486static int bnxt_flash_firmware_from_file(struct net_device *dev,
2487 u16 dir_type,
2488 const char *filename)
2489{
2490 const struct firmware *fw;
2491 int rc;
2492
2493 rc = request_firmware(&fw, filename, &dev->dev);
2494 if (rc != 0) {
2495 netdev_err(dev, "Error %d requesting firmware file: %s\n",
2496 rc, filename);
2497 return rc;
2498 }
2499 if (bnxt_dir_type_is_ape_bin_format(dir_type))
2500 rc = bnxt_flash_firmware(dev, dir_type, fw->data, fw->size);
2501 else if (bnxt_dir_type_is_other_exec_format(dir_type))
2502 rc = bnxt_flash_microcode(dev, dir_type, fw->data, fw->size);
2503 else
2504 rc = bnxt_flash_nvram(dev, dir_type, BNX_DIR_ORDINAL_FIRST,
2505 0, 0, 0, fw->data, fw->size);
2506 release_firmware(fw);
2507 return rc;
2508}
2509
2510#define MSG_INTEGRITY_ERR "PKG install error : Data integrity on NVM"
2511#define MSG_INVALID_PKG "PKG install error : Invalid package"
2512#define MSG_AUTHENTICATION_ERR "PKG install error : Authentication error"
2513#define MSG_INVALID_DEV "PKG install error : Invalid device"
2514#define MSG_INTERNAL_ERR "PKG install error : Internal error"
2515#define MSG_NO_PKG_UPDATE_AREA_ERR "PKG update area not created in nvram"
2516#define MSG_NO_SPACE_ERR "PKG insufficient update area in nvram"
2517#define MSG_ANTI_ROLLBACK_ERR "HWRM_NVM_INSTALL_UPDATE failure due to Anti-rollback detected"
2518#define MSG_GENERIC_FAILURE_ERR "HWRM_NVM_INSTALL_UPDATE failure"
2519
2520static int nvm_update_err_to_stderr(struct net_device *dev, u8 result,
2521 struct netlink_ext_ack *extack)
2522{
2523 switch (result) {
2524 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_TYPE_PARAMETER:
2525 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_INDEX_PARAMETER:
2526 case NVM_INSTALL_UPDATE_RESP_RESULT_INSTALL_DATA_ERROR:
2527 case NVM_INSTALL_UPDATE_RESP_RESULT_INSTALL_CHECKSUM_ERROR:
2528 case NVM_INSTALL_UPDATE_RESP_RESULT_ITEM_NOT_FOUND:
2529 case NVM_INSTALL_UPDATE_RESP_RESULT_ITEM_LOCKED:
2530 BNXT_NVM_ERR_MSG(dev, extack, MSG_INTEGRITY_ERR);
2531 return -EINVAL;
2532 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_PREREQUISITE:
2533 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_FILE_HEADER:
2534 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_SIGNATURE:
2535 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_PROP_STREAM:
2536 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_PROP_LENGTH:
2537 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_MANIFEST:
2538 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_TRAILER:
2539 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_CHECKSUM:
2540 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_ITEM_CHECKSUM:
2541 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_DATA_LENGTH:
2542 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_DIRECTIVE:
2543 case NVM_INSTALL_UPDATE_RESP_RESULT_DUPLICATE_ITEM:
2544 case NVM_INSTALL_UPDATE_RESP_RESULT_ZERO_LENGTH_ITEM:
2545 BNXT_NVM_ERR_MSG(dev, extack, MSG_INVALID_PKG);
2546 return -ENOPKG;
2547 case NVM_INSTALL_UPDATE_RESP_RESULT_INSTALL_AUTHENTICATION_ERROR:
2548 BNXT_NVM_ERR_MSG(dev, extack, MSG_AUTHENTICATION_ERR);
2549 return -EPERM;
2550 case NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_CHIP_REV:
2551 case NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_DEVICE_ID:
2552 case NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_SUBSYS_VENDOR:
2553 case NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_SUBSYS_ID:
2554 case NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_PLATFORM:
2555 BNXT_NVM_ERR_MSG(dev, extack, MSG_INVALID_DEV);
2556 return -EOPNOTSUPP;
2557 default:
2558 BNXT_NVM_ERR_MSG(dev, extack, MSG_INTERNAL_ERR);
2559 return -EIO;
2560 }
2561}
2562
2563#define BNXT_PKG_DMA_SIZE 0x40000
2564#define BNXT_NVM_MORE_FLAG (cpu_to_le16(NVM_MODIFY_REQ_FLAGS_BATCH_MODE))
2565#define BNXT_NVM_LAST_FLAG (cpu_to_le16(NVM_MODIFY_REQ_FLAGS_BATCH_LAST))
2566
2567int bnxt_flash_package_from_fw_obj(struct net_device *dev, const struct firmware *fw,
2568 u32 install_type, struct netlink_ext_ack *extack)
2569{
2570 struct hwrm_nvm_install_update_input *install;
2571 struct hwrm_nvm_install_update_output *resp;
2572 struct hwrm_nvm_modify_input *modify;
2573 struct bnxt *bp = netdev_priv(dev);
2574 bool defrag_attempted = false;
2575 dma_addr_t dma_handle;
2576 u8 *kmem = NULL;
2577 u32 modify_len;
2578 u32 item_len;
2579 u8 cmd_err;
2580 u16 index;
2581 int rc;
2582
2583 bnxt_hwrm_fw_set_time(bp);
2584
2585 rc = hwrm_req_init(bp, modify, HWRM_NVM_MODIFY);
2586 if (rc)
2587 return rc;
2588
2589
2590
2591
2592 modify_len = roundup_pow_of_two(fw->size);
2593 modify_len = min_t(u32, modify_len, BNXT_PKG_DMA_SIZE);
2594 while (1) {
2595 kmem = hwrm_req_dma_slice(bp, modify, modify_len, &dma_handle);
2596 if (!kmem && modify_len > PAGE_SIZE)
2597 modify_len /= 2;
2598 else
2599 break;
2600 }
2601 if (!kmem) {
2602 hwrm_req_drop(bp, modify);
2603 return -ENOMEM;
2604 }
2605
2606 rc = hwrm_req_init(bp, install, HWRM_NVM_INSTALL_UPDATE);
2607 if (rc) {
2608 hwrm_req_drop(bp, modify);
2609 return rc;
2610 }
2611
2612 hwrm_req_timeout(bp, modify, bp->hwrm_cmd_max_timeout);
2613 hwrm_req_timeout(bp, install, bp->hwrm_cmd_max_timeout);
2614
2615 hwrm_req_hold(bp, modify);
2616 modify->host_src_addr = cpu_to_le64(dma_handle);
2617
2618 resp = hwrm_req_hold(bp, install);
2619 if ((install_type & 0xffff) == 0)
2620 install_type >>= 16;
2621 install->install_type = cpu_to_le32(install_type);
2622
2623 do {
2624 u32 copied = 0, len = modify_len;
2625
2626 rc = bnxt_find_nvram_item(dev, BNX_DIR_TYPE_UPDATE,
2627 BNX_DIR_ORDINAL_FIRST,
2628 BNX_DIR_EXT_NONE,
2629 &index, &item_len, NULL);
2630 if (rc) {
2631 BNXT_NVM_ERR_MSG(dev, extack, MSG_NO_PKG_UPDATE_AREA_ERR);
2632 break;
2633 }
2634 if (fw->size > item_len) {
2635 BNXT_NVM_ERR_MSG(dev, extack, MSG_NO_SPACE_ERR);
2636 rc = -EFBIG;
2637 break;
2638 }
2639
2640 modify->dir_idx = cpu_to_le16(index);
2641
2642 if (fw->size > modify_len)
2643 modify->flags = BNXT_NVM_MORE_FLAG;
2644 while (copied < fw->size) {
2645 u32 balance = fw->size - copied;
2646
2647 if (balance <= modify_len) {
2648 len = balance;
2649 if (copied)
2650 modify->flags |= BNXT_NVM_LAST_FLAG;
2651 }
2652 memcpy(kmem, fw->data + copied, len);
2653 modify->len = cpu_to_le32(len);
2654 modify->offset = cpu_to_le32(copied);
2655 rc = hwrm_req_send(bp, modify);
2656 if (rc)
2657 goto pkg_abort;
2658 copied += len;
2659 }
2660
2661 rc = hwrm_req_send_silent(bp, install);
2662 if (!rc)
2663 break;
2664
2665 if (defrag_attempted) {
2666
2667
2668
2669 break;
2670 }
2671
2672 cmd_err = ((struct hwrm_err_output *)resp)->cmd_err;
2673
2674 switch (cmd_err) {
2675 case NVM_INSTALL_UPDATE_CMD_ERR_CODE_ANTI_ROLLBACK:
2676 BNXT_NVM_ERR_MSG(dev, extack, MSG_ANTI_ROLLBACK_ERR);
2677 rc = -EALREADY;
2678 break;
2679 case NVM_INSTALL_UPDATE_CMD_ERR_CODE_FRAG_ERR:
2680 install->flags =
2681 cpu_to_le16(NVM_INSTALL_UPDATE_REQ_FLAGS_ALLOWED_TO_DEFRAG);
2682
2683 rc = hwrm_req_send_silent(bp, install);
2684 if (!rc)
2685 break;
2686
2687 cmd_err = ((struct hwrm_err_output *)resp)->cmd_err;
2688
2689 if (cmd_err == NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE) {
2690
2691
2692
2693 defrag_attempted = true;
2694 install->flags = 0;
2695 rc = bnxt_flash_nvram(bp->dev,
2696 BNX_DIR_TYPE_UPDATE,
2697 BNX_DIR_ORDINAL_FIRST,
2698 0, 0, item_len, NULL, 0);
2699 if (!rc)
2700 break;
2701 }
2702 fallthrough;
2703 default:
2704 BNXT_NVM_ERR_MSG(dev, extack, MSG_GENERIC_FAILURE_ERR);
2705 }
2706 } while (defrag_attempted && !rc);
2707
2708pkg_abort:
2709 hwrm_req_drop(bp, modify);
2710 hwrm_req_drop(bp, install);
2711
2712 if (resp->result) {
2713 netdev_err(dev, "PKG install error = %d, problem_item = %d\n",
2714 (s8)resp->result, (int)resp->problem_item);
2715 rc = nvm_update_err_to_stderr(dev, resp->result, extack);
2716 }
2717 if (rc == -EACCES)
2718 bnxt_print_admin_err(bp);
2719 return rc;
2720}
2721
2722static int bnxt_flash_package_from_file(struct net_device *dev, const char *filename,
2723 u32 install_type, struct netlink_ext_ack *extack)
2724{
2725 const struct firmware *fw;
2726 int rc;
2727
2728 rc = request_firmware(&fw, filename, &dev->dev);
2729 if (rc != 0) {
2730 netdev_err(dev, "PKG error %d requesting file: %s\n",
2731 rc, filename);
2732 return rc;
2733 }
2734
2735 rc = bnxt_flash_package_from_fw_obj(dev, fw, install_type, extack);
2736
2737 release_firmware(fw);
2738
2739 return rc;
2740}
2741
2742static int bnxt_flash_device(struct net_device *dev,
2743 struct ethtool_flash *flash)
2744{
2745 if (!BNXT_PF((struct bnxt *)netdev_priv(dev))) {
2746 netdev_err(dev, "flashdev not supported from a virtual function\n");
2747 return -EINVAL;
2748 }
2749
2750 if (flash->region == ETHTOOL_FLASH_ALL_REGIONS ||
2751 flash->region > 0xffff)
2752 return bnxt_flash_package_from_file(dev, flash->data,
2753 flash->region, NULL);
2754
2755 return bnxt_flash_firmware_from_file(dev, flash->region, flash->data);
2756}
2757
2758static int nvm_get_dir_info(struct net_device *dev, u32 *entries, u32 *length)
2759{
2760 struct hwrm_nvm_get_dir_info_output *output;
2761 struct hwrm_nvm_get_dir_info_input *req;
2762 struct bnxt *bp = netdev_priv(dev);
2763 int rc;
2764
2765 rc = hwrm_req_init(bp, req, HWRM_NVM_GET_DIR_INFO);
2766 if (rc)
2767 return rc;
2768
2769 output = hwrm_req_hold(bp, req);
2770 rc = hwrm_req_send(bp, req);
2771 if (!rc) {
2772 *entries = le32_to_cpu(output->entries);
2773 *length = le32_to_cpu(output->entry_length);
2774 }
2775 hwrm_req_drop(bp, req);
2776 return rc;
2777}
2778
2779static int bnxt_get_eeprom_len(struct net_device *dev)
2780{
2781 struct bnxt *bp = netdev_priv(dev);
2782
2783 if (BNXT_VF(bp))
2784 return 0;
2785
2786
2787
2788
2789 return -1;
2790}
2791
2792static int bnxt_get_nvram_directory(struct net_device *dev, u32 len, u8 *data)
2793{
2794 struct bnxt *bp = netdev_priv(dev);
2795 int rc;
2796 u32 dir_entries;
2797 u32 entry_length;
2798 u8 *buf;
2799 size_t buflen;
2800 dma_addr_t dma_handle;
2801 struct hwrm_nvm_get_dir_entries_input *req;
2802
2803 rc = nvm_get_dir_info(dev, &dir_entries, &entry_length);
2804 if (rc != 0)
2805 return rc;
2806
2807 if (!dir_entries || !entry_length)
2808 return -EIO;
2809
2810
2811 if (len < 2)
2812 return -EINVAL;
2813
2814 *data++ = dir_entries;
2815 *data++ = entry_length;
2816 len -= 2;
2817 memset(data, 0xff, len);
2818
2819 rc = hwrm_req_init(bp, req, HWRM_NVM_GET_DIR_ENTRIES);
2820 if (rc)
2821 return rc;
2822
2823 buflen = dir_entries * entry_length;
2824 buf = hwrm_req_dma_slice(bp, req, buflen, &dma_handle);
2825 if (!buf) {
2826 hwrm_req_drop(bp, req);
2827 return -ENOMEM;
2828 }
2829 req->host_dest_addr = cpu_to_le64(dma_handle);
2830
2831 hwrm_req_hold(bp, req);
2832 rc = hwrm_req_send(bp, req);
2833 if (rc == 0)
2834 memcpy(data, buf, len > buflen ? buflen : len);
2835 hwrm_req_drop(bp, req);
2836 return rc;
2837}
2838
2839static int bnxt_get_nvram_item(struct net_device *dev, u32 index, u32 offset,
2840 u32 length, u8 *data)
2841{
2842 struct bnxt *bp = netdev_priv(dev);
2843 int rc;
2844 u8 *buf;
2845 dma_addr_t dma_handle;
2846 struct hwrm_nvm_read_input *req;
2847
2848 if (!length)
2849 return -EINVAL;
2850
2851 rc = hwrm_req_init(bp, req, HWRM_NVM_READ);
2852 if (rc)
2853 return rc;
2854
2855 buf = hwrm_req_dma_slice(bp, req, length, &dma_handle);
2856 if (!buf) {
2857 hwrm_req_drop(bp, req);
2858 return -ENOMEM;
2859 }
2860
2861 req->host_dest_addr = cpu_to_le64(dma_handle);
2862 req->dir_idx = cpu_to_le16(index);
2863 req->offset = cpu_to_le32(offset);
2864 req->len = cpu_to_le32(length);
2865
2866 hwrm_req_hold(bp, req);
2867 rc = hwrm_req_send(bp, req);
2868 if (rc == 0)
2869 memcpy(data, buf, length);
2870 hwrm_req_drop(bp, req);
2871 return rc;
2872}
2873
2874static int bnxt_find_nvram_item(struct net_device *dev, u16 type, u16 ordinal,
2875 u16 ext, u16 *index, u32 *item_length,
2876 u32 *data_length)
2877{
2878 struct hwrm_nvm_find_dir_entry_output *output;
2879 struct hwrm_nvm_find_dir_entry_input *req;
2880 struct bnxt *bp = netdev_priv(dev);
2881 int rc;
2882
2883 rc = hwrm_req_init(bp, req, HWRM_NVM_FIND_DIR_ENTRY);
2884 if (rc)
2885 return rc;
2886
2887 req->enables = 0;
2888 req->dir_idx = 0;
2889 req->dir_type = cpu_to_le16(type);
2890 req->dir_ordinal = cpu_to_le16(ordinal);
2891 req->dir_ext = cpu_to_le16(ext);
2892 req->opt_ordinal = NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_EQ;
2893 output = hwrm_req_hold(bp, req);
2894 rc = hwrm_req_send_silent(bp, req);
2895 if (rc == 0) {
2896 if (index)
2897 *index = le16_to_cpu(output->dir_idx);
2898 if (item_length)
2899 *item_length = le32_to_cpu(output->dir_item_length);
2900 if (data_length)
2901 *data_length = le32_to_cpu(output->dir_data_length);
2902 }
2903 hwrm_req_drop(bp, req);
2904 return rc;
2905}
2906
2907static char *bnxt_parse_pkglog(int desired_field, u8 *data, size_t datalen)
2908{
2909 char *retval = NULL;
2910 char *p;
2911 char *value;
2912 int field = 0;
2913
2914 if (datalen < 1)
2915 return NULL;
2916
2917 data[datalen - 1] = 0;
2918 for (p = data; *p != 0; p++) {
2919 field = 0;
2920 retval = NULL;
2921 while (*p != 0 && *p != '\n') {
2922 value = p;
2923 while (*p != 0 && *p != '\t' && *p != '\n')
2924 p++;
2925 if (field == desired_field)
2926 retval = value;
2927 if (*p != '\t')
2928 break;
2929 *p = 0;
2930 field++;
2931 p++;
2932 }
2933 if (*p == 0)
2934 break;
2935 *p = 0;
2936 }
2937 return retval;
2938}
2939
2940int bnxt_get_pkginfo(struct net_device *dev, char *ver, int size)
2941{
2942 struct bnxt *bp = netdev_priv(dev);
2943 u16 index = 0;
2944 char *pkgver;
2945 u32 pkglen;
2946 u8 *pkgbuf;
2947 int rc;
2948
2949 rc = bnxt_find_nvram_item(dev, BNX_DIR_TYPE_PKG_LOG,
2950 BNX_DIR_ORDINAL_FIRST, BNX_DIR_EXT_NONE,
2951 &index, NULL, &pkglen);
2952 if (rc)
2953 return rc;
2954
2955 pkgbuf = kzalloc(pkglen, GFP_KERNEL);
2956 if (!pkgbuf) {
2957 dev_err(&bp->pdev->dev, "Unable to allocate memory for pkg version, length = %u\n",
2958 pkglen);
2959 return -ENOMEM;
2960 }
2961
2962 rc = bnxt_get_nvram_item(dev, index, 0, pkglen, pkgbuf);
2963 if (rc)
2964 goto err;
2965
2966 pkgver = bnxt_parse_pkglog(BNX_PKG_LOG_FIELD_IDX_PKG_VERSION, pkgbuf,
2967 pkglen);
2968 if (pkgver && *pkgver != 0 && isdigit(*pkgver))
2969 strscpy(ver, pkgver, size);
2970 else
2971 rc = -ENOENT;
2972
2973err:
2974 kfree(pkgbuf);
2975
2976 return rc;
2977}
2978
2979static void bnxt_get_pkgver(struct net_device *dev)
2980{
2981 struct bnxt *bp = netdev_priv(dev);
2982 char buf[FW_VER_STR_LEN];
2983 int len;
2984
2985 if (!bnxt_get_pkginfo(dev, buf, sizeof(buf))) {
2986 len = strlen(bp->fw_ver_str);
2987 snprintf(bp->fw_ver_str + len, FW_VER_STR_LEN - len - 1,
2988 "/pkg %s", buf);
2989 }
2990}
2991
2992static int bnxt_get_eeprom(struct net_device *dev,
2993 struct ethtool_eeprom *eeprom,
2994 u8 *data)
2995{
2996 u32 index;
2997 u32 offset;
2998
2999 if (eeprom->offset == 0)
3000 return bnxt_get_nvram_directory(dev, eeprom->len, data);
3001
3002 index = eeprom->offset >> 24;
3003 offset = eeprom->offset & 0xffffff;
3004
3005 if (index == 0) {
3006 netdev_err(dev, "unsupported index value: %d\n", index);
3007 return -EINVAL;
3008 }
3009
3010 return bnxt_get_nvram_item(dev, index - 1, offset, eeprom->len, data);
3011}
3012
3013static int bnxt_erase_nvram_directory(struct net_device *dev, u8 index)
3014{
3015 struct hwrm_nvm_erase_dir_entry_input *req;
3016 struct bnxt *bp = netdev_priv(dev);
3017 int rc;
3018
3019 rc = hwrm_req_init(bp, req, HWRM_NVM_ERASE_DIR_ENTRY);
3020 if (rc)
3021 return rc;
3022
3023 req->dir_idx = cpu_to_le16(index);
3024 return hwrm_req_send(bp, req);
3025}
3026
3027static int bnxt_set_eeprom(struct net_device *dev,
3028 struct ethtool_eeprom *eeprom,
3029 u8 *data)
3030{
3031 struct bnxt *bp = netdev_priv(dev);
3032 u8 index, dir_op;
3033 u16 type, ext, ordinal, attr;
3034
3035 if (!BNXT_PF(bp)) {
3036 netdev_err(dev, "NVM write not supported from a virtual function\n");
3037 return -EINVAL;
3038 }
3039
3040 type = eeprom->magic >> 16;
3041
3042 if (type == 0xffff) {
3043 index = eeprom->magic & 0xff;
3044 dir_op = eeprom->magic >> 8;
3045 if (index == 0)
3046 return -EINVAL;
3047 switch (dir_op) {
3048 case 0x0e:
3049 if (eeprom->offset != ~eeprom->magic)
3050 return -EINVAL;
3051 return bnxt_erase_nvram_directory(dev, index - 1);
3052 default:
3053 return -EINVAL;
3054 }
3055 }
3056
3057
3058 if (bnxt_dir_type_is_executable(type))
3059 return -EOPNOTSUPP;
3060 ext = eeprom->magic & 0xffff;
3061 ordinal = eeprom->offset >> 16;
3062 attr = eeprom->offset & 0xffff;
3063
3064 return bnxt_flash_nvram(dev, type, ordinal, ext, attr, 0, data,
3065 eeprom->len);
3066}
3067
3068static int bnxt_set_eee(struct net_device *dev, struct ethtool_eee *edata)
3069{
3070 struct bnxt *bp = netdev_priv(dev);
3071 struct ethtool_eee *eee = &bp->eee;
3072 struct bnxt_link_info *link_info = &bp->link_info;
3073 u32 advertising;
3074 int rc = 0;
3075
3076 if (!BNXT_PHY_CFG_ABLE(bp))
3077 return -EOPNOTSUPP;
3078
3079 if (!(bp->phy_flags & BNXT_PHY_FL_EEE_CAP))
3080 return -EOPNOTSUPP;
3081
3082 mutex_lock(&bp->link_lock);
3083 advertising = _bnxt_fw_to_ethtool_adv_spds(link_info->advertising, 0);
3084 if (!edata->eee_enabled)
3085 goto eee_ok;
3086
3087 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) {
3088 netdev_warn(dev, "EEE requires autoneg\n");
3089 rc = -EINVAL;
3090 goto eee_exit;
3091 }
3092 if (edata->tx_lpi_enabled) {
3093 if (bp->lpi_tmr_hi && (edata->tx_lpi_timer > bp->lpi_tmr_hi ||
3094 edata->tx_lpi_timer < bp->lpi_tmr_lo)) {
3095 netdev_warn(dev, "Valid LPI timer range is %d and %d microsecs\n",
3096 bp->lpi_tmr_lo, bp->lpi_tmr_hi);
3097 rc = -EINVAL;
3098 goto eee_exit;
3099 } else if (!bp->lpi_tmr_hi) {
3100 edata->tx_lpi_timer = eee->tx_lpi_timer;
3101 }
3102 }
3103 if (!edata->advertised) {
3104 edata->advertised = advertising & eee->supported;
3105 } else if (edata->advertised & ~advertising) {
3106 netdev_warn(dev, "EEE advertised %x must be a subset of autoneg advertised speeds %x\n",
3107 edata->advertised, advertising);
3108 rc = -EINVAL;
3109 goto eee_exit;
3110 }
3111
3112 eee->advertised = edata->advertised;
3113 eee->tx_lpi_enabled = edata->tx_lpi_enabled;
3114 eee->tx_lpi_timer = edata->tx_lpi_timer;
3115eee_ok:
3116 eee->eee_enabled = edata->eee_enabled;
3117
3118 if (netif_running(dev))
3119 rc = bnxt_hwrm_set_link_setting(bp, false, true);
3120
3121eee_exit:
3122 mutex_unlock(&bp->link_lock);
3123 return rc;
3124}
3125
3126static int bnxt_get_eee(struct net_device *dev, struct ethtool_eee *edata)
3127{
3128 struct bnxt *bp = netdev_priv(dev);
3129
3130 if (!(bp->phy_flags & BNXT_PHY_FL_EEE_CAP))
3131 return -EOPNOTSUPP;
3132
3133 *edata = bp->eee;
3134 if (!bp->eee.eee_enabled) {
3135
3136
3137
3138 edata->advertised = 0;
3139 edata->tx_lpi_enabled = 0;
3140 }
3141
3142 if (!bp->eee.eee_active)
3143 edata->lp_advertised = 0;
3144
3145 return 0;
3146}
3147
3148static int bnxt_read_sfp_module_eeprom_info(struct bnxt *bp, u16 i2c_addr,
3149 u16 page_number, u16 start_addr,
3150 u16 data_length, u8 *buf)
3151{
3152 struct hwrm_port_phy_i2c_read_output *output;
3153 struct hwrm_port_phy_i2c_read_input *req;
3154 int rc, byte_offset = 0;
3155
3156 rc = hwrm_req_init(bp, req, HWRM_PORT_PHY_I2C_READ);
3157 if (rc)
3158 return rc;
3159
3160 output = hwrm_req_hold(bp, req);
3161 req->i2c_slave_addr = i2c_addr;
3162 req->page_number = cpu_to_le16(page_number);
3163 req->port_id = cpu_to_le16(bp->pf.port_id);
3164 do {
3165 u16 xfer_size;
3166
3167 xfer_size = min_t(u16, data_length, BNXT_MAX_PHY_I2C_RESP_SIZE);
3168 data_length -= xfer_size;
3169 req->page_offset = cpu_to_le16(start_addr + byte_offset);
3170 req->data_length = xfer_size;
3171 req->enables = cpu_to_le32(start_addr + byte_offset ?
3172 PORT_PHY_I2C_READ_REQ_ENABLES_PAGE_OFFSET : 0);
3173 rc = hwrm_req_send(bp, req);
3174 if (!rc)
3175 memcpy(buf + byte_offset, output->data, xfer_size);
3176 byte_offset += xfer_size;
3177 } while (!rc && data_length > 0);
3178 hwrm_req_drop(bp, req);
3179
3180 return rc;
3181}
3182
3183static int bnxt_get_module_info(struct net_device *dev,
3184 struct ethtool_modinfo *modinfo)
3185{
3186 u8 data[SFF_DIAG_SUPPORT_OFFSET + 1];
3187 struct bnxt *bp = netdev_priv(dev);
3188 int rc;
3189
3190
3191
3192
3193
3194 if (bp->link_info.module_status >
3195 PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG)
3196 return -EOPNOTSUPP;
3197
3198
3199 if (bp->hwrm_spec_code < 0x10202)
3200 return -EOPNOTSUPP;
3201
3202 rc = bnxt_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A0, 0, 0,
3203 SFF_DIAG_SUPPORT_OFFSET + 1,
3204 data);
3205 if (!rc) {
3206 u8 module_id = data[0];
3207 u8 diag_supported = data[SFF_DIAG_SUPPORT_OFFSET];
3208
3209 switch (module_id) {
3210 case SFF_MODULE_ID_SFP:
3211 modinfo->type = ETH_MODULE_SFF_8472;
3212 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN;
3213 if (!diag_supported)
3214 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN;
3215 break;
3216 case SFF_MODULE_ID_QSFP:
3217 case SFF_MODULE_ID_QSFP_PLUS:
3218 modinfo->type = ETH_MODULE_SFF_8436;
3219 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN;
3220 break;
3221 case SFF_MODULE_ID_QSFP28:
3222 modinfo->type = ETH_MODULE_SFF_8636;
3223 modinfo->eeprom_len = ETH_MODULE_SFF_8636_LEN;
3224 break;
3225 default:
3226 rc = -EOPNOTSUPP;
3227 break;
3228 }
3229 }
3230 return rc;
3231}
3232
3233static int bnxt_get_module_eeprom(struct net_device *dev,
3234 struct ethtool_eeprom *eeprom,
3235 u8 *data)
3236{
3237 struct bnxt *bp = netdev_priv(dev);
3238 u16 start = eeprom->offset, length = eeprom->len;
3239 int rc = 0;
3240
3241 memset(data, 0, eeprom->len);
3242
3243
3244 if (start < ETH_MODULE_SFF_8436_LEN) {
3245 if (start + eeprom->len > ETH_MODULE_SFF_8436_LEN)
3246 length = ETH_MODULE_SFF_8436_LEN - start;
3247 rc = bnxt_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A0, 0,
3248 start, length, data);
3249 if (rc)
3250 return rc;
3251 start += length;
3252 data += length;
3253 length = eeprom->len - length;
3254 }
3255
3256
3257 if (length) {
3258 start -= ETH_MODULE_SFF_8436_LEN;
3259 rc = bnxt_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A2, 0,
3260 start, length, data);
3261 }
3262 return rc;
3263}
3264
3265static int bnxt_nway_reset(struct net_device *dev)
3266{
3267 int rc = 0;
3268
3269 struct bnxt *bp = netdev_priv(dev);
3270 struct bnxt_link_info *link_info = &bp->link_info;
3271
3272 if (!BNXT_PHY_CFG_ABLE(bp))
3273 return -EOPNOTSUPP;
3274
3275 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED))
3276 return -EINVAL;
3277
3278 if (netif_running(dev))
3279 rc = bnxt_hwrm_set_link_setting(bp, true, false);
3280
3281 return rc;
3282}
3283
3284static int bnxt_set_phys_id(struct net_device *dev,
3285 enum ethtool_phys_id_state state)
3286{
3287 struct hwrm_port_led_cfg_input *req;
3288 struct bnxt *bp = netdev_priv(dev);
3289 struct bnxt_pf_info *pf = &bp->pf;
3290 struct bnxt_led_cfg *led_cfg;
3291 u8 led_state;
3292 __le16 duration;
3293 int rc, i;
3294
3295 if (!bp->num_leds || BNXT_VF(bp))
3296 return -EOPNOTSUPP;
3297
3298 if (state == ETHTOOL_ID_ACTIVE) {
3299 led_state = PORT_LED_CFG_REQ_LED0_STATE_BLINKALT;
3300 duration = cpu_to_le16(500);
3301 } else if (state == ETHTOOL_ID_INACTIVE) {
3302 led_state = PORT_LED_CFG_REQ_LED1_STATE_DEFAULT;
3303 duration = cpu_to_le16(0);
3304 } else {
3305 return -EINVAL;
3306 }
3307 rc = hwrm_req_init(bp, req, HWRM_PORT_LED_CFG);
3308 if (rc)
3309 return rc;
3310
3311 req->port_id = cpu_to_le16(pf->port_id);
3312 req->num_leds = bp->num_leds;
3313 led_cfg = (struct bnxt_led_cfg *)&req->led0_id;
3314 for (i = 0; i < bp->num_leds; i++, led_cfg++) {
3315 req->enables |= BNXT_LED_DFLT_ENABLES(i);
3316 led_cfg->led_id = bp->leds[i].led_id;
3317 led_cfg->led_state = led_state;
3318 led_cfg->led_blink_on = duration;
3319 led_cfg->led_blink_off = duration;
3320 led_cfg->led_group_id = bp->leds[i].led_group_id;
3321 }
3322 return hwrm_req_send(bp, req);
3323}
3324
3325static int bnxt_hwrm_selftest_irq(struct bnxt *bp, u16 cmpl_ring)
3326{
3327 struct hwrm_selftest_irq_input *req;
3328 int rc;
3329
3330 rc = hwrm_req_init(bp, req, HWRM_SELFTEST_IRQ);
3331 if (rc)
3332 return rc;
3333
3334 req->cmpl_ring = cpu_to_le16(cmpl_ring);
3335 return hwrm_req_send(bp, req);
3336}
3337
3338static int bnxt_test_irq(struct bnxt *bp)
3339{
3340 int i;
3341
3342 for (i = 0; i < bp->cp_nr_rings; i++) {
3343 u16 cmpl_ring = bp->grp_info[i].cp_fw_ring_id;
3344 int rc;
3345
3346 rc = bnxt_hwrm_selftest_irq(bp, cmpl_ring);
3347 if (rc)
3348 return rc;
3349 }
3350 return 0;
3351}
3352
3353static int bnxt_hwrm_mac_loopback(struct bnxt *bp, bool enable)
3354{
3355 struct hwrm_port_mac_cfg_input *req;
3356 int rc;
3357
3358 rc = hwrm_req_init(bp, req, HWRM_PORT_MAC_CFG);
3359 if (rc)
3360 return rc;
3361
3362 req->enables = cpu_to_le32(PORT_MAC_CFG_REQ_ENABLES_LPBK);
3363 if (enable)
3364 req->lpbk = PORT_MAC_CFG_REQ_LPBK_LOCAL;
3365 else
3366 req->lpbk = PORT_MAC_CFG_REQ_LPBK_NONE;
3367 return hwrm_req_send(bp, req);
3368}
3369
3370static int bnxt_query_force_speeds(struct bnxt *bp, u16 *force_speeds)
3371{
3372 struct hwrm_port_phy_qcaps_output *resp;
3373 struct hwrm_port_phy_qcaps_input *req;
3374 int rc;
3375
3376 rc = hwrm_req_init(bp, req, HWRM_PORT_PHY_QCAPS);
3377 if (rc)
3378 return rc;
3379
3380 resp = hwrm_req_hold(bp, req);
3381 rc = hwrm_req_send(bp, req);
3382 if (!rc)
3383 *force_speeds = le16_to_cpu(resp->supported_speeds_force_mode);
3384
3385 hwrm_req_drop(bp, req);
3386 return rc;
3387}
3388
3389static int bnxt_disable_an_for_lpbk(struct bnxt *bp,
3390 struct hwrm_port_phy_cfg_input *req)
3391{
3392 struct bnxt_link_info *link_info = &bp->link_info;
3393 u16 fw_advertising;
3394 u16 fw_speed;
3395 int rc;
3396
3397 if (!link_info->autoneg ||
3398 (bp->phy_flags & BNXT_PHY_FL_AN_PHY_LPBK))
3399 return 0;
3400
3401 rc = bnxt_query_force_speeds(bp, &fw_advertising);
3402 if (rc)
3403 return rc;
3404
3405 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_1GB;
3406 if (BNXT_LINK_IS_UP(bp))
3407 fw_speed = bp->link_info.link_speed;
3408 else if (fw_advertising & BNXT_LINK_SPEED_MSK_10GB)
3409 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10GB;
3410 else if (fw_advertising & BNXT_LINK_SPEED_MSK_25GB)
3411 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_25GB;
3412 else if (fw_advertising & BNXT_LINK_SPEED_MSK_40GB)
3413 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_40GB;
3414 else if (fw_advertising & BNXT_LINK_SPEED_MSK_50GB)
3415 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_50GB;
3416
3417 req->force_link_speed = cpu_to_le16(fw_speed);
3418 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE |
3419 PORT_PHY_CFG_REQ_FLAGS_RESET_PHY);
3420 rc = hwrm_req_send(bp, req);
3421 req->flags = 0;
3422 req->force_link_speed = cpu_to_le16(0);
3423 return rc;
3424}
3425
3426static int bnxt_hwrm_phy_loopback(struct bnxt *bp, bool enable, bool ext)
3427{
3428 struct hwrm_port_phy_cfg_input *req;
3429 int rc;
3430
3431 rc = hwrm_req_init(bp, req, HWRM_PORT_PHY_CFG);
3432 if (rc)
3433 return rc;
3434
3435
3436 hwrm_req_hold(bp, req);
3437
3438 if (enable) {
3439 bnxt_disable_an_for_lpbk(bp, req);
3440 if (ext)
3441 req->lpbk = PORT_PHY_CFG_REQ_LPBK_EXTERNAL;
3442 else
3443 req->lpbk = PORT_PHY_CFG_REQ_LPBK_LOCAL;
3444 } else {
3445 req->lpbk = PORT_PHY_CFG_REQ_LPBK_NONE;
3446 }
3447 req->enables = cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_LPBK);
3448 rc = hwrm_req_send(bp, req);
3449 hwrm_req_drop(bp, req);
3450 return rc;
3451}
3452
3453static int bnxt_rx_loopback(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
3454 u32 raw_cons, int pkt_size)
3455{
3456 struct bnxt_napi *bnapi = cpr->bnapi;
3457 struct bnxt_rx_ring_info *rxr;
3458 struct bnxt_sw_rx_bd *rx_buf;
3459 struct rx_cmp *rxcmp;
3460 u16 cp_cons, cons;
3461 u8 *data;
3462 u32 len;
3463 int i;
3464
3465 rxr = bnapi->rx_ring;
3466 cp_cons = RING_CMP(raw_cons);
3467 rxcmp = (struct rx_cmp *)
3468 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
3469 cons = rxcmp->rx_cmp_opaque;
3470 rx_buf = &rxr->rx_buf_ring[cons];
3471 data = rx_buf->data_ptr;
3472 len = le32_to_cpu(rxcmp->rx_cmp_len_flags_type) >> RX_CMP_LEN_SHIFT;
3473 if (len != pkt_size)
3474 return -EIO;
3475 i = ETH_ALEN;
3476 if (!ether_addr_equal(data + i, bnapi->bp->dev->dev_addr))
3477 return -EIO;
3478 i += ETH_ALEN;
3479 for ( ; i < pkt_size; i++) {
3480 if (data[i] != (u8)(i & 0xff))
3481 return -EIO;
3482 }
3483 return 0;
3484}
3485
3486static int bnxt_poll_loopback(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
3487 int pkt_size)
3488{
3489 struct tx_cmp *txcmp;
3490 int rc = -EIO;
3491 u32 raw_cons;
3492 u32 cons;
3493 int i;
3494
3495 raw_cons = cpr->cp_raw_cons;
3496 for (i = 0; i < 200; i++) {
3497 cons = RING_CMP(raw_cons);
3498 txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)];
3499
3500 if (!TX_CMP_VALID(txcmp, raw_cons)) {
3501 udelay(5);
3502 continue;
3503 }
3504
3505
3506
3507
3508 dma_rmb();
3509 if (TX_CMP_TYPE(txcmp) == CMP_TYPE_RX_L2_CMP) {
3510 rc = bnxt_rx_loopback(bp, cpr, raw_cons, pkt_size);
3511 raw_cons = NEXT_RAW_CMP(raw_cons);
3512 raw_cons = NEXT_RAW_CMP(raw_cons);
3513 break;
3514 }
3515 raw_cons = NEXT_RAW_CMP(raw_cons);
3516 }
3517 cpr->cp_raw_cons = raw_cons;
3518 return rc;
3519}
3520
3521static int bnxt_run_loopback(struct bnxt *bp)
3522{
3523 struct bnxt_tx_ring_info *txr = &bp->tx_ring[0];
3524 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[0];
3525 struct bnxt_cp_ring_info *cpr;
3526 int pkt_size, i = 0;
3527 struct sk_buff *skb;
3528 dma_addr_t map;
3529 u8 *data;
3530 int rc;
3531
3532 cpr = &rxr->bnapi->cp_ring;
3533 if (bp->flags & BNXT_FLAG_CHIP_P5)
3534 cpr = cpr->cp_ring_arr[BNXT_RX_HDL];
3535 pkt_size = min(bp->dev->mtu + ETH_HLEN, bp->rx_copy_thresh);
3536 skb = netdev_alloc_skb(bp->dev, pkt_size);
3537 if (!skb)
3538 return -ENOMEM;
3539 data = skb_put(skb, pkt_size);
3540 ether_addr_copy(&data[i], bp->dev->dev_addr);
3541 i += ETH_ALEN;
3542 ether_addr_copy(&data[i], bp->dev->dev_addr);
3543 i += ETH_ALEN;
3544 for ( ; i < pkt_size; i++)
3545 data[i] = (u8)(i & 0xff);
3546
3547 map = dma_map_single(&bp->pdev->dev, skb->data, pkt_size,
3548 DMA_TO_DEVICE);
3549 if (dma_mapping_error(&bp->pdev->dev, map)) {
3550 dev_kfree_skb(skb);
3551 return -EIO;
3552 }
3553 bnxt_xmit_bd(bp, txr, map, pkt_size, NULL);
3554
3555
3556 wmb();
3557
3558 bnxt_db_write(bp, &txr->tx_db, txr->tx_prod);
3559 rc = bnxt_poll_loopback(bp, cpr, pkt_size);
3560
3561 dma_unmap_single(&bp->pdev->dev, map, pkt_size, DMA_TO_DEVICE);
3562 dev_kfree_skb(skb);
3563 return rc;
3564}
3565
3566static int bnxt_run_fw_tests(struct bnxt *bp, u8 test_mask, u8 *test_results)
3567{
3568 struct hwrm_selftest_exec_output *resp;
3569 struct hwrm_selftest_exec_input *req;
3570 int rc;
3571
3572 rc = hwrm_req_init(bp, req, HWRM_SELFTEST_EXEC);
3573 if (rc)
3574 return rc;
3575
3576 hwrm_req_timeout(bp, req, bp->test_info->timeout);
3577 req->flags = test_mask;
3578
3579 resp = hwrm_req_hold(bp, req);
3580 rc = hwrm_req_send(bp, req);
3581 *test_results = resp->test_success;
3582 hwrm_req_drop(bp, req);
3583 return rc;
3584}
3585
3586#define BNXT_DRV_TESTS 4
3587#define BNXT_MACLPBK_TEST_IDX (bp->num_tests - BNXT_DRV_TESTS)
3588#define BNXT_PHYLPBK_TEST_IDX (BNXT_MACLPBK_TEST_IDX + 1)
3589#define BNXT_EXTLPBK_TEST_IDX (BNXT_MACLPBK_TEST_IDX + 2)
3590#define BNXT_IRQ_TEST_IDX (BNXT_MACLPBK_TEST_IDX + 3)
3591
3592static void bnxt_self_test(struct net_device *dev, struct ethtool_test *etest,
3593 u64 *buf)
3594{
3595 struct bnxt *bp = netdev_priv(dev);
3596 bool do_ext_lpbk = false;
3597 bool offline = false;
3598 u8 test_results = 0;
3599 u8 test_mask = 0;
3600 int rc = 0, i;
3601
3602 if (!bp->num_tests || !BNXT_PF(bp))
3603 return;
3604 memset(buf, 0, sizeof(u64) * bp->num_tests);
3605 if (!netif_running(dev)) {
3606 etest->flags |= ETH_TEST_FL_FAILED;
3607 return;
3608 }
3609
3610 if ((etest->flags & ETH_TEST_FL_EXTERNAL_LB) &&
3611 (bp->phy_flags & BNXT_PHY_FL_EXT_LPBK))
3612 do_ext_lpbk = true;
3613
3614 if (etest->flags & ETH_TEST_FL_OFFLINE) {
3615 if (bp->pf.active_vfs || !BNXT_SINGLE_PF(bp)) {
3616 etest->flags |= ETH_TEST_FL_FAILED;
3617 netdev_warn(dev, "Offline tests cannot be run with active VFs or on shared PF\n");
3618 return;
3619 }
3620 offline = true;
3621 }
3622
3623 for (i = 0; i < bp->num_tests - BNXT_DRV_TESTS; i++) {
3624 u8 bit_val = 1 << i;
3625
3626 if (!(bp->test_info->offline_mask & bit_val))
3627 test_mask |= bit_val;
3628 else if (offline)
3629 test_mask |= bit_val;
3630 }
3631 if (!offline) {
3632 bnxt_run_fw_tests(bp, test_mask, &test_results);
3633 } else {
3634 bnxt_ulp_stop(bp);
3635 rc = bnxt_close_nic(bp, true, false);
3636 if (rc) {
3637 bnxt_ulp_start(bp, rc);
3638 return;
3639 }
3640 bnxt_run_fw_tests(bp, test_mask, &test_results);
3641
3642 buf[BNXT_MACLPBK_TEST_IDX] = 1;
3643 bnxt_hwrm_mac_loopback(bp, true);
3644 msleep(250);
3645 rc = bnxt_half_open_nic(bp);
3646 if (rc) {
3647 bnxt_hwrm_mac_loopback(bp, false);
3648 etest->flags |= ETH_TEST_FL_FAILED;
3649 bnxt_ulp_start(bp, rc);
3650 return;
3651 }
3652 if (bnxt_run_loopback(bp))
3653 etest->flags |= ETH_TEST_FL_FAILED;
3654 else
3655 buf[BNXT_MACLPBK_TEST_IDX] = 0;
3656
3657 bnxt_hwrm_mac_loopback(bp, false);
3658 bnxt_hwrm_phy_loopback(bp, true, false);
3659 msleep(1000);
3660 if (bnxt_run_loopback(bp)) {
3661 buf[BNXT_PHYLPBK_TEST_IDX] = 1;
3662 etest->flags |= ETH_TEST_FL_FAILED;
3663 }
3664 if (do_ext_lpbk) {
3665 etest->flags |= ETH_TEST_FL_EXTERNAL_LB_DONE;
3666 bnxt_hwrm_phy_loopback(bp, true, true);
3667 msleep(1000);
3668 if (bnxt_run_loopback(bp)) {
3669 buf[BNXT_EXTLPBK_TEST_IDX] = 1;
3670 etest->flags |= ETH_TEST_FL_FAILED;
3671 }
3672 }
3673 bnxt_hwrm_phy_loopback(bp, false, false);
3674 bnxt_half_close_nic(bp);
3675 rc = bnxt_open_nic(bp, true, true);
3676 bnxt_ulp_start(bp, rc);
3677 }
3678 if (rc || bnxt_test_irq(bp)) {
3679 buf[BNXT_IRQ_TEST_IDX] = 1;
3680 etest->flags |= ETH_TEST_FL_FAILED;
3681 }
3682 for (i = 0; i < bp->num_tests - BNXT_DRV_TESTS; i++) {
3683 u8 bit_val = 1 << i;
3684
3685 if ((test_mask & bit_val) && !(test_results & bit_val)) {
3686 buf[i] = 1;
3687 etest->flags |= ETH_TEST_FL_FAILED;
3688 }
3689 }
3690}
3691
3692static int bnxt_reset(struct net_device *dev, u32 *flags)
3693{
3694 struct bnxt *bp = netdev_priv(dev);
3695 bool reload = false;
3696 u32 req = *flags;
3697
3698 if (!req)
3699 return -EINVAL;
3700
3701 if (!BNXT_PF(bp)) {
3702 netdev_err(dev, "Reset is not supported from a VF\n");
3703 return -EOPNOTSUPP;
3704 }
3705
3706 if (pci_vfs_assigned(bp->pdev) &&
3707 !(bp->fw_cap & BNXT_FW_CAP_HOT_RESET)) {
3708 netdev_err(dev,
3709 "Reset not allowed when VFs are assigned to VMs\n");
3710 return -EBUSY;
3711 }
3712
3713 if ((req & BNXT_FW_RESET_CHIP) == BNXT_FW_RESET_CHIP) {
3714
3715 if (bp->hwrm_spec_code >= 0x10803) {
3716 if (!bnxt_firmware_reset_chip(dev)) {
3717 netdev_info(dev, "Firmware reset request successful.\n");
3718 if (!(bp->fw_cap & BNXT_FW_CAP_HOT_RESET))
3719 reload = true;
3720 *flags &= ~BNXT_FW_RESET_CHIP;
3721 }
3722 } else if (req == BNXT_FW_RESET_CHIP) {
3723 return -EOPNOTSUPP;
3724 }
3725 }
3726
3727 if (req & BNXT_FW_RESET_AP) {
3728
3729 if (bp->hwrm_spec_code >= 0x10803) {
3730 if (!bnxt_firmware_reset_ap(dev)) {
3731 netdev_info(dev, "Reset application processor successful.\n");
3732 reload = true;
3733 *flags &= ~BNXT_FW_RESET_AP;
3734 }
3735 } else if (req == BNXT_FW_RESET_AP) {
3736 return -EOPNOTSUPP;
3737 }
3738 }
3739
3740 if (reload)
3741 netdev_info(dev, "Reload driver to complete reset\n");
3742
3743 return 0;
3744}
3745
3746static int bnxt_set_dump(struct net_device *dev, struct ethtool_dump *dump)
3747{
3748 struct bnxt *bp = netdev_priv(dev);
3749
3750 if (dump->flag > BNXT_DUMP_CRASH) {
3751 netdev_info(dev, "Supports only Live(0) and Crash(1) dumps.\n");
3752 return -EINVAL;
3753 }
3754
3755 if (!IS_ENABLED(CONFIG_TEE_BNXT_FW) && dump->flag == BNXT_DUMP_CRASH) {
3756 netdev_info(dev, "Cannot collect crash dump as TEE_BNXT_FW config option is not enabled.\n");
3757 return -EOPNOTSUPP;
3758 }
3759
3760 bp->dump_flag = dump->flag;
3761 return 0;
3762}
3763
3764static int bnxt_get_dump_flag(struct net_device *dev, struct ethtool_dump *dump)
3765{
3766 struct bnxt *bp = netdev_priv(dev);
3767
3768 if (bp->hwrm_spec_code < 0x10801)
3769 return -EOPNOTSUPP;
3770
3771 dump->version = bp->ver_resp.hwrm_fw_maj_8b << 24 |
3772 bp->ver_resp.hwrm_fw_min_8b << 16 |
3773 bp->ver_resp.hwrm_fw_bld_8b << 8 |
3774 bp->ver_resp.hwrm_fw_rsvd_8b;
3775
3776 dump->flag = bp->dump_flag;
3777 dump->len = bnxt_get_coredump_length(bp, bp->dump_flag);
3778 return 0;
3779}
3780
3781static int bnxt_get_dump_data(struct net_device *dev, struct ethtool_dump *dump,
3782 void *buf)
3783{
3784 struct bnxt *bp = netdev_priv(dev);
3785
3786 if (bp->hwrm_spec_code < 0x10801)
3787 return -EOPNOTSUPP;
3788
3789 memset(buf, 0, dump->len);
3790
3791 dump->flag = bp->dump_flag;
3792 return bnxt_get_coredump(bp, dump->flag, buf, &dump->len);
3793}
3794
3795static int bnxt_get_ts_info(struct net_device *dev,
3796 struct ethtool_ts_info *info)
3797{
3798 struct bnxt *bp = netdev_priv(dev);
3799 struct bnxt_ptp_cfg *ptp;
3800
3801 ptp = bp->ptp_cfg;
3802 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE |
3803 SOF_TIMESTAMPING_RX_SOFTWARE |
3804 SOF_TIMESTAMPING_SOFTWARE;
3805
3806 info->phc_index = -1;
3807 if (!ptp)
3808 return 0;
3809
3810 info->so_timestamping |= SOF_TIMESTAMPING_TX_HARDWARE |
3811 SOF_TIMESTAMPING_RX_HARDWARE |
3812 SOF_TIMESTAMPING_RAW_HARDWARE;
3813 if (ptp->ptp_clock)
3814 info->phc_index = ptp_clock_index(ptp->ptp_clock);
3815
3816 info->tx_types = (1 << HWTSTAMP_TX_OFF) | (1 << HWTSTAMP_TX_ON);
3817
3818 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) |
3819 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) |
3820 (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT);
3821
3822 if (bp->fw_cap & BNXT_FW_CAP_RX_ALL_PKT_TS)
3823 info->rx_filters |= (1 << HWTSTAMP_FILTER_ALL);
3824 return 0;
3825}
3826
3827void bnxt_ethtool_init(struct bnxt *bp)
3828{
3829 struct hwrm_selftest_qlist_output *resp;
3830 struct hwrm_selftest_qlist_input *req;
3831 struct bnxt_test_info *test_info;
3832 struct net_device *dev = bp->dev;
3833 int i, rc;
3834
3835 if (!(bp->fw_cap & BNXT_FW_CAP_PKG_VER))
3836 bnxt_get_pkgver(dev);
3837
3838 bp->num_tests = 0;
3839 if (bp->hwrm_spec_code < 0x10704 || !BNXT_PF(bp))
3840 return;
3841
3842 test_info = bp->test_info;
3843 if (!test_info) {
3844 test_info = kzalloc(sizeof(*bp->test_info), GFP_KERNEL);
3845 if (!test_info)
3846 return;
3847 bp->test_info = test_info;
3848 }
3849
3850 if (hwrm_req_init(bp, req, HWRM_SELFTEST_QLIST))
3851 return;
3852
3853 resp = hwrm_req_hold(bp, req);
3854 rc = hwrm_req_send_silent(bp, req);
3855 if (rc)
3856 goto ethtool_init_exit;
3857
3858 bp->num_tests = resp->num_tests + BNXT_DRV_TESTS;
3859 if (bp->num_tests > BNXT_MAX_TEST)
3860 bp->num_tests = BNXT_MAX_TEST;
3861
3862 test_info->offline_mask = resp->offline_tests;
3863 test_info->timeout = le16_to_cpu(resp->test_timeout);
3864 if (!test_info->timeout)
3865 test_info->timeout = HWRM_CMD_TIMEOUT;
3866 for (i = 0; i < bp->num_tests; i++) {
3867 char *str = test_info->string[i];
3868 char *fw_str = resp->test0_name + i * 32;
3869
3870 if (i == BNXT_MACLPBK_TEST_IDX) {
3871 strcpy(str, "Mac loopback test (offline)");
3872 } else if (i == BNXT_PHYLPBK_TEST_IDX) {
3873 strcpy(str, "Phy loopback test (offline)");
3874 } else if (i == BNXT_EXTLPBK_TEST_IDX) {
3875 strcpy(str, "Ext loopback test (offline)");
3876 } else if (i == BNXT_IRQ_TEST_IDX) {
3877 strcpy(str, "Interrupt_test (offline)");
3878 } else {
3879 strlcpy(str, fw_str, ETH_GSTRING_LEN);
3880 strncat(str, " test", ETH_GSTRING_LEN - strlen(str));
3881 if (test_info->offline_mask & (1 << i))
3882 strncat(str, " (offline)",
3883 ETH_GSTRING_LEN - strlen(str));
3884 else
3885 strncat(str, " (online)",
3886 ETH_GSTRING_LEN - strlen(str));
3887 }
3888 }
3889
3890ethtool_init_exit:
3891 hwrm_req_drop(bp, req);
3892}
3893
3894static void bnxt_get_eth_phy_stats(struct net_device *dev,
3895 struct ethtool_eth_phy_stats *phy_stats)
3896{
3897 struct bnxt *bp = netdev_priv(dev);
3898 u64 *rx;
3899
3900 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS_EXT))
3901 return;
3902
3903 rx = bp->rx_port_stats_ext.sw_stats;
3904 phy_stats->SymbolErrorDuringCarrier =
3905 *(rx + BNXT_RX_STATS_EXT_OFFSET(rx_pcs_symbol_err));
3906}
3907
3908static void bnxt_get_eth_mac_stats(struct net_device *dev,
3909 struct ethtool_eth_mac_stats *mac_stats)
3910{
3911 struct bnxt *bp = netdev_priv(dev);
3912 u64 *rx, *tx;
3913
3914 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS))
3915 return;
3916
3917 rx = bp->port_stats.sw_stats;
3918 tx = bp->port_stats.sw_stats + BNXT_TX_PORT_STATS_BYTE_OFFSET / 8;
3919
3920 mac_stats->FramesReceivedOK =
3921 BNXT_GET_RX_PORT_STATS64(rx, rx_good_frames);
3922 mac_stats->FramesTransmittedOK =
3923 BNXT_GET_TX_PORT_STATS64(tx, tx_good_frames);
3924 mac_stats->FrameCheckSequenceErrors =
3925 BNXT_GET_RX_PORT_STATS64(rx, rx_fcs_err_frames);
3926 mac_stats->AlignmentErrors =
3927 BNXT_GET_RX_PORT_STATS64(rx, rx_align_err_frames);
3928 mac_stats->OutOfRangeLengthField =
3929 BNXT_GET_RX_PORT_STATS64(rx, rx_oor_len_frames);
3930}
3931
3932static void bnxt_get_eth_ctrl_stats(struct net_device *dev,
3933 struct ethtool_eth_ctrl_stats *ctrl_stats)
3934{
3935 struct bnxt *bp = netdev_priv(dev);
3936 u64 *rx;
3937
3938 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS))
3939 return;
3940
3941 rx = bp->port_stats.sw_stats;
3942 ctrl_stats->MACControlFramesReceived =
3943 BNXT_GET_RX_PORT_STATS64(rx, rx_ctrl_frames);
3944}
3945
3946static const struct ethtool_rmon_hist_range bnxt_rmon_ranges[] = {
3947 { 0, 64 },
3948 { 65, 127 },
3949 { 128, 255 },
3950 { 256, 511 },
3951 { 512, 1023 },
3952 { 1024, 1518 },
3953 { 1519, 2047 },
3954 { 2048, 4095 },
3955 { 4096, 9216 },
3956 { 9217, 16383 },
3957 {}
3958};
3959
3960static void bnxt_get_rmon_stats(struct net_device *dev,
3961 struct ethtool_rmon_stats *rmon_stats,
3962 const struct ethtool_rmon_hist_range **ranges)
3963{
3964 struct bnxt *bp = netdev_priv(dev);
3965 u64 *rx, *tx;
3966
3967 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS))
3968 return;
3969
3970 rx = bp->port_stats.sw_stats;
3971 tx = bp->port_stats.sw_stats + BNXT_TX_PORT_STATS_BYTE_OFFSET / 8;
3972
3973 rmon_stats->jabbers =
3974 BNXT_GET_RX_PORT_STATS64(rx, rx_jbr_frames);
3975 rmon_stats->oversize_pkts =
3976 BNXT_GET_RX_PORT_STATS64(rx, rx_ovrsz_frames);
3977 rmon_stats->undersize_pkts =
3978 BNXT_GET_RX_PORT_STATS64(rx, rx_undrsz_frames);
3979
3980 rmon_stats->hist[0] = BNXT_GET_RX_PORT_STATS64(rx, rx_64b_frames);
3981 rmon_stats->hist[1] = BNXT_GET_RX_PORT_STATS64(rx, rx_65b_127b_frames);
3982 rmon_stats->hist[2] = BNXT_GET_RX_PORT_STATS64(rx, rx_128b_255b_frames);
3983 rmon_stats->hist[3] = BNXT_GET_RX_PORT_STATS64(rx, rx_256b_511b_frames);
3984 rmon_stats->hist[4] =
3985 BNXT_GET_RX_PORT_STATS64(rx, rx_512b_1023b_frames);
3986 rmon_stats->hist[5] =
3987 BNXT_GET_RX_PORT_STATS64(rx, rx_1024b_1518b_frames);
3988 rmon_stats->hist[6] =
3989 BNXT_GET_RX_PORT_STATS64(rx, rx_1519b_2047b_frames);
3990 rmon_stats->hist[7] =
3991 BNXT_GET_RX_PORT_STATS64(rx, rx_2048b_4095b_frames);
3992 rmon_stats->hist[8] =
3993 BNXT_GET_RX_PORT_STATS64(rx, rx_4096b_9216b_frames);
3994 rmon_stats->hist[9] =
3995 BNXT_GET_RX_PORT_STATS64(rx, rx_9217b_16383b_frames);
3996
3997 rmon_stats->hist_tx[0] =
3998 BNXT_GET_TX_PORT_STATS64(tx, tx_64b_frames);
3999 rmon_stats->hist_tx[1] =
4000 BNXT_GET_TX_PORT_STATS64(tx, tx_65b_127b_frames);
4001 rmon_stats->hist_tx[2] =
4002 BNXT_GET_TX_PORT_STATS64(tx, tx_128b_255b_frames);
4003 rmon_stats->hist_tx[3] =
4004 BNXT_GET_TX_PORT_STATS64(tx, tx_256b_511b_frames);
4005 rmon_stats->hist_tx[4] =
4006 BNXT_GET_TX_PORT_STATS64(tx, tx_512b_1023b_frames);
4007 rmon_stats->hist_tx[5] =
4008 BNXT_GET_TX_PORT_STATS64(tx, tx_1024b_1518b_frames);
4009 rmon_stats->hist_tx[6] =
4010 BNXT_GET_TX_PORT_STATS64(tx, tx_1519b_2047b_frames);
4011 rmon_stats->hist_tx[7] =
4012 BNXT_GET_TX_PORT_STATS64(tx, tx_2048b_4095b_frames);
4013 rmon_stats->hist_tx[8] =
4014 BNXT_GET_TX_PORT_STATS64(tx, tx_4096b_9216b_frames);
4015 rmon_stats->hist_tx[9] =
4016 BNXT_GET_TX_PORT_STATS64(tx, tx_9217b_16383b_frames);
4017
4018 *ranges = bnxt_rmon_ranges;
4019}
4020
4021void bnxt_ethtool_free(struct bnxt *bp)
4022{
4023 kfree(bp->test_info);
4024 bp->test_info = NULL;
4025}
4026
4027const struct ethtool_ops bnxt_ethtool_ops = {
4028 .supported_coalesce_params = ETHTOOL_COALESCE_USECS |
4029 ETHTOOL_COALESCE_MAX_FRAMES |
4030 ETHTOOL_COALESCE_USECS_IRQ |
4031 ETHTOOL_COALESCE_MAX_FRAMES_IRQ |
4032 ETHTOOL_COALESCE_STATS_BLOCK_USECS |
4033 ETHTOOL_COALESCE_USE_ADAPTIVE_RX |
4034 ETHTOOL_COALESCE_USE_CQE,
4035 .get_link_ksettings = bnxt_get_link_ksettings,
4036 .set_link_ksettings = bnxt_set_link_ksettings,
4037 .get_fec_stats = bnxt_get_fec_stats,
4038 .get_fecparam = bnxt_get_fecparam,
4039 .set_fecparam = bnxt_set_fecparam,
4040 .get_pause_stats = bnxt_get_pause_stats,
4041 .get_pauseparam = bnxt_get_pauseparam,
4042 .set_pauseparam = bnxt_set_pauseparam,
4043 .get_drvinfo = bnxt_get_drvinfo,
4044 .get_regs_len = bnxt_get_regs_len,
4045 .get_regs = bnxt_get_regs,
4046 .get_wol = bnxt_get_wol,
4047 .set_wol = bnxt_set_wol,
4048 .get_coalesce = bnxt_get_coalesce,
4049 .set_coalesce = bnxt_set_coalesce,
4050 .get_msglevel = bnxt_get_msglevel,
4051 .set_msglevel = bnxt_set_msglevel,
4052 .get_sset_count = bnxt_get_sset_count,
4053 .get_strings = bnxt_get_strings,
4054 .get_ethtool_stats = bnxt_get_ethtool_stats,
4055 .set_ringparam = bnxt_set_ringparam,
4056 .get_ringparam = bnxt_get_ringparam,
4057 .get_channels = bnxt_get_channels,
4058 .set_channels = bnxt_set_channels,
4059 .get_rxnfc = bnxt_get_rxnfc,
4060 .set_rxnfc = bnxt_set_rxnfc,
4061 .get_rxfh_indir_size = bnxt_get_rxfh_indir_size,
4062 .get_rxfh_key_size = bnxt_get_rxfh_key_size,
4063 .get_rxfh = bnxt_get_rxfh,
4064 .set_rxfh = bnxt_set_rxfh,
4065 .flash_device = bnxt_flash_device,
4066 .get_eeprom_len = bnxt_get_eeprom_len,
4067 .get_eeprom = bnxt_get_eeprom,
4068 .set_eeprom = bnxt_set_eeprom,
4069 .get_link = bnxt_get_link,
4070 .get_eee = bnxt_get_eee,
4071 .set_eee = bnxt_set_eee,
4072 .get_module_info = bnxt_get_module_info,
4073 .get_module_eeprom = bnxt_get_module_eeprom,
4074 .nway_reset = bnxt_nway_reset,
4075 .set_phys_id = bnxt_set_phys_id,
4076 .self_test = bnxt_self_test,
4077 .get_ts_info = bnxt_get_ts_info,
4078 .reset = bnxt_reset,
4079 .set_dump = bnxt_set_dump,
4080 .get_dump_flag = bnxt_get_dump_flag,
4081 .get_dump_data = bnxt_get_dump_data,
4082 .get_eth_phy_stats = bnxt_get_eth_phy_stats,
4083 .get_eth_mac_stats = bnxt_get_eth_mac_stats,
4084 .get_eth_ctrl_stats = bnxt_get_eth_ctrl_stats,
4085 .get_rmon_stats = bnxt_get_rmon_stats,
4086};
4087
