1
2
3
4#ifndef __HCLGE_COMM_CMD_H
5#define __HCLGE_COMM_CMD_H
6#include <linux/types.h>
7
8#include "hnae3.h"
9
10#define HCLGE_COMM_CMD_FLAG_IN BIT(0)
11#define HCLGE_COMM_CMD_FLAG_NEXT BIT(2)
12#define HCLGE_COMM_CMD_FLAG_WR BIT(3)
13#define HCLGE_COMM_CMD_FLAG_NO_INTR BIT(4)
14
15#define HCLGE_COMM_SEND_SYNC(flag) \
16 ((flag) & HCLGE_COMM_CMD_FLAG_NO_INTR)
17
18#define HCLGE_COMM_LINK_EVENT_REPORT_EN_B 0
19#define HCLGE_COMM_NCSI_ERROR_REPORT_EN_B 1
20#define HCLGE_COMM_PHY_IMP_EN_B 2
21#define HCLGE_COMM_MAC_STATS_EXT_EN_B 3
22#define HCLGE_COMM_SYNC_RX_RING_HEAD_EN_B 4
23
24#define hclge_comm_dev_phy_imp_supported(ae_dev) \
25 test_bit(HNAE3_DEV_SUPPORT_PHY_IMP_B, (ae_dev)->caps)
26
27#define HCLGE_COMM_TYPE_CRQ 0
28#define HCLGE_COMM_TYPE_CSQ 1
29
30#define HCLGE_COMM_CMDQ_CLEAR_WAIT_TIME 200
31
32
33#define HCLGE_COMM_NIC_CSQ_BASEADDR_L_REG 0x27000
34#define HCLGE_COMM_NIC_CSQ_BASEADDR_H_REG 0x27004
35#define HCLGE_COMM_NIC_CSQ_DEPTH_REG 0x27008
36#define HCLGE_COMM_NIC_CSQ_TAIL_REG 0x27010
37#define HCLGE_COMM_NIC_CSQ_HEAD_REG 0x27014
38#define HCLGE_COMM_NIC_CRQ_BASEADDR_L_REG 0x27018
39#define HCLGE_COMM_NIC_CRQ_BASEADDR_H_REG 0x2701C
40#define HCLGE_COMM_NIC_CRQ_DEPTH_REG 0x27020
41#define HCLGE_COMM_NIC_CRQ_TAIL_REG 0x27024
42#define HCLGE_COMM_NIC_CRQ_HEAD_REG 0x27028
43
44#define HCLGE_COMM_VECTOR0_CMDQ_SRC_REG 0x27100
45
46#define HCLGE_COMM_VECTOR0_CMDQ_STATE_REG 0x27104
47#define HCLGE_COMM_CMDQ_INTR_EN_REG 0x27108
48#define HCLGE_COMM_CMDQ_INTR_GEN_REG 0x2710C
49#define HCLGE_COMM_CMDQ_INTR_STS_REG 0x27104
50
51
52#define HCLGE_COMM_NIC_SW_RST_RDY_B 16
53#define HCLGE_COMM_NIC_SW_RST_RDY BIT(HCLGE_COMM_NIC_SW_RST_RDY_B)
54#define HCLGE_COMM_NIC_CMQ_DESC_NUM_S 3
55#define HCLGE_COMM_NIC_CMQ_DESC_NUM 1024
56#define HCLGE_COMM_CMDQ_TX_TIMEOUT 30000
57
58enum hclge_opcode_type {
59
60 HCLGE_OPC_QUERY_FW_VER = 0x0001,
61 HCLGE_OPC_CFG_RST_TRIGGER = 0x0020,
62 HCLGE_OPC_GBL_RST_STATUS = 0x0021,
63 HCLGE_OPC_QUERY_FUNC_STATUS = 0x0022,
64 HCLGE_OPC_QUERY_PF_RSRC = 0x0023,
65 HCLGE_OPC_QUERY_VF_RSRC = 0x0024,
66 HCLGE_OPC_GET_CFG_PARAM = 0x0025,
67 HCLGE_OPC_PF_RST_DONE = 0x0026,
68 HCLGE_OPC_QUERY_VF_RST_RDY = 0x0027,
69
70 HCLGE_OPC_STATS_64_BIT = 0x0030,
71 HCLGE_OPC_STATS_32_BIT = 0x0031,
72 HCLGE_OPC_STATS_MAC = 0x0032,
73 HCLGE_OPC_QUERY_MAC_REG_NUM = 0x0033,
74 HCLGE_OPC_STATS_MAC_ALL = 0x0034,
75
76 HCLGE_OPC_QUERY_REG_NUM = 0x0040,
77 HCLGE_OPC_QUERY_32_BIT_REG = 0x0041,
78 HCLGE_OPC_QUERY_64_BIT_REG = 0x0042,
79 HCLGE_OPC_DFX_BD_NUM = 0x0043,
80 HCLGE_OPC_DFX_BIOS_COMMON_REG = 0x0044,
81 HCLGE_OPC_DFX_SSU_REG_0 = 0x0045,
82 HCLGE_OPC_DFX_SSU_REG_1 = 0x0046,
83 HCLGE_OPC_DFX_IGU_EGU_REG = 0x0047,
84 HCLGE_OPC_DFX_RPU_REG_0 = 0x0048,
85 HCLGE_OPC_DFX_RPU_REG_1 = 0x0049,
86 HCLGE_OPC_DFX_NCSI_REG = 0x004A,
87 HCLGE_OPC_DFX_RTC_REG = 0x004B,
88 HCLGE_OPC_DFX_PPP_REG = 0x004C,
89 HCLGE_OPC_DFX_RCB_REG = 0x004D,
90 HCLGE_OPC_DFX_TQP_REG = 0x004E,
91 HCLGE_OPC_DFX_SSU_REG_2 = 0x004F,
92
93 HCLGE_OPC_QUERY_DEV_SPECS = 0x0050,
94
95
96 HCLGE_OPC_CONFIG_MAC_MODE = 0x0301,
97 HCLGE_OPC_CONFIG_AN_MODE = 0x0304,
98 HCLGE_OPC_QUERY_LINK_STATUS = 0x0307,
99 HCLGE_OPC_CONFIG_MAX_FRM_SIZE = 0x0308,
100 HCLGE_OPC_CONFIG_SPEED_DUP = 0x0309,
101 HCLGE_OPC_QUERY_MAC_TNL_INT = 0x0310,
102 HCLGE_OPC_MAC_TNL_INT_EN = 0x0311,
103 HCLGE_OPC_CLEAR_MAC_TNL_INT = 0x0312,
104 HCLGE_OPC_COMMON_LOOPBACK = 0x0315,
105 HCLGE_OPC_CONFIG_FEC_MODE = 0x031A,
106 HCLGE_OPC_QUERY_ROH_TYPE_INFO = 0x0389,
107
108
109 HCLGE_OPC_PTP_INT_EN = 0x0501,
110 HCLGE_OPC_PTP_MODE_CFG = 0x0507,
111
112
113 HCLGE_OPC_CFG_MAC_PAUSE_EN = 0x0701,
114 HCLGE_OPC_CFG_PFC_PAUSE_EN = 0x0702,
115 HCLGE_OPC_CFG_MAC_PARA = 0x0703,
116 HCLGE_OPC_CFG_PFC_PARA = 0x0704,
117 HCLGE_OPC_QUERY_MAC_TX_PKT_CNT = 0x0705,
118 HCLGE_OPC_QUERY_MAC_RX_PKT_CNT = 0x0706,
119 HCLGE_OPC_QUERY_PFC_TX_PKT_CNT = 0x0707,
120 HCLGE_OPC_QUERY_PFC_RX_PKT_CNT = 0x0708,
121 HCLGE_OPC_PRI_TO_TC_MAPPING = 0x0709,
122 HCLGE_OPC_QOS_MAP = 0x070A,
123
124
125 HCLGE_OPC_TM_PG_TO_PRI_LINK = 0x0804,
126 HCLGE_OPC_TM_QS_TO_PRI_LINK = 0x0805,
127 HCLGE_OPC_TM_NQ_TO_QS_LINK = 0x0806,
128 HCLGE_OPC_TM_RQ_TO_QS_LINK = 0x0807,
129 HCLGE_OPC_TM_PORT_WEIGHT = 0x0808,
130 HCLGE_OPC_TM_PG_WEIGHT = 0x0809,
131 HCLGE_OPC_TM_QS_WEIGHT = 0x080A,
132 HCLGE_OPC_TM_PRI_WEIGHT = 0x080B,
133 HCLGE_OPC_TM_PRI_C_SHAPPING = 0x080C,
134 HCLGE_OPC_TM_PRI_P_SHAPPING = 0x080D,
135 HCLGE_OPC_TM_PG_C_SHAPPING = 0x080E,
136 HCLGE_OPC_TM_PG_P_SHAPPING = 0x080F,
137 HCLGE_OPC_TM_PORT_SHAPPING = 0x0810,
138 HCLGE_OPC_TM_PG_SCH_MODE_CFG = 0x0812,
139 HCLGE_OPC_TM_PRI_SCH_MODE_CFG = 0x0813,
140 HCLGE_OPC_TM_QS_SCH_MODE_CFG = 0x0814,
141 HCLGE_OPC_TM_BP_TO_QSET_MAPPING = 0x0815,
142 HCLGE_OPC_TM_NODES = 0x0816,
143 HCLGE_OPC_ETS_TC_WEIGHT = 0x0843,
144 HCLGE_OPC_QSET_DFX_STS = 0x0844,
145 HCLGE_OPC_PRI_DFX_STS = 0x0845,
146 HCLGE_OPC_PG_DFX_STS = 0x0846,
147 HCLGE_OPC_PORT_DFX_STS = 0x0847,
148 HCLGE_OPC_SCH_NQ_CNT = 0x0848,
149 HCLGE_OPC_SCH_RQ_CNT = 0x0849,
150 HCLGE_OPC_TM_INTERNAL_STS = 0x0850,
151 HCLGE_OPC_TM_INTERNAL_CNT = 0x0851,
152 HCLGE_OPC_TM_INTERNAL_STS_1 = 0x0852,
153
154
155 HCLGE_OPC_TX_BUFF_ALLOC = 0x0901,
156 HCLGE_OPC_RX_PRIV_BUFF_ALLOC = 0x0902,
157 HCLGE_OPC_RX_PRIV_WL_ALLOC = 0x0903,
158 HCLGE_OPC_RX_COM_THRD_ALLOC = 0x0904,
159 HCLGE_OPC_RX_COM_WL_ALLOC = 0x0905,
160 HCLGE_OPC_RX_GBL_PKT_CNT = 0x0906,
161
162
163 HCLGE_OPC_SET_TQP_MAP = 0x0A01,
164
165
166 HCLGE_OPC_CFG_TX_QUEUE = 0x0B01,
167 HCLGE_OPC_QUERY_TX_POINTER = 0x0B02,
168 HCLGE_OPC_QUERY_TX_STATS = 0x0B03,
169 HCLGE_OPC_TQP_TX_QUEUE_TC = 0x0B04,
170 HCLGE_OPC_CFG_RX_QUEUE = 0x0B11,
171 HCLGE_OPC_QUERY_RX_POINTER = 0x0B12,
172 HCLGE_OPC_QUERY_RX_STATS = 0x0B13,
173 HCLGE_OPC_STASH_RX_QUEUE_LRO = 0x0B16,
174 HCLGE_OPC_CFG_RX_QUEUE_LRO = 0x0B17,
175 HCLGE_OPC_CFG_COM_TQP_QUEUE = 0x0B20,
176 HCLGE_OPC_RESET_TQP_QUEUE = 0x0B22,
177
178
179 HCLGE_OPC_PPU_PF_OTHER_INT_DFX = 0x0B4A,
180
181
182 HCLGE_OPC_TSO_GENERIC_CONFIG = 0x0C01,
183 HCLGE_OPC_GRO_GENERIC_CONFIG = 0x0C10,
184
185
186 HCLGE_OPC_RSS_GENERIC_CONFIG = 0x0D01,
187 HCLGE_OPC_RSS_INDIR_TABLE = 0x0D07,
188 HCLGE_OPC_RSS_TC_MODE = 0x0D08,
189 HCLGE_OPC_RSS_INPUT_TUPLE = 0x0D02,
190
191
192 HCLGE_OPC_CFG_PROMISC_MODE = 0x0E01,
193
194
195 HCLGE_OPC_VLAN_PORT_TX_CFG = 0x0F01,
196 HCLGE_OPC_VLAN_PORT_RX_CFG = 0x0F02,
197
198
199 HCLGE_OPC_ADD_RING_TO_VECTOR = 0x1503,
200 HCLGE_OPC_DEL_RING_TO_VECTOR = 0x1504,
201
202
203 HCLGE_OPC_MAC_VLAN_ADD = 0x1000,
204 HCLGE_OPC_MAC_VLAN_REMOVE = 0x1001,
205 HCLGE_OPC_MAC_VLAN_TYPE_ID = 0x1002,
206 HCLGE_OPC_MAC_VLAN_INSERT = 0x1003,
207 HCLGE_OPC_MAC_VLAN_ALLOCATE = 0x1004,
208 HCLGE_OPC_MAC_ETHTYPE_ADD = 0x1010,
209 HCLGE_OPC_MAC_ETHTYPE_REMOVE = 0x1011,
210
211
212 HCLGE_OPC_MAC_VLAN_SWITCH_PARAM = 0x1033,
213
214
215 HCLGE_OPC_VLAN_FILTER_CTRL = 0x1100,
216 HCLGE_OPC_VLAN_FILTER_PF_CFG = 0x1101,
217 HCLGE_OPC_VLAN_FILTER_VF_CFG = 0x1102,
218 HCLGE_OPC_PORT_VLAN_BYPASS = 0x1103,
219
220
221 HCLGE_OPC_FD_MODE_CTRL = 0x1200,
222 HCLGE_OPC_FD_GET_ALLOCATION = 0x1201,
223 HCLGE_OPC_FD_KEY_CONFIG = 0x1202,
224 HCLGE_OPC_FD_TCAM_OP = 0x1203,
225 HCLGE_OPC_FD_AD_OP = 0x1204,
226 HCLGE_OPC_FD_CNT_OP = 0x1205,
227 HCLGE_OPC_FD_USER_DEF_OP = 0x1207,
228 HCLGE_OPC_FD_QB_CTRL = 0x1210,
229 HCLGE_OPC_FD_QB_AD_OP = 0x1211,
230
231
232 HCLGE_OPC_MDIO_CONFIG = 0x1900,
233
234
235 HCLGE_OPC_QCN_MOD_CFG = 0x1A01,
236 HCLGE_OPC_QCN_GRP_TMPLT_CFG = 0x1A02,
237 HCLGE_OPC_QCN_SHAPPING_CFG = 0x1A03,
238 HCLGE_OPC_QCN_SHAPPING_BS_CFG = 0x1A04,
239 HCLGE_OPC_QCN_QSET_LINK_CFG = 0x1A05,
240 HCLGE_OPC_QCN_RP_STATUS_GET = 0x1A06,
241 HCLGE_OPC_QCN_AJUST_INIT = 0x1A07,
242 HCLGE_OPC_QCN_DFX_CNT_STATUS = 0x1A08,
243
244
245 HCLGEVF_OPC_MBX_PF_TO_VF = 0x2000,
246 HCLGEVF_OPC_MBX_VF_TO_PF = 0x2001,
247
248
249 HCLGE_OPC_LED_STATUS_CFG = 0xB000,
250
251
252 HCLGE_OPC_CLEAR_HW_RESOURCE = 0x700B,
253
254
255 HCLGE_OPC_QUERY_NCL_CONFIG = 0x7011,
256
257
258 HCLGE_OPC_IMP_STATS_BD = 0x7012,
259 HCLGE_OPC_IMP_STATS_INFO = 0x7013,
260 HCLGE_OPC_IMP_COMPAT_CFG = 0x701A,
261
262
263 HCLGE_OPC_GET_SFP_EEPROM = 0x7100,
264 HCLGE_OPC_GET_SFP_EXIST = 0x7101,
265 HCLGE_OPC_GET_SFP_INFO = 0x7104,
266
267
268 HCLGE_MAC_COMMON_INT_EN = 0x030E,
269 HCLGE_TM_SCH_ECC_INT_EN = 0x0829,
270 HCLGE_SSU_ECC_INT_CMD = 0x0989,
271 HCLGE_SSU_COMMON_INT_CMD = 0x098C,
272 HCLGE_PPU_MPF_ECC_INT_CMD = 0x0B40,
273 HCLGE_PPU_MPF_OTHER_INT_CMD = 0x0B41,
274 HCLGE_PPU_PF_OTHER_INT_CMD = 0x0B42,
275 HCLGE_COMMON_ECC_INT_CFG = 0x1505,
276 HCLGE_QUERY_RAS_INT_STS_BD_NUM = 0x1510,
277 HCLGE_QUERY_CLEAR_MPF_RAS_INT = 0x1511,
278 HCLGE_QUERY_CLEAR_PF_RAS_INT = 0x1512,
279 HCLGE_QUERY_MSIX_INT_STS_BD_NUM = 0x1513,
280 HCLGE_QUERY_CLEAR_ALL_MPF_MSIX_INT = 0x1514,
281 HCLGE_QUERY_CLEAR_ALL_PF_MSIX_INT = 0x1515,
282 HCLGE_QUERY_ALL_ERR_BD_NUM = 0x1516,
283 HCLGE_QUERY_ALL_ERR_INFO = 0x1517,
284 HCLGE_CONFIG_ROCEE_RAS_INT_EN = 0x1580,
285 HCLGE_QUERY_CLEAR_ROCEE_RAS_INT = 0x1581,
286 HCLGE_ROCEE_PF_RAS_INT_CMD = 0x1584,
287 HCLGE_QUERY_ROCEE_ECC_RAS_INFO_CMD = 0x1585,
288 HCLGE_QUERY_ROCEE_AXI_RAS_INFO_CMD = 0x1586,
289 HCLGE_IGU_EGU_TNL_INT_EN = 0x1803,
290 HCLGE_IGU_COMMON_INT_EN = 0x1806,
291 HCLGE_TM_QCN_MEM_INT_CFG = 0x1A14,
292 HCLGE_PPP_CMD0_INT_CMD = 0x2100,
293 HCLGE_PPP_CMD1_INT_CMD = 0x2101,
294 HCLGE_MAC_ETHERTYPE_IDX_RD = 0x2105,
295 HCLGE_NCSI_INT_EN = 0x2401,
296
297
298 HCLGE_OPC_MAC_ADDR_CHECK = 0x9004,
299
300
301 HCLGE_OPC_PHY_LINK_KSETTING = 0x7025,
302 HCLGE_OPC_PHY_REG = 0x7026,
303
304
305 HCLGE_OPC_QUERY_LINK_DIAGNOSIS = 0x702A,
306};
307
308enum hclge_comm_cmd_return_status {
309 HCLGE_COMM_CMD_EXEC_SUCCESS = 0,
310 HCLGE_COMM_CMD_NO_AUTH = 1,
311 HCLGE_COMM_CMD_NOT_SUPPORTED = 2,
312 HCLGE_COMM_CMD_QUEUE_FULL = 3,
313 HCLGE_COMM_CMD_NEXT_ERR = 4,
314 HCLGE_COMM_CMD_UNEXE_ERR = 5,
315 HCLGE_COMM_CMD_PARA_ERR = 6,
316 HCLGE_COMM_CMD_RESULT_ERR = 7,
317 HCLGE_COMM_CMD_TIMEOUT = 8,
318 HCLGE_COMM_CMD_HILINK_ERR = 9,
319 HCLGE_COMM_CMD_QUEUE_ILLEGAL = 10,
320 HCLGE_COMM_CMD_INVALID = 11,
321};
322
323enum HCLGE_COMM_CAP_BITS {
324 HCLGE_COMM_CAP_UDP_GSO_B,
325 HCLGE_COMM_CAP_QB_B,
326 HCLGE_COMM_CAP_FD_FORWARD_TC_B,
327 HCLGE_COMM_CAP_PTP_B,
328 HCLGE_COMM_CAP_INT_QL_B,
329 HCLGE_COMM_CAP_HW_TX_CSUM_B,
330 HCLGE_COMM_CAP_TX_PUSH_B,
331 HCLGE_COMM_CAP_PHY_IMP_B,
332 HCLGE_COMM_CAP_TQP_TXRX_INDEP_B,
333 HCLGE_COMM_CAP_HW_PAD_B,
334 HCLGE_COMM_CAP_STASH_B,
335 HCLGE_COMM_CAP_UDP_TUNNEL_CSUM_B,
336 HCLGE_COMM_CAP_RAS_IMP_B = 12,
337 HCLGE_COMM_CAP_FEC_B = 13,
338 HCLGE_COMM_CAP_PAUSE_B = 14,
339 HCLGE_COMM_CAP_RXD_ADV_LAYOUT_B = 15,
340 HCLGE_COMM_CAP_PORT_VLAN_BYPASS_B = 17,
341 HCLGE_COMM_CAP_CQ_B = 18,
342};
343
344enum HCLGE_COMM_API_CAP_BITS {
345 HCLGE_COMM_API_CAP_FLEX_RSS_TBL_B,
346};
347
348
349struct hclge_comm_caps_bit_map {
350 u16 imp_bit;
351 u16 local_bit;
352};
353
354struct hclge_comm_firmware_compat_cmd {
355 __le32 compat;
356 u8 rsv[20];
357};
358
359enum hclge_comm_cmd_state {
360 HCLGE_COMM_STATE_CMD_DISABLE,
361};
362
363struct hclge_comm_errcode {
364 u32 imp_errcode;
365 int common_errno;
366};
367
368#define HCLGE_COMM_QUERY_CAP_LENGTH 3
369struct hclge_comm_query_version_cmd {
370 __le32 firmware;
371 __le32 hardware;
372 __le32 api_caps;
373 __le32 caps[HCLGE_COMM_QUERY_CAP_LENGTH];
374};
375
376#define HCLGE_DESC_DATA_LEN 6
377struct hclge_desc {
378 __le16 opcode;
379 __le16 flag;
380 __le16 retval;
381 __le16 rsv;
382 __le32 data[HCLGE_DESC_DATA_LEN];
383};
384
385struct hclge_comm_cmq_ring {
386 dma_addr_t desc_dma_addr;
387 struct hclge_desc *desc;
388 struct pci_dev *pdev;
389 u32 head;
390 u32 tail;
391
392 u16 buf_size;
393 u16 desc_num;
394 int next_to_use;
395 int next_to_clean;
396 u8 ring_type;
397 spinlock_t lock;
398};
399
400enum hclge_comm_cmd_status {
401 HCLGE_COMM_STATUS_SUCCESS = 0,
402 HCLGE_COMM_ERR_CSQ_FULL = -1,
403 HCLGE_COMM_ERR_CSQ_TIMEOUT = -2,
404 HCLGE_COMM_ERR_CSQ_ERROR = -3,
405};
406
407struct hclge_comm_cmq {
408 struct hclge_comm_cmq_ring csq;
409 struct hclge_comm_cmq_ring crq;
410 u16 tx_timeout;
411 enum hclge_comm_cmd_status last_status;
412};
413
414struct hclge_comm_hw {
415 void __iomem *io_base;
416 void __iomem *mem_base;
417 struct hclge_comm_cmq cmq;
418 unsigned long comm_state;
419};
420
421static inline void hclge_comm_write_reg(void __iomem *base, u32 reg, u32 value)
422{
423 writel(value, base + reg);
424}
425
426static inline u32 hclge_comm_read_reg(u8 __iomem *base, u32 reg)
427{
428 u8 __iomem *reg_addr = READ_ONCE(base);
429
430 return readl(reg_addr + reg);
431}
432
433#define hclge_comm_write_dev(a, reg, value) \
434 hclge_comm_write_reg((a)->io_base, reg, value)
435#define hclge_comm_read_dev(a, reg) \
436 hclge_comm_read_reg((a)->io_base, reg)
437
438void hclge_comm_cmd_init_regs(struct hclge_comm_hw *hw);
439int hclge_comm_cmd_query_version_and_capability(struct hnae3_ae_dev *ae_dev,
440 struct hclge_comm_hw *hw,
441 u32 *fw_version, bool is_pf);
442int hclge_comm_alloc_cmd_queue(struct hclge_comm_hw *hw, int ring_type);
443int hclge_comm_cmd_send(struct hclge_comm_hw *hw, struct hclge_desc *desc,
444 int num);
445void hclge_comm_cmd_reuse_desc(struct hclge_desc *desc, bool is_read);
446int hclge_comm_firmware_compat_config(struct hnae3_ae_dev *ae_dev,
447 struct hclge_comm_hw *hw, bool en);
448void hclge_comm_free_cmd_desc(struct hclge_comm_cmq_ring *ring);
449void hclge_comm_cmd_setup_basic_desc(struct hclge_desc *desc,
450 enum hclge_opcode_type opcode,
451 bool is_read);
452void hclge_comm_cmd_uninit(struct hnae3_ae_dev *ae_dev,
453 struct hclge_comm_hw *hw);
454int hclge_comm_cmd_queue_init(struct pci_dev *pdev, struct hclge_comm_hw *hw);
455int hclge_comm_cmd_init(struct hnae3_ae_dev *ae_dev, struct hclge_comm_hw *hw,
456 u32 *fw_version, bool is_pf,
457 unsigned long reset_pending);
458
459#endif
460
