1
2
3
4#include <linux/vmalloc.h>
5
6#include "ice_common.h"
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21static int
22ice_aq_read_nvm(struct ice_hw *hw, u16 module_typeid, u32 offset, u16 length,
23 void *data, bool last_command, bool read_shadow_ram,
24 struct ice_sq_cd *cd)
25{
26 struct ice_aq_desc desc;
27 struct ice_aqc_nvm *cmd;
28
29 cmd = &desc.params.nvm;
30
31 if (offset > ICE_AQC_NVM_MAX_OFFSET)
32 return -EINVAL;
33
34 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_nvm_read);
35
36 if (!read_shadow_ram && module_typeid == ICE_AQC_NVM_START_POINT)
37 cmd->cmd_flags |= ICE_AQC_NVM_FLASH_ONLY;
38
39
40 if (last_command)
41 cmd->cmd_flags |= ICE_AQC_NVM_LAST_CMD;
42 cmd->module_typeid = cpu_to_le16(module_typeid);
43 cmd->offset_low = cpu_to_le16(offset & 0xFFFF);
44 cmd->offset_high = (offset >> 16) & 0xFF;
45 cmd->length = cpu_to_le16(length);
46
47 return ice_aq_send_cmd(hw, &desc, data, length, cd);
48}
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65int
66ice_read_flat_nvm(struct ice_hw *hw, u32 offset, u32 *length, u8 *data,
67 bool read_shadow_ram)
68{
69 u32 inlen = *length;
70 u32 bytes_read = 0;
71 bool last_cmd;
72 int status;
73
74 *length = 0;
75
76
77 if (read_shadow_ram && ((offset + inlen) > (hw->flash.sr_words * 2u))) {
78 ice_debug(hw, ICE_DBG_NVM, "NVM error: requested offset is beyond Shadow RAM limit\n");
79 return -EINVAL;
80 }
81
82 do {
83 u32 read_size, sector_offset;
84
85
86
87
88
89
90 sector_offset = offset % ICE_AQ_MAX_BUF_LEN;
91 read_size = min_t(u32, ICE_AQ_MAX_BUF_LEN - sector_offset,
92 inlen - bytes_read);
93
94 last_cmd = !(bytes_read + read_size < inlen);
95
96 status = ice_aq_read_nvm(hw, ICE_AQC_NVM_START_POINT,
97 offset, read_size,
98 data + bytes_read, last_cmd,
99 read_shadow_ram, NULL);
100 if (status)
101 break;
102
103 bytes_read += read_size;
104 offset += read_size;
105 } while (!last_cmd);
106
107 *length = bytes_read;
108 return status;
109}
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124int
125ice_aq_update_nvm(struct ice_hw *hw, u16 module_typeid, u32 offset,
126 u16 length, void *data, bool last_command, u8 command_flags,
127 struct ice_sq_cd *cd)
128{
129 struct ice_aq_desc desc;
130 struct ice_aqc_nvm *cmd;
131
132 cmd = &desc.params.nvm;
133
134
135 if (offset & 0xFF000000)
136 return -EINVAL;
137
138 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_nvm_write);
139
140 cmd->cmd_flags |= command_flags;
141
142
143 if (last_command)
144 cmd->cmd_flags |= ICE_AQC_NVM_LAST_CMD;
145 cmd->module_typeid = cpu_to_le16(module_typeid);
146 cmd->offset_low = cpu_to_le16(offset & 0xFFFF);
147 cmd->offset_high = (offset >> 16) & 0xFF;
148 cmd->length = cpu_to_le16(length);
149
150 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD);
151
152 return ice_aq_send_cmd(hw, &desc, data, length, cd);
153}
154
155
156
157
158
159
160
161
162
163int ice_aq_erase_nvm(struct ice_hw *hw, u16 module_typeid, struct ice_sq_cd *cd)
164{
165 struct ice_aq_desc desc;
166 struct ice_aqc_nvm *cmd;
167
168 cmd = &desc.params.nvm;
169
170 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_nvm_erase);
171
172 cmd->module_typeid = cpu_to_le16(module_typeid);
173 cmd->length = cpu_to_le16(ICE_AQC_NVM_ERASE_LEN);
174 cmd->offset_low = 0;
175 cmd->offset_high = 0;
176
177 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
178}
179
180
181
182
183
184
185
186
187
188static int ice_read_sr_word_aq(struct ice_hw *hw, u16 offset, u16 *data)
189{
190 u32 bytes = sizeof(u16);
191 __le16 data_local;
192 int status;
193
194
195
196
197 status = ice_read_flat_nvm(hw, offset * sizeof(u16), &bytes,
198 (__force u8 *)&data_local, true);
199 if (status)
200 return status;
201
202 *data = le16_to_cpu(data_local);
203 return 0;
204}
205
206
207
208
209
210
211
212
213int ice_acquire_nvm(struct ice_hw *hw, enum ice_aq_res_access_type access)
214{
215 if (hw->flash.blank_nvm_mode)
216 return 0;
217
218 return ice_acquire_res(hw, ICE_NVM_RES_ID, access, ICE_NVM_TIMEOUT);
219}
220
221
222
223
224
225
226
227void ice_release_nvm(struct ice_hw *hw)
228{
229 if (hw->flash.blank_nvm_mode)
230 return;
231
232 ice_release_res(hw, ICE_NVM_RES_ID);
233}
234
235
236
237
238
239
240
241
242
243
244
245
246
247static u32 ice_get_flash_bank_offset(struct ice_hw *hw, enum ice_bank_select bank, u16 module)
248{
249 struct ice_bank_info *banks = &hw->flash.banks;
250 enum ice_flash_bank active_bank;
251 bool second_bank_active;
252 u32 offset, size;
253
254 switch (module) {
255 case ICE_SR_1ST_NVM_BANK_PTR:
256 offset = banks->nvm_ptr;
257 size = banks->nvm_size;
258 active_bank = banks->nvm_bank;
259 break;
260 case ICE_SR_1ST_OROM_BANK_PTR:
261 offset = banks->orom_ptr;
262 size = banks->orom_size;
263 active_bank = banks->orom_bank;
264 break;
265 case ICE_SR_NETLIST_BANK_PTR:
266 offset = banks->netlist_ptr;
267 size = banks->netlist_size;
268 active_bank = banks->netlist_bank;
269 break;
270 default:
271 ice_debug(hw, ICE_DBG_NVM, "Unexpected value for flash module: 0x%04x\n", module);
272 return 0;
273 }
274
275 switch (active_bank) {
276 case ICE_1ST_FLASH_BANK:
277 second_bank_active = false;
278 break;
279 case ICE_2ND_FLASH_BANK:
280 second_bank_active = true;
281 break;
282 default:
283 ice_debug(hw, ICE_DBG_NVM, "Unexpected value for active flash bank: %u\n",
284 active_bank);
285 return 0;
286 }
287
288
289
290
291
292 switch (bank) {
293 case ICE_ACTIVE_FLASH_BANK:
294 return offset + (second_bank_active ? size : 0);
295 case ICE_INACTIVE_FLASH_BANK:
296 return offset + (second_bank_active ? 0 : size);
297 }
298
299 ice_debug(hw, ICE_DBG_NVM, "Unexpected value for flash bank selection: %u\n", bank);
300 return 0;
301}
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320static int
321ice_read_flash_module(struct ice_hw *hw, enum ice_bank_select bank, u16 module,
322 u32 offset, u8 *data, u32 length)
323{
324 int status;
325 u32 start;
326
327 start = ice_get_flash_bank_offset(hw, bank, module);
328 if (!start) {
329 ice_debug(hw, ICE_DBG_NVM, "Unable to calculate flash bank offset for module 0x%04x\n",
330 module);
331 return -EINVAL;
332 }
333
334 status = ice_acquire_nvm(hw, ICE_RES_READ);
335 if (status)
336 return status;
337
338 status = ice_read_flat_nvm(hw, start + offset, &length, data, false);
339
340 ice_release_nvm(hw);
341
342 return status;
343}
344
345
346
347
348
349
350
351
352
353
354
355static int
356ice_read_nvm_module(struct ice_hw *hw, enum ice_bank_select bank, u32 offset, u16 *data)
357{
358 __le16 data_local;
359 int status;
360
361 status = ice_read_flash_module(hw, bank, ICE_SR_1ST_NVM_BANK_PTR, offset * sizeof(u16),
362 (__force u8 *)&data_local, sizeof(u16));
363 if (!status)
364 *data = le16_to_cpu(data_local);
365
366 return status;
367}
368
369
370
371
372
373
374
375
376
377
378
379static int
380ice_read_nvm_sr_copy(struct ice_hw *hw, enum ice_bank_select bank, u32 offset, u16 *data)
381{
382 return ice_read_nvm_module(hw, bank, ICE_NVM_SR_COPY_WORD_OFFSET + offset, data);
383}
384
385
386
387
388
389
390
391
392
393
394static int
395ice_read_netlist_module(struct ice_hw *hw, enum ice_bank_select bank, u32 offset, u16 *data)
396{
397 __le16 data_local;
398 int status;
399
400 status = ice_read_flash_module(hw, bank, ICE_SR_NETLIST_BANK_PTR, offset * sizeof(u16),
401 (__force u8 *)&data_local, sizeof(u16));
402 if (!status)
403 *data = le16_to_cpu(data_local);
404
405 return status;
406}
407
408
409
410
411
412
413
414
415
416int ice_read_sr_word(struct ice_hw *hw, u16 offset, u16 *data)
417{
418 int status;
419
420 status = ice_acquire_nvm(hw, ICE_RES_READ);
421 if (!status) {
422 status = ice_read_sr_word_aq(hw, offset, data);
423 ice_release_nvm(hw);
424 }
425
426 return status;
427}
428
429
430
431
432
433
434
435
436
437
438
439
440int
441ice_get_pfa_module_tlv(struct ice_hw *hw, u16 *module_tlv, u16 *module_tlv_len,
442 u16 module_type)
443{
444 u16 pfa_len, pfa_ptr;
445 u16 next_tlv;
446 int status;
447
448 status = ice_read_sr_word(hw, ICE_SR_PFA_PTR, &pfa_ptr);
449 if (status) {
450 ice_debug(hw, ICE_DBG_INIT, "Preserved Field Array pointer.\n");
451 return status;
452 }
453 status = ice_read_sr_word(hw, pfa_ptr, &pfa_len);
454 if (status) {
455 ice_debug(hw, ICE_DBG_INIT, "Failed to read PFA length.\n");
456 return status;
457 }
458
459
460
461 next_tlv = pfa_ptr + 1;
462 while (next_tlv < pfa_ptr + pfa_len) {
463 u16 tlv_sub_module_type;
464 u16 tlv_len;
465
466
467 status = ice_read_sr_word(hw, next_tlv, &tlv_sub_module_type);
468 if (status) {
469 ice_debug(hw, ICE_DBG_INIT, "Failed to read TLV type.\n");
470 break;
471 }
472
473 status = ice_read_sr_word(hw, next_tlv + 1, &tlv_len);
474 if (status) {
475 ice_debug(hw, ICE_DBG_INIT, "Failed to read TLV length.\n");
476 break;
477 }
478 if (tlv_sub_module_type == module_type) {
479 if (tlv_len) {
480 *module_tlv = next_tlv;
481 *module_tlv_len = tlv_len;
482 return 0;
483 }
484 return -EINVAL;
485 }
486
487
488
489 next_tlv = next_tlv + tlv_len + 2;
490 }
491
492 return -ENOENT;
493}
494
495
496
497
498
499
500
501
502
503int ice_read_pba_string(struct ice_hw *hw, u8 *pba_num, u32 pba_num_size)
504{
505 u16 pba_tlv, pba_tlv_len;
506 u16 pba_word, pba_size;
507 int status;
508 u16 i;
509
510 status = ice_get_pfa_module_tlv(hw, &pba_tlv, &pba_tlv_len,
511 ICE_SR_PBA_BLOCK_PTR);
512 if (status) {
513 ice_debug(hw, ICE_DBG_INIT, "Failed to read PBA Block TLV.\n");
514 return status;
515 }
516
517
518 status = ice_read_sr_word(hw, (pba_tlv + 2), &pba_size);
519 if (status) {
520 ice_debug(hw, ICE_DBG_INIT, "Failed to read PBA Section size.\n");
521 return status;
522 }
523
524 if (pba_tlv_len < pba_size) {
525 ice_debug(hw, ICE_DBG_INIT, "Invalid PBA Block TLV size.\n");
526 return -EINVAL;
527 }
528
529
530
531
532 pba_size--;
533 if (pba_num_size < (((u32)pba_size * 2) + 1)) {
534 ice_debug(hw, ICE_DBG_INIT, "Buffer too small for PBA data.\n");
535 return -EINVAL;
536 }
537
538 for (i = 0; i < pba_size; i++) {
539 status = ice_read_sr_word(hw, (pba_tlv + 2 + 1) + i, &pba_word);
540 if (status) {
541 ice_debug(hw, ICE_DBG_INIT, "Failed to read PBA Block word %d.\n", i);
542 return status;
543 }
544
545 pba_num[(i * 2)] = (pba_word >> 8) & 0xFF;
546 pba_num[(i * 2) + 1] = pba_word & 0xFF;
547 }
548 pba_num[(pba_size * 2)] = '\0';
549
550 return status;
551}
552
553
554
555
556
557
558
559
560
561
562static int
563ice_get_nvm_ver_info(struct ice_hw *hw, enum ice_bank_select bank, struct ice_nvm_info *nvm)
564{
565 u16 eetrack_lo, eetrack_hi, ver;
566 int status;
567
568 status = ice_read_nvm_sr_copy(hw, bank, ICE_SR_NVM_DEV_STARTER_VER, &ver);
569 if (status) {
570 ice_debug(hw, ICE_DBG_NVM, "Failed to read DEV starter version.\n");
571 return status;
572 }
573
574 nvm->major = (ver & ICE_NVM_VER_HI_MASK) >> ICE_NVM_VER_HI_SHIFT;
575 nvm->minor = (ver & ICE_NVM_VER_LO_MASK) >> ICE_NVM_VER_LO_SHIFT;
576
577 status = ice_read_nvm_sr_copy(hw, bank, ICE_SR_NVM_EETRACK_LO, &eetrack_lo);
578 if (status) {
579 ice_debug(hw, ICE_DBG_NVM, "Failed to read EETRACK lo.\n");
580 return status;
581 }
582 status = ice_read_nvm_sr_copy(hw, bank, ICE_SR_NVM_EETRACK_HI, &eetrack_hi);
583 if (status) {
584 ice_debug(hw, ICE_DBG_NVM, "Failed to read EETRACK hi.\n");
585 return status;
586 }
587
588 nvm->eetrack = (eetrack_hi << 16) | eetrack_lo;
589
590 return 0;
591}
592
593
594
595
596
597
598
599
600
601
602int ice_get_inactive_nvm_ver(struct ice_hw *hw, struct ice_nvm_info *nvm)
603{
604 return ice_get_nvm_ver_info(hw, ICE_INACTIVE_FLASH_BANK, nvm);
605}
606
607
608
609
610
611
612
613
614
615
616static int
617ice_get_orom_civd_data(struct ice_hw *hw, enum ice_bank_select bank,
618 struct ice_orom_civd_info *civd)
619{
620 u8 *orom_data;
621 int status;
622 u32 offset;
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637 orom_data = vzalloc(hw->flash.banks.orom_size);
638 if (!orom_data)
639 return -ENOMEM;
640
641 status = ice_read_flash_module(hw, bank, ICE_SR_1ST_OROM_BANK_PTR, 0,
642 orom_data, hw->flash.banks.orom_size);
643 if (status) {
644 vfree(orom_data);
645 ice_debug(hw, ICE_DBG_NVM, "Unable to read Option ROM data\n");
646 return status;
647 }
648
649
650 for (offset = 0; (offset + 512) <= hw->flash.banks.orom_size; offset += 512) {
651 struct ice_orom_civd_info *tmp;
652 u8 sum = 0, i;
653
654 tmp = (struct ice_orom_civd_info *)&orom_data[offset];
655
656
657 if (memcmp("$CIV", tmp->signature, sizeof(tmp->signature)) != 0)
658 continue;
659
660 ice_debug(hw, ICE_DBG_NVM, "Found CIVD section at offset %u\n",
661 offset);
662
663
664 for (i = 0; i < sizeof(*tmp); i++)
665
666 sum += ((u8 *)tmp)[i];
667
668 if (sum) {
669 ice_debug(hw, ICE_DBG_NVM, "Found CIVD data with invalid checksum of %u\n",
670 sum);
671 goto err_invalid_checksum;
672 }
673
674 *civd = *tmp;
675 vfree(orom_data);
676 return 0;
677 }
678
679 ice_debug(hw, ICE_DBG_NVM, "Unable to locate CIVD data within the Option ROM\n");
680
681err_invalid_checksum:
682 vfree(orom_data);
683 return -EIO;
684}
685
686
687
688
689
690
691
692
693
694
695static int
696ice_get_orom_ver_info(struct ice_hw *hw, enum ice_bank_select bank, struct ice_orom_info *orom)
697{
698 struct ice_orom_civd_info civd;
699 u32 combo_ver;
700 int status;
701
702 status = ice_get_orom_civd_data(hw, bank, &civd);
703 if (status) {
704 ice_debug(hw, ICE_DBG_NVM, "Failed to locate valid Option ROM CIVD data\n");
705 return status;
706 }
707
708 combo_ver = le32_to_cpu(civd.combo_ver);
709
710 orom->major = (u8)((combo_ver & ICE_OROM_VER_MASK) >> ICE_OROM_VER_SHIFT);
711 orom->patch = (u8)(combo_ver & ICE_OROM_VER_PATCH_MASK);
712 orom->build = (u16)((combo_ver & ICE_OROM_VER_BUILD_MASK) >> ICE_OROM_VER_BUILD_SHIFT);
713
714 return 0;
715}
716
717
718
719
720
721
722
723
724
725
726int ice_get_inactive_orom_ver(struct ice_hw *hw, struct ice_orom_info *orom)
727{
728 return ice_get_orom_ver_info(hw, ICE_INACTIVE_FLASH_BANK, orom);
729}
730
731
732
733
734
735
736
737
738
739
740
741static int
742ice_get_netlist_info(struct ice_hw *hw, enum ice_bank_select bank,
743 struct ice_netlist_info *netlist)
744{
745 u16 module_id, length, node_count, i;
746 u16 *id_blk;
747 int status;
748
749 status = ice_read_netlist_module(hw, bank, ICE_NETLIST_TYPE_OFFSET, &module_id);
750 if (status)
751 return status;
752
753 if (module_id != ICE_NETLIST_LINK_TOPO_MOD_ID) {
754 ice_debug(hw, ICE_DBG_NVM, "Expected netlist module_id ID of 0x%04x, but got 0x%04x\n",
755 ICE_NETLIST_LINK_TOPO_MOD_ID, module_id);
756 return -EIO;
757 }
758
759 status = ice_read_netlist_module(hw, bank, ICE_LINK_TOPO_MODULE_LEN, &length);
760 if (status)
761 return status;
762
763
764 if (length < ICE_NETLIST_ID_BLK_SIZE) {
765 ice_debug(hw, ICE_DBG_NVM, "Netlist Link Topology module too small. Expected at least %u words, but got %u words.\n",
766 ICE_NETLIST_ID_BLK_SIZE, length);
767 return -EIO;
768 }
769
770 status = ice_read_netlist_module(hw, bank, ICE_LINK_TOPO_NODE_COUNT, &node_count);
771 if (status)
772 return status;
773 node_count &= ICE_LINK_TOPO_NODE_COUNT_M;
774
775 id_blk = kcalloc(ICE_NETLIST_ID_BLK_SIZE, sizeof(*id_blk), GFP_KERNEL);
776 if (!id_blk)
777 return -ENOMEM;
778
779
780 status = ice_read_flash_module(hw, bank, ICE_SR_NETLIST_BANK_PTR,
781 ICE_NETLIST_ID_BLK_OFFSET(node_count) * sizeof(u16),
782 (u8 *)id_blk, ICE_NETLIST_ID_BLK_SIZE * sizeof(u16));
783 if (status)
784 goto exit_error;
785
786 for (i = 0; i < ICE_NETLIST_ID_BLK_SIZE; i++)
787 id_blk[i] = le16_to_cpu(((__force __le16 *)id_blk)[i]);
788
789 netlist->major = id_blk[ICE_NETLIST_ID_BLK_MAJOR_VER_HIGH] << 16 |
790 id_blk[ICE_NETLIST_ID_BLK_MAJOR_VER_LOW];
791 netlist->minor = id_blk[ICE_NETLIST_ID_BLK_MINOR_VER_HIGH] << 16 |
792 id_blk[ICE_NETLIST_ID_BLK_MINOR_VER_LOW];
793 netlist->type = id_blk[ICE_NETLIST_ID_BLK_TYPE_HIGH] << 16 |
794 id_blk[ICE_NETLIST_ID_BLK_TYPE_LOW];
795 netlist->rev = id_blk[ICE_NETLIST_ID_BLK_REV_HIGH] << 16 |
796 id_blk[ICE_NETLIST_ID_BLK_REV_LOW];
797 netlist->cust_ver = id_blk[ICE_NETLIST_ID_BLK_CUST_VER];
798
799 netlist->hash = id_blk[ICE_NETLIST_ID_BLK_SHA_HASH_WORD(15)] << 16 |
800 id_blk[ICE_NETLIST_ID_BLK_SHA_HASH_WORD(14)];
801
802exit_error:
803 kfree(id_blk);
804
805 return status;
806}
807
808
809
810
811
812
813
814
815
816
817int ice_get_inactive_netlist_ver(struct ice_hw *hw, struct ice_netlist_info *netlist)
818{
819 return ice_get_netlist_info(hw, ICE_INACTIVE_FLASH_BANK, netlist);
820}
821
822
823
824
825
826
827
828
829
830static int ice_discover_flash_size(struct ice_hw *hw)
831{
832 u32 min_size = 0, max_size = ICE_AQC_NVM_MAX_OFFSET + 1;
833 int status;
834
835 status = ice_acquire_nvm(hw, ICE_RES_READ);
836 if (status)
837 return status;
838
839 while ((max_size - min_size) > 1) {
840 u32 offset = (max_size + min_size) / 2;
841 u32 len = 1;
842 u8 data;
843
844 status = ice_read_flat_nvm(hw, offset, &len, &data, false);
845 if (status == -EIO &&
846 hw->adminq.sq_last_status == ICE_AQ_RC_EINVAL) {
847 ice_debug(hw, ICE_DBG_NVM, "%s: New upper bound of %u bytes\n",
848 __func__, offset);
849 status = 0;
850 max_size = offset;
851 } else if (!status) {
852 ice_debug(hw, ICE_DBG_NVM, "%s: New lower bound of %u bytes\n",
853 __func__, offset);
854 min_size = offset;
855 } else {
856
857 goto err_read_flat_nvm;
858 }
859 }
860
861 ice_debug(hw, ICE_DBG_NVM, "Predicted flash size is %u bytes\n", max_size);
862
863 hw->flash.flash_size = max_size;
864
865err_read_flat_nvm:
866 ice_release_nvm(hw);
867
868 return status;
869}
870
871
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885static int ice_read_sr_pointer(struct ice_hw *hw, u16 offset, u32 *pointer)
886{
887 int status;
888 u16 value;
889
890 status = ice_read_sr_word(hw, offset, &value);
891 if (status)
892 return status;
893
894
895 if (value & ICE_SR_NVM_PTR_4KB_UNITS)
896 *pointer = (value & ~ICE_SR_NVM_PTR_4KB_UNITS) * 4 * 1024;
897 else
898 *pointer = value * 2;
899
900 return 0;
901}
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916static int ice_read_sr_area_size(struct ice_hw *hw, u16 offset, u32 *size)
917{
918 int status;
919 u16 value;
920
921 status = ice_read_sr_word(hw, offset, &value);
922 if (status)
923 return status;
924
925
926 *size = value * 4 * 1024;
927
928 return 0;
929}
930
931
932
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934
935
936
937
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939
940
941static int ice_determine_active_flash_banks(struct ice_hw *hw)
942{
943 struct ice_bank_info *banks = &hw->flash.banks;
944 u16 ctrl_word;
945 int status;
946
947 status = ice_read_sr_word(hw, ICE_SR_NVM_CTRL_WORD, &ctrl_word);
948 if (status) {
949 ice_debug(hw, ICE_DBG_NVM, "Failed to read the Shadow RAM control word\n");
950 return status;
951 }
952
953
954 if ((ctrl_word & ICE_SR_CTRL_WORD_1_M) >> ICE_SR_CTRL_WORD_1_S != ICE_SR_CTRL_WORD_VALID) {
955 ice_debug(hw, ICE_DBG_NVM, "Shadow RAM control word is invalid\n");
956 return -EIO;
957 }
958
959 if (!(ctrl_word & ICE_SR_CTRL_WORD_NVM_BANK))
960 banks->nvm_bank = ICE_1ST_FLASH_BANK;
961 else
962 banks->nvm_bank = ICE_2ND_FLASH_BANK;
963
964 if (!(ctrl_word & ICE_SR_CTRL_WORD_OROM_BANK))
965 banks->orom_bank = ICE_1ST_FLASH_BANK;
966 else
967 banks->orom_bank = ICE_2ND_FLASH_BANK;
968
969 if (!(ctrl_word & ICE_SR_CTRL_WORD_NETLIST_BANK))
970 banks->netlist_bank = ICE_1ST_FLASH_BANK;
971 else
972 banks->netlist_bank = ICE_2ND_FLASH_BANK;
973
974 status = ice_read_sr_pointer(hw, ICE_SR_1ST_NVM_BANK_PTR, &banks->nvm_ptr);
975 if (status) {
976 ice_debug(hw, ICE_DBG_NVM, "Failed to read NVM bank pointer\n");
977 return status;
978 }
979
980 status = ice_read_sr_area_size(hw, ICE_SR_NVM_BANK_SIZE, &banks->nvm_size);
981 if (status) {
982 ice_debug(hw, ICE_DBG_NVM, "Failed to read NVM bank area size\n");
983 return status;
984 }
985
986 status = ice_read_sr_pointer(hw, ICE_SR_1ST_OROM_BANK_PTR, &banks->orom_ptr);
987 if (status) {
988 ice_debug(hw, ICE_DBG_NVM, "Failed to read OROM bank pointer\n");
989 return status;
990 }
991
992 status = ice_read_sr_area_size(hw, ICE_SR_OROM_BANK_SIZE, &banks->orom_size);
993 if (status) {
994 ice_debug(hw, ICE_DBG_NVM, "Failed to read OROM bank area size\n");
995 return status;
996 }
997
998 status = ice_read_sr_pointer(hw, ICE_SR_NETLIST_BANK_PTR, &banks->netlist_ptr);
999 if (status) {
1000 ice_debug(hw, ICE_DBG_NVM, "Failed to read Netlist bank pointer\n");
1001 return status;
1002 }
1003
1004 status = ice_read_sr_area_size(hw, ICE_SR_NETLIST_BANK_SIZE, &banks->netlist_size);
1005 if (status) {
1006 ice_debug(hw, ICE_DBG_NVM, "Failed to read Netlist bank area size\n");
1007 return status;
1008 }
1009
1010 return 0;
1011}
1012
1013
1014
1015
1016
1017
1018
1019
1020int ice_init_nvm(struct ice_hw *hw)
1021{
1022 struct ice_flash_info *flash = &hw->flash;
1023 u32 fla, gens_stat;
1024 u8 sr_size;
1025 int status;
1026
1027
1028
1029
1030 gens_stat = rd32(hw, GLNVM_GENS);
1031 sr_size = (gens_stat & GLNVM_GENS_SR_SIZE_M) >> GLNVM_GENS_SR_SIZE_S;
1032
1033
1034 flash->sr_words = BIT(sr_size) * ICE_SR_WORDS_IN_1KB;
1035
1036
1037 fla = rd32(hw, GLNVM_FLA);
1038 if (fla & GLNVM_FLA_LOCKED_M) {
1039 flash->blank_nvm_mode = false;
1040 } else {
1041
1042 flash->blank_nvm_mode = true;
1043 ice_debug(hw, ICE_DBG_NVM, "NVM init error: unsupported blank mode.\n");
1044 return -EIO;
1045 }
1046
1047 status = ice_discover_flash_size(hw);
1048 if (status) {
1049 ice_debug(hw, ICE_DBG_NVM, "NVM init error: failed to discover flash size.\n");
1050 return status;
1051 }
1052
1053 status = ice_determine_active_flash_banks(hw);
1054 if (status) {
1055 ice_debug(hw, ICE_DBG_NVM, "Failed to determine active flash banks.\n");
1056 return status;
1057 }
1058
1059 status = ice_get_nvm_ver_info(hw, ICE_ACTIVE_FLASH_BANK, &flash->nvm);
1060 if (status) {
1061 ice_debug(hw, ICE_DBG_INIT, "Failed to read NVM info.\n");
1062 return status;
1063 }
1064
1065 status = ice_get_orom_ver_info(hw, ICE_ACTIVE_FLASH_BANK, &flash->orom);
1066 if (status)
1067 ice_debug(hw, ICE_DBG_INIT, "Failed to read Option ROM info.\n");
1068
1069
1070 status = ice_get_netlist_info(hw, ICE_ACTIVE_FLASH_BANK, &flash->netlist);
1071 if (status)
1072 ice_debug(hw, ICE_DBG_INIT, "Failed to read netlist info.\n");
1073
1074 return 0;
1075}
1076
1077
1078
1079
1080
1081
1082
1083int ice_nvm_validate_checksum(struct ice_hw *hw)
1084{
1085 struct ice_aqc_nvm_checksum *cmd;
1086 struct ice_aq_desc desc;
1087 int status;
1088
1089 status = ice_acquire_nvm(hw, ICE_RES_READ);
1090 if (status)
1091 return status;
1092
1093 cmd = &desc.params.nvm_checksum;
1094
1095 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_nvm_checksum);
1096 cmd->flags = ICE_AQC_NVM_CHECKSUM_VERIFY;
1097
1098 status = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
1099 ice_release_nvm(hw);
1100
1101 if (!status)
1102 if (le16_to_cpu(cmd->checksum) != ICE_AQC_NVM_CHECKSUM_CORRECT)
1103 status = -EIO;
1104
1105 return status;
1106}
1107
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1110
1111
1112
1113
1114
1115
1116
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1118
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1120
1121
1122
1123
1124int ice_nvm_write_activate(struct ice_hw *hw, u8 cmd_flags, u8 *response_flags)
1125{
1126 struct ice_aqc_nvm *cmd;
1127 struct ice_aq_desc desc;
1128 int err;
1129
1130 cmd = &desc.params.nvm;
1131 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_nvm_write_activate);
1132
1133 cmd->cmd_flags = cmd_flags;
1134
1135 err = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
1136 if (!err && response_flags)
1137 *response_flags = cmd->cmd_flags;
1138
1139 return err;
1140}
1141
1142
1143
1144
1145
1146
1147
1148
1149int ice_aq_nvm_update_empr(struct ice_hw *hw)
1150{
1151 struct ice_aq_desc desc;
1152
1153 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_nvm_update_empr);
1154
1155 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
1156}
1157
1158
1159
1160
1161
1162
1163
1164
1165
1166
1167
1168
1169
1170
1171
1172int
1173ice_nvm_set_pkg_data(struct ice_hw *hw, bool del_pkg_data_flag, u8 *data,
1174 u16 length, struct ice_sq_cd *cd)
1175{
1176 struct ice_aqc_nvm_pkg_data *cmd;
1177 struct ice_aq_desc desc;
1178
1179 if (length != 0 && !data)
1180 return -EINVAL;
1181
1182 cmd = &desc.params.pkg_data;
1183
1184 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_nvm_pkg_data);
1185 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD);
1186
1187 if (del_pkg_data_flag)
1188 cmd->cmd_flags |= ICE_AQC_NVM_PKG_DELETE;
1189
1190 return ice_aq_send_cmd(hw, &desc, data, length, cd);
1191}
1192
1193
1194
1195
1196
1197
1198
1199
1200
1201
1202
1203
1204
1205
1206
1207
1208
1209int
1210ice_nvm_pass_component_tbl(struct ice_hw *hw, u8 *data, u16 length,
1211 u8 transfer_flag, u8 *comp_response,
1212 u8 *comp_response_code, struct ice_sq_cd *cd)
1213{
1214 struct ice_aqc_nvm_pass_comp_tbl *cmd;
1215 struct ice_aq_desc desc;
1216 int status;
1217
1218 if (!data || !comp_response || !comp_response_code)
1219 return -EINVAL;
1220
1221 cmd = &desc.params.pass_comp_tbl;
1222
1223 ice_fill_dflt_direct_cmd_desc(&desc,
1224 ice_aqc_opc_nvm_pass_component_tbl);
1225 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD);
1226
1227 cmd->transfer_flag = transfer_flag;
1228 status = ice_aq_send_cmd(hw, &desc, data, length, cd);
1229
1230 if (!status) {
1231 *comp_response = cmd->component_response;
1232 *comp_response_code = cmd->component_response_code;
1233 }
1234 return status;
1235}
1236