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17#ifndef _HAL_H_
18#define _HAL_H_
19
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32
33
34#define WCN36XX_HAL_VER_MAJOR 1
35#define WCN36XX_HAL_VER_MINOR 4
36#define WCN36XX_HAL_VER_VERSION 1
37#define WCN36XX_HAL_VER_REVISION 2
38
39
40#define WCN36XX_HAL_MAX_ENUM_SIZE 0x7FFFFFFF
41#define WCN36XX_HAL_MSG_TYPE_MAX_ENUM_SIZE 0x7FFF
42
43
44#define STACFG_MAX_TC 8
45
46
47#define WCN36XX_HAL_MAX_AC 4
48
49#define WCN36XX_HAL_IPV4_ADDR_LEN 4
50
51#define WCN36XX_HAL_STA_INVALID_IDX 0xFF
52#define WCN36XX_HAL_BSS_INVALID_IDX 0xFF
53
54
55#define BEACON_TEMPLATE_SIZE 0x180
56
57
58#define TIM_MIN_PVM_SIZE 6
59
60
61#define PARAM_BCN_INTERVAL_CHANGED (1 << 0)
62#define PARAM_SHORT_PREAMBLE_CHANGED (1 << 1)
63#define PARAM_SHORT_SLOT_TIME_CHANGED (1 << 2)
64#define PARAM_llACOEXIST_CHANGED (1 << 3)
65#define PARAM_llBCOEXIST_CHANGED (1 << 4)
66#define PARAM_llGCOEXIST_CHANGED (1 << 5)
67#define PARAM_HT20MHZCOEXIST_CHANGED (1<<6)
68#define PARAM_NON_GF_DEVICES_PRESENT_CHANGED (1<<7)
69#define PARAM_RIFS_MODE_CHANGED (1<<8)
70#define PARAM_LSIG_TXOP_FULL_SUPPORT_CHANGED (1<<9)
71#define PARAM_OBSS_MODE_CHANGED (1<<10)
72#define PARAM_BEACON_UPDATE_MASK \
73 (PARAM_BCN_INTERVAL_CHANGED | \
74 PARAM_SHORT_PREAMBLE_CHANGED | \
75 PARAM_SHORT_SLOT_TIME_CHANGED | \
76 PARAM_llACOEXIST_CHANGED | \
77 PARAM_llBCOEXIST_CHANGED | \
78 PARAM_llGCOEXIST_CHANGED | \
79 PARAM_HT20MHZCOEXIST_CHANGED | \
80 PARAM_NON_GF_DEVICES_PRESENT_CHANGED | \
81 PARAM_RIFS_MODE_CHANGED | \
82 PARAM_LSIG_TXOP_FULL_SUPPORT_CHANGED | \
83 PARAM_OBSS_MODE_CHANGED)
84
85
86#define DUMPCMD_RSP_BUFFER 100
87
88
89#define WCN36XX_HAL_VERSION_LENGTH 64
90
91
92#define WCN36XX_AMPDU_START_THRESH 20
93
94#define WCN36XX_MAX_SCAN_SSIDS 9
95#define WCN36XX_MAX_SCAN_IE_LEN 500
96
97
98enum wcn36xx_hal_host_msg_type {
99
100 WCN36XX_HAL_START_REQ = 0,
101 WCN36XX_HAL_START_RSP = 1,
102 WCN36XX_HAL_STOP_REQ = 2,
103 WCN36XX_HAL_STOP_RSP = 3,
104
105
106 WCN36XX_HAL_INIT_SCAN_REQ = 4,
107 WCN36XX_HAL_INIT_SCAN_RSP = 5,
108 WCN36XX_HAL_START_SCAN_REQ = 6,
109 WCN36XX_HAL_START_SCAN_RSP = 7,
110 WCN36XX_HAL_END_SCAN_REQ = 8,
111 WCN36XX_HAL_END_SCAN_RSP = 9,
112 WCN36XX_HAL_FINISH_SCAN_REQ = 10,
113 WCN36XX_HAL_FINISH_SCAN_RSP = 11,
114
115
116 WCN36XX_HAL_CONFIG_STA_REQ = 12,
117 WCN36XX_HAL_CONFIG_STA_RSP = 13,
118 WCN36XX_HAL_DELETE_STA_REQ = 14,
119 WCN36XX_HAL_DELETE_STA_RSP = 15,
120 WCN36XX_HAL_CONFIG_BSS_REQ = 16,
121 WCN36XX_HAL_CONFIG_BSS_RSP = 17,
122 WCN36XX_HAL_DELETE_BSS_REQ = 18,
123 WCN36XX_HAL_DELETE_BSS_RSP = 19,
124
125
126 WCN36XX_HAL_JOIN_REQ = 20,
127 WCN36XX_HAL_JOIN_RSP = 21,
128 WCN36XX_HAL_POST_ASSOC_REQ = 22,
129 WCN36XX_HAL_POST_ASSOC_RSP = 23,
130
131
132 WCN36XX_HAL_SET_BSSKEY_REQ = 24,
133 WCN36XX_HAL_SET_BSSKEY_RSP = 25,
134 WCN36XX_HAL_SET_STAKEY_REQ = 26,
135 WCN36XX_HAL_SET_STAKEY_RSP = 27,
136 WCN36XX_HAL_RMV_BSSKEY_REQ = 28,
137 WCN36XX_HAL_RMV_BSSKEY_RSP = 29,
138 WCN36XX_HAL_RMV_STAKEY_REQ = 30,
139 WCN36XX_HAL_RMV_STAKEY_RSP = 31,
140
141
142 WCN36XX_HAL_ADD_TS_REQ = 32,
143 WCN36XX_HAL_ADD_TS_RSP = 33,
144 WCN36XX_HAL_DEL_TS_REQ = 34,
145 WCN36XX_HAL_DEL_TS_RSP = 35,
146 WCN36XX_HAL_UPD_EDCA_PARAMS_REQ = 36,
147 WCN36XX_HAL_UPD_EDCA_PARAMS_RSP = 37,
148 WCN36XX_HAL_ADD_BA_REQ = 38,
149 WCN36XX_HAL_ADD_BA_RSP = 39,
150 WCN36XX_HAL_DEL_BA_REQ = 40,
151 WCN36XX_HAL_DEL_BA_RSP = 41,
152
153 WCN36XX_HAL_CH_SWITCH_REQ = 42,
154 WCN36XX_HAL_CH_SWITCH_RSP = 43,
155 WCN36XX_HAL_SET_LINK_ST_REQ = 44,
156 WCN36XX_HAL_SET_LINK_ST_RSP = 45,
157 WCN36XX_HAL_GET_STATS_REQ = 46,
158 WCN36XX_HAL_GET_STATS_RSP = 47,
159 WCN36XX_HAL_UPDATE_CFG_REQ = 48,
160 WCN36XX_HAL_UPDATE_CFG_RSP = 49,
161
162 WCN36XX_HAL_MISSED_BEACON_IND = 50,
163 WCN36XX_HAL_UNKNOWN_ADDR2_FRAME_RX_IND = 51,
164 WCN36XX_HAL_MIC_FAILURE_IND = 52,
165 WCN36XX_HAL_FATAL_ERROR_IND = 53,
166 WCN36XX_HAL_SET_KEYDONE_MSG = 54,
167
168
169 WCN36XX_HAL_DOWNLOAD_NV_REQ = 55,
170 WCN36XX_HAL_DOWNLOAD_NV_RSP = 56,
171
172 WCN36XX_HAL_ADD_BA_SESSION_REQ = 57,
173 WCN36XX_HAL_ADD_BA_SESSION_RSP = 58,
174 WCN36XX_HAL_TRIGGER_BA_REQ = 59,
175 WCN36XX_HAL_TRIGGER_BA_RSP = 60,
176 WCN36XX_HAL_UPDATE_BEACON_REQ = 61,
177 WCN36XX_HAL_UPDATE_BEACON_RSP = 62,
178 WCN36XX_HAL_SEND_BEACON_REQ = 63,
179 WCN36XX_HAL_SEND_BEACON_RSP = 64,
180
181 WCN36XX_HAL_SET_BCASTKEY_REQ = 65,
182 WCN36XX_HAL_SET_BCASTKEY_RSP = 66,
183 WCN36XX_HAL_DELETE_STA_CONTEXT_IND = 67,
184 WCN36XX_HAL_UPDATE_PROBE_RSP_TEMPLATE_REQ = 68,
185 WCN36XX_HAL_UPDATE_PROBE_RSP_TEMPLATE_RSP = 69,
186
187
188 WCN36XX_HAL_PROCESS_PTT_REQ = 70,
189 WCN36XX_HAL_PROCESS_PTT_RSP = 71,
190
191
192 WCN36XX_HAL_SIGNAL_BTAMP_EVENT_REQ = 72,
193 WCN36XX_HAL_SIGNAL_BTAMP_EVENT_RSP = 73,
194 WCN36XX_HAL_TL_HAL_FLUSH_AC_REQ = 74,
195 WCN36XX_HAL_TL_HAL_FLUSH_AC_RSP = 75,
196
197 WCN36XX_HAL_ENTER_IMPS_REQ = 76,
198 WCN36XX_HAL_EXIT_IMPS_REQ = 77,
199 WCN36XX_HAL_ENTER_BMPS_REQ = 78,
200 WCN36XX_HAL_EXIT_BMPS_REQ = 79,
201 WCN36XX_HAL_ENTER_UAPSD_REQ = 80,
202 WCN36XX_HAL_EXIT_UAPSD_REQ = 81,
203 WCN36XX_HAL_UPDATE_UAPSD_PARAM_REQ = 82,
204 WCN36XX_HAL_CONFIGURE_RXP_FILTER_REQ = 83,
205 WCN36XX_HAL_ADD_BCN_FILTER_REQ = 84,
206 WCN36XX_HAL_REM_BCN_FILTER_REQ = 85,
207 WCN36XX_HAL_ADD_WOWL_BCAST_PTRN = 86,
208 WCN36XX_HAL_DEL_WOWL_BCAST_PTRN = 87,
209 WCN36XX_HAL_ENTER_WOWL_REQ = 88,
210 WCN36XX_HAL_EXIT_WOWL_REQ = 89,
211 WCN36XX_HAL_HOST_OFFLOAD_REQ = 90,
212 WCN36XX_HAL_SET_RSSI_THRESH_REQ = 91,
213 WCN36XX_HAL_GET_RSSI_REQ = 92,
214 WCN36XX_HAL_SET_UAPSD_AC_PARAMS_REQ = 93,
215 WCN36XX_HAL_CONFIGURE_APPS_CPU_WAKEUP_STATE_REQ = 94,
216
217 WCN36XX_HAL_ENTER_IMPS_RSP = 95,
218 WCN36XX_HAL_EXIT_IMPS_RSP = 96,
219 WCN36XX_HAL_ENTER_BMPS_RSP = 97,
220 WCN36XX_HAL_EXIT_BMPS_RSP = 98,
221 WCN36XX_HAL_ENTER_UAPSD_RSP = 99,
222 WCN36XX_HAL_EXIT_UAPSD_RSP = 100,
223 WCN36XX_HAL_SET_UAPSD_AC_PARAMS_RSP = 101,
224 WCN36XX_HAL_UPDATE_UAPSD_PARAM_RSP = 102,
225 WCN36XX_HAL_CONFIGURE_RXP_FILTER_RSP = 103,
226 WCN36XX_HAL_ADD_BCN_FILTER_RSP = 104,
227 WCN36XX_HAL_REM_BCN_FILTER_RSP = 105,
228 WCN36XX_HAL_SET_RSSI_THRESH_RSP = 106,
229 WCN36XX_HAL_HOST_OFFLOAD_RSP = 107,
230 WCN36XX_HAL_ADD_WOWL_BCAST_PTRN_RSP = 108,
231 WCN36XX_HAL_DEL_WOWL_BCAST_PTRN_RSP = 109,
232 WCN36XX_HAL_ENTER_WOWL_RSP = 110,
233 WCN36XX_HAL_EXIT_WOWL_RSP = 111,
234 WCN36XX_HAL_RSSI_NOTIFICATION_IND = 112,
235 WCN36XX_HAL_GET_RSSI_RSP = 113,
236 WCN36XX_HAL_CONFIGURE_APPS_CPU_WAKEUP_STATE_RSP = 114,
237
238
239 WCN36XX_HAL_SET_MAX_TX_POWER_REQ = 115,
240 WCN36XX_HAL_SET_MAX_TX_POWER_RSP = 116,
241
242
243 WCN36XX_HAL_AGGR_ADD_TS_REQ = 117,
244 WCN36XX_HAL_AGGR_ADD_TS_RSP = 118,
245
246
247 WCN36XX_HAL_SET_P2P_GONOA_REQ = 119,
248 WCN36XX_HAL_SET_P2P_GONOA_RSP = 120,
249
250
251 WCN36XX_HAL_DUMP_COMMAND_REQ = 121,
252 WCN36XX_HAL_DUMP_COMMAND_RSP = 122,
253
254
255 WCN36XX_HAL_START_OEM_DATA_REQ = 123,
256 WCN36XX_HAL_START_OEM_DATA_RSP = 124,
257
258
259 WCN36XX_HAL_ADD_STA_SELF_REQ = 125,
260 WCN36XX_HAL_ADD_STA_SELF_RSP = 126,
261
262
263 WCN36XX_HAL_DEL_STA_SELF_REQ = 127,
264 WCN36XX_HAL_DEL_STA_SELF_RSP = 128,
265
266
267 WCN36XX_HAL_COEX_IND = 129,
268
269
270 WCN36XX_HAL_OTA_TX_COMPL_IND = 130,
271
272
273 WCN36XX_HAL_HOST_SUSPEND_IND = 131,
274 WCN36XX_HAL_HOST_RESUME_REQ = 132,
275 WCN36XX_HAL_HOST_RESUME_RSP = 133,
276
277 WCN36XX_HAL_SET_TX_POWER_REQ = 134,
278 WCN36XX_HAL_SET_TX_POWER_RSP = 135,
279 WCN36XX_HAL_GET_TX_POWER_REQ = 136,
280 WCN36XX_HAL_GET_TX_POWER_RSP = 137,
281
282 WCN36XX_HAL_P2P_NOA_ATTR_IND = 138,
283
284 WCN36XX_HAL_ENABLE_RADAR_DETECT_REQ = 139,
285 WCN36XX_HAL_ENABLE_RADAR_DETECT_RSP = 140,
286 WCN36XX_HAL_GET_TPC_REPORT_REQ = 141,
287 WCN36XX_HAL_GET_TPC_REPORT_RSP = 142,
288 WCN36XX_HAL_RADAR_DETECT_IND = 143,
289 WCN36XX_HAL_RADAR_DETECT_INTR_IND = 144,
290 WCN36XX_HAL_KEEP_ALIVE_REQ = 145,
291 WCN36XX_HAL_KEEP_ALIVE_RSP = 146,
292
293
294 WCN36XX_HAL_SET_PREF_NETWORK_REQ = 147,
295 WCN36XX_HAL_SET_PREF_NETWORK_RSP = 148,
296 WCN36XX_HAL_SET_RSSI_FILTER_REQ = 149,
297 WCN36XX_HAL_SET_RSSI_FILTER_RSP = 150,
298 WCN36XX_HAL_UPDATE_SCAN_PARAM_REQ = 151,
299 WCN36XX_HAL_UPDATE_SCAN_PARAM_RSP = 152,
300 WCN36XX_HAL_PREF_NETW_FOUND_IND = 153,
301
302 WCN36XX_HAL_SET_TX_PER_TRACKING_REQ = 154,
303 WCN36XX_HAL_SET_TX_PER_TRACKING_RSP = 155,
304 WCN36XX_HAL_TX_PER_HIT_IND = 156,
305
306 WCN36XX_HAL_8023_MULTICAST_LIST_REQ = 157,
307 WCN36XX_HAL_8023_MULTICAST_LIST_RSP = 158,
308
309 WCN36XX_HAL_SET_PACKET_FILTER_REQ = 159,
310 WCN36XX_HAL_SET_PACKET_FILTER_RSP = 160,
311 WCN36XX_HAL_PACKET_FILTER_MATCH_COUNT_REQ = 161,
312 WCN36XX_HAL_PACKET_FILTER_MATCH_COUNT_RSP = 162,
313 WCN36XX_HAL_CLEAR_PACKET_FILTER_REQ = 163,
314 WCN36XX_HAL_CLEAR_PACKET_FILTER_RSP = 164,
315
316
317
318
319
320 WCN36XX_HAL_INIT_SCAN_CON_REQ = 165,
321
322 WCN36XX_HAL_SET_POWER_PARAMS_REQ = 166,
323 WCN36XX_HAL_SET_POWER_PARAMS_RSP = 167,
324
325 WCN36XX_HAL_TSM_STATS_REQ = 168,
326 WCN36XX_HAL_TSM_STATS_RSP = 169,
327
328
329 WCN36XX_HAL_WAKE_REASON_IND = 170,
330
331
332 WCN36XX_HAL_GTK_OFFLOAD_REQ = 171,
333 WCN36XX_HAL_GTK_OFFLOAD_RSP = 172,
334 WCN36XX_HAL_GTK_OFFLOAD_GETINFO_REQ = 173,
335 WCN36XX_HAL_GTK_OFFLOAD_GETINFO_RSP = 174,
336
337 WCN36XX_HAL_FEATURE_CAPS_EXCHANGE_REQ = 175,
338 WCN36XX_HAL_FEATURE_CAPS_EXCHANGE_RSP = 176,
339 WCN36XX_HAL_EXCLUDE_UNENCRYPTED_IND = 177,
340
341 WCN36XX_HAL_SET_THERMAL_MITIGATION_REQ = 178,
342 WCN36XX_HAL_SET_THERMAL_MITIGATION_RSP = 179,
343
344 WCN36XX_HAL_UPDATE_VHT_OP_MODE_REQ = 182,
345 WCN36XX_HAL_UPDATE_VHT_OP_MODE_RSP = 183,
346
347 WCN36XX_HAL_P2P_NOA_START_IND = 184,
348
349 WCN36XX_HAL_GET_ROAM_RSSI_REQ = 185,
350 WCN36XX_HAL_GET_ROAM_RSSI_RSP = 186,
351
352 WCN36XX_HAL_CLASS_B_STATS_IND = 187,
353 WCN36XX_HAL_DEL_BA_IND = 188,
354 WCN36XX_HAL_DHCP_START_IND = 189,
355 WCN36XX_HAL_DHCP_STOP_IND = 190,
356
357
358 WCN36XX_HAL_START_SCAN_OFFLOAD_REQ = 204,
359 WCN36XX_HAL_START_SCAN_OFFLOAD_RSP = 205,
360 WCN36XX_HAL_STOP_SCAN_OFFLOAD_REQ = 206,
361 WCN36XX_HAL_STOP_SCAN_OFFLOAD_RSP = 207,
362 WCN36XX_HAL_UPDATE_CHANNEL_LIST_REQ = 208,
363 WCN36XX_HAL_UPDATE_CHANNEL_LIST_RSP = 209,
364 WCN36XX_HAL_SCAN_OFFLOAD_IND = 210,
365
366 WCN36XX_HAL_AVOID_FREQ_RANGE_IND = 233,
367
368 WCN36XX_HAL_PRINT_REG_INFO_IND = 259,
369
370 WCN36XX_HAL_MSG_MAX = WCN36XX_HAL_MSG_TYPE_MAX_ENUM_SIZE
371};
372
373
374enum wcn36xx_hal_host_msg_version {
375 WCN36XX_HAL_MSG_VERSION0 = 0,
376 WCN36XX_HAL_MSG_VERSION1 = 1,
377
378 WCN36XX_HAL_MSG_WCNSS_CTRL_VERSION = 0x7FFF,
379 WCN36XX_HAL_MSG_VERSION_MAX_FIELD = WCN36XX_HAL_MSG_WCNSS_CTRL_VERSION
380};
381
382enum driver_type {
383 DRIVER_TYPE_PRODUCTION = 0,
384 DRIVER_TYPE_MFG = 1,
385 DRIVER_TYPE_DVT = 2,
386 DRIVER_TYPE_MAX = WCN36XX_HAL_MAX_ENUM_SIZE
387};
388
389enum wcn36xx_hal_stop_type {
390 HAL_STOP_TYPE_SYS_RESET,
391 HAL_STOP_TYPE_SYS_DEEP_SLEEP,
392 HAL_STOP_TYPE_RF_KILL,
393 HAL_STOP_TYPE_MAX = WCN36XX_HAL_MAX_ENUM_SIZE
394};
395
396enum wcn36xx_hal_sys_mode {
397 HAL_SYS_MODE_NORMAL,
398 HAL_SYS_MODE_LEARN,
399 HAL_SYS_MODE_SCAN,
400 HAL_SYS_MODE_PROMISC,
401 HAL_SYS_MODE_SUSPEND_LINK,
402 HAL_SYS_MODE_ROAM_SCAN,
403 HAL_SYS_MODE_ROAM_SUSPEND_LINK,
404 HAL_SYS_MODE_MAX = WCN36XX_HAL_MAX_ENUM_SIZE
405};
406
407enum phy_chan_bond_state {
408
409 PHY_SINGLE_CHANNEL_CENTERED = 0,
410
411
412 PHY_DOUBLE_CHANNEL_LOW_PRIMARY = 1,
413
414
415 PHY_DOUBLE_CHANNEL_CENTERED = 2,
416
417
418 PHY_DOUBLE_CHANNEL_HIGH_PRIMARY = 3,
419
420
421 PHY_QUADRUPLE_CHANNEL_20MHZ_LOW_40MHZ_CENTERED = 4,
422
423
424 PHY_QUADRUPLE_CHANNEL_20MHZ_CENTERED_40MHZ_CENTERED = 5,
425
426
427 PHY_QUADRUPLE_CHANNEL_20MHZ_HIGH_40MHZ_CENTERED = 6,
428
429
430 PHY_QUADRUPLE_CHANNEL_20MHZ_LOW_40MHZ_LOW = 7,
431
432
433 PHY_QUADRUPLE_CHANNEL_20MHZ_HIGH_40MHZ_LOW = 8,
434
435
436 PHY_QUADRUPLE_CHANNEL_20MHZ_LOW_40MHZ_HIGH = 9,
437
438
439 PHY_QUADRUPLE_CHANNEL_20MHZ_HIGH_40MHZ_HIGH = 10,
440
441 PHY_CHANNEL_BONDING_STATE_MAX = WCN36XX_HAL_MAX_ENUM_SIZE
442};
443
444
445enum wcn36xx_hal_ht_mimo_state {
446
447 WCN36XX_HAL_HT_MIMO_PS_STATIC = 0,
448
449
450 WCN36XX_HAL_HT_MIMO_PS_DYNAMIC = 1,
451
452
453 WCN36XX_HAL_HT_MIMO_PS_NA = 2,
454
455
456 WCN36XX_HAL_HT_MIMO_PS_NO_LIMIT = 3,
457
458 WCN36XX_HAL_HT_MIMO_PS_MAX = WCN36XX_HAL_MAX_ENUM_SIZE
459};
460
461
462enum sta_rate_mode {
463 STA_TAURUS = 0,
464 STA_TITAN,
465 STA_POLARIS,
466 STA_11b,
467 STA_11bg,
468 STA_11a,
469 STA_11n,
470 STA_11ac,
471 STA_INVALID_RATE_MODE = WCN36XX_HAL_MAX_ENUM_SIZE
472};
473
474
475#define WCN36XX_HAL_NUM_DSSS_RATES 4
476
477
478#define WCN36XX_HAL_NUM_OFDM_RATES 8
479
480
481#define WCN36XX_HAL_NUM_POLARIS_RATES 3
482
483#define WCN36XX_HAL_MAC_MAX_SUPPORTED_MCS_SET 16
484
485enum wcn36xx_hal_bss_type {
486 WCN36XX_HAL_INFRASTRUCTURE_MODE,
487
488
489 WCN36XX_HAL_INFRA_AP_MODE,
490
491 WCN36XX_HAL_IBSS_MODE,
492
493
494 WCN36XX_HAL_BTAMP_STA_MODE,
495
496
497 WCN36XX_HAL_BTAMP_AP_MODE,
498
499 WCN36XX_HAL_AUTO_MODE,
500
501 WCN36XX_HAL_DONOT_USE_BSS_TYPE = WCN36XX_HAL_MAX_ENUM_SIZE
502};
503
504enum wcn36xx_hal_nw_type {
505 WCN36XX_HAL_11A_NW_TYPE,
506 WCN36XX_HAL_11B_NW_TYPE,
507 WCN36XX_HAL_11G_NW_TYPE,
508 WCN36XX_HAL_11N_NW_TYPE,
509 WCN36XX_HAL_DONOT_USE_NW_TYPE = WCN36XX_HAL_MAX_ENUM_SIZE
510};
511
512#define WCN36XX_HAL_MAC_RATESET_EID_MAX 12
513
514enum wcn36xx_hal_ht_operating_mode {
515
516 WCN36XX_HAL_HT_OP_MODE_PURE,
517
518
519 WCN36XX_HAL_HT_OP_MODE_OVERLAP_LEGACY,
520
521
522 WCN36XX_HAL_HT_OP_MODE_NO_LEGACY_20MHZ_HT,
523
524
525 WCN36XX_HAL_HT_OP_MODE_MIXED,
526
527 WCN36XX_HAL_HT_OP_MODE_MAX = WCN36XX_HAL_MAX_ENUM_SIZE
528};
529
530
531enum ani_ed_type {
532 WCN36XX_HAL_ED_NONE,
533 WCN36XX_HAL_ED_WEP40,
534 WCN36XX_HAL_ED_WEP104,
535 WCN36XX_HAL_ED_TKIP,
536 WCN36XX_HAL_ED_CCMP,
537 WCN36XX_HAL_ED_WPI,
538 WCN36XX_HAL_ED_AES_128_CMAC,
539 WCN36XX_HAL_ED_NOT_IMPLEMENTED = WCN36XX_HAL_MAX_ENUM_SIZE
540};
541
542#define WLAN_MAX_KEY_RSC_LEN 16
543#define WLAN_WAPI_KEY_RSC_LEN 16
544
545
546#define WCN36XX_HAL_MAC_MAX_KEY_LENGTH 32
547#define WCN36XX_HAL_MAC_MAX_NUM_OF_DEFAULT_KEYS 4
548
549
550
551
552enum ani_key_direction {
553 WCN36XX_HAL_TX_ONLY,
554 WCN36XX_HAL_RX_ONLY,
555 WCN36XX_HAL_TX_RX,
556 WCN36XX_HAL_TX_DEFAULT,
557 WCN36XX_HAL_DONOT_USE_KEY_DIRECTION = WCN36XX_HAL_MAX_ENUM_SIZE
558};
559
560enum ani_wep_type {
561 WCN36XX_HAL_WEP_STATIC,
562 WCN36XX_HAL_WEP_DYNAMIC,
563 WCN36XX_HAL_WEP_MAX = WCN36XX_HAL_MAX_ENUM_SIZE
564};
565
566enum wcn36xx_hal_link_state {
567
568 WCN36XX_HAL_LINK_IDLE_STATE = 0,
569 WCN36XX_HAL_LINK_PREASSOC_STATE = 1,
570 WCN36XX_HAL_LINK_POSTASSOC_STATE = 2,
571 WCN36XX_HAL_LINK_AP_STATE = 3,
572 WCN36XX_HAL_LINK_IBSS_STATE = 4,
573
574
575 WCN36XX_HAL_LINK_BTAMP_PREASSOC_STATE = 5,
576 WCN36XX_HAL_LINK_BTAMP_POSTASSOC_STATE = 6,
577 WCN36XX_HAL_LINK_BTAMP_AP_STATE = 7,
578 WCN36XX_HAL_LINK_BTAMP_STA_STATE = 8,
579
580
581 WCN36XX_HAL_LINK_LEARN_STATE = 9,
582 WCN36XX_HAL_LINK_SCAN_STATE = 10,
583 WCN36XX_HAL_LINK_FINISH_SCAN_STATE = 11,
584 WCN36XX_HAL_LINK_INIT_CAL_STATE = 12,
585 WCN36XX_HAL_LINK_FINISH_CAL_STATE = 13,
586 WCN36XX_HAL_LINK_LISTEN_STATE = 14,
587
588 WCN36XX_HAL_LINK_MAX = WCN36XX_HAL_MAX_ENUM_SIZE
589};
590
591enum wcn36xx_hal_stats_mask {
592 HAL_SUMMARY_STATS_INFO = 0x00000001,
593 HAL_GLOBAL_CLASS_A_STATS_INFO = 0x00000002,
594 HAL_GLOBAL_CLASS_B_STATS_INFO = 0x00000004,
595 HAL_GLOBAL_CLASS_C_STATS_INFO = 0x00000008,
596 HAL_GLOBAL_CLASS_D_STATS_INFO = 0x00000010,
597 HAL_PER_STA_STATS_INFO = 0x00000020
598};
599
600
601enum bt_amp_event_type {
602 BTAMP_EVENT_CONNECTION_START,
603 BTAMP_EVENT_CONNECTION_STOP,
604 BTAMP_EVENT_CONNECTION_TERMINATED,
605
606
607 BTAMP_EVENT_TYPE_MAX = WCN36XX_HAL_MAX_ENUM_SIZE,
608};
609
610
611enum pe_stats_mask {
612 PE_SUMMARY_STATS_INFO = 0x00000001,
613 PE_GLOBAL_CLASS_A_STATS_INFO = 0x00000002,
614 PE_GLOBAL_CLASS_B_STATS_INFO = 0x00000004,
615 PE_GLOBAL_CLASS_C_STATS_INFO = 0x00000008,
616 PE_GLOBAL_CLASS_D_STATS_INFO = 0x00000010,
617 PE_PER_STA_STATS_INFO = 0x00000020,
618
619
620 PE_STATS_TYPE_MAX = WCN36XX_HAL_MAX_ENUM_SIZE
621};
622
623
624
625
626#define WCN36XX_HAL_CFG_STA_ID 0
627#define WCN36XX_HAL_CFG_CURRENT_TX_ANTENNA 1
628#define WCN36XX_HAL_CFG_CURRENT_RX_ANTENNA 2
629#define WCN36XX_HAL_CFG_LOW_GAIN_OVERRIDE 3
630#define WCN36XX_HAL_CFG_POWER_STATE_PER_CHAIN 4
631#define WCN36XX_HAL_CFG_CAL_PERIOD 5
632#define WCN36XX_HAL_CFG_CAL_CONTROL 6
633#define WCN36XX_HAL_CFG_PROXIMITY 7
634#define WCN36XX_HAL_CFG_NETWORK_DENSITY 8
635#define WCN36XX_HAL_CFG_MAX_MEDIUM_TIME 9
636#define WCN36XX_HAL_CFG_MAX_MPDUS_IN_AMPDU 10
637#define WCN36XX_HAL_CFG_RTS_THRESHOLD 11
638#define WCN36XX_HAL_CFG_SHORT_RETRY_LIMIT 12
639#define WCN36XX_HAL_CFG_LONG_RETRY_LIMIT 13
640#define WCN36XX_HAL_CFG_FRAGMENTATION_THRESHOLD 14
641#define WCN36XX_HAL_CFG_DYNAMIC_THRESHOLD_ZERO 15
642#define WCN36XX_HAL_CFG_DYNAMIC_THRESHOLD_ONE 16
643#define WCN36XX_HAL_CFG_DYNAMIC_THRESHOLD_TWO 17
644#define WCN36XX_HAL_CFG_FIXED_RATE 18
645#define WCN36XX_HAL_CFG_RETRYRATE_POLICY 19
646#define WCN36XX_HAL_CFG_RETRYRATE_SECONDARY 20
647#define WCN36XX_HAL_CFG_RETRYRATE_TERTIARY 21
648#define WCN36XX_HAL_CFG_FORCE_POLICY_PROTECTION 22
649#define WCN36XX_HAL_CFG_FIXED_RATE_MULTICAST_24GHZ 23
650#define WCN36XX_HAL_CFG_FIXED_RATE_MULTICAST_5GHZ 24
651#define WCN36XX_HAL_CFG_DEFAULT_RATE_INDEX_24GHZ 25
652#define WCN36XX_HAL_CFG_DEFAULT_RATE_INDEX_5GHZ 26
653#define WCN36XX_HAL_CFG_MAX_BA_SESSIONS 27
654#define WCN36XX_HAL_CFG_PS_DATA_INACTIVITY_TIMEOUT 28
655#define WCN36XX_HAL_CFG_PS_ENABLE_BCN_FILTER 29
656#define WCN36XX_HAL_CFG_PS_ENABLE_RSSI_MONITOR 30
657#define WCN36XX_HAL_CFG_NUM_BEACON_PER_RSSI_AVERAGE 31
658#define WCN36XX_HAL_CFG_STATS_PERIOD 32
659#define WCN36XX_HAL_CFG_CFP_MAX_DURATION 33
660#define WCN36XX_HAL_CFG_FRAME_TRANS_ENABLED 34
661#define WCN36XX_HAL_CFG_DTIM_PERIOD 35
662#define WCN36XX_HAL_CFG_EDCA_WMM_ACBK 36
663#define WCN36XX_HAL_CFG_EDCA_WMM_ACBE 37
664#define WCN36XX_HAL_CFG_EDCA_WMM_ACVO 38
665#define WCN36XX_HAL_CFG_EDCA_WMM_ACVI 39
666#define WCN36XX_HAL_CFG_BA_THRESHOLD_HIGH 40
667#define WCN36XX_HAL_CFG_MAX_BA_BUFFERS 41
668#define WCN36XX_HAL_CFG_RPE_POLLING_THRESHOLD 42
669#define WCN36XX_HAL_CFG_RPE_AGING_THRESHOLD_FOR_AC0_REG 43
670#define WCN36XX_HAL_CFG_RPE_AGING_THRESHOLD_FOR_AC1_REG 44
671#define WCN36XX_HAL_CFG_RPE_AGING_THRESHOLD_FOR_AC2_REG 45
672#define WCN36XX_HAL_CFG_RPE_AGING_THRESHOLD_FOR_AC3_REG 46
673#define WCN36XX_HAL_CFG_NO_OF_ONCHIP_REORDER_SESSIONS 47
674#define WCN36XX_HAL_CFG_PS_LISTEN_INTERVAL 48
675#define WCN36XX_HAL_CFG_PS_HEART_BEAT_THRESHOLD 49
676#define WCN36XX_HAL_CFG_PS_NTH_BEACON_FILTER 50
677#define WCN36XX_HAL_CFG_PS_MAX_PS_POLL 51
678#define WCN36XX_HAL_CFG_PS_MIN_RSSI_THRESHOLD 52
679#define WCN36XX_HAL_CFG_PS_RSSI_FILTER_PERIOD 53
680#define WCN36XX_HAL_CFG_PS_BROADCAST_FRAME_FILTER_ENABLE 54
681#define WCN36XX_HAL_CFG_PS_IGNORE_DTIM 55
682#define WCN36XX_HAL_CFG_PS_ENABLE_BCN_EARLY_TERM 56
683#define WCN36XX_HAL_CFG_DYNAMIC_PS_POLL_VALUE 57
684#define WCN36XX_HAL_CFG_PS_NULLDATA_AP_RESP_TIMEOUT 58
685#define WCN36XX_HAL_CFG_TELE_BCN_WAKEUP_EN 59
686#define WCN36XX_HAL_CFG_TELE_BCN_TRANS_LI 60
687#define WCN36XX_HAL_CFG_TELE_BCN_TRANS_LI_IDLE_BCNS 61
688#define WCN36XX_HAL_CFG_TELE_BCN_MAX_LI 62
689#define WCN36XX_HAL_CFG_TELE_BCN_MAX_LI_IDLE_BCNS 63
690#define WCN36XX_HAL_CFG_TX_PWR_CTRL_ENABLE 64
691#define WCN36XX_HAL_CFG_VALID_RADAR_CHANNEL_LIST 65
692#define WCN36XX_HAL_CFG_TX_POWER_24_20 66
693#define WCN36XX_HAL_CFG_TX_POWER_24_40 67
694#define WCN36XX_HAL_CFG_TX_POWER_50_20 68
695#define WCN36XX_HAL_CFG_TX_POWER_50_40 69
696#define WCN36XX_HAL_CFG_MCAST_BCAST_FILTER_SETTING 70
697#define WCN36XX_HAL_CFG_BCN_EARLY_TERM_WAKEUP_INTERVAL 71
698#define WCN36XX_HAL_CFG_MAX_TX_POWER_2_4 72
699#define WCN36XX_HAL_CFG_MAX_TX_POWER_5 73
700#define WCN36XX_HAL_CFG_INFRA_STA_KEEP_ALIVE_PERIOD 74
701#define WCN36XX_HAL_CFG_ENABLE_CLOSE_LOOP 75
702#define WCN36XX_HAL_CFG_BTC_EXECUTION_MODE 76
703#define WCN36XX_HAL_CFG_BTC_DHCP_BT_SLOTS_TO_BLOCK 77
704#define WCN36XX_HAL_CFG_BTC_A2DP_DHCP_BT_SUB_INTERVALS 78
705#define WCN36XX_HAL_CFG_PS_TX_INACTIVITY_TIMEOUT 79
706#define WCN36XX_HAL_CFG_WCNSS_API_VERSION 80
707#define WCN36XX_HAL_CFG_AP_KEEPALIVE_TIMEOUT 81
708#define WCN36XX_HAL_CFG_GO_KEEPALIVE_TIMEOUT 82
709#define WCN36XX_HAL_CFG_ENABLE_MC_ADDR_LIST 83
710#define WCN36XX_HAL_CFG_BTC_STATIC_LEN_INQ_BT 84
711#define WCN36XX_HAL_CFG_BTC_STATIC_LEN_PAGE_BT 85
712#define WCN36XX_HAL_CFG_BTC_STATIC_LEN_CONN_BT 86
713#define WCN36XX_HAL_CFG_BTC_STATIC_LEN_LE_BT 87
714#define WCN36XX_HAL_CFG_BTC_STATIC_LEN_INQ_WLAN 88
715#define WCN36XX_HAL_CFG_BTC_STATIC_LEN_PAGE_WLAN 89
716#define WCN36XX_HAL_CFG_BTC_STATIC_LEN_CONN_WLAN 90
717#define WCN36XX_HAL_CFG_BTC_STATIC_LEN_LE_WLAN 91
718#define WCN36XX_HAL_CFG_BTC_DYN_MAX_LEN_BT 92
719#define WCN36XX_HAL_CFG_BTC_DYN_MAX_LEN_WLAN 93
720#define WCN36XX_HAL_CFG_BTC_MAX_SCO_BLOCK_PERC 94
721#define WCN36XX_HAL_CFG_BTC_DHCP_PROT_ON_A2DP 95
722#define WCN36XX_HAL_CFG_BTC_DHCP_PROT_ON_SCO 96
723#define WCN36XX_HAL_CFG_ENABLE_UNICAST_FILTER 97
724#define WCN36XX_HAL_CFG_MAX_ASSOC_LIMIT 98
725#define WCN36XX_HAL_CFG_ENABLE_LPWR_IMG_TRANSITION 99
726#define WCN36XX_HAL_CFG_ENABLE_MCC_ADAPTIVE_SCHEDULER 100
727#define WCN36XX_HAL_CFG_ENABLE_DETECT_PS_SUPPORT 101
728#define WCN36XX_HAL_CFG_AP_LINK_MONITOR_TIMEOUT 102
729#define WCN36XX_HAL_CFG_BTC_DWELL_TIME_MULTIPLIER 103
730#define WCN36XX_HAL_CFG_ENABLE_TDLS_OXYGEN_MODE 104
731#define WCN36XX_HAL_CFG_ENABLE_NAT_KEEP_ALIVE_FILTER 105
732#define WCN36XX_HAL_CFG_ENABLE_SAP_OBSS_PROT 106
733#define WCN36XX_HAL_CFG_PSPOLL_DATA_RECEP_TIMEOUT 107
734#define WCN36XX_HAL_CFG_TDLS_PUAPSD_BUFFER_STA_CAPABLE 108
735#define WCN36XX_HAL_CFG_TDLS_PUAPSD_MASK 109
736#define WCN36XX_HAL_CFG_TDLS_PUAPSD_INACTIVITY_TIME 110
737#define WCN36XX_HAL_CFG_TDLS_PUAPSD_RX_FRAME_THRESHOLD 111
738#define WCN36XX_HAL_CFG_ANTENNA_DIVERSITY 112
739#define WCN36XX_HAL_CFG_ATH_DISABLE 113
740#define WCN36XX_HAL_CFG_FLEXCONNECT_POWER_FACTOR 114
741#define WCN36XX_HAL_CFG_ENABLE_ADAPTIVE_RX_DRAIN 115
742#define WCN36XX_HAL_CFG_TDLS_OFF_CHANNEL_CAPABLE 116
743#define WCN36XX_HAL_CFG_MWS_COEX_V1_WAN_FREQ 117
744#define WCN36XX_HAL_CFG_MWS_COEX_V1_WLAN_FREQ 118
745#define WCN36XX_HAL_CFG_MWS_COEX_V1_CONFIG 119
746#define WCN36XX_HAL_CFG_MWS_COEX_V1_CONFIG2 120
747#define WCN36XX_HAL_CFG_MWS_COEX_V2_WAN_FREQ 121
748#define WCN36XX_HAL_CFG_MWS_COEX_V2_WLAN_FREQ 122
749#define WCN36XX_HAL_CFG_MWS_COEX_V2_CONFIG 123
750#define WCN36XX_HAL_CFG_MWS_COEX_V2_CONFIG2 124
751#define WCN36XX_HAL_CFG_MWS_COEX_V3_WAN_FREQ 125
752#define WCN36XX_HAL_CFG_MWS_COEX_V3_WLAN_FREQ 126
753#define WCN36XX_HAL_CFG_MWS_COEX_V3_CONFIG 127
754#define WCN36XX_HAL_CFG_MWS_COEX_V3_CONFIG2 128
755#define WCN36XX_HAL_CFG_MWS_COEX_V4_WAN_FREQ 129
756#define WCN36XX_HAL_CFG_MWS_COEX_V4_WLAN_FREQ 130
757#define WCN36XX_HAL_CFG_MWS_COEX_V4_CONFIG 131
758#define WCN36XX_HAL_CFG_MWS_COEX_V4_CONFIG2 132
759#define WCN36XX_HAL_CFG_MWS_COEX_V5_WAN_FREQ 133
760#define WCN36XX_HAL_CFG_MWS_COEX_V5_WLAN_FREQ 134
761#define WCN36XX_HAL_CFG_MWS_COEX_V5_CONFIG 135
762#define WCN36XX_HAL_CFG_MWS_COEX_V5_CONFIG2 136
763#define WCN36XX_HAL_CFG_MWS_COEX_V6_WAN_FREQ 137
764#define WCN36XX_HAL_CFG_MWS_COEX_V6_WLAN_FREQ 138
765#define WCN36XX_HAL_CFG_MWS_COEX_V6_CONFIG 139
766#define WCN36XX_HAL_CFG_MWS_COEX_V6_CONFIG2 140
767#define WCN36XX_HAL_CFG_MWS_COEX_V7_WAN_FREQ 141
768#define WCN36XX_HAL_CFG_MWS_COEX_V7_WLAN_FREQ 142
769#define WCN36XX_HAL_CFG_MWS_COEX_V7_CONFIG 143
770#define WCN36XX_HAL_CFG_MWS_COEX_V7_CONFIG2 144
771#define WCN36XX_HAL_CFG_MWS_COEX_V8_WAN_FREQ 145
772#define WCN36XX_HAL_CFG_MWS_COEX_V8_WLAN_FREQ 146
773#define WCN36XX_HAL_CFG_MWS_COEX_V8_CONFIG 147
774#define WCN36XX_HAL_CFG_MWS_COEX_V8_CONFIG2 148
775#define WCN36XX_HAL_CFG_MWS_COEX_V9_WAN_FREQ 149
776#define WCN36XX_HAL_CFG_MWS_COEX_V9_WLAN_FREQ 150
777#define WCN36XX_HAL_CFG_MWS_COEX_V9_CONFIG 151
778#define WCN36XX_HAL_CFG_MWS_COEX_V9_CONFIG2 152
779#define WCN36XX_HAL_CFG_MWS_COEX_V10_WAN_FREQ 153
780#define WCN36XX_HAL_CFG_MWS_COEX_V10_WLAN_FREQ 154
781#define WCN36XX_HAL_CFG_MWS_COEX_V10_CONFIG 155
782#define WCN36XX_HAL_CFG_MWS_COEX_V10_CONFIG2 156
783#define WCN36XX_HAL_CFG_MWS_COEX_MODEM_BACKOFF 157
784#define WCN36XX_HAL_CFG_MWS_COEX_CONFIG1 158
785#define WCN36XX_HAL_CFG_MWS_COEX_CONFIG2 159
786#define WCN36XX_HAL_CFG_MWS_COEX_CONFIG3 160
787#define WCN36XX_HAL_CFG_MWS_COEX_CONFIG4 161
788#define WCN36XX_HAL_CFG_MWS_COEX_CONFIG5 162
789#define WCN36XX_HAL_CFG_MWS_COEX_CONFIG6 163
790#define WCN36XX_HAL_CFG_SAR_POWER_BACKOFF 164
791#define WCN36XX_HAL_CFG_GO_LINK_MONITOR_TIMEOUT 165
792#define WCN36XX_HAL_CFG_BTC_STATIC_OPP_WLAN_ACTIVE_WLAN_LEN 166
793#define WCN36XX_HAL_CFG_BTC_STATIC_OPP_WLAN_ACTIVE_BT_LEN 167
794#define WCN36XX_HAL_CFG_BTC_SAP_STATIC_OPP_ACTIVE_WLAN_LEN 168
795#define WCN36XX_HAL_CFG_BTC_SAP_STATIC_OPP_ACTIVE_BT_LEN 169
796#define WCN36XX_HAL_CFG_RMC_FIXED_RATE 170
797#define WCN36XX_HAL_CFG_ASD_PROBE_INTERVAL 171
798#define WCN36XX_HAL_CFG_ASD_TRIGGER_THRESHOLD 172
799#define WCN36XX_HAL_CFG_ASD_RTT_RSSI_HYST_THRESHOLD 173
800#define WCN36XX_HAL_CFG_BTC_CTS2S_ON_STA_DURING_SCO 174
801#define WCN36XX_HAL_CFG_SHORT_PREAMBLE 175
802#define WCN36XX_HAL_CFG_SHORT_SLOT_TIME 176
803#define WCN36XX_HAL_CFG_DELAYED_BA 177
804#define WCN36XX_HAL_CFG_IMMEDIATE_BA 178
805#define WCN36XX_HAL_CFG_DOT11_MODE 179
806#define WCN36XX_HAL_CFG_HT_CAPS 180
807#define WCN36XX_HAL_CFG_AMPDU_PARAMS 181
808#define WCN36XX_HAL_CFG_TX_BF_INFO 182
809#define WCN36XX_HAL_CFG_ASC_CAP_INFO 183
810#define WCN36XX_HAL_CFG_EXT_HT_CAPS 184
811#define WCN36XX_HAL_CFG_QOS_ENABLED 185
812#define WCN36XX_HAL_CFG_WME_ENABLED 186
813#define WCN36XX_HAL_CFG_WSM_ENABLED 187
814#define WCN36XX_HAL_CFG_WMM_ENABLED 188
815#define WCN36XX_HAL_CFG_UAPSD_PER_AC_BITMASK 189
816#define WCN36XX_HAL_CFG_MCS_RATES 190
817#define WCN36XX_HAL_CFG_VHT_CAPS 191
818#define WCN36XX_HAL_CFG_VHT_RX_SUPP_MCS 192
819#define WCN36XX_HAL_CFG_VHT_TX_SUPP_MCS 193
820#define WCN36XX_HAL_CFG_RA_FILTER_ENABLE 194
821#define WCN36XX_HAL_CFG_RA_RATE_LIMIT_INTERVAL 195
822#define WCN36XX_HAL_CFG_BTC_FATAL_HID_NSNIFF_BLK 196
823#define WCN36XX_HAL_CFG_BTC_CRITICAL_HID_NSNIFF_BLK 197
824#define WCN36XX_HAL_CFG_BTC_DYN_A2DP_TX_QUEUE_THOLD 198
825#define WCN36XX_HAL_CFG_BTC_DYN_OPP_TX_QUEUE_THOLD 199
826#define WCN36XX_HAL_CFG_LINK_FAIL_TIMEOUT 200
827#define WCN36XX_HAL_CFG_MAX_UAPSD_CONSEC_SP 201
828#define WCN36XX_HAL_CFG_MAX_UAPSD_CONSEC_RX_CNT 202
829#define WCN36XX_HAL_CFG_MAX_UAPSD_CONSEC_TX_CNT 203
830#define WCN36XX_HAL_CFG_MAX_UAPSD_CONSEC_RX_CNT_MEAS_WINDOW 204
831#define WCN36XX_HAL_CFG_MAX_UAPSD_CONSEC_TX_CNT_MEAS_WINDOW 205
832#define WCN36XX_HAL_CFG_MAX_PSPOLL_IN_WMM_UAPSD_PS_MODE 206
833#define WCN36XX_HAL_CFG_MAX_UAPSD_INACTIVITY_INTERVALS 207
834#define WCN36XX_HAL_CFG_ENABLE_DYNAMIC_WMMPS 208
835#define WCN36XX_HAL_CFG_BURST_MODE_BE_TXOP_VALUE 209
836#define WCN36XX_HAL_CFG_ENABLE_DYNAMIC_RA_START_RATE 210
837#define WCN36XX_HAL_CFG_BTC_FAST_WLAN_CONN_PREF 211
838#define WCN36XX_HAL_CFG_ENABLE_RTSCTS_HTVHT 212
839#define WCN36XX_HAL_CFG_BTC_STATIC_OPP_WLAN_IDLE_WLAN_LEN 213
840#define WCN36XX_HAL_CFG_BTC_STATIC_OPP_WLAN_IDLE_BT_LEN 214
841#define WCN36XX_HAL_CFG_LINK_FAIL_TX_CNT 215
842#define WCN36XX_HAL_CFG_TOGGLE_ARP_BDRATES 216
843#define WCN36XX_HAL_CFG_OPTIMIZE_CA_EVENT 217
844#define WCN36XX_HAL_CFG_EXT_SCAN_CONC_MODE 218
845#define WCN36XX_HAL_CFG_BAR_WAKEUP_HOST_DISABLE 219
846#define WCN36XX_HAL_CFG_SAR_BOFFSET_CORRECTION_ENABLE 220
847#define WCN36XX_HAL_CFG_UNITS_OF_BCN_WAIT_TIME 221
848#define WCN36XX_HAL_CFG_CONS_BCNMISS_COUNT 222
849#define WCN36XX_HAL_CFG_BTC_DISABLE_WLAN_LINK_CRITICAL 223
850#define WCN36XX_HAL_CFG_DISABLE_SCAN_DURING_SCO 224
851#define WCN36XX_HAL_CFG_TRIGGER_NULLFRAME_BEFORE_HB 225
852#define WCN36XX_HAL_CFG_ENABLE_POWERSAVE_OFFLOAD 226
853#define WCN36XX_HAL_CFG_MAX_PARAMS 227
854
855
856
857
858
859
860
861#define WCN36XX_HAL_CFG_ENABLE_DYNAMIC_RA_START_RATE 210
862
863
864
865
866struct wcnss_wlan_version {
867 u8 revision;
868 u8 version;
869 u8 minor;
870 u8 major;
871} __packed;
872
873
874struct wcn36xx_hal_keys {
875 u8 id;
876
877
878 u8 unicast;
879
880 enum ani_key_direction direction;
881
882
883 u8 rsc[WLAN_MAX_KEY_RSC_LEN];
884
885
886 u8 pae_role;
887
888 u16 length;
889 u8 key[WCN36XX_HAL_MAC_MAX_KEY_LENGTH];
890} __packed;
891
892
893
894
895
896struct wcn36xx_hal_set_sta_key_params {
897
898 u16 sta_index;
899
900
901 enum ani_ed_type enc_type;
902
903
904 enum ani_wep_type wep_type;
905
906
907 u8 def_wep_idx;
908
909
910 struct wcn36xx_hal_keys key[WCN36XX_HAL_MAC_MAX_NUM_OF_DEFAULT_KEYS];
911
912
913
914
915
916 u8 single_tid_rc;
917
918} __packed;
919
920
921struct wcn36xx_hal_msg_header {
922 enum wcn36xx_hal_host_msg_type msg_type:16;
923 enum wcn36xx_hal_host_msg_version msg_version:16;
924 u32 len;
925} __packed;
926
927
928struct wcn36xx_hal_cfg {
929
930
931 u16 id;
932
933
934
935 u16 len;
936
937
938 u16 pad_bytes;
939
940
941 u16 reserve;
942
943
944
945} __packed;
946
947struct wcn36xx_hal_mac_start_parameters {
948
949 enum driver_type type;
950
951
952 u32 len;
953
954
955
956
957
958
959
960} __packed;
961
962struct wcn36xx_hal_mac_start_req_msg {
963
964 struct wcn36xx_hal_msg_header header;
965 struct wcn36xx_hal_mac_start_parameters params;
966} __packed;
967
968struct wcn36xx_hal_mac_start_rsp_params {
969
970 u16 status;
971
972
973 u8 stations;
974
975
976 u8 bssids;
977
978
979 struct wcnss_wlan_version version;
980
981
982 u8 crm_version[WCN36XX_HAL_VERSION_LENGTH];
983
984
985 u8 wlan_version[WCN36XX_HAL_VERSION_LENGTH];
986
987} __packed;
988
989struct wcn36xx_hal_mac_start_rsp_msg {
990 struct wcn36xx_hal_msg_header header;
991 struct wcn36xx_hal_mac_start_rsp_params start_rsp_params;
992} __packed;
993
994struct wcn36xx_hal_mac_stop_req_params {
995
996 enum wcn36xx_hal_stop_type reason;
997
998} __packed;
999
1000struct wcn36xx_hal_mac_stop_req_msg {
1001 struct wcn36xx_hal_msg_header header;
1002 struct wcn36xx_hal_mac_stop_req_params stop_req_params;
1003} __packed;
1004
1005struct wcn36xx_hal_mac_stop_rsp_msg {
1006 struct wcn36xx_hal_msg_header header;
1007
1008
1009 u32 status;
1010} __packed;
1011
1012struct wcn36xx_hal_update_cfg_req_msg {
1013
1014
1015
1016
1017 struct wcn36xx_hal_msg_header header;
1018
1019
1020 u32 len;
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030} __packed;
1031
1032struct wcn36xx_hal_update_cfg_rsp_msg {
1033 struct wcn36xx_hal_msg_header header;
1034
1035
1036 u32 status;
1037
1038} __packed;
1039
1040
1041struct wcn36xx_hal_mac_frame_ctl {
1042
1043#ifndef ANI_LITTLE_BIT_ENDIAN
1044
1045 u8 subType:4;
1046 u8 type:2;
1047 u8 protVer:2;
1048
1049 u8 order:1;
1050 u8 wep:1;
1051 u8 moreData:1;
1052 u8 powerMgmt:1;
1053 u8 retry:1;
1054 u8 moreFrag:1;
1055 u8 fromDS:1;
1056 u8 toDS:1;
1057
1058#else
1059
1060 u8 protVer:2;
1061 u8 type:2;
1062 u8 subType:4;
1063
1064 u8 toDS:1;
1065 u8 fromDS:1;
1066 u8 moreFrag:1;
1067 u8 retry:1;
1068 u8 powerMgmt:1;
1069 u8 moreData:1;
1070 u8 wep:1;
1071 u8 order:1;
1072
1073#endif
1074
1075};
1076
1077
1078struct wcn36xx_hal_mac_seq_ctl {
1079 u8 fragNum:4;
1080 u8 seqNumLo:4;
1081 u8 seqNumHi:8;
1082};
1083
1084
1085struct wcn36xx_hal_mac_mgmt_hdr {
1086 struct wcn36xx_hal_mac_frame_ctl fc;
1087 u8 durationLo;
1088 u8 durationHi;
1089 u8 da[6];
1090 u8 sa[6];
1091 u8 bssId[6];
1092 struct wcn36xx_hal_mac_seq_ctl seqControl;
1093};
1094
1095
1096#define WCN36XX_HAL_NUM_BSSID 2
1097
1098
1099struct wcn36xx_hal_scan_entry {
1100 u8 bss_index[WCN36XX_HAL_NUM_BSSID];
1101 u8 active_bss_count;
1102};
1103
1104struct wcn36xx_hal_init_scan_req_msg {
1105 struct wcn36xx_hal_msg_header header;
1106
1107
1108
1109 enum wcn36xx_hal_sys_mode mode;
1110
1111
1112 u8 bssid[ETH_ALEN];
1113
1114
1115 u8 notify;
1116
1117
1118
1119 u8 frame_type;
1120
1121
1122
1123
1124
1125 u8 frame_len;
1126
1127
1128
1129 struct wcn36xx_hal_mac_mgmt_hdr mac_mgmt_hdr;
1130
1131
1132 struct wcn36xx_hal_scan_entry scan_entry;
1133};
1134
1135struct wcn36xx_hal_init_scan_con_req_msg {
1136 struct wcn36xx_hal_msg_header header;
1137
1138
1139
1140 enum wcn36xx_hal_sys_mode mode;
1141
1142
1143 u8 bssid[ETH_ALEN];
1144
1145
1146 u8 notify;
1147
1148
1149
1150 u8 frame_type;
1151
1152
1153
1154
1155
1156 u8 frame_length;
1157
1158
1159
1160 struct wcn36xx_hal_mac_mgmt_hdr mac_mgmt_hdr;
1161
1162
1163 struct wcn36xx_hal_scan_entry scan_entry;
1164
1165
1166 u8 use_noa;
1167
1168
1169 u16 scan_duration;
1170
1171};
1172
1173struct wcn36xx_hal_init_scan_rsp_msg {
1174 struct wcn36xx_hal_msg_header header;
1175
1176
1177 u32 status;
1178
1179} __packed;
1180
1181struct wcn36xx_hal_start_scan_req_msg {
1182 struct wcn36xx_hal_msg_header header;
1183
1184
1185 u8 scan_channel;
1186} __packed;
1187
1188struct wcn36xx_hal_start_rsp_msg {
1189 struct wcn36xx_hal_msg_header header;
1190
1191
1192 u32 status;
1193
1194 u32 start_tsf[2];
1195 u8 tx_mgmt_power;
1196
1197} __packed;
1198
1199struct wcn36xx_hal_end_scan_req_msg {
1200 struct wcn36xx_hal_msg_header header;
1201
1202
1203
1204
1205 u8 scan_channel;
1206} __packed;
1207
1208struct wcn36xx_hal_end_scan_rsp_msg {
1209 struct wcn36xx_hal_msg_header header;
1210
1211
1212 u32 status;
1213} __packed;
1214
1215struct wcn36xx_hal_finish_scan_req_msg {
1216 struct wcn36xx_hal_msg_header header;
1217
1218
1219
1220 enum wcn36xx_hal_sys_mode mode;
1221
1222
1223 u8 oper_channel;
1224
1225
1226
1227
1228 enum phy_chan_bond_state cb_state;
1229
1230
1231 u8 bssid[ETH_ALEN];
1232
1233
1234 u8 notify;
1235
1236
1237
1238 u8 frame_type;
1239
1240
1241
1242
1243
1244 u8 frame_length;
1245
1246
1247
1248 struct wcn36xx_hal_mac_mgmt_hdr mac_mgmt_hdr;
1249
1250
1251 struct wcn36xx_hal_scan_entry scan_entry;
1252
1253} __packed;
1254
1255struct wcn36xx_hal_finish_scan_rsp_msg {
1256 struct wcn36xx_hal_msg_header header;
1257
1258
1259 u32 status;
1260
1261} __packed;
1262
1263enum wcn36xx_hal_scan_type {
1264 WCN36XX_HAL_SCAN_TYPE_PASSIVE = 0x00,
1265 WCN36XX_HAL_SCAN_TYPE_ACTIVE = WCN36XX_HAL_MAX_ENUM_SIZE
1266};
1267
1268struct wcn36xx_hal_mac_ssid {
1269 u8 length;
1270 u8 ssid[32];
1271} __packed;
1272
1273struct wcn36xx_hal_start_scan_offload_req_msg {
1274 struct wcn36xx_hal_msg_header header;
1275
1276
1277 u8 num_bssid;
1278 u8 bssids[4][ETH_ALEN];
1279
1280
1281 u8 num_ssid;
1282 struct wcn36xx_hal_mac_ssid ssids[10];
1283
1284
1285 u8 scan_hidden;
1286
1287
1288 u8 mac[ETH_ALEN];
1289
1290
1291 enum wcn36xx_hal_bss_type bss_type;
1292
1293
1294 enum wcn36xx_hal_scan_type scan_type;
1295
1296
1297 u32 min_ch_time;
1298
1299
1300 u32 max_ch_time;
1301
1302
1303 u8 p2p_search;
1304
1305
1306 u8 num_channel;
1307 u8 channels[80];
1308
1309
1310 u16 ie_len;
1311 u8 ie[WCN36XX_MAX_SCAN_IE_LEN];
1312} __packed;
1313
1314struct wcn36xx_hal_start_scan_offload_rsp_msg {
1315 struct wcn36xx_hal_msg_header header;
1316
1317
1318 u32 status;
1319} __packed;
1320
1321enum wcn36xx_hal_scan_offload_ind_type {
1322
1323 WCN36XX_HAL_SCAN_IND_STARTED = 0x01,
1324
1325 WCN36XX_HAL_SCAN_IND_COMPLETED = 0x02,
1326
1327 WCN36XX_HAL_SCAN_IND_FOREIGN_CHANNEL = 0x08,
1328
1329 WCN36XX_HAL_SCAN_IND_DEQUEUED = 0x10,
1330
1331 WCN36XX_HAL_SCAN_IND_PREEMPTED = 0x20,
1332
1333 WCN36XX_HAL_SCAN_IND_FAILED = 0x40,
1334
1335 WCN36XX_HAL_SCAN_IND_RESTARTED = 0x80,
1336 WCN36XX_HAL_SCAN_IND_MAX = WCN36XX_HAL_MAX_ENUM_SIZE
1337};
1338
1339struct wcn36xx_hal_scan_offload_ind {
1340 struct wcn36xx_hal_msg_header header;
1341
1342 u32 type;
1343 u32 channel_mhz;
1344 u32 scan_id;
1345} __packed;
1346
1347struct wcn36xx_hal_stop_scan_offload_req_msg {
1348 struct wcn36xx_hal_msg_header header;
1349} __packed;
1350
1351struct wcn36xx_hal_stop_scan_offload_rsp_msg {
1352 struct wcn36xx_hal_msg_header header;
1353
1354
1355 u32 status;
1356} __packed;
1357
1358#define WCN36XX_HAL_CHAN_REG1_MIN_PWR_MASK 0x000000ff
1359#define WCN36XX_HAL_CHAN_REG1_MAX_PWR_MASK 0x0000ff00
1360#define WCN36XX_HAL_CHAN_REG1_REG_PWR_MASK 0x00ff0000
1361#define WCN36XX_HAL_CHAN_REG1_CLASS_ID_MASK 0xff000000
1362#define WCN36XX_HAL_CHAN_REG2_ANT_GAIN_MASK 0x000000ff
1363#define WCN36XX_HAL_CHAN_INFO_FLAG_PASSIVE BIT(7)
1364#define WCN36XX_HAL_CHAN_INFO_FLAG_DFS BIT(10)
1365#define WCN36XX_HAL_CHAN_INFO_FLAG_HT BIT(11)
1366#define WCN36XX_HAL_CHAN_INFO_FLAG_VHT BIT(12)
1367#define WCN36XX_HAL_CHAN_INFO_PHY_11A 0
1368#define WCN36XX_HAL_CHAN_INFO_PHY_11BG 1
1369#define WCN36XX_HAL_DEFAULT_ANT_GAIN 6
1370#define WCN36XX_HAL_DEFAULT_MIN_POWER 6
1371
1372struct wcn36xx_hal_channel_param {
1373 u32 mhz;
1374 u32 band_center_freq1;
1375 u32 band_center_freq2;
1376 u32 channel_info;
1377 u32 reg_info_1;
1378 u32 reg_info_2;
1379} __packed;
1380
1381struct wcn36xx_hal_update_channel_list_req_msg {
1382 struct wcn36xx_hal_msg_header header;
1383
1384 u8 num_channel;
1385 struct wcn36xx_hal_channel_param channels[80];
1386} __packed;
1387
1388enum wcn36xx_hal_rate_index {
1389 HW_RATE_INDEX_1MBPS = 0x82,
1390 HW_RATE_INDEX_2MBPS = 0x84,
1391 HW_RATE_INDEX_5_5MBPS = 0x8B,
1392 HW_RATE_INDEX_6MBPS = 0x0C,
1393 HW_RATE_INDEX_9MBPS = 0x12,
1394 HW_RATE_INDEX_11MBPS = 0x96,
1395 HW_RATE_INDEX_12MBPS = 0x18,
1396 HW_RATE_INDEX_18MBPS = 0x24,
1397 HW_RATE_INDEX_24MBPS = 0x30,
1398 HW_RATE_INDEX_36MBPS = 0x48,
1399 HW_RATE_INDEX_48MBPS = 0x60,
1400 HW_RATE_INDEX_54MBPS = 0x6C
1401};
1402
1403struct wcn36xx_hal_supported_rates {
1404
1405
1406
1407
1408
1409
1410
1411
1412
1413
1414
1415
1416
1417
1418
1419
1420
1421
1422
1423 enum sta_rate_mode op_rate_mode;
1424
1425
1426
1427 u16 dsss_rates[WCN36XX_HAL_NUM_DSSS_RATES];
1428 u16 ofdm_rates[WCN36XX_HAL_NUM_OFDM_RATES];
1429 u16 legacy_rates[WCN36XX_HAL_NUM_POLARIS_RATES];
1430 u16 reserved;
1431
1432
1433
1434
1435
1436
1437 u32 enhanced_rate_bitmap;
1438
1439
1440
1441
1442
1443 u8 supported_mcs_set[WCN36XX_HAL_MAC_MAX_SUPPORTED_MCS_SET];
1444
1445
1446
1447
1448
1449
1450
1451 u16 rx_highest_data_rate;
1452
1453} __packed;
1454
1455struct wcn36xx_hal_config_sta_params {
1456
1457 u8 bssid[ETH_ALEN];
1458
1459
1460 u16 aid;
1461
1462
1463 u8 type;
1464
1465
1466 u8 short_preamble_supported;
1467
1468
1469 u8 mac[ETH_ALEN];
1470
1471
1472 u16 listen_interval;
1473
1474
1475 u8 wmm_enabled;
1476
1477
1478 u8 ht_capable;
1479
1480
1481 u8 tx_channel_width_set;
1482
1483
1484 u8 rifs_mode;
1485
1486
1487
1488
1489 u8 lsig_txop_protection;
1490
1491
1492
1493 u8 max_ampdu_size;
1494
1495
1496 u8 max_ampdu_density;
1497
1498
1499 u8 max_amsdu_size;
1500
1501
1502 u8 sgi_40mhz;
1503
1504
1505 u8 sgi_20Mhz;
1506
1507
1508
1509 struct wcn36xx_hal_supported_rates supported_rates;
1510
1511
1512 u8 rmf;
1513
1514
1515 u32 encrypt_type;
1516
1517
1518
1519
1520 u8 action;
1521
1522
1523
1524
1525 u8 uapsd;
1526
1527
1528 u8 max_sp_len;
1529
1530
1531
1532 u8 green_field_capable;
1533
1534
1535 enum wcn36xx_hal_ht_mimo_state mimo_ps;
1536
1537
1538 u8 delayed_ba_support;
1539
1540
1541 u8 max_ampdu_duration;
1542
1543
1544
1545
1546
1547 u8 dsss_cck_mode_40mhz;
1548
1549
1550
1551 u8 sta_index;
1552
1553
1554
1555
1556 u8 bssid_index;
1557
1558 u8 p2p;
1559
1560
1561
1562
1563} __packed;
1564
1565struct wcn36xx_hal_config_sta_req_msg {
1566 struct wcn36xx_hal_msg_header header;
1567 struct wcn36xx_hal_config_sta_params sta_params;
1568} __packed;
1569
1570struct wcn36xx_hal_supported_rates_v1 {
1571
1572
1573
1574
1575
1576
1577
1578
1579
1580
1581
1582
1583
1584
1585
1586
1587
1588
1589 enum sta_rate_mode op_rate_mode;
1590
1591
1592
1593
1594 u16 dsss_rates[WCN36XX_HAL_NUM_DSSS_RATES];
1595 u16 ofdm_rates[WCN36XX_HAL_NUM_OFDM_RATES];
1596 u16 legacy_rates[WCN36XX_HAL_NUM_POLARIS_RATES];
1597 u16 reserved;
1598
1599
1600
1601
1602
1603
1604
1605 u32 enhanced_rate_bitmap;
1606
1607
1608
1609
1610 u8 supported_mcs_set[WCN36XX_HAL_MAC_MAX_SUPPORTED_MCS_SET];
1611
1612
1613
1614
1615
1616
1617 u16 rx_highest_data_rate;
1618
1619
1620
1621
1622 u16 vht_rx_mcs_map;
1623
1624
1625
1626
1627 u16 vht_rx_highest_data_rate;
1628
1629
1630
1631
1632 u16 vht_tx_mcs_map;
1633
1634
1635
1636
1637 u16 vht_tx_highest_data_rate;
1638} __packed;
1639
1640struct wcn36xx_hal_config_sta_params_v1 {
1641
1642 u8 bssid[ETH_ALEN];
1643
1644
1645 u16 aid;
1646
1647
1648 u8 type;
1649
1650
1651 u8 short_preamble_supported;
1652
1653
1654 u8 mac[ETH_ALEN];
1655
1656
1657 u16 listen_interval;
1658
1659
1660 u8 wmm_enabled;
1661
1662
1663 u8 ht_capable;
1664
1665
1666 u8 tx_channel_width_set;
1667
1668
1669 u8 rifs_mode;
1670
1671
1672
1673
1674 u8 lsig_txop_protection;
1675
1676
1677
1678 u8 max_ampdu_size;
1679
1680
1681 u8 max_ampdu_density;
1682
1683
1684 u8 max_amsdu_size;
1685
1686
1687 u8 sgi_40mhz;
1688
1689
1690 u8 sgi_20Mhz;
1691
1692
1693 u8 rmf;
1694
1695
1696 u32 encrypt_type;
1697
1698
1699
1700
1701 u8 action;
1702
1703
1704
1705
1706 u8 uapsd;
1707
1708
1709 u8 max_sp_len;
1710
1711
1712
1713 u8 green_field_capable;
1714
1715
1716 enum wcn36xx_hal_ht_mimo_state mimo_ps;
1717
1718
1719 u8 delayed_ba_support;
1720
1721
1722 u8 max_ampdu_duration;
1723
1724
1725
1726
1727
1728 u8 dsss_cck_mode_40mhz;
1729
1730
1731
1732 u8 sta_index;
1733
1734
1735
1736
1737 u8 bssid_index;
1738
1739 u8 p2p;
1740
1741
1742 u8 ht_ldpc_enabled:1;
1743 u8 vht_ldpc_enabled:1;
1744 u8 vht_tx_bf_enabled:1;
1745 u8 vht_tx_mu_beamformee_capable:1;
1746 u8 reserved:4;
1747
1748
1749 struct wcn36xx_hal_supported_rates_v1 supported_rates;
1750
1751 u8 vht_capable;
1752 u8 vht_tx_channel_width_set;
1753
1754} __packed;
1755
1756#define WCN36XX_DIFF_STA_PARAMS_V1_NOVHT 10
1757
1758struct wcn36xx_hal_config_sta_req_msg_v1 {
1759 struct wcn36xx_hal_msg_header header;
1760 struct wcn36xx_hal_config_sta_params_v1 sta_params;
1761} __packed;
1762
1763struct config_sta_rsp_params {
1764
1765 u32 status;
1766
1767
1768 u8 sta_index;
1769
1770
1771 u8 bssid_index;
1772
1773
1774 u8 dpu_index;
1775
1776
1777 u8 bcast_dpu_index;
1778
1779
1780 u8 bcast_mgmt_dpu_idx;
1781
1782
1783 u8 uc_ucast_sig;
1784
1785
1786 u8 uc_bcast_sig;
1787
1788
1789 u8 uc_mgmt_sig;
1790
1791 u8 p2p;
1792
1793} __packed;
1794
1795struct wcn36xx_hal_config_sta_rsp_msg {
1796 struct wcn36xx_hal_msg_header header;
1797
1798 struct config_sta_rsp_params params;
1799} __packed;
1800
1801
1802struct wcn36xx_hal_delete_sta_req_msg {
1803 struct wcn36xx_hal_msg_header header;
1804
1805
1806 u8 sta_index;
1807
1808} __packed;
1809
1810
1811struct wcn36xx_hal_delete_sta_rsp_msg {
1812 struct wcn36xx_hal_msg_header header;
1813
1814
1815 u32 status;
1816
1817
1818 u8 sta_id;
1819} __packed;
1820
1821
1822
1823struct wcn36xx_hal_rate_set {
1824 u8 num_rates;
1825 u8 rate[WCN36XX_HAL_MAC_RATESET_EID_MAX];
1826} __packed;
1827
1828
1829struct wcn36xx_hal_aci_aifsn {
1830#ifndef ANI_LITTLE_BIT_ENDIAN
1831 u8 rsvd:1;
1832 u8 aci:2;
1833 u8 acm:1;
1834 u8 aifsn:4;
1835#else
1836 u8 aifsn:4;
1837 u8 acm:1;
1838 u8 aci:2;
1839 u8 rsvd:1;
1840#endif
1841} __packed;
1842
1843
1844struct wcn36xx_hal_mac_cw {
1845#ifndef ANI_LITTLE_BIT_ENDIAN
1846 u8 max:4;
1847 u8 min:4;
1848#else
1849 u8 min:4;
1850 u8 max:4;
1851#endif
1852} __packed;
1853
1854struct wcn36xx_hal_edca_param_record {
1855 struct wcn36xx_hal_aci_aifsn aci;
1856 struct wcn36xx_hal_mac_cw cw;
1857 u16 txop_limit;
1858} __packed;
1859
1860
1861
1862enum wcn36xx_hal_con_mode {
1863 WCN36XX_HAL_STA_MODE = 0,
1864
1865
1866
1867 WCN36XX_HAL_STA_SAP_MODE = 1,
1868
1869 WCN36XX_HAL_P2P_CLIENT_MODE,
1870 WCN36XX_HAL_P2P_GO_MODE,
1871 WCN36XX_HAL_MONITOR_MODE,
1872};
1873
1874
1875
1876
1877
1878
1879enum wcn36xx_hal_concurrency_mode {
1880 HAL_STA = 1,
1881 HAL_SAP = 2,
1882
1883
1884 HAL_STA_SAP = 3,
1885
1886 HAL_P2P_CLIENT = 4,
1887 HAL_P2P_GO = 8,
1888 HAL_MAX_CONCURRENCY_PERSONA = 4
1889};
1890
1891struct wcn36xx_hal_config_bss_params {
1892
1893 u8 bssid[ETH_ALEN];
1894
1895
1896 u8 self_mac_addr[ETH_ALEN];
1897
1898
1899 enum wcn36xx_hal_bss_type bss_type;
1900
1901
1902 u8 oper_mode;
1903
1904
1905 enum wcn36xx_hal_nw_type nw_type;
1906
1907
1908 u8 short_slot_time_supported;
1909
1910
1911 u8 lla_coexist;
1912
1913
1914 u8 llb_coexist;
1915
1916
1917 u8 llg_coexist;
1918
1919
1920 u8 ht20_coexist;
1921
1922
1923 u8 lln_non_gf_coexist;
1924
1925
1926 u8 lsig_tx_op_protection_full_support;
1927
1928
1929 u8 rifs_mode;
1930
1931
1932 u16 beacon_interval;
1933
1934
1935 u8 dtim_period;
1936
1937
1938 u8 tx_channel_width_set;
1939
1940
1941 u8 oper_channel;
1942
1943
1944 u8 ext_channel;
1945
1946
1947 u8 reserved;
1948
1949
1950
1951
1952
1953
1954
1955
1956
1957
1958 struct wcn36xx_hal_config_sta_params sta;
1959
1960 struct wcn36xx_hal_mac_ssid ssid;
1961
1962
1963
1964
1965
1966 u8 action;
1967
1968
1969 struct wcn36xx_hal_rate_set rateset;
1970
1971
1972 u8 ht;
1973
1974
1975 u8 obss_prot_enabled;
1976
1977
1978 u8 rmf;
1979
1980
1981 enum wcn36xx_hal_ht_operating_mode ht_oper_mode;
1982
1983
1984 u8 dual_cts_protection;
1985
1986
1987 u8 max_probe_resp_retry_limit;
1988
1989
1990 u8 hidden_ssid;
1991
1992
1993 u8 proxy_probe_resp;
1994
1995
1996
1997
1998
1999 u8 edca_params_valid;
2000
2001
2002 struct wcn36xx_hal_edca_param_record acbe;
2003
2004
2005 struct wcn36xx_hal_edca_param_record acbk;
2006
2007
2008 struct wcn36xx_hal_edca_param_record acvi;
2009
2010
2011 struct wcn36xx_hal_edca_param_record acvo;
2012
2013
2014 u8 ext_set_sta_key_param_valid;
2015
2016
2017 struct wcn36xx_hal_set_sta_key_params ext_set_sta_key_param;
2018
2019
2020
2021 u8 wcn36xx_hal_persona;
2022
2023 u8 spectrum_mgt_enable;
2024
2025
2026 s8 tx_mgmt_power;
2027
2028
2029
2030 s8 max_tx_power;
2031} __packed;
2032
2033struct wcn36xx_hal_config_bss_req_msg {
2034 struct wcn36xx_hal_msg_header header;
2035 struct wcn36xx_hal_config_bss_params bss_params;
2036} __packed;
2037
2038struct wcn36xx_hal_config_bss_params_v1 {
2039
2040 u8 bssid[ETH_ALEN];
2041
2042
2043 u8 self_mac_addr[ETH_ALEN];
2044
2045
2046 enum wcn36xx_hal_bss_type bss_type;
2047
2048
2049 u8 oper_mode;
2050
2051
2052 enum wcn36xx_hal_nw_type nw_type;
2053
2054
2055 u8 short_slot_time_supported;
2056
2057
2058 u8 lla_coexist;
2059
2060
2061 u8 llb_coexist;
2062
2063
2064 u8 llg_coexist;
2065
2066
2067 u8 ht20_coexist;
2068
2069
2070 u8 lln_non_gf_coexist;
2071
2072
2073 u8 lsig_tx_op_protection_full_support;
2074
2075
2076 u8 rifs_mode;
2077
2078
2079 u16 beacon_interval;
2080
2081
2082 u8 dtim_period;
2083
2084
2085 u8 tx_channel_width_set;
2086
2087
2088 u8 oper_channel;
2089
2090
2091 u8 ext_channel;
2092
2093
2094 u8 reserved;
2095
2096
2097 struct wcn36xx_hal_mac_ssid ssid;
2098
2099
2100
2101
2102
2103 u8 action;
2104
2105
2106 struct wcn36xx_hal_rate_set rateset;
2107
2108
2109 u8 ht;
2110
2111
2112 u8 obss_prot_enabled;
2113
2114
2115 u8 rmf;
2116
2117
2118 enum wcn36xx_hal_ht_operating_mode ht_oper_mode;
2119
2120
2121 u8 dual_cts_protection;
2122
2123
2124 u8 max_probe_resp_retry_limit;
2125
2126
2127 u8 hidden_ssid;
2128
2129
2130 u8 proxy_probe_resp;
2131
2132
2133
2134
2135
2136 u8 edca_params_valid;
2137
2138
2139 struct wcn36xx_hal_edca_param_record acbe;
2140
2141
2142 struct wcn36xx_hal_edca_param_record acbk;
2143
2144
2145 struct wcn36xx_hal_edca_param_record acvi;
2146
2147
2148 struct wcn36xx_hal_edca_param_record acvo;
2149
2150
2151 u8 ext_set_sta_key_param_valid;
2152
2153
2154 struct wcn36xx_hal_set_sta_key_params ext_set_sta_key_param;
2155
2156
2157
2158 u8 wcn36xx_hal_persona;
2159
2160 u8 spectrum_mgt_enable;
2161
2162
2163 s8 tx_mgmt_power;
2164
2165
2166
2167 s8 max_tx_power;
2168
2169
2170
2171
2172
2173
2174
2175
2176
2177 struct wcn36xx_hal_config_sta_params_v1 sta;
2178
2179 u8 vht_capable;
2180 u8 vht_tx_channel_width_set;
2181
2182} __packed;
2183
2184#define WCN36XX_DIFF_BSS_PARAMS_V1_NOVHT (WCN36XX_DIFF_STA_PARAMS_V1_NOVHT + 2)
2185
2186struct wcn36xx_hal_config_bss_req_msg_v1 {
2187 struct wcn36xx_hal_msg_header header;
2188 struct wcn36xx_hal_config_bss_params_v1 bss_params;
2189} __packed;
2190
2191struct wcn36xx_hal_config_bss_rsp_params {
2192
2193 u32 status;
2194
2195
2196 u8 bss_index;
2197
2198
2199 u8 dpu_desc_index;
2200
2201
2202 u8 ucast_dpu_signature;
2203
2204
2205 u8 bcast_dpu_desc_indx;
2206
2207
2208 u8 bcast_dpu_signature;
2209
2210
2211 u8 mgmt_dpu_desc_index;
2212
2213
2214 u8 mgmt_dpu_signature;
2215
2216
2217 u8 bss_sta_index;
2218
2219
2220 u8 bss_self_sta_index;
2221
2222
2223 u8 bss_bcast_sta_idx;
2224
2225
2226 u8 mac[ETH_ALEN];
2227
2228
2229 s8 tx_mgmt_power;
2230
2231} __packed;
2232
2233struct wcn36xx_hal_config_bss_rsp_msg {
2234 struct wcn36xx_hal_msg_header header;
2235 struct wcn36xx_hal_config_bss_rsp_params bss_rsp_params;
2236} __packed;
2237
2238struct wcn36xx_hal_delete_bss_req_msg {
2239 struct wcn36xx_hal_msg_header header;
2240
2241
2242 u8 bss_index;
2243
2244} __packed;
2245
2246struct wcn36xx_hal_delete_bss_rsp_msg {
2247 struct wcn36xx_hal_msg_header header;
2248
2249
2250 u32 status;
2251
2252
2253 u8 bss_index;
2254
2255} __packed;
2256
2257struct wcn36xx_hal_join_req_msg {
2258 struct wcn36xx_hal_msg_header header;
2259
2260
2261 u8 bssid[ETH_ALEN];
2262
2263
2264 u8 channel;
2265
2266
2267 u8 self_sta_mac_addr[ETH_ALEN];
2268
2269
2270 u8 local_power_constraint;
2271
2272
2273 enum phy_chan_bond_state secondary_channel_offset;
2274
2275
2276 enum wcn36xx_hal_link_state link_state;
2277
2278
2279 s8 max_tx_power;
2280} __packed;
2281
2282struct wcn36xx_hal_join_rsp_msg {
2283 struct wcn36xx_hal_msg_header header;
2284
2285
2286 u32 status;
2287
2288
2289 u8 tx_mgmt_power;
2290} __packed;
2291
2292struct post_assoc_req_msg {
2293 struct wcn36xx_hal_msg_header header;
2294
2295 struct wcn36xx_hal_config_sta_params sta_params;
2296 struct wcn36xx_hal_config_bss_params bss_params;
2297};
2298
2299struct post_assoc_rsp_msg {
2300 struct wcn36xx_hal_msg_header header;
2301 struct config_sta_rsp_params sta_rsp_params;
2302 struct wcn36xx_hal_config_bss_rsp_params bss_rsp_params;
2303};
2304
2305
2306struct wcn36xx_hal_set_bss_key_req_msg {
2307 struct wcn36xx_hal_msg_header header;
2308
2309
2310 u8 bss_idx;
2311
2312
2313 enum ani_ed_type enc_type;
2314
2315
2316 u8 num_keys;
2317
2318
2319 struct wcn36xx_hal_keys keys[WCN36XX_HAL_MAC_MAX_NUM_OF_DEFAULT_KEYS];
2320
2321
2322
2323 u8 single_tid_rc;
2324} __packed;
2325
2326
2327struct wcn36xx_hal_set_bss_key_req_msg_tagged {
2328 struct wcn36xx_hal_set_bss_key_req_msg Msg;
2329 u32 tag;
2330} __packed;
2331
2332struct wcn36xx_hal_set_bss_key_rsp_msg {
2333 struct wcn36xx_hal_msg_header header;
2334
2335
2336 u32 status;
2337} __packed;
2338
2339
2340
2341
2342
2343
2344
2345struct wcn36xx_hal_set_sta_key_req_msg {
2346 struct wcn36xx_hal_msg_header header;
2347 struct wcn36xx_hal_set_sta_key_params set_sta_key_params;
2348} __packed;
2349
2350struct wcn36xx_hal_set_sta_key_rsp_msg {
2351 struct wcn36xx_hal_msg_header header;
2352
2353
2354 u32 status;
2355} __packed;
2356
2357struct wcn36xx_hal_remove_bss_key_req_msg {
2358 struct wcn36xx_hal_msg_header header;
2359
2360
2361 u8 bss_idx;
2362
2363
2364 enum ani_ed_type enc_type;
2365
2366
2367 u8 key_id;
2368
2369
2370
2371 enum ani_wep_type wep_type;
2372} __packed;
2373
2374struct wcn36xx_hal_remove_bss_key_rsp_msg {
2375 struct wcn36xx_hal_msg_header header;
2376
2377
2378 u32 status;
2379} __packed;
2380
2381
2382
2383
2384struct wcn36xx_hal_remove_sta_key_req_msg {
2385 struct wcn36xx_hal_msg_header header;
2386
2387
2388 u16 sta_idx;
2389
2390
2391 enum ani_ed_type enc_type;
2392
2393
2394 u8 key_id;
2395
2396
2397
2398 u8 unicast;
2399
2400} __packed;
2401
2402struct wcn36xx_hal_remove_sta_key_rsp_msg {
2403 struct wcn36xx_hal_msg_header header;
2404
2405
2406 u32 status;
2407
2408} __packed;
2409
2410#ifdef FEATURE_OEM_DATA_SUPPORT
2411
2412#ifndef OEM_DATA_REQ_SIZE
2413#define OEM_DATA_REQ_SIZE 134
2414#endif
2415
2416#ifndef OEM_DATA_RSP_SIZE
2417#define OEM_DATA_RSP_SIZE 1968
2418#endif
2419
2420struct start_oem_data_req_msg {
2421 struct wcn36xx_hal_msg_header header;
2422
2423 u32 status;
2424 tSirMacAddr self_mac_addr;
2425 u8 oem_data_req[OEM_DATA_REQ_SIZE];
2426
2427};
2428
2429struct start_oem_data_rsp_msg {
2430 struct wcn36xx_hal_msg_header header;
2431
2432 u8 oem_data_rsp[OEM_DATA_RSP_SIZE];
2433};
2434
2435#endif
2436
2437struct wcn36xx_hal_switch_channel_req_msg {
2438 struct wcn36xx_hal_msg_header header;
2439
2440
2441 u8 channel_number;
2442
2443
2444 u8 local_power_constraint;
2445
2446
2447 enum phy_chan_bond_state secondary_channel_offset;
2448
2449
2450 u8 tx_mgmt_power;
2451
2452
2453 u8 max_tx_power;
2454
2455
2456 u8 self_sta_mac_addr[ETH_ALEN];
2457
2458
2459
2460
2461
2462
2463
2464
2465
2466
2467 u8 bssid[ETH_ALEN];
2468} __packed;
2469
2470struct wcn36xx_hal_switch_channel_rsp_msg {
2471 struct wcn36xx_hal_msg_header header;
2472
2473
2474 u32 status;
2475
2476
2477 u8 channel_number;
2478
2479
2480 u8 tx_mgmt_power;
2481
2482
2483 u8 bssid[ETH_ALEN];
2484
2485} __packed;
2486
2487struct wcn36xx_hal_process_ptt_msg_req_msg {
2488 struct wcn36xx_hal_msg_header header;
2489
2490
2491 u8 ptt_msg[];
2492} __packed;
2493
2494struct wcn36xx_hal_process_ptt_msg_rsp_msg {
2495 struct wcn36xx_hal_msg_header header;
2496
2497
2498 u32 ptt_msg_resp_status;
2499
2500 u8 ptt_msg[];
2501} __packed;
2502
2503struct update_edca_params_req_msg {
2504 struct wcn36xx_hal_msg_header header;
2505
2506
2507 u16 bss_index;
2508
2509
2510 struct wcn36xx_hal_edca_param_record acbe;
2511
2512
2513 struct wcn36xx_hal_edca_param_record acbk;
2514
2515
2516 struct wcn36xx_hal_edca_param_record acvi;
2517
2518
2519 struct wcn36xx_hal_edca_param_record acvo;
2520};
2521
2522struct update_edca_params_rsp_msg {
2523 struct wcn36xx_hal_msg_header header;
2524
2525
2526 u32 status;
2527};
2528
2529struct dpu_stats_params {
2530
2531 u16 sta_index;
2532
2533
2534 u8 enc_mode;
2535
2536
2537 u32 status;
2538
2539
2540 u32 send_blocks;
2541 u32 recv_blocks;
2542 u32 replays;
2543 u8 mic_error_cnt;
2544 u32 prot_excl_cnt;
2545 u16 format_err_cnt;
2546 u16 un_decryptable_cnt;
2547 u32 decrypt_err_cnt;
2548 u32 decrypt_ok_cnt;
2549};
2550
2551struct wcn36xx_hal_stats_req_msg {
2552 struct wcn36xx_hal_msg_header header;
2553
2554
2555 u32 sta_id;
2556
2557
2558 u32 stats_mask;
2559};
2560
2561struct ani_summary_stats_info {
2562
2563
2564 u32 retry_cnt[4];
2565
2566
2567
2568
2569 u32 multiple_retry_cnt[4];
2570
2571
2572
2573
2574 u32 tx_frm_cnt[4];
2575
2576
2577
2578 u32 rx_frm_cnt;
2579
2580
2581 u32 frm_dup_cnt;
2582
2583
2584 u32 fail_cnt[4];
2585
2586
2587
2588 u32 rts_fail_cnt;
2589
2590
2591
2592 u32 ack_fail_cnt;
2593
2594
2595
2596 u32 rts_succ_cnt;
2597
2598
2599
2600
2601 u32 rx_discard_cnt;
2602
2603
2604
2605
2606 u32 rx_error_cnt;
2607
2608
2609
2610
2611 u32 tx_byte_cnt;
2612};
2613
2614
2615enum tx_rate_info {
2616
2617 HAL_TX_RATE_LEGACY = 0x1,
2618
2619
2620 HAL_TX_RATE_HT20 = 0x2,
2621
2622
2623 HAL_TX_RATE_HT40 = 0x4,
2624
2625
2626 HAL_TX_RATE_SGI = 0x8,
2627
2628
2629 HAL_TX_RATE_LGI = 0x10,
2630
2631
2632 HAL_TX_RATE_VHT20 = 0x20,
2633 HAL_TX_RATE_VHT40 = 0x40,
2634 HAL_TX_RATE_VHT80 = 0x80,
2635};
2636
2637struct ani_global_class_a_stats_info {
2638
2639
2640 u32 rx_frag_cnt;
2641
2642
2643
2644
2645 u32 promiscuous_rx_frag_cnt;
2646
2647
2648
2649
2650
2651 u32 rx_input_sensitivity;
2652
2653
2654
2655 u32 max_pwr;
2656
2657
2658
2659
2660 u32 sync_fail_cnt;
2661
2662
2663
2664 u32 tx_rate;
2665
2666
2667 u32 mcs_index;
2668
2669
2670
2671 u32 tx_rate_flags;
2672};
2673
2674struct ani_global_security_stats {
2675
2676
2677
2678 u32 rx_wep_unencrypted_frm_cnt;
2679
2680
2681
2682 u32 rx_mic_fail_cnt;
2683
2684
2685
2686 u32 tkip_icv_err;
2687
2688
2689
2690 u32 aes_ccmp_format_err;
2691
2692
2693
2694 u32 aes_ccmp_replay_cnt;
2695
2696
2697
2698
2699 u32 aes_ccmp_decrpt_err;
2700
2701
2702
2703 u32 wep_undecryptable_cnt;
2704
2705
2706
2707 u32 wep_icv_err;
2708
2709
2710
2711 u32 rx_decrypt_succ_cnt;
2712
2713
2714
2715 u32 rx_decrypt_fail_cnt;
2716};
2717
2718struct ani_global_class_b_stats_info {
2719 struct ani_global_security_stats uc_stats;
2720 struct ani_global_security_stats mc_bc_stats;
2721};
2722
2723struct ani_global_class_c_stats_info {
2724
2725
2726
2727 u32 rx_amsdu_cnt;
2728
2729
2730
2731 u32 rx_ampdu_cnt;
2732
2733
2734
2735 u32 tx_20_frm_cnt;
2736
2737
2738
2739 u32 rx_20_frm_cnt;
2740
2741
2742
2743 u32 rx_mpdu_in_ampdu_cnt;
2744
2745
2746
2747
2748 u32 ampdu_delimiter_crc_err;
2749};
2750
2751struct ani_per_sta_stats_info {
2752
2753
2754 u32 tx_frag_cnt[4];
2755
2756
2757 u32 tx_ampdu_cnt;
2758
2759
2760
2761 u32 tx_mpdu_in_ampdu_cnt;
2762};
2763
2764struct wcn36xx_hal_stats_rsp_msg {
2765 struct wcn36xx_hal_msg_header header;
2766
2767
2768 u32 status;
2769
2770
2771 u32 sta_index;
2772
2773
2774 u32 stats_mask;
2775
2776
2777 u16 msg_type;
2778
2779
2780 u16 msg_len;
2781};
2782
2783struct wcn36xx_hal_set_link_state_req_msg {
2784 struct wcn36xx_hal_msg_header header;
2785
2786 u8 bssid[ETH_ALEN];
2787 enum wcn36xx_hal_link_state state;
2788 u8 self_mac_addr[ETH_ALEN];
2789
2790} __packed;
2791
2792struct set_link_state_rsp_msg {
2793 struct wcn36xx_hal_msg_header header;
2794
2795
2796 u32 status;
2797};
2798
2799
2800struct wcn36xx_hal_ts_info_tfc {
2801#ifndef ANI_LITTLE_BIT_ENDIAN
2802 u16 ackPolicy:2;
2803 u16 userPrio:3;
2804 u16 psb:1;
2805 u16 aggregation:1;
2806 u16 accessPolicy:2;
2807 u16 direction:2;
2808 u16 tsid:4;
2809 u16 trafficType:1;
2810#else
2811 u16 trafficType:1;
2812 u16 tsid:4;
2813 u16 direction:2;
2814 u16 accessPolicy:2;
2815 u16 aggregation:1;
2816 u16 psb:1;
2817 u16 userPrio:3;
2818 u16 ackPolicy:2;
2819#endif
2820};
2821
2822
2823struct wcn36xx_hal_ts_info_sch {
2824#ifndef ANI_LITTLE_BIT_ENDIAN
2825 u8 rsvd:7;
2826 u8 schedule:1;
2827#else
2828 u8 schedule:1;
2829 u8 rsvd:7;
2830#endif
2831};
2832
2833
2834struct wcn36xx_hal_ts_info {
2835 struct wcn36xx_hal_ts_info_tfc traffic;
2836 struct wcn36xx_hal_ts_info_sch schedule;
2837};
2838
2839
2840struct wcn36xx_hal_tspec_ie {
2841 u8 type;
2842 u8 length;
2843 struct wcn36xx_hal_ts_info ts_info;
2844 u16 nom_msdu_size;
2845 u16 max_msdu_size;
2846 u32 min_svc_interval;
2847 u32 max_svc_interval;
2848 u32 inact_interval;
2849 u32 suspend_interval;
2850 u32 svc_start_time;
2851 u32 min_data_rate;
2852 u32 mean_data_rate;
2853 u32 peak_data_rate;
2854 u32 max_burst_sz;
2855 u32 delay_bound;
2856 u32 min_phy_rate;
2857 u16 surplus_bw;
2858 u16 medium_time;
2859};
2860
2861struct add_ts_req_msg {
2862 struct wcn36xx_hal_msg_header header;
2863
2864
2865 u16 sta_index;
2866
2867
2868 u16 tspec_index;
2869
2870
2871 struct wcn36xx_hal_tspec_ie tspec;
2872
2873
2874
2875
2876 u8 uapsd;
2877
2878
2879
2880
2881 u32 service_interval[WCN36XX_HAL_MAX_AC];
2882
2883
2884 u32 suspend_interval[WCN36XX_HAL_MAX_AC];
2885
2886
2887 u32 delay_interval[WCN36XX_HAL_MAX_AC];
2888};
2889
2890struct add_rs_rsp_msg {
2891 struct wcn36xx_hal_msg_header header;
2892
2893
2894 u32 status;
2895};
2896
2897struct del_ts_req_msg {
2898 struct wcn36xx_hal_msg_header header;
2899
2900
2901 u16 sta_index;
2902
2903
2904 u16 tspec_index;
2905
2906
2907 u8 bssid[ETH_ALEN];
2908};
2909
2910struct del_ts_rsp_msg {
2911 struct wcn36xx_hal_msg_header header;
2912
2913
2914 u32 status;
2915};
2916
2917
2918
2919
2920
2921struct wcn36xx_hal_add_ba_session_req_msg {
2922 struct wcn36xx_hal_msg_header header;
2923
2924
2925 u16 sta_index;
2926
2927
2928 u8 mac_addr[ETH_ALEN];
2929
2930
2931
2932 u8 dialog_token;
2933
2934
2935
2936 u8 tid;
2937
2938
2939
2940 u8 policy;
2941
2942
2943
2944
2945
2946
2947
2948 u16 buffer_size;
2949
2950
2951 u16 timeout;
2952
2953
2954
2955
2956 u16 ssn;
2957
2958
2959
2960
2961 u8 direction;
2962} __packed;
2963
2964struct wcn36xx_hal_add_ba_session_rsp_msg {
2965 struct wcn36xx_hal_msg_header header;
2966
2967
2968 u32 status;
2969
2970
2971 u8 dialog_token;
2972
2973
2974 u8 ba_tid;
2975
2976
2977 u8 ba_buffer_size;
2978
2979 u8 ba_session_id;
2980
2981
2982 u8 win_size;
2983
2984
2985 u8 sta_index;
2986
2987
2988 u16 ssn;
2989} __packed;
2990
2991struct wcn36xx_hal_add_ba_req_msg {
2992 struct wcn36xx_hal_msg_header header;
2993
2994
2995 u8 session_id;
2996
2997
2998 u8 win_size;
2999
3000#ifdef FEATURE_ON_CHIP_REORDERING
3001 u8 reordering_done_on_chip;
3002#endif
3003} __packed;
3004
3005struct wcn36xx_hal_add_ba_rsp_msg {
3006 struct wcn36xx_hal_msg_header header;
3007
3008
3009 u32 status;
3010
3011
3012 u8 dialog_token;
3013} __packed;
3014
3015struct add_ba_info {
3016 u16 ba_enable:1;
3017 u16 starting_seq_num:12;
3018 u16 reserved:3;
3019};
3020
3021struct wcn36xx_hal_trigger_ba_rsp_candidate {
3022 u8 sta_addr[ETH_ALEN];
3023 struct add_ba_info ba_info[STACFG_MAX_TC];
3024} __packed;
3025
3026struct wcn36xx_hal_trigger_ba_req_candidate {
3027 u8 sta_index;
3028 u8 tid_bitmap;
3029} __packed;
3030
3031struct wcn36xx_hal_trigger_ba_req_msg {
3032 struct wcn36xx_hal_msg_header header;
3033
3034
3035 u8 session_id;
3036
3037
3038
3039
3040 u16 candidate_cnt;
3041
3042} __packed;
3043
3044struct wcn36xx_hal_trigger_ba_rsp_msg {
3045 struct wcn36xx_hal_msg_header header;
3046
3047
3048 u8 bssid[ETH_ALEN];
3049
3050
3051 u32 status;
3052
3053
3054
3055
3056 u16 candidate_cnt;
3057} __packed;
3058
3059struct wcn36xx_hal_del_ba_req_msg {
3060 struct wcn36xx_hal_msg_header header;
3061
3062
3063 u16 sta_index;
3064
3065
3066 u8 tid;
3067
3068
3069
3070
3071 u8 direction;
3072} __packed;
3073
3074struct wcn36xx_hal_del_ba_rsp_msg {
3075 struct wcn36xx_hal_msg_header header;
3076
3077
3078 u32 status;
3079} __packed;
3080
3081struct tsm_stats_req_msg {
3082 struct wcn36xx_hal_msg_header header;
3083
3084
3085 u8 tid;
3086
3087 u8 bssid[ETH_ALEN];
3088};
3089
3090struct tsm_stats_rsp_msg {
3091 struct wcn36xx_hal_msg_header header;
3092
3093
3094 u32 status;
3095
3096
3097 u16 uplink_pkt_queue_delay;
3098
3099
3100 u16 uplink_pkt_queue_delay_hist[4];
3101
3102
3103 u32 uplink_pkt_tx_delay;
3104
3105
3106 u16 uplink_pkt_loss;
3107
3108
3109 u16 uplink_pkt_count;
3110
3111
3112 u8 roaming_count;
3113
3114
3115 u16 roaming_delay;
3116};
3117
3118struct set_key_done_msg {
3119 struct wcn36xx_hal_msg_header header;
3120
3121
3122 u8 bssidx;
3123 u8 enc_type;
3124};
3125
3126struct wcn36xx_hal_nv_img_download_req_msg {
3127
3128
3129
3130
3131 struct wcn36xx_hal_msg_header header;
3132
3133
3134
3135
3136
3137
3138
3139
3140
3141 u16 frag_number;
3142
3143
3144
3145
3146
3147
3148 u16 last_fragment;
3149
3150
3151 u32 nv_img_buffer_size;
3152
3153
3154
3155
3156} __packed;
3157
3158struct wcn36xx_hal_nv_img_download_rsp_msg {
3159 struct wcn36xx_hal_msg_header header;
3160
3161
3162
3163 u32 status;
3164} __packed;
3165
3166struct wcn36xx_hal_nv_store_ind {
3167
3168
3169 struct wcn36xx_hal_msg_header header;
3170
3171
3172 u32 table_id;
3173
3174
3175 u32 nv_blob_size;
3176
3177
3178
3179};
3180
3181
3182
3183#define WCN36XX_HAL_CIPHER_SEQ_CTR_SIZE 6
3184
3185
3186
3187
3188struct mic_failure_ind_msg {
3189 struct wcn36xx_hal_msg_header header;
3190
3191 u8 bssid[ETH_ALEN];
3192
3193
3194 u8 src_addr[ETH_ALEN];
3195
3196
3197 u8 ta_addr[ETH_ALEN];
3198
3199 u8 dst_addr[ETH_ALEN];
3200
3201 u8 multicast;
3202
3203
3204 u8 iv1;
3205
3206
3207 u8 key_id;
3208
3209
3210 u8 tsc[WCN36XX_HAL_CIPHER_SEQ_CTR_SIZE];
3211
3212
3213 u8 rx_addr[ETH_ALEN];
3214};
3215
3216struct update_vht_op_mode_req_msg {
3217 struct wcn36xx_hal_msg_header header;
3218
3219 u16 op_mode;
3220 u16 sta_id;
3221};
3222
3223struct update_vht_op_mode_params_rsp_msg {
3224 struct wcn36xx_hal_msg_header header;
3225
3226 u32 status;
3227};
3228
3229struct update_beacon_req_msg {
3230 struct wcn36xx_hal_msg_header header;
3231
3232 u8 bss_index;
3233
3234
3235
3236 u8 short_preamble;
3237
3238
3239 u8 short_slot_time;
3240
3241
3242 u16 beacon_interval;
3243
3244
3245 u8 lla_coexist;
3246 u8 llb_coexist;
3247 u8 llg_coexist;
3248 u8 ht20_coexist;
3249 u8 lln_non_gf_coexist;
3250 u8 lsig_tx_op_protection_full_support;
3251 u8 rifs_mode;
3252
3253 u16 param_change_bitmap;
3254};
3255
3256struct update_beacon_rsp_msg {
3257 struct wcn36xx_hal_msg_header header;
3258 u32 status;
3259};
3260
3261struct wcn36xx_hal_send_beacon_req_msg {
3262 struct wcn36xx_hal_msg_header header;
3263
3264
3265 u32 beacon_length6;
3266
3267
3268 u32 beacon_length;
3269
3270
3271 u8 beacon[BEACON_TEMPLATE_SIZE - sizeof(u32)];
3272
3273 u8 bssid[ETH_ALEN];
3274
3275
3276 u32 tim_ie_offset;
3277
3278
3279 u16 p2p_ie_offset;
3280} __packed;
3281
3282struct send_beacon_rsp_msg {
3283 struct wcn36xx_hal_msg_header header;
3284 u32 status;
3285} __packed;
3286
3287struct enable_radar_req_msg {
3288 struct wcn36xx_hal_msg_header header;
3289
3290 u8 bssid[ETH_ALEN];
3291 u8 channel;
3292};
3293
3294struct enable_radar_rsp_msg {
3295 struct wcn36xx_hal_msg_header header;
3296
3297
3298 u8 bssid[ETH_ALEN];
3299
3300
3301 u32 status;
3302};
3303
3304struct radar_detect_intr_ind_msg {
3305 struct wcn36xx_hal_msg_header header;
3306
3307 u8 radar_det_channel;
3308};
3309
3310struct radar_detect_ind_msg {
3311 struct wcn36xx_hal_msg_header header;
3312
3313
3314 u8 channel_number;
3315
3316
3317 u16 radar_pulse_width;
3318
3319
3320 u16 num_radar_pulse;
3321};
3322
3323struct wcn36xx_hal_get_tpc_report_req_msg {
3324 struct wcn36xx_hal_msg_header header;
3325
3326 u8 sta[ETH_ALEN];
3327 u8 dialog_token;
3328 u8 txpower;
3329};
3330
3331struct wcn36xx_hal_get_tpc_report_rsp_msg {
3332 struct wcn36xx_hal_msg_header header;
3333
3334
3335 u32 status;
3336};
3337
3338struct wcn36xx_hal_send_probe_resp_req_msg {
3339 struct wcn36xx_hal_msg_header header;
3340
3341 u8 probe_resp_template[BEACON_TEMPLATE_SIZE];
3342 u32 probe_resp_template_len;
3343 u32 proxy_probe_req_valid_ie_bmap[8];
3344 u8 bssid[ETH_ALEN];
3345};
3346
3347struct send_probe_resp_rsp_msg {
3348 struct wcn36xx_hal_msg_header header;
3349
3350
3351 u32 status;
3352};
3353
3354struct send_unknown_frame_rx_ind_msg {
3355 struct wcn36xx_hal_msg_header header;
3356
3357
3358 u32 status;
3359};
3360
3361struct wcn36xx_hal_delete_sta_context_ind_msg {
3362 struct wcn36xx_hal_msg_header header;
3363
3364 u16 aid;
3365 u16 sta_id;
3366
3367
3368 u8 bssid[ETH_ALEN];
3369
3370
3371 u8 addr2[ETH_ALEN];
3372
3373
3374 u16 reason_code;
3375} __packed;
3376
3377struct indicate_del_sta {
3378 struct wcn36xx_hal_msg_header header;
3379 u8 aid;
3380 u8 sta_index;
3381 u8 bss_index;
3382 u8 reason_code;
3383 u32 status;
3384};
3385
3386struct bt_amp_event_msg {
3387 struct wcn36xx_hal_msg_header header;
3388
3389 enum bt_amp_event_type btAmpEventType;
3390};
3391
3392struct bt_amp_event_rsp {
3393 struct wcn36xx_hal_msg_header header;
3394
3395
3396 u32 status;
3397};
3398
3399struct tl_hal_flush_ac_req_msg {
3400 struct wcn36xx_hal_msg_header header;
3401
3402
3403 u8 sta_id;
3404
3405
3406 u8 tid;
3407};
3408
3409struct tl_hal_flush_ac_rsp_msg {
3410 struct wcn36xx_hal_msg_header header;
3411
3412
3413 u8 sta_id;
3414
3415
3416 u8 tid;
3417
3418
3419 u32 status;
3420};
3421
3422struct wcn36xx_hal_enter_imps_req_msg {
3423 struct wcn36xx_hal_msg_header header;
3424} __packed;
3425
3426struct wcn36xx_hal_exit_imps_req_msg {
3427 struct wcn36xx_hal_msg_header header;
3428} __packed;
3429
3430struct wcn36xx_hal_enter_bmps_req_msg {
3431 struct wcn36xx_hal_msg_header header;
3432
3433 u8 bss_index;
3434
3435
3436#ifndef BUILD_QWPTTSTATIC
3437 u64 tbtt;
3438#endif
3439 u8 dtim_count;
3440
3441
3442
3443 u8 dtim_period;
3444
3445
3446 u32 rssi_filter_period;
3447
3448 u32 num_beacon_per_rssi_average;
3449 u8 rssi_filter_enable;
3450} __packed;
3451
3452struct wcn36xx_hal_exit_bmps_req_msg {
3453 struct wcn36xx_hal_msg_header header;
3454
3455 u8 send_data_null;
3456 u8 bss_index;
3457} __packed;
3458
3459struct wcn36xx_hal_missed_beacon_ind_msg {
3460 struct wcn36xx_hal_msg_header header;
3461
3462 u8 bss_index;
3463} __packed;
3464
3465
3466
3467struct beacon_filter_ie {
3468 u8 element_id;
3469 u8 check_ie_presence;
3470 u8 offset;
3471 u8 value;
3472 u8 bitmask;
3473 u8 ref;
3474} __packed;
3475
3476#define WCN36XX_FILTER_CAPABILITY_MASK 0x73cf
3477#define WCN36XX_FILTER_IE_DS_CHANNEL_MASK 0x00
3478#define WCN36XX_FILTER_IE_ERP_FILTER_MASK 0xF8
3479#define WCN36XX_FILTER_IE_EDCA_FILTER_MASK 0xF0
3480#define WCN36XX_FILTER_IE_QOS_FILTER_MASK 0xF0
3481#define WCN36XX_FILTER_IE_CHANNEL_SWITCH_MASK 0x00
3482#define WCN36XX_FILTER_IE_HT_BYTE0_FILTER_MASK 0x00
3483#define WCN36XX_FILTER_IE_HT_BYTE1_FILTER_MASK 0xF8
3484#define WCN36XX_FILTER_IE_HT_BYTE2_FILTER_MASK 0xEB
3485#define WCN36XX_FILTER_IE_HT_BYTE5_FILTER_MASK 0xFD
3486#define WCN36XX_FILTER_IE_PWR_CONSTRAINT_MASK 0x00
3487#define WCN36XX_FILTER_IE_OPMODE_NOTIF_MASK 0x00
3488#define WCN36XX_FILTER_IE_VHTOP_CHWIDTH_MASK 0xFC
3489#define WCN36XX_FILTER_IE_RSN_MASK 0x00
3490#define WCN36XX_FILTER_IE_VENDOR_MASK 0x00
3491
3492
3493
3494
3495
3496struct wcn36xx_hal_add_bcn_filter_req_msg {
3497 struct wcn36xx_hal_msg_header header;
3498
3499 u16 capability_info;
3500 u16 capability_mask;
3501 u16 beacon_interval;
3502 u16 ie_num;
3503 u8 bss_index;
3504 u8 reserved;
3505} __packed;
3506
3507struct wcn36xx_hal_rem_bcn_filter_req {
3508 struct wcn36xx_hal_msg_header header;
3509
3510 u8 ie_Count;
3511 u8 rem_ie_id[1];
3512} __packed;
3513
3514#define WCN36XX_HAL_IPV4_ARP_REPLY_OFFLOAD 0
3515#define WCN36XX_HAL_IPV6_NEIGHBOR_DISCOVERY_OFFLOAD 1
3516#define WCN36XX_HAL_IPV6_NS_OFFLOAD 2
3517#define WCN36XX_HAL_IPV6_ADDR_LEN 16
3518#define WCN36XX_HAL_OFFLOAD_DISABLE 0
3519#define WCN36XX_HAL_OFFLOAD_ENABLE 1
3520#define WCN36XX_HAL_OFFLOAD_BCAST_FILTER_ENABLE 0x2
3521#define WCN36XX_HAL_OFFLOAD_MCAST_FILTER_ENABLE 0x4
3522#define WCN36XX_HAL_OFFLOAD_NS_AND_MCAST_FILTER_ENABLE \
3523 (WCN36XX_HAL_OFFLOAD_ENABLE | WCN36XX_HAL_OFFLOAD_MCAST_FILTER_ENABLE)
3524#define WCN36XX_HAL_OFFLOAD_ARP_AND_BCAST_FILTER_ENABLE \
3525 (WCN36XX_HAL_OFFLOAD_ENABLE | WCN36XX_HAL_OFFLOAD_BCAST_FILTER_ENABLE)
3526#define WCN36XX_HAL_IPV6_OFFLOAD_ADDR_MAX 0x02
3527
3528struct wcn36xx_hal_ns_offload_params {
3529 u8 src_ipv6_addr[WCN36XX_HAL_IPV6_ADDR_LEN];
3530 u8 self_ipv6_addr[WCN36XX_HAL_IPV6_ADDR_LEN];
3531
3532
3533 u8 target_ipv6_addr1[WCN36XX_HAL_IPV6_ADDR_LEN];
3534 u8 target_ipv6_addr2[WCN36XX_HAL_IPV6_ADDR_LEN];
3535
3536 u8 self_addr[ETH_ALEN];
3537 u8 src_ipv6_addr_valid:1;
3538 u8 target_ipv6_addr1_valid:1;
3539 u8 target_ipv6_addr2_valid:1;
3540 u8 reserved1:5;
3541
3542
3543 u8 reserved2;
3544
3545
3546 u32 slot_index;
3547 u8 bss_index;
3548} __packed;
3549
3550struct wcn36xx_hal_host_offload_req {
3551 u8 offload_type;
3552
3553
3554 u8 enable;
3555
3556 union {
3557 u8 host_ipv4_addr[4];
3558 u8 host_ipv6_addr[WCN36XX_HAL_IPV6_ADDR_LEN];
3559 } u;
3560} __packed;
3561
3562struct wcn36xx_hal_host_offload_req_msg {
3563 struct wcn36xx_hal_msg_header header;
3564 struct wcn36xx_hal_host_offload_req host_offload_params;
3565 struct wcn36xx_hal_ns_offload_params ns_offload_params;
3566} __packed;
3567
3568
3569#define WCN36XX_HAL_KEEP_ALIVE_NULL_PKT 1
3570#define WCN36XX_HAL_KEEP_ALIVE_UNSOLICIT_ARP_RSP 2
3571
3572
3573#define WCN36XX_HAL_KEEP_ALIVE_DISABLE 0
3574#define WCN36XX_HAL_KEEP_ALIVE_ENABLE 1
3575#define WCN36XX_KEEP_ALIVE_TIME_PERIOD 30
3576
3577
3578struct wcn36xx_hal_keep_alive_req_msg {
3579 struct wcn36xx_hal_msg_header header;
3580
3581 u8 packet_type;
3582 u32 time_period;
3583 u8 host_ipv4_addr[WCN36XX_HAL_IPV4_ADDR_LEN];
3584 u8 dest_ipv4_addr[WCN36XX_HAL_IPV4_ADDR_LEN];
3585 u8 dest_addr[ETH_ALEN];
3586 u8 bss_index;
3587} __packed;
3588
3589struct wcn36xx_hal_rssi_threshold_req_msg {
3590 struct wcn36xx_hal_msg_header header;
3591
3592 s8 threshold1:8;
3593 s8 threshold2:8;
3594 s8 threshold3:8;
3595 u8 thres1_pos_notify:1;
3596 u8 thres1_neg_notify:1;
3597 u8 thres2_pos_notify:1;
3598 u8 thres2_neg_notify:1;
3599 u8 thres3_pos_notify:1;
3600 u8 thres3_neg_notify:1;
3601 u8 reserved10:2;
3602};
3603
3604struct wcn36xx_hal_enter_uapsd_req_msg {
3605 struct wcn36xx_hal_msg_header header;
3606
3607 u8 bk_delivery:1;
3608 u8 be_delivery:1;
3609 u8 vi_delivery:1;
3610 u8 vo_delivery:1;
3611 u8 bk_trigger:1;
3612 u8 be_trigger:1;
3613 u8 vi_trigger:1;
3614 u8 vo_trigger:1;
3615 u8 bss_index;
3616};
3617
3618struct wcn36xx_hal_exit_uapsd_req_msg {
3619 struct wcn36xx_hal_msg_header header;
3620 u8 bss_index;
3621};
3622
3623#define WCN36XX_HAL_WOWL_BCAST_PATTERN_MAX_SIZE 128
3624#define WCN36XX_HAL_WOWL_BCAST_MAX_NUM_PATTERNS 16
3625
3626struct wcn36xx_hal_wowl_add_bcast_ptrn_req_msg {
3627 struct wcn36xx_hal_msg_header header;
3628
3629
3630 u8 id;
3631
3632
3633
3634 u8 byte_Offset;
3635
3636
3637 u8 size;
3638
3639
3640 u8 pattern[WCN36XX_HAL_WOWL_BCAST_PATTERN_MAX_SIZE];
3641
3642
3643 u8 mask_size;
3644
3645
3646 u8 mask[WCN36XX_HAL_WOWL_BCAST_PATTERN_MAX_SIZE];
3647
3648
3649 u8 extra[WCN36XX_HAL_WOWL_BCAST_PATTERN_MAX_SIZE];
3650
3651
3652 u8 mask_extra[WCN36XX_HAL_WOWL_BCAST_PATTERN_MAX_SIZE];
3653
3654 u8 bss_index;
3655};
3656
3657struct wcn36xx_hal_wow_del_bcast_ptrn_req_msg {
3658 struct wcn36xx_hal_msg_header header;
3659
3660
3661 u8 id;
3662 u8 bss_index;
3663};
3664
3665struct wcn36xx_hal_wowl_enter_req_msg {
3666 struct wcn36xx_hal_msg_header header;
3667
3668
3669 u8 magic_packet_enable;
3670
3671
3672 u8 magic_pattern[ETH_ALEN];
3673
3674
3675
3676
3677
3678
3679 u8 pattern_filtering_enable;
3680
3681
3682
3683
3684
3685
3686
3687 u8 ucast_pattern_filtering_enable;
3688
3689
3690
3691
3692
3693 u8 wow_channel_switch_receive;
3694
3695
3696
3697
3698
3699 u8 wow_deauth_receive;
3700
3701
3702
3703
3704
3705 u8 wow_disassoc_receive;
3706
3707
3708
3709
3710
3711
3712 u8 wow_max_missed_beacons;
3713
3714
3715
3716
3717
3718
3719 u8 wow_max_sleep;
3720
3721
3722
3723
3724
3725 u8 wow_eap_id_request_enable;
3726
3727
3728
3729
3730 u8 wow_eapol_4way_enable;
3731
3732
3733
3734
3735 u8 wow_net_scan_offload_match;
3736
3737
3738
3739
3740 u8 wow_gtk_rekey_error;
3741
3742
3743
3744 u8 wow_bss_connection_loss;
3745
3746 u8 bss_index;
3747};
3748
3749struct wcn36xx_hal_wowl_exit_req_msg {
3750 struct wcn36xx_hal_msg_header header;
3751
3752 u8 bss_index;
3753};
3754
3755struct wcn36xx_hal_get_rssi_req_msg {
3756 struct wcn36xx_hal_msg_header header;
3757};
3758
3759struct wcn36xx_hal_get_roam_rssi_req_msg {
3760 struct wcn36xx_hal_msg_header header;
3761
3762
3763 u32 sta_id;
3764};
3765
3766struct wcn36xx_hal_set_uapsd_ac_params_req_msg {
3767 struct wcn36xx_hal_msg_header header;
3768
3769
3770 u8 sta_idx;
3771
3772
3773 u8 ac;
3774
3775
3776 u8 up;
3777
3778
3779 u32 service_interval;
3780
3781
3782 u32 suspend_interval;
3783
3784
3785 u32 delay_interval;
3786};
3787
3788struct wcn36xx_hal_configure_rxp_filter_req_msg {
3789 struct wcn36xx_hal_msg_header header;
3790
3791 u8 set_mcst_bcst_filter_setting;
3792 u8 set_mcst_bcst_filter;
3793};
3794
3795struct wcn36xx_hal_enter_imps_rsp_msg {
3796 struct wcn36xx_hal_msg_header header;
3797
3798
3799 u32 status;
3800};
3801
3802struct wcn36xx_hal_exit_imps_rsp_msg {
3803 struct wcn36xx_hal_msg_header header;
3804
3805
3806 u32 status;
3807};
3808
3809struct wcn36xx_hal_enter_bmps_rsp_msg {
3810 struct wcn36xx_hal_msg_header header;
3811
3812
3813 u32 status;
3814
3815 u8 bss_index;
3816} __packed;
3817
3818struct wcn36xx_hal_exit_bmps_rsp_msg {
3819 struct wcn36xx_hal_msg_header header;
3820
3821
3822 u32 status;
3823
3824 u8 bss_index;
3825} __packed;
3826
3827struct wcn36xx_hal_enter_uapsd_rsp_msg {
3828 struct wcn36xx_hal_msg_header header;
3829
3830
3831 u32 status;
3832
3833 u8 bss_index;
3834};
3835
3836struct wcn36xx_hal_exit_uapsd_rsp_msg {
3837 struct wcn36xx_hal_msg_header header;
3838
3839
3840 u32 status;
3841
3842 u8 bss_index;
3843};
3844
3845struct wcn36xx_hal_rssi_notification_ind_msg {
3846 struct wcn36xx_hal_msg_header header;
3847
3848 u32 rssi_thres1_pos_cross:1;
3849 u32 rssi_thres1_neg_cross:1;
3850 u32 rssi_thres2_pos_cross:1;
3851 u32 rssi_thres2_neg_cross:1;
3852 u32 rssi_thres3_pos_cross:1;
3853 u32 rssi_thres3_neg_cross:1;
3854 u32 avg_rssi:8;
3855 u32 reserved:18;
3856
3857};
3858
3859struct wcn36xx_hal_get_rssio_rsp_msg {
3860 struct wcn36xx_hal_msg_header header;
3861
3862
3863 u32 status;
3864 s8 rssi;
3865
3866};
3867
3868struct wcn36xx_hal_get_roam_rssi_rsp_msg {
3869 struct wcn36xx_hal_msg_header header;
3870
3871
3872 u32 status;
3873
3874 u8 sta_id;
3875 s8 rssi;
3876};
3877
3878struct wcn36xx_hal_wowl_enter_rsp_msg {
3879 struct wcn36xx_hal_msg_header header;
3880
3881
3882 u32 status;
3883 u8 bss_index;
3884};
3885
3886struct wcn36xx_hal_wowl_exit_rsp_msg {
3887 struct wcn36xx_hal_msg_header header;
3888
3889
3890 u32 status;
3891 u8 bss_index;
3892};
3893
3894struct wcn36xx_hal_add_bcn_filter_rsp_msg {
3895 struct wcn36xx_hal_msg_header header;
3896
3897
3898 u32 status;
3899};
3900
3901struct wcn36xx_hal_rem_bcn_filter_rsp_msg {
3902 struct wcn36xx_hal_msg_header header;
3903
3904
3905 u32 status;
3906};
3907
3908struct wcn36xx_hal_add_wowl_bcast_ptrn_rsp_msg {
3909 struct wcn36xx_hal_msg_header header;
3910
3911
3912 u32 status;
3913 u8 bss_index;
3914};
3915
3916struct wcn36xx_hal_del_wowl_bcast_ptrn_rsp_msg {
3917 struct wcn36xx_hal_msg_header header;
3918
3919
3920 u32 status;
3921 u8 bss_index;
3922};
3923
3924struct wcn36xx_hal_host_offload_rsp_msg {
3925 struct wcn36xx_hal_msg_header header;
3926
3927
3928 u32 status;
3929};
3930
3931struct wcn36xx_hal_keep_alive_rsp_msg {
3932 struct wcn36xx_hal_msg_header header;
3933
3934
3935 u32 status;
3936};
3937
3938struct wcn36xx_hal_set_rssi_thresh_rsp_msg {
3939 struct wcn36xx_hal_msg_header header;
3940
3941
3942 u32 status;
3943};
3944
3945struct wcn36xx_hal_set_uapsd_ac_params_rsp_msg {
3946 struct wcn36xx_hal_msg_header header;
3947
3948
3949 u32 status;
3950};
3951
3952struct wcn36xx_hal_configure_rxp_filter_rsp_msg {
3953 struct wcn36xx_hal_msg_header header;
3954
3955
3956 u32 status;
3957};
3958
3959struct set_max_tx_pwr_req {
3960 struct wcn36xx_hal_msg_header header;
3961
3962
3963
3964
3965 u8 bssid[ETH_ALEN];
3966
3967 u8 self_addr[ETH_ALEN];
3968
3969
3970 u8 power;
3971};
3972
3973struct set_max_tx_pwr_rsp_msg {
3974 struct wcn36xx_hal_msg_header header;
3975
3976
3977 u8 power;
3978
3979
3980 u32 status;
3981};
3982
3983struct set_tx_pwr_req_msg {
3984 struct wcn36xx_hal_msg_header header;
3985
3986
3987 u32 tx_power;
3988
3989 u8 bss_index;
3990};
3991
3992struct set_tx_pwr_rsp_msg {
3993 struct wcn36xx_hal_msg_header header;
3994
3995
3996 u32 status;
3997};
3998
3999struct get_tx_pwr_req_msg {
4000 struct wcn36xx_hal_msg_header header;
4001
4002 u8 sta_id;
4003};
4004
4005struct get_tx_pwr_rsp_msg {
4006 struct wcn36xx_hal_msg_header header;
4007
4008
4009 u32 status;
4010
4011
4012 u32 tx_power;
4013};
4014
4015struct set_p2p_gonoa_req_msg {
4016 struct wcn36xx_hal_msg_header header;
4017
4018 u8 opp_ps;
4019 u32 ct_window;
4020 u8 count;
4021 u32 duration;
4022 u32 interval;
4023 u32 single_noa_duration;
4024 u8 ps_selection;
4025};
4026
4027struct set_p2p_gonoa_rsp_msg {
4028 struct wcn36xx_hal_msg_header header;
4029
4030
4031 u32 status;
4032};
4033
4034struct wcn36xx_hal_add_sta_self_req {
4035 struct wcn36xx_hal_msg_header header;
4036
4037 u8 self_addr[ETH_ALEN];
4038 u32 status;
4039} __packed;
4040
4041struct wcn36xx_hal_add_sta_self_rsp_msg {
4042 struct wcn36xx_hal_msg_header header;
4043
4044
4045 u32 status;
4046
4047
4048 u8 self_sta_index;
4049
4050
4051 u8 dpu_index;
4052
4053
4054 u8 dpu_signature;
4055} __packed;
4056
4057struct wcn36xx_hal_del_sta_self_req_msg {
4058 struct wcn36xx_hal_msg_header header;
4059
4060 u8 self_addr[ETH_ALEN];
4061} __packed;
4062
4063struct wcn36xx_hal_del_sta_self_rsp_msg {
4064 struct wcn36xx_hal_msg_header header;
4065
4066
4067 u32 status;
4068
4069 u8 self_addr[ETH_ALEN];
4070} __packed;
4071
4072struct aggr_add_ts_req {
4073 struct wcn36xx_hal_msg_header header;
4074
4075
4076 u16 sta_idx;
4077
4078
4079
4080
4081 u16 tspec_index;
4082
4083
4084 struct wcn36xx_hal_tspec_ie tspec[WCN36XX_HAL_MAX_AC];
4085
4086
4087
4088
4089 u8 uapsd;
4090
4091
4092
4093
4094 u32 service_interval[WCN36XX_HAL_MAX_AC];
4095
4096
4097 u32 suspend_interval[WCN36XX_HAL_MAX_AC];
4098
4099
4100 u32 delay_interval[WCN36XX_HAL_MAX_AC];
4101};
4102
4103struct aggr_add_ts_rsp_msg {
4104 struct wcn36xx_hal_msg_header header;
4105
4106
4107 u32 status0;
4108
4109
4110 u32 status1;
4111};
4112
4113struct wcn36xx_hal_configure_apps_cpu_wakeup_state_req_msg {
4114 struct wcn36xx_hal_msg_header header;
4115
4116 u8 is_apps_cpu_awake;
4117};
4118
4119struct wcn36xx_hal_configure_apps_cpu_wakeup_state_rsp_msg {
4120 struct wcn36xx_hal_msg_header header;
4121
4122
4123 u32 status;
4124};
4125
4126struct wcn36xx_hal_dump_cmd_req_msg {
4127 struct wcn36xx_hal_msg_header header;
4128
4129 u32 arg1;
4130 u32 arg2;
4131 u32 arg3;
4132 u32 arg4;
4133 u32 arg5;
4134} __packed;
4135
4136struct wcn36xx_hal_dump_cmd_rsp_msg {
4137 struct wcn36xx_hal_msg_header header;
4138
4139
4140 u32 status;
4141
4142
4143 u32 rsp_length;
4144
4145
4146
4147 u8 rsp_buffer[DUMPCMD_RSP_BUFFER];
4148} __packed;
4149
4150#define WLAN_COEX_IND_DATA_SIZE (4)
4151#define WLAN_COEX_IND_TYPE_DISABLE_HB_MONITOR (0)
4152#define WLAN_COEX_IND_TYPE_ENABLE_HB_MONITOR (1)
4153
4154struct coex_ind_msg {
4155 struct wcn36xx_hal_msg_header header;
4156
4157
4158 u32 type;
4159
4160
4161 u32 data[WLAN_COEX_IND_DATA_SIZE];
4162};
4163
4164struct wcn36xx_hal_tx_compl_ind_msg {
4165 struct wcn36xx_hal_msg_header header;
4166
4167
4168 u32 status;
4169};
4170
4171struct wcn36xx_hal_wlan_host_suspend_ind_msg {
4172 struct wcn36xx_hal_msg_header header;
4173
4174 u32 configured_mcst_bcst_filter_setting;
4175 u32 active_session_count;
4176};
4177
4178struct wcn36xx_hal_wlan_exclude_unencrpted_ind_msg {
4179 struct wcn36xx_hal_msg_header header;
4180
4181 u8 dot11_exclude_unencrypted;
4182 u8 bssid[ETH_ALEN];
4183};
4184
4185struct noa_attr_ind_msg {
4186 struct wcn36xx_hal_msg_header header;
4187
4188 u8 index;
4189 u8 opp_ps_flag;
4190 u16 ctwin;
4191
4192 u16 noa1_interval_count;
4193 u16 bss_index;
4194 u32 noa1_duration;
4195 u32 noa1_interval;
4196 u32 noa1_starttime;
4197
4198 u16 noa2_interval_count;
4199 u16 reserved2;
4200 u32 noa2_duration;
4201 u32 noa2_interval;
4202 u32 noa2_start_time;
4203
4204 u32 status;
4205};
4206
4207struct noa_start_ind_msg {
4208 struct wcn36xx_hal_msg_header header;
4209
4210 u32 status;
4211 u32 bss_index;
4212};
4213
4214struct wcn36xx_hal_wlan_host_resume_req_msg {
4215 struct wcn36xx_hal_msg_header header;
4216
4217 u8 configured_mcst_bcst_filter_setting;
4218};
4219
4220struct wcn36xx_hal_host_resume_rsp_msg {
4221 struct wcn36xx_hal_msg_header header;
4222
4223
4224 u32 status;
4225};
4226
4227struct wcn36xx_hal_del_ba_ind_msg {
4228 struct wcn36xx_hal_msg_header header;
4229
4230 u16 sta_idx;
4231
4232
4233 u8 peer_addr[ETH_ALEN];
4234
4235
4236 u8 ba_tid;
4237
4238
4239
4240
4241
4242 u8 direction;
4243
4244 u32 reason_code;
4245
4246
4247 u8 bssid[ETH_ALEN];
4248};
4249
4250
4251
4252
4253#define WCN36XX_HAL_PNO_MAX_NETW_CHANNELS 26
4254
4255
4256#define WCN36XX_HAL_PNO_MAX_NETW_CHANNELS_EX 60
4257
4258
4259#define WCN36XX_HAL_PNO_MAX_SUPP_NETWORKS 16
4260
4261
4262#define WCN36XX_HAL_PNO_MAX_SCAN_TIMERS 10
4263
4264
4265#define WCN36XX_HAL_PNO_MAX_PROBE_SIZE 450
4266
4267
4268
4269
4270
4271
4272
4273
4274
4275
4276enum pno_mode {
4277 PNO_MODE_IMMEDIATE,
4278 PNO_MODE_ON_SUSPEND,
4279 PNO_MODE_ON_RESUME,
4280 PNO_MODE_MAX = WCN36XX_HAL_MAX_ENUM_SIZE
4281};
4282
4283
4284enum auth_type {
4285 AUTH_TYPE_ANY = 0,
4286 AUTH_TYPE_OPEN_SYSTEM = 1,
4287
4288
4289 AUTH_TYPE_WPA = 2,
4290 AUTH_TYPE_WPA_PSK = 3,
4291
4292 AUTH_TYPE_RSN = 4,
4293 AUTH_TYPE_RSN_PSK = 5,
4294 AUTH_TYPE_FT_RSN = 6,
4295 AUTH_TYPE_FT_RSN_PSK = 7,
4296 AUTH_TYPE_WAPI_WAI_CERTIFICATE = 8,
4297 AUTH_TYPE_WAPI_WAI_PSK = 9,
4298
4299 AUTH_TYPE_MAX = WCN36XX_HAL_MAX_ENUM_SIZE
4300};
4301
4302
4303enum ed_type {
4304 ED_ANY = 0,
4305 ED_NONE = 1,
4306 ED_WEP = 2,
4307 ED_TKIP = 3,
4308 ED_CCMP = 4,
4309 ED_WPI = 5,
4310
4311 ED_TYPE_MAX = WCN36XX_HAL_MAX_ENUM_SIZE
4312};
4313
4314
4315enum ssid_bcast_type {
4316 BCAST_UNKNOWN = 0,
4317 BCAST_NORMAL = 1,
4318 BCAST_HIDDEN = 2,
4319
4320 BCAST_TYPE_MAX = WCN36XX_HAL_MAX_ENUM_SIZE
4321};
4322
4323
4324struct network_type {
4325
4326 struct wcn36xx_hal_mac_ssid ssid;
4327
4328
4329 enum auth_type authentication;
4330
4331
4332 enum ed_type encryption;
4333
4334
4335
4336 u8 channel_count;
4337 u8 channels[WCN36XX_HAL_PNO_MAX_NETW_CHANNELS];
4338
4339
4340 u8 rssi_threshold;
4341};
4342
4343struct scan_timer {
4344
4345 u32 value;
4346
4347
4348
4349 u32 repeat;
4350
4351
4352
4353
4354};
4355
4356
4357struct scan_timers_type {
4358
4359 u8 count;
4360
4361
4362
4363
4364
4365
4366
4367
4368 struct scan_timer values[WCN36XX_HAL_PNO_MAX_SCAN_TIMERS];
4369};
4370
4371
4372struct set_pref_netw_list_req {
4373 struct wcn36xx_hal_msg_header header;
4374
4375
4376 u32 enable;
4377
4378
4379 enum pno_mode mode;
4380
4381
4382 u32 networks_count;
4383
4384
4385 struct network_type networks[WCN36XX_HAL_PNO_MAX_SUPP_NETWORKS];
4386
4387
4388 struct scan_timers_type scan_timers;
4389
4390
4391 u16 band_24g_probe_size;
4392 u8 band_24g_probe_template[WCN36XX_HAL_PNO_MAX_PROBE_SIZE];
4393
4394
4395 u16 band_5g_probe_size;
4396 u8 band_5g_probe_template[WCN36XX_HAL_PNO_MAX_PROBE_SIZE];
4397};
4398
4399
4400struct network_type_new {
4401
4402 struct wcn36xx_hal_mac_ssid ssid;
4403
4404
4405 enum auth_type authentication;
4406
4407
4408 enum ed_type encryption;
4409
4410
4411 enum ssid_bcast_type bcast_network_type;
4412
4413
4414
4415 u8 channel_count;
4416 u8 channels[WCN36XX_HAL_PNO_MAX_NETW_CHANNELS];
4417
4418
4419 u8 rssi_threshold;
4420};
4421
4422
4423struct set_pref_netw_list_req_new {
4424 struct wcn36xx_hal_msg_header header;
4425
4426
4427 u32 enable;
4428
4429
4430 enum pno_mode mode;
4431
4432
4433 u32 networks_count;
4434
4435
4436 struct network_type_new networks[WCN36XX_HAL_PNO_MAX_SUPP_NETWORKS];
4437
4438
4439 struct scan_timers_type scan_timers;
4440
4441
4442 u16 band_24g_probe_size;
4443 u8 band_24g_probe_template[WCN36XX_HAL_PNO_MAX_PROBE_SIZE];
4444
4445
4446 u16 band_5g_probe_size;
4447 u8 band_5g_probe_template[WCN36XX_HAL_PNO_MAX_PROBE_SIZE];
4448};
4449
4450
4451struct set_pref_netw_list_resp {
4452 struct wcn36xx_hal_msg_header header;
4453
4454
4455
4456 u32 status;
4457};
4458
4459
4460struct pref_netw_found_ind {
4461
4462 struct wcn36xx_hal_msg_header header;
4463
4464
4465 struct wcn36xx_hal_mac_ssid ssid;
4466
4467
4468 u8 rssi;
4469};
4470
4471
4472struct set_rssi_filter_req {
4473 struct wcn36xx_hal_msg_header header;
4474
4475
4476 u8 rssi_threshold;
4477};
4478
4479
4480struct set_rssi_filter_resp {
4481 struct wcn36xx_hal_msg_header header;
4482
4483
4484 u32 status;
4485};
4486
4487
4488
4489struct wcn36xx_hal_update_scan_params_req {
4490
4491 struct wcn36xx_hal_msg_header header;
4492
4493
4494 u8 dot11d_enabled;
4495
4496
4497 u8 dot11d_resolved;
4498
4499
4500 u8 channel_count;
4501 u8 channels[WCN36XX_HAL_PNO_MAX_NETW_CHANNELS];
4502
4503
4504 u16 active_min_ch_time;
4505
4506
4507 u16 active_max_ch_time;
4508
4509
4510 u16 passive_min_ch_time;
4511
4512
4513 u16 passive_max_ch_time;
4514
4515
4516 enum phy_chan_bond_state state;
4517} __packed;
4518
4519
4520
4521struct wcn36xx_hal_update_scan_params_req_ex {
4522
4523 struct wcn36xx_hal_msg_header header;
4524
4525
4526 u8 dot11d_enabled;
4527
4528
4529 u8 dot11d_resolved;
4530
4531
4532 u8 channel_count;
4533 u8 channels[WCN36XX_HAL_PNO_MAX_NETW_CHANNELS_EX];
4534
4535
4536 u16 active_min_ch_time;
4537
4538
4539 u16 active_max_ch_time;
4540
4541
4542 u16 passive_min_ch_time;
4543
4544
4545 u16 passive_max_ch_time;
4546
4547
4548 enum phy_chan_bond_state state;
4549} __packed;
4550
4551
4552
4553struct wcn36xx_hal_update_scan_params_resp {
4554
4555 struct wcn36xx_hal_msg_header header;
4556
4557
4558 u32 status;
4559} __packed;
4560
4561struct wcn36xx_hal_set_tx_per_tracking_req_msg {
4562 struct wcn36xx_hal_msg_header header;
4563
4564
4565 u8 tx_per_tracking_enable;
4566
4567
4568 u8 tx_per_tracking_period;
4569
4570
4571 u8 tx_per_tracking_ratio;
4572
4573
4574
4575 u32 tx_per_tracking_watermark;
4576};
4577
4578struct wcn36xx_hal_set_tx_per_tracking_rsp_msg {
4579 struct wcn36xx_hal_msg_header header;
4580
4581
4582 u32 status;
4583
4584};
4585
4586struct tx_per_hit_ind_msg {
4587 struct wcn36xx_hal_msg_header header;
4588};
4589
4590
4591#define WCN36XX_HAL_PROTOCOL_DATA_LEN 8
4592#define WCN36XX_HAL_MAX_NUM_MULTICAST_ADDRESS 240
4593#define WCN36XX_HAL_MAX_NUM_FILTERS 20
4594#define WCN36XX_HAL_MAX_CMP_PER_FILTER 10
4595
4596enum wcn36xx_hal_receive_packet_filter_type {
4597 HAL_RCV_FILTER_TYPE_INVALID,
4598 HAL_RCV_FILTER_TYPE_FILTER_PKT,
4599 HAL_RCV_FILTER_TYPE_BUFFER_PKT,
4600 HAL_RCV_FILTER_TYPE_MAX_ENUM_SIZE
4601};
4602
4603enum wcn36xx_hal_rcv_pkt_flt_protocol_type {
4604 HAL_FILTER_PROTO_TYPE_INVALID,
4605 HAL_FILTER_PROTO_TYPE_MAC,
4606 HAL_FILTER_PROTO_TYPE_ARP,
4607 HAL_FILTER_PROTO_TYPE_IPV4,
4608 HAL_FILTER_PROTO_TYPE_IPV6,
4609 HAL_FILTER_PROTO_TYPE_UDP,
4610 HAL_FILTER_PROTO_TYPE_MAX
4611};
4612
4613enum wcn36xx_hal_rcv_pkt_flt_cmp_flag_type {
4614 HAL_FILTER_CMP_TYPE_INVALID,
4615 HAL_FILTER_CMP_TYPE_EQUAL,
4616 HAL_FILTER_CMP_TYPE_MASK_EQUAL,
4617 HAL_FILTER_CMP_TYPE_NOT_EQUAL,
4618 HAL_FILTER_CMP_TYPE_MAX
4619};
4620
4621struct wcn36xx_hal_rcv_pkt_filter_params {
4622 u8 protocol_layer;
4623 u8 cmp_flag;
4624
4625
4626 u16 data_length;
4627
4628
4629 u8 data_offset;
4630
4631
4632 u8 reserved;
4633
4634
4635 u8 compare_data[WCN36XX_HAL_PROTOCOL_DATA_LEN];
4636
4637
4638 u8 data_mask[WCN36XX_HAL_PROTOCOL_DATA_LEN];
4639};
4640
4641struct wcn36xx_hal_sessionized_rcv_pkt_filter_cfg_type {
4642 u8 id;
4643 u8 type;
4644 u8 params_count;
4645 u32 coleasce_time;
4646 u8 bss_index;
4647 struct wcn36xx_hal_rcv_pkt_filter_params params[1];
4648};
4649
4650struct wcn36xx_hal_set_rcv_pkt_filter_req_msg {
4651 struct wcn36xx_hal_msg_header header;
4652
4653 u8 id;
4654 u8 type;
4655 u8 params_count;
4656 u32 coalesce_time;
4657 struct wcn36xx_hal_rcv_pkt_filter_params params[1];
4658};
4659
4660struct wcn36xx_hal_rcv_flt_mc_addr_list_type {
4661
4662 u8 data_offset;
4663
4664 u32 mc_addr_count;
4665 u8 mc_addr[WCN36XX_HAL_MAX_NUM_MULTICAST_ADDRESS][ETH_ALEN];
4666 u8 bss_index;
4667} __packed;
4668
4669struct wcn36xx_hal_set_pkt_filter_rsp_msg {
4670 struct wcn36xx_hal_msg_header header;
4671
4672
4673 u32 status;
4674
4675 u8 bss_index;
4676};
4677
4678struct wcn36xx_hal_rcv_flt_pkt_match_cnt_req_msg {
4679 struct wcn36xx_hal_msg_header header;
4680
4681 u8 bss_index;
4682};
4683
4684struct wcn36xx_hal_rcv_flt_pkt_match_cnt {
4685 u8 id;
4686 u32 match_cnt;
4687};
4688
4689struct wcn36xx_hal_rcv_flt_pkt_match_cnt_rsp_msg {
4690 struct wcn36xx_hal_msg_header header;
4691
4692
4693 u32 status;
4694
4695 u32 match_count;
4696 struct wcn36xx_hal_rcv_flt_pkt_match_cnt
4697 matches[WCN36XX_HAL_MAX_NUM_FILTERS];
4698 u8 bss_index;
4699};
4700
4701struct wcn36xx_hal_rcv_flt_pkt_clear_param {
4702
4703 u32 status;
4704 u8 id;
4705 u8 bss_index;
4706};
4707
4708struct wcn36xx_hal_rcv_flt_pkt_clear_req_msg {
4709 struct wcn36xx_hal_msg_header header;
4710 struct wcn36xx_hal_rcv_flt_pkt_clear_param param;
4711};
4712
4713struct wcn36xx_hal_rcv_flt_pkt_clear_rsp_msg {
4714 struct wcn36xx_hal_msg_header header;
4715 struct wcn36xx_hal_rcv_flt_pkt_clear_param param;
4716};
4717
4718struct wcn36xx_hal_rcv_flt_pkt_set_mc_list_req_msg {
4719 struct wcn36xx_hal_msg_header header;
4720 struct wcn36xx_hal_rcv_flt_mc_addr_list_type mc_addr_list;
4721} __packed;
4722
4723struct wcn36xx_hal_rcv_flt_pkt_set_mc_list_rsp_msg {
4724 struct wcn36xx_hal_msg_header header;
4725 u32 status;
4726 u8 bss_index;
4727};
4728
4729
4730
4731struct wcn36xx_hal_set_power_params_req_msg {
4732 struct wcn36xx_hal_msg_header header;
4733
4734
4735 u32 ignore_dtim;
4736
4737
4738 u32 dtim_period;
4739
4740
4741 u32 listen_interval;
4742
4743
4744 u32 bcast_mcast_filter;
4745
4746
4747 u32 enable_bet;
4748
4749
4750 u32 bet_interval;
4751} __packed;
4752
4753struct wcn36xx_hal_set_power_params_resp {
4754
4755 struct wcn36xx_hal_msg_header header;
4756
4757
4758 u32 status;
4759} __packed;
4760
4761
4762
4763enum place_holder_in_cap_bitmap {
4764 MCC = 0,
4765 P2P = 1,
4766 DOT11AC = 2,
4767 SLM_SESSIONIZATION = 3,
4768 DOT11AC_OPMODE = 4,
4769 SAP32STA = 5,
4770 TDLS = 6,
4771 P2P_GO_NOA_DECOUPLE_INIT_SCAN = 7,
4772 WLANACTIVE_OFFLOAD = 8,
4773 BEACON_OFFLOAD = 9,
4774 SCAN_OFFLOAD = 10,
4775 ROAM_OFFLOAD = 11,
4776 BCN_MISS_OFFLOAD = 12,
4777 STA_POWERSAVE = 13,
4778 STA_ADVANCED_PWRSAVE = 14,
4779 AP_UAPSD = 15,
4780 AP_DFS = 16,
4781 BLOCKACK = 17,
4782 PHY_ERR = 18,
4783 BCN_FILTER = 19,
4784 RTT = 20,
4785 RATECTRL = 21,
4786 WOW = 22,
4787 WLAN_ROAM_SCAN_OFFLOAD = 23,
4788 SPECULATIVE_PS_POLL = 24,
4789 SCAN_SCH = 25,
4790 IBSS_HEARTBEAT_OFFLOAD = 26,
4791 WLAN_SCAN_OFFLOAD = 27,
4792 WLAN_PERIODIC_TX_PTRN = 28,
4793 ADVANCE_TDLS = 29,
4794 BATCH_SCAN = 30,
4795 FW_IN_TX_PATH = 31,
4796 EXTENDED_NSOFFLOAD_SLOT = 32,
4797 CH_SWITCH_V1 = 33,
4798 HT40_OBSS_SCAN = 34,
4799 UPDATE_CHANNEL_LIST = 35,
4800 WLAN_MCADDR_FLT = 36,
4801 WLAN_CH144 = 37,
4802 NAN = 38,
4803 TDLS_SCAN_COEXISTENCE = 39,
4804 LINK_LAYER_STATS_MEAS = 40,
4805 MU_MIMO = 41,
4806 EXTENDED_SCAN = 42,
4807 DYNAMIC_WMM_PS = 43,
4808 MAC_SPOOFED_SCAN = 44,
4809 BMU_ERROR_GENERIC_RECOVERY = 45,
4810 DISA = 46,
4811 FW_STATS = 47,
4812 WPS_PRBRSP_TMPL = 48,
4813 BCN_IE_FLT_DELTA = 49,
4814 TDLS_OFF_CHANNEL = 51,
4815 RTT3 = 52,
4816 MGMT_FRAME_LOGGING = 53,
4817 ENHANCED_TXBD_COMPLETION = 54,
4818 LOGGING_ENHANCEMENT = 55,
4819 EXT_SCAN_ENHANCED = 56,
4820 MEMORY_DUMP_SUPPORTED = 57,
4821 PER_PKT_STATS_SUPPORTED = 58,
4822 EXT_LL_STAT = 60,
4823 WIFI_CONFIG = 61,
4824 ANTENNA_DIVERSITY_SELECTION = 62,
4825
4826 MAX_FEATURE_SUPPORTED = 128,
4827};
4828
4829#define WCN36XX_HAL_CAPS_SIZE 4
4830
4831struct wcn36xx_hal_feat_caps_msg {
4832
4833 struct wcn36xx_hal_msg_header header;
4834
4835 u32 feat_caps[WCN36XX_HAL_CAPS_SIZE];
4836} __packed;
4837
4838
4839enum gtk_rekey_status {
4840 WCN36XX_HAL_GTK_REKEY_STATUS_SUCCESS = 0,
4841
4842
4843 WCN36XX_HAL_GTK_REKEY_STATUS_NOT_HANDLED = 1,
4844
4845
4846 WCN36XX_HAL_GTK_REKEY_STATUS_MIC_ERROR = 2,
4847
4848
4849 WCN36XX_HAL_GTK_REKEY_STATUS_DECRYPT_ERROR = 3,
4850
4851
4852 WCN36XX_HAL_GTK_REKEY_STATUS_REPLAY_ERROR = 4,
4853
4854
4855 WCN36XX_HAL_GTK_REKEY_STATUS_MISSING_KDE = 5,
4856
4857
4858 WCN36XX_HAL_GTK_REKEY_STATUS_MISSING_IGTK_KDE = 6,
4859
4860
4861 WCN36XX_HAL_GTK_REKEY_STATUS_INSTALL_ERROR = 7,
4862
4863
4864 WCN36XX_HAL_GTK_REKEY_STATUS_IGTK_INSTALL_ERROR = 8,
4865
4866
4867 WCN36XX_HAL_GTK_REKEY_STATUS_RESP_TX_ERROR = 9,
4868
4869
4870 WCN36XX_HAL_GTK_REKEY_STATUS_GEN_ERROR = 255
4871};
4872
4873
4874enum wake_reason_type {
4875 WCN36XX_HAL_WAKE_REASON_NONE = 0,
4876
4877
4878 WCN36XX_HAL_WAKE_REASON_MAGIC_PACKET = 1,
4879
4880
4881 WCN36XX_HAL_WAKE_REASON_PATTERN_MATCH = 2,
4882
4883
4884 WCN36XX_HAL_WAKE_REASON_EAPID_PACKET = 3,
4885
4886
4887 WCN36XX_HAL_WAKE_REASON_EAPOL4WAY_PACKET = 4,
4888
4889
4890 WCN36XX_HAL_WAKE_REASON_NETSCAN_OFFL_MATCH = 5,
4891
4892
4893 WCN36XX_HAL_WAKE_REASON_GTK_REKEY_STATUS = 6,
4894
4895
4896 WCN36XX_HAL_WAKE_REASON_BSS_CONN_LOST = 7,
4897};
4898
4899
4900
4901
4902
4903
4904
4905
4906
4907
4908
4909
4910
4911
4912
4913
4914struct wcn36xx_hal_wake_reason_ind {
4915 struct wcn36xx_hal_msg_header header;
4916
4917
4918 u32 reason;
4919
4920
4921 u32 reason_arg;
4922
4923
4924
4925
4926 u32 stored_data_len;
4927
4928
4929 u32 actual_data_len;
4930
4931
4932
4933 u8 data_start[1];
4934
4935 u32 bss_index:8;
4936 u32 reserved:24;
4937};
4938
4939#define WCN36XX_HAL_GTK_KEK_BYTES 16
4940#define WCN36XX_HAL_GTK_KCK_BYTES 16
4941
4942#define WCN36XX_HAL_GTK_OFFLOAD_FLAGS_DISABLE (1 << 0)
4943
4944#define GTK_SET_BSS_KEY_TAG 0x1234AA55
4945
4946struct wcn36xx_hal_gtk_offload_req_msg {
4947 struct wcn36xx_hal_msg_header header;
4948
4949
4950 u32 flags;
4951
4952
4953 u8 kck[WCN36XX_HAL_GTK_KCK_BYTES];
4954
4955
4956 u8 kek[WCN36XX_HAL_GTK_KEK_BYTES];
4957
4958
4959 u64 key_replay_counter;
4960
4961 u8 bss_index;
4962} __packed;
4963
4964struct wcn36xx_hal_gtk_offload_rsp_msg {
4965 struct wcn36xx_hal_msg_header header;
4966
4967
4968 u32 status;
4969
4970 u8 bss_index;
4971};
4972
4973struct wcn36xx_hal_gtk_offload_get_info_req_msg {
4974 struct wcn36xx_hal_msg_header header;
4975 u8 bss_index;
4976} __packed;
4977
4978struct wcn36xx_hal_gtk_offload_get_info_rsp_msg {
4979 struct wcn36xx_hal_msg_header header;
4980
4981
4982 u32 status;
4983
4984
4985 u32 last_rekey_status;
4986
4987
4988 u64 key_replay_counter;
4989
4990
4991 u32 total_rekey_count;
4992
4993
4994 u32 gtk_rekey_count;
4995
4996
4997 u32 igtk_rekey_count;
4998
4999 u8 bss_index;
5000} __packed;
5001
5002struct dhcp_info {
5003
5004 u8 device_mode;
5005
5006 u8 addr[ETH_ALEN];
5007};
5008
5009struct dhcp_ind_status {
5010 struct wcn36xx_hal_msg_header header;
5011
5012
5013 u32 status;
5014};
5015
5016
5017
5018
5019
5020
5021
5022
5023
5024
5025enum wcn36xx_hal_thermal_mitigation_mode_type {
5026 HAL_THERMAL_MITIGATION_MODE_INVALID = -1,
5027 HAL_THERMAL_MITIGATION_MODE_0,
5028 HAL_THERMAL_MITIGATION_MODE_1,
5029 HAL_THERMAL_MITIGATION_MODE_2,
5030 HAL_THERMAL_MITIGATION_MODE_MAX = WCN36XX_HAL_MAX_ENUM_SIZE,
5031};
5032
5033
5034
5035
5036
5037
5038
5039
5040
5041
5042
5043
5044
5045
5046
5047
5048
5049
5050
5051enum wcn36xx_hal_thermal_mitigation_level_type {
5052 HAL_THERMAL_MITIGATION_LEVEL_INVALID = -1,
5053 HAL_THERMAL_MITIGATION_LEVEL_0,
5054 HAL_THERMAL_MITIGATION_LEVEL_1,
5055 HAL_THERMAL_MITIGATION_LEVEL_2,
5056 HAL_THERMAL_MITIGATION_LEVEL_3,
5057 HAL_THERMAL_MITIGATION_LEVEL_4,
5058 HAL_THERMAL_MITIGATION_LEVEL_MAX = WCN36XX_HAL_MAX_ENUM_SIZE,
5059};
5060
5061
5062
5063struct set_thermal_mitigation_req_msg {
5064 struct wcn36xx_hal_msg_header header;
5065
5066
5067 enum wcn36xx_hal_thermal_mitigation_mode_type mode;
5068
5069
5070 enum wcn36xx_hal_thermal_mitigation_level_type level;
5071};
5072
5073struct set_thermal_mitigation_resp {
5074
5075 struct wcn36xx_hal_msg_header header;
5076
5077
5078 u32 status;
5079};
5080
5081
5082
5083struct stats_class_b_ind {
5084 struct wcn36xx_hal_msg_header header;
5085
5086
5087 u32 duration;
5088
5089
5090
5091
5092 u32 tx_bytes_pushed;
5093 u32 tx_packets_pushed;
5094
5095
5096 u32 rx_bytes_rcvd;
5097 u32 rx_packets_rcvd;
5098 u32 rx_time_total;
5099};
5100
5101
5102struct wcn36xx_hal_print_reg_info_ind {
5103 struct wcn36xx_hal_msg_header header;
5104
5105 u32 count;
5106 u32 scenario;
5107 u32 reason;
5108
5109 struct {
5110 u32 addr;
5111 u32 value;
5112 } regs[];
5113} __packed;
5114
5115#endif
5116