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11#ifndef __iwl_commands_h__
12#define __iwl_commands_h__
13
14#include <linux/ieee80211.h>
15#include <linux/types.h>
16
17
18enum {
19 REPLY_ALIVE = 0x1,
20 REPLY_ERROR = 0x2,
21 REPLY_ECHO = 0x3,
22
23
24 REPLY_RXON = 0x10,
25 REPLY_RXON_ASSOC = 0x11,
26 REPLY_QOS_PARAM = 0x13,
27 REPLY_RXON_TIMING = 0x14,
28
29
30 REPLY_ADD_STA = 0x18,
31 REPLY_REMOVE_STA = 0x19,
32 REPLY_REMOVE_ALL_STA = 0x1a,
33 REPLY_TXFIFO_FLUSH = 0x1e,
34
35
36 REPLY_WEPKEY = 0x20,
37
38
39 REPLY_TX = 0x1c,
40 REPLY_LEDS_CMD = 0x48,
41 REPLY_TX_LINK_QUALITY_CMD = 0x4e,
42
43
44 COEX_PRIORITY_TABLE_CMD = 0x5a,
45 COEX_MEDIUM_NOTIFICATION = 0x5b,
46 COEX_EVENT_CMD = 0x5c,
47
48
49 TEMPERATURE_NOTIFICATION = 0x62,
50 CALIBRATION_CFG_CMD = 0x65,
51 CALIBRATION_RES_NOTIFICATION = 0x66,
52 CALIBRATION_COMPLETE_NOTIFICATION = 0x67,
53
54
55 REPLY_QUIET_CMD = 0x71,
56 REPLY_CHANNEL_SWITCH = 0x72,
57 CHANNEL_SWITCH_NOTIFICATION = 0x73,
58 REPLY_SPECTRUM_MEASUREMENT_CMD = 0x74,
59 SPECTRUM_MEASURE_NOTIFICATION = 0x75,
60
61
62 POWER_TABLE_CMD = 0x77,
63 PM_SLEEP_NOTIFICATION = 0x7A,
64 PM_DEBUG_STATISTIC_NOTIFIC = 0x7B,
65
66
67 REPLY_SCAN_CMD = 0x80,
68 REPLY_SCAN_ABORT_CMD = 0x81,
69 SCAN_START_NOTIFICATION = 0x82,
70 SCAN_RESULTS_NOTIFICATION = 0x83,
71 SCAN_COMPLETE_NOTIFICATION = 0x84,
72
73
74 BEACON_NOTIFICATION = 0x90,
75 REPLY_TX_BEACON = 0x91,
76 WHO_IS_AWAKE_NOTIFICATION = 0x94,
77
78
79 REPLY_TX_POWER_DBM_CMD = 0x95,
80 QUIET_NOTIFICATION = 0x96,
81 REPLY_TX_PWR_TABLE_CMD = 0x97,
82 REPLY_TX_POWER_DBM_CMD_V1 = 0x98,
83 TX_ANT_CONFIGURATION_CMD = 0x98,
84 MEASURE_ABORT_NOTIFICATION = 0x99,
85
86
87 REPLY_BT_CONFIG = 0x9b,
88
89
90 REPLY_STATISTICS_CMD = 0x9c,
91 STATISTICS_NOTIFICATION = 0x9d,
92
93
94 REPLY_CARD_STATE_CMD = 0xa0,
95 CARD_STATE_NOTIFICATION = 0xa1,
96
97
98 MISSED_BEACONS_NOTIFICATION = 0xa2,
99
100 REPLY_CT_KILL_CONFIG_CMD = 0xa4,
101 SENSITIVITY_CMD = 0xa8,
102 REPLY_PHY_CALIBRATION_CMD = 0xb0,
103 REPLY_RX_PHY_CMD = 0xc0,
104 REPLY_RX_MPDU_CMD = 0xc1,
105 REPLY_RX = 0xc3,
106 REPLY_COMPRESSED_BA = 0xc5,
107
108
109 REPLY_BT_COEX_PRIO_TABLE = 0xcc,
110 REPLY_BT_COEX_PROT_ENV = 0xcd,
111 REPLY_BT_COEX_PROFILE_NOTIF = 0xce,
112
113
114 REPLY_WIPAN_PARAMS = 0xb2,
115 REPLY_WIPAN_RXON = 0xb3,
116 REPLY_WIPAN_RXON_TIMING = 0xb4,
117 REPLY_WIPAN_RXON_ASSOC = 0xb6,
118 REPLY_WIPAN_QOS_PARAM = 0xb7,
119 REPLY_WIPAN_WEPKEY = 0xb8,
120 REPLY_WIPAN_P2P_CHANNEL_SWITCH = 0xb9,
121 REPLY_WIPAN_NOA_NOTIFICATION = 0xbc,
122 REPLY_WIPAN_DEACTIVATION_COMPLETE = 0xbd,
123
124 REPLY_WOWLAN_PATTERNS = 0xe0,
125 REPLY_WOWLAN_WAKEUP_FILTER = 0xe1,
126 REPLY_WOWLAN_TSC_RSC_PARAMS = 0xe2,
127 REPLY_WOWLAN_TKIP_PARAMS = 0xe3,
128 REPLY_WOWLAN_KEK_KCK_MATERIAL = 0xe4,
129 REPLY_WOWLAN_GET_STATUS = 0xe5,
130 REPLY_D3_CONFIG = 0xd3,
131
132 REPLY_MAX = 0xff
133};
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143
144#define IWL_MIN_NUM_QUEUES 11
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148
149#define IWL_DEFAULT_CMD_QUEUE_NUM 4
150#define IWL_IPAN_CMD_QUEUE_NUM 9
151
152#define IWL_TX_FIFO_BK 0
153#define IWL_TX_FIFO_BE 1
154#define IWL_TX_FIFO_VI 2
155#define IWL_TX_FIFO_VO 3
156#define IWL_TX_FIFO_BK_IPAN IWL_TX_FIFO_BK
157#define IWL_TX_FIFO_BE_IPAN 4
158#define IWL_TX_FIFO_VI_IPAN IWL_TX_FIFO_VI
159#define IWL_TX_FIFO_VO_IPAN 5
160
161#define IWL_TX_FIFO_AUX 5
162#define IWL_TX_FIFO_UNUSED 255
163
164#define IWLAGN_CMD_FIFO_NUM 7
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171#define IWL_IPAN_MCAST_QUEUE 8
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221#define RATE_MCS_CODE_MSK 0x7
222#define RATE_MCS_SPATIAL_POS 3
223#define RATE_MCS_SPATIAL_MSK 0x18
224#define RATE_MCS_HT_DUP_POS 5
225#define RATE_MCS_HT_DUP_MSK 0x20
226
227#define RATE_MCS_RATE_MSK 0xff
228
229
230#define RATE_MCS_FLAGS_POS 8
231#define RATE_MCS_HT_POS 8
232#define RATE_MCS_HT_MSK 0x100
233
234
235#define RATE_MCS_CCK_POS 9
236#define RATE_MCS_CCK_MSK 0x200
237
238
239#define RATE_MCS_GF_POS 10
240#define RATE_MCS_GF_MSK 0x400
241
242
243#define RATE_MCS_HT40_POS 11
244#define RATE_MCS_HT40_MSK 0x800
245
246
247#define RATE_MCS_DUP_POS 12
248#define RATE_MCS_DUP_MSK 0x1000
249
250
251#define RATE_MCS_SGI_POS 13
252#define RATE_MCS_SGI_MSK 0x2000
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258#define RATE_MCS_ANT_POS 14
259#define RATE_MCS_ANT_A_MSK 0x04000
260#define RATE_MCS_ANT_B_MSK 0x08000
261#define RATE_MCS_ANT_C_MSK 0x10000
262#define RATE_MCS_ANT_AB_MSK (RATE_MCS_ANT_A_MSK | RATE_MCS_ANT_B_MSK)
263#define RATE_MCS_ANT_ABC_MSK (RATE_MCS_ANT_AB_MSK | RATE_MCS_ANT_C_MSK)
264#define RATE_ANT_NUM 3
265
266#define POWER_TABLE_NUM_ENTRIES 33
267#define POWER_TABLE_NUM_HT_OFDM_ENTRIES 32
268#define POWER_TABLE_CCK_ENTRY 32
269
270#define IWL_PWR_NUM_HT_OFDM_ENTRIES 24
271#define IWL_PWR_CCK_ENTRIES 2
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280struct tx_power_dual_stream {
281 __le32 dw;
282} __packed;
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288#define IWLAGN_TX_POWER_AUTO 0x7f
289#define IWLAGN_TX_POWER_NO_CLOSED (0x1 << 6)
290
291struct iwlagn_tx_power_dbm_cmd {
292 s8 global_lmt;
293 u8 flags;
294 s8 srv_chan_lmt;
295 u8 reserved;
296} __packed;
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304struct iwl_tx_ant_config_cmd {
305 __le32 valid;
306} __packed;
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313
314#define UCODE_VALID_OK cpu_to_le32(0x1)
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362struct iwl_error_event_table {
363 u32 valid;
364 u32 error_id;
365 u32 pc;
366 u32 blink1;
367 u32 blink2;
368 u32 ilink1;
369 u32 ilink2;
370 u32 data1;
371 u32 data2;
372 u32 line;
373 u32 bcon_time;
374 u32 tsf_low;
375 u32 tsf_hi;
376 u32 gp1;
377 u32 gp2;
378 u32 gp3;
379 u32 ucode_ver;
380 u32 hw_ver;
381 u32 brd_ver;
382 u32 log_pc;
383 u32 frame_ptr;
384 u32 stack_ptr;
385 u32 hcmd;
386 u32 isr0;
387
388 u32 isr1;
389
390 u32 isr2;
391
392 u32 isr3;
393
394 u32 isr4;
395
396 u32 isr_pref;
397 u32 wait_event;
398 u32 l2p_control;
399 u32 l2p_duration;
400 u32 l2p_mhvalid;
401 u32 l2p_addr_match;
402 u32 lmpm_pmg_sel;
403
404 u32 u_timestamp;
405
406 u32 flow_handler;
407} __packed;
408
409struct iwl_alive_resp {
410 u8 ucode_minor;
411 u8 ucode_major;
412 __le16 reserved1;
413 u8 sw_rev[8];
414 u8 ver_type;
415 u8 ver_subtype;
416 __le16 reserved2;
417 __le32 log_event_table_ptr;
418 __le32 error_event_table_ptr;
419 __le32 timestamp;
420 __le32 is_valid;
421} __packed;
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425
426struct iwl_error_resp {
427 __le32 error_type;
428 u8 cmd_id;
429 u8 reserved1;
430 __le16 bad_cmd_seq_num;
431 __le32 error_info;
432 __le64 timestamp;
433} __packed;
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444
445enum {
446 RXON_DEV_TYPE_AP = 1,
447 RXON_DEV_TYPE_ESS = 3,
448 RXON_DEV_TYPE_IBSS = 4,
449 RXON_DEV_TYPE_SNIFFER = 6,
450 RXON_DEV_TYPE_CP = 7,
451 RXON_DEV_TYPE_2STA = 8,
452 RXON_DEV_TYPE_P2P = 9,
453};
454
455
456#define RXON_RX_CHAIN_DRIVER_FORCE_MSK cpu_to_le16(0x1 << 0)
457#define RXON_RX_CHAIN_DRIVER_FORCE_POS (0)
458#define RXON_RX_CHAIN_VALID_MSK cpu_to_le16(0x7 << 1)
459#define RXON_RX_CHAIN_VALID_POS (1)
460#define RXON_RX_CHAIN_FORCE_SEL_MSK cpu_to_le16(0x7 << 4)
461#define RXON_RX_CHAIN_FORCE_SEL_POS (4)
462#define RXON_RX_CHAIN_FORCE_MIMO_SEL_MSK cpu_to_le16(0x7 << 7)
463#define RXON_RX_CHAIN_FORCE_MIMO_SEL_POS (7)
464#define RXON_RX_CHAIN_CNT_MSK cpu_to_le16(0x3 << 10)
465#define RXON_RX_CHAIN_CNT_POS (10)
466#define RXON_RX_CHAIN_MIMO_CNT_MSK cpu_to_le16(0x3 << 12)
467#define RXON_RX_CHAIN_MIMO_CNT_POS (12)
468#define RXON_RX_CHAIN_MIMO_FORCE_MSK cpu_to_le16(0x1 << 14)
469#define RXON_RX_CHAIN_MIMO_FORCE_POS (14)
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472
473#define RXON_FLG_BAND_24G_MSK cpu_to_le32(1 << 0)
474#define RXON_FLG_CCK_MSK cpu_to_le32(1 << 1)
475
476#define RXON_FLG_AUTO_DETECT_MSK cpu_to_le32(1 << 2)
477
478#define RXON_FLG_TGG_PROTECT_MSK cpu_to_le32(1 << 3)
479
480#define RXON_FLG_SHORT_SLOT_MSK cpu_to_le32(1 << 4)
481#define RXON_FLG_SHORT_PREAMBLE_MSK cpu_to_le32(1 << 5)
482
483#define RXON_FLG_DIS_DIV_MSK cpu_to_le32(1 << 7)
484#define RXON_FLG_ANT_SEL_MSK cpu_to_le32(0x0f00)
485#define RXON_FLG_ANT_A_MSK cpu_to_le32(1 << 8)
486#define RXON_FLG_ANT_B_MSK cpu_to_le32(1 << 9)
487
488#define RXON_FLG_RADAR_DETECT_MSK cpu_to_le32(1 << 12)
489#define RXON_FLG_TGJ_NARROW_BAND_MSK cpu_to_le32(1 << 13)
490
491
492#define RXON_FLG_TSF2HOST_MSK cpu_to_le32(1 << 15)
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495
496#define RXON_FLG_CTRL_CHANNEL_LOC_POS (22)
497#define RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK cpu_to_le32(0x1 << 22)
498
499#define RXON_FLG_HT_OPERATING_MODE_POS (23)
500
501#define RXON_FLG_HT_PROT_MSK cpu_to_le32(0x1 << 23)
502#define RXON_FLG_HT40_PROT_MSK cpu_to_le32(0x2 << 23)
503
504#define RXON_FLG_CHANNEL_MODE_POS (25)
505#define RXON_FLG_CHANNEL_MODE_MSK cpu_to_le32(0x3 << 25)
506
507
508enum {
509 CHANNEL_MODE_LEGACY = 0,
510 CHANNEL_MODE_PURE_40 = 1,
511 CHANNEL_MODE_MIXED = 2,
512 CHANNEL_MODE_RESERVED = 3,
513};
514#define RXON_FLG_CHANNEL_MODE_LEGACY cpu_to_le32(CHANNEL_MODE_LEGACY << RXON_FLG_CHANNEL_MODE_POS)
515#define RXON_FLG_CHANNEL_MODE_PURE_40 cpu_to_le32(CHANNEL_MODE_PURE_40 << RXON_FLG_CHANNEL_MODE_POS)
516#define RXON_FLG_CHANNEL_MODE_MIXED cpu_to_le32(CHANNEL_MODE_MIXED << RXON_FLG_CHANNEL_MODE_POS)
517
518
519#define RXON_FLG_SELF_CTS_EN cpu_to_le32(0x1<<30)
520
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522
523#define RXON_FILTER_PROMISC_MSK cpu_to_le32(1 << 0)
524
525#define RXON_FILTER_CTL2HOST_MSK cpu_to_le32(1 << 1)
526
527#define RXON_FILTER_ACCEPT_GRP_MSK cpu_to_le32(1 << 2)
528
529#define RXON_FILTER_DIS_DECRYPT_MSK cpu_to_le32(1 << 3)
530
531#define RXON_FILTER_DIS_GRP_DECRYPT_MSK cpu_to_le32(1 << 4)
532
533#define RXON_FILTER_ASSOC_MSK cpu_to_le32(1 << 5)
534
535#define RXON_FILTER_BCON_AWARE_MSK cpu_to_le32(1 << 6)
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555struct iwl_rxon_cmd {
556 u8 node_addr[6];
557 __le16 reserved1;
558 u8 bssid_addr[6];
559 __le16 reserved2;
560 u8 wlap_bssid_addr[6];
561 __le16 reserved3;
562 u8 dev_type;
563 u8 air_propagation;
564 __le16 rx_chain;
565 u8 ofdm_basic_rates;
566 u8 cck_basic_rates;
567 __le16 assoc_id;
568 __le32 flags;
569 __le32 filter_flags;
570 __le16 channel;
571 u8 ofdm_ht_single_stream_basic_rates;
572 u8 ofdm_ht_dual_stream_basic_rates;
573 u8 ofdm_ht_triple_stream_basic_rates;
574 u8 reserved5;
575 __le16 acquisition_data;
576 __le16 reserved6;
577} __packed;
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582struct iwl_rxon_assoc_cmd {
583 __le32 flags;
584 __le32 filter_flags;
585 u8 ofdm_basic_rates;
586 u8 cck_basic_rates;
587 __le16 reserved1;
588 u8 ofdm_ht_single_stream_basic_rates;
589 u8 ofdm_ht_dual_stream_basic_rates;
590 u8 ofdm_ht_triple_stream_basic_rates;
591 u8 reserved2;
592 __le16 rx_chain_select_flags;
593 __le16 acquisition_data;
594 __le32 reserved3;
595} __packed;
596
597#define IWL_CONN_MAX_LISTEN_INTERVAL 10
598#define IWL_MAX_UCODE_BEACON_INTERVAL 4
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602
603struct iwl_rxon_time_cmd {
604 __le64 timestamp;
605 __le16 beacon_interval;
606 __le16 atim_window;
607 __le32 beacon_init_val;
608 __le16 listen_interval;
609 u8 dtim_period;
610 u8 delta_cp_bss_tbtts;
611} __packed;
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627struct iwl5000_channel_switch_cmd {
628 u8 band;
629 u8 expect_beacon;
630 __le16 channel;
631 __le32 rxon_flags;
632 __le32 rxon_filter_flags;
633 __le32 switch_time;
634 __le32 reserved[2][IWL_PWR_NUM_HT_OFDM_ENTRIES + IWL_PWR_CCK_ENTRIES];
635} __packed;
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648struct iwl6000_channel_switch_cmd {
649 u8 band;
650 u8 expect_beacon;
651 __le16 channel;
652 __le32 rxon_flags;
653 __le32 rxon_filter_flags;
654 __le32 switch_time;
655 __le32 reserved[3][IWL_PWR_NUM_HT_OFDM_ENTRIES + IWL_PWR_CCK_ENTRIES];
656} __packed;
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661struct iwl_csa_notification {
662 __le16 band;
663 __le16 channel;
664 __le32 status;
665} __packed;
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689struct iwl_ac_qos {
690 __le16 cw_min;
691 __le16 cw_max;
692 u8 aifsn;
693 u8 reserved1;
694 __le16 edca_txop;
695} __packed;
696
697
698#define QOS_PARAM_FLG_UPDATE_EDCA_MSK cpu_to_le32(0x01)
699#define QOS_PARAM_FLG_TGN_MSK cpu_to_le32(0x02)
700#define QOS_PARAM_FLG_TXOP_TYPE_MSK cpu_to_le32(0x10)
701
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703#define AC_NUM 4
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711struct iwl_qosparam_cmd {
712 __le32 qos_flags;
713 struct iwl_ac_qos ac[AC_NUM];
714} __packed;
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726#define IWL_AP_ID 0
727#define IWL_AP_ID_PAN 1
728#define IWL_STA_ID 2
729#define IWLAGN_PAN_BCAST_ID 14
730#define IWLAGN_BROADCAST_ID 15
731#define IWLAGN_STATION_COUNT 16
732
733#define IWL_TID_NON_QOS IWL_MAX_TID_COUNT
734
735#define STA_FLG_TX_RATE_MSK cpu_to_le32(1 << 2)
736#define STA_FLG_PWR_SAVE_MSK cpu_to_le32(1 << 8)
737#define STA_FLG_PAN_STATION cpu_to_le32(1 << 13)
738#define STA_FLG_RTS_MIMO_PROT_MSK cpu_to_le32(1 << 17)
739#define STA_FLG_AGG_MPDU_8US_MSK cpu_to_le32(1 << 18)
740#define STA_FLG_MAX_AGG_SIZE_POS (19)
741#define STA_FLG_MAX_AGG_SIZE_MSK cpu_to_le32(3 << 19)
742#define STA_FLG_HT40_EN_MSK cpu_to_le32(1 << 21)
743#define STA_FLG_MIMO_DIS_MSK cpu_to_le32(1 << 22)
744#define STA_FLG_AGG_MPDU_DENSITY_POS (23)
745#define STA_FLG_AGG_MPDU_DENSITY_MSK cpu_to_le32(7 << 23)
746
747
748#define STA_CONTROL_MODIFY_MSK 0x01
749
750
751#define STA_KEY_FLG_ENCRYPT_MSK cpu_to_le16(0x0007)
752#define STA_KEY_FLG_NO_ENC cpu_to_le16(0x0000)
753#define STA_KEY_FLG_WEP cpu_to_le16(0x0001)
754#define STA_KEY_FLG_CCMP cpu_to_le16(0x0002)
755#define STA_KEY_FLG_TKIP cpu_to_le16(0x0003)
756
757#define STA_KEY_FLG_KEYID_POS 8
758#define STA_KEY_FLG_INVALID cpu_to_le16(0x0800)
759
760#define STA_KEY_FLG_MAP_KEY_MSK cpu_to_le16(0x0008)
761
762
763#define STA_KEY_FLG_KEY_SIZE_MSK cpu_to_le16(0x1000)
764#define STA_KEY_MULTICAST_MSK cpu_to_le16(0x4000)
765#define STA_KEY_MAX_NUM 8
766#define STA_KEY_MAX_NUM_PAN 16
767
768#define IWLAGN_HW_KEY_DEFAULT 0xfe
769
770
771#define STA_MODIFY_KEY_MASK 0x01
772#define STA_MODIFY_TID_DISABLE_TX 0x02
773#define STA_MODIFY_TX_RATE_MSK 0x04
774#define STA_MODIFY_ADDBA_TID_MSK 0x08
775#define STA_MODIFY_DELBA_TID_MSK 0x10
776#define STA_MODIFY_SLEEP_TX_COUNT_MSK 0x20
777
778
779struct iwl_keyinfo {
780 __le16 key_flags;
781 u8 tkip_rx_tsc_byte2;
782 u8 reserved1;
783 __le16 tkip_rx_ttak[5];
784 u8 key_offset;
785 u8 reserved2;
786 u8 key[16];
787 __le64 tx_secur_seq_cnt;
788 __le64 hw_tkip_mic_rx_key;
789 __le64 hw_tkip_mic_tx_key;
790} __packed;
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804struct sta_id_modify {
805 u8 addr[ETH_ALEN];
806 __le16 reserved1;
807 u8 sta_id;
808 u8 modify_mask;
809 __le16 reserved2;
810} __packed;
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838struct iwl_addsta_cmd {
839 u8 mode;
840 u8 reserved[3];
841 struct sta_id_modify sta;
842 struct iwl_keyinfo key;
843 __le32 station_flags;
844 __le32 station_flags_msk;
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848
849 __le16 tid_disable_tx;
850 __le16 legacy_reserved;
851
852
853
854 u8 add_immediate_ba_tid;
855
856
857
858 u8 remove_immediate_ba_tid;
859
860
861
862 __le16 add_immediate_ba_ssn;
863
864
865
866
867
868
869 __le16 sleep_tx_count;
870
871 __le16 reserved2;
872} __packed;
873
874
875#define ADD_STA_SUCCESS_MSK 0x1
876#define ADD_STA_NO_ROOM_IN_TABLE 0x2
877#define ADD_STA_NO_BLOCK_ACK_RESOURCE 0x4
878#define ADD_STA_MODIFY_NON_EXIST_STA 0x8
879
880
881
882struct iwl_add_sta_resp {
883 u8 status;
884} __packed;
885
886#define REM_STA_SUCCESS_MSK 0x1
887
888
889
890struct iwl_rem_sta_resp {
891 u8 status;
892} __packed;
893
894
895
896
897struct iwl_rem_sta_cmd {
898 u8 num_sta;
899 u8 reserved[3];
900 u8 addr[ETH_ALEN];
901 u8 reserved2[2];
902} __packed;
903
904
905
906#define IWL_SCD_BK_MSK BIT(0)
907#define IWL_SCD_BE_MSK BIT(1)
908#define IWL_SCD_VI_MSK BIT(2)
909#define IWL_SCD_VO_MSK BIT(3)
910#define IWL_SCD_MGMT_MSK BIT(3)
911
912
913#define IWL_PAN_SCD_BK_MSK BIT(4)
914#define IWL_PAN_SCD_BE_MSK BIT(5)
915#define IWL_PAN_SCD_VI_MSK BIT(6)
916#define IWL_PAN_SCD_VO_MSK BIT(7)
917#define IWL_PAN_SCD_MGMT_MSK BIT(7)
918#define IWL_PAN_SCD_MULTICAST_MSK BIT(8)
919
920#define IWL_AGG_TX_QUEUE_MSK 0xffc00
921
922#define IWL_DROP_ALL BIT(1)
923
924
925
926
927
928
929
930
931
932
933
934
935
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937
938
939
940
941
942
943
944
945struct iwl_txfifo_flush_cmd_v3 {
946 __le32 queue_control;
947 __le16 flush_control;
948 __le16 reserved;
949} __packed;
950
951struct iwl_txfifo_flush_cmd_v2 {
952 __le16 queue_control;
953 __le16 flush_control;
954} __packed;
955
956
957
958
959struct iwl_wep_key {
960 u8 key_index;
961 u8 key_offset;
962 u8 reserved1[2];
963 u8 key_size;
964 u8 reserved2[3];
965 u8 key[16];
966} __packed;
967
968struct iwl_wep_cmd {
969 u8 num_keys;
970 u8 global_key_type;
971 u8 flags;
972 u8 reserved;
973 struct iwl_wep_key key[];
974} __packed;
975
976#define WEP_KEY_WEP_TYPE 1
977#define WEP_KEYS_MAX 4
978#define WEP_INVALID_OFFSET 0xff
979#define WEP_KEY_LEN_64 5
980#define WEP_KEY_LEN_128 13
981
982
983
984
985
986
987
988#define RX_RES_STATUS_NO_CRC32_ERROR cpu_to_le32(1 << 0)
989#define RX_RES_STATUS_NO_RXE_OVERFLOW cpu_to_le32(1 << 1)
990
991#define RX_RES_PHY_FLAGS_BAND_24_MSK cpu_to_le16(1 << 0)
992#define RX_RES_PHY_FLAGS_MOD_CCK_MSK cpu_to_le16(1 << 1)
993#define RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK cpu_to_le16(1 << 2)
994#define RX_RES_PHY_FLAGS_NARROW_BAND_MSK cpu_to_le16(1 << 3)
995#define RX_RES_PHY_FLAGS_ANTENNA_MSK 0x70
996#define RX_RES_PHY_FLAGS_ANTENNA_POS 4
997#define RX_RES_PHY_FLAGS_AGG_MSK cpu_to_le16(1 << 7)
998
999#define RX_RES_STATUS_SEC_TYPE_MSK (0x7 << 8)
1000#define RX_RES_STATUS_SEC_TYPE_NONE (0x0 << 8)
1001#define RX_RES_STATUS_SEC_TYPE_WEP (0x1 << 8)
1002#define RX_RES_STATUS_SEC_TYPE_CCMP (0x2 << 8)
1003#define RX_RES_STATUS_SEC_TYPE_TKIP (0x3 << 8)
1004#define RX_RES_STATUS_SEC_TYPE_ERR (0x7 << 8)
1005
1006#define RX_RES_STATUS_STATION_FOUND (1<<6)
1007#define RX_RES_STATUS_NO_STATION_INFO_MISMATCH (1<<7)
1008
1009#define RX_RES_STATUS_DECRYPT_TYPE_MSK (0x3 << 11)
1010#define RX_RES_STATUS_NOT_DECRYPT (0x0 << 11)
1011#define RX_RES_STATUS_DECRYPT_OK (0x3 << 11)
1012#define RX_RES_STATUS_BAD_ICV_MIC (0x1 << 11)
1013#define RX_RES_STATUS_BAD_KEY_TTAK (0x2 << 11)
1014
1015#define RX_MPDU_RES_STATUS_ICV_OK (0x20)
1016#define RX_MPDU_RES_STATUS_MIC_OK (0x40)
1017#define RX_MPDU_RES_STATUS_TTAK_OK (1 << 7)
1018#define RX_MPDU_RES_STATUS_DEC_DONE_MSK (0x800)
1019
1020
1021#define IWLAGN_RX_RES_PHY_CNT 8
1022#define IWLAGN_RX_RES_AGC_IDX 1
1023#define IWLAGN_RX_RES_RSSI_AB_IDX 2
1024#define IWLAGN_RX_RES_RSSI_C_IDX 3
1025#define IWLAGN_OFDM_AGC_MSK 0xfe00
1026#define IWLAGN_OFDM_AGC_BIT_POS 9
1027#define IWLAGN_OFDM_RSSI_INBAND_A_BITMSK 0x00ff
1028#define IWLAGN_OFDM_RSSI_ALLBAND_A_BITMSK 0xff00
1029#define IWLAGN_OFDM_RSSI_A_BIT_POS 0
1030#define IWLAGN_OFDM_RSSI_INBAND_B_BITMSK 0xff0000
1031#define IWLAGN_OFDM_RSSI_ALLBAND_B_BITMSK 0xff000000
1032#define IWLAGN_OFDM_RSSI_B_BIT_POS 16
1033#define IWLAGN_OFDM_RSSI_INBAND_C_BITMSK 0x00ff
1034#define IWLAGN_OFDM_RSSI_ALLBAND_C_BITMSK 0xff00
1035#define IWLAGN_OFDM_RSSI_C_BIT_POS 0
1036
1037struct iwlagn_non_cfg_phy {
1038 __le32 non_cfg_phy[IWLAGN_RX_RES_PHY_CNT];
1039} __packed;
1040
1041
1042
1043
1044
1045
1046struct iwl_rx_phy_res {
1047 u8 non_cfg_phy_cnt;
1048 u8 cfg_phy_cnt;
1049 u8 stat_id;
1050 u8 reserved1;
1051 __le64 timestamp;
1052 __le32 beacon_time_stamp;
1053 __le16 phy_flags;
1054 __le16 channel;
1055 u8 non_cfg_phy_buf[32];
1056 __le32 rate_n_flags;
1057 __le16 byte_count;
1058 __le16 frame_time;
1059} __packed;
1060
1061struct iwl_rx_mpdu_res_start {
1062 __le16 byte_count;
1063 __le16 reserved;
1064} __packed;
1065
1066
1067
1068
1069
1070
1071
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1090
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1094
1095
1096
1097
1098#define TX_CMD_FLG_PROT_REQUIRE_MSK cpu_to_le32(1 << 0)
1099
1100
1101
1102
1103#define TX_CMD_FLG_ACK_MSK cpu_to_le32(1 << 3)
1104
1105
1106
1107
1108
1109
1110
1111#define TX_CMD_FLG_STA_RATE_MSK cpu_to_le32(1 << 4)
1112
1113
1114
1115#define TX_CMD_FLG_IMM_BA_RSP_MASK cpu_to_le32(1 << 6)
1116
1117
1118#define TX_CMD_FLG_ANT_SEL_MSK cpu_to_le32(0xf00)
1119
1120
1121
1122#define TX_CMD_FLG_IGNORE_BT cpu_to_le32(1 << 12)
1123
1124
1125
1126
1127
1128#define TX_CMD_FLG_SEQ_CTL_MSK cpu_to_le32(1 << 13)
1129
1130
1131
1132#define TX_CMD_FLG_MORE_FRAG_MSK cpu_to_le32(1 << 14)
1133
1134
1135
1136
1137#define TX_CMD_FLG_TSF_MSK cpu_to_le32(1 << 16)
1138
1139
1140
1141
1142
1143
1144
1145#define TX_CMD_FLG_MH_PAD_MSK cpu_to_le32(1 << 20)
1146
1147
1148
1149#define TX_CMD_FLG_AGG_CCMP_MSK cpu_to_le32(1 << 22)
1150
1151
1152#define TX_CMD_FLG_DUR_MSK cpu_to_le32(1 << 25)
1153
1154
1155
1156
1157
1158#define TX_CMD_SEC_WEP 0x01
1159#define TX_CMD_SEC_CCM 0x02
1160#define TX_CMD_SEC_TKIP 0x03
1161#define TX_CMD_SEC_MSK 0x03
1162#define TX_CMD_SEC_SHIFT 6
1163#define TX_CMD_SEC_KEY128 0x08
1164
1165
1166
1167
1168
1169
1170
1171
1172
1173struct iwl_dram_scratch {
1174 u8 try_cnt;
1175 u8 bt_kill_cnt;
1176 __le16 reserved;
1177} __packed;
1178
1179struct iwl_tx_cmd {
1180
1181
1182
1183
1184
1185
1186
1187
1188
1189
1190 __le16 len;
1191
1192
1193
1194
1195
1196
1197 __le16 next_frame_len;
1198
1199 __le32 tx_flags;
1200
1201
1202
1203 struct iwl_dram_scratch scratch;
1204
1205
1206 __le32 rate_n_flags;
1207
1208
1209 u8 sta_id;
1210
1211
1212 u8 sec_ctl;
1213
1214
1215
1216
1217
1218
1219
1220
1221 u8 initial_rate_index;
1222 u8 reserved;
1223 u8 key[16];
1224 __le16 next_frame_flags;
1225 __le16 reserved2;
1226 union {
1227 __le32 life_time;
1228 __le32 attempt;
1229 } stop_time;
1230
1231
1232
1233 __le32 dram_lsb_ptr;
1234 u8 dram_msb_ptr;
1235
1236 u8 rts_retry_limit;
1237 u8 data_retry_limit;
1238 u8 tid_tspec;
1239 union {
1240 __le16 pm_frame_timeout;
1241 __le16 attempt_duration;
1242 } timeout;
1243
1244
1245
1246
1247
1248 __le16 driver_txop;
1249
1250
1251
1252
1253
1254 union {
1255 DECLARE_FLEX_ARRAY(u8, payload);
1256 DECLARE_FLEX_ARRAY(struct ieee80211_hdr, hdr);
1257 };
1258} __packed;
1259
1260
1261
1262
1263
1264
1265
1266
1267enum {
1268 TX_STATUS_SUCCESS = 0x01,
1269 TX_STATUS_DIRECT_DONE = 0x02,
1270
1271 TX_STATUS_POSTPONE_DELAY = 0x40,
1272 TX_STATUS_POSTPONE_FEW_BYTES = 0x41,
1273 TX_STATUS_POSTPONE_BT_PRIO = 0x42,
1274 TX_STATUS_POSTPONE_QUIET_PERIOD = 0x43,
1275 TX_STATUS_POSTPONE_CALC_TTAK = 0x44,
1276
1277 TX_STATUS_FAIL_INTERNAL_CROSSED_RETRY = 0x81,
1278 TX_STATUS_FAIL_SHORT_LIMIT = 0x82,
1279 TX_STATUS_FAIL_LONG_LIMIT = 0x83,
1280 TX_STATUS_FAIL_FIFO_UNDERRUN = 0x84,
1281 TX_STATUS_FAIL_DRAIN_FLOW = 0x85,
1282 TX_STATUS_FAIL_RFKILL_FLUSH = 0x86,
1283 TX_STATUS_FAIL_LIFE_EXPIRE = 0x87,
1284 TX_STATUS_FAIL_DEST_PS = 0x88,
1285 TX_STATUS_FAIL_HOST_ABORTED = 0x89,
1286 TX_STATUS_FAIL_BT_RETRY = 0x8a,
1287 TX_STATUS_FAIL_STA_INVALID = 0x8b,
1288 TX_STATUS_FAIL_FRAG_DROPPED = 0x8c,
1289 TX_STATUS_FAIL_TID_DISABLE = 0x8d,
1290 TX_STATUS_FAIL_FIFO_FLUSHED = 0x8e,
1291 TX_STATUS_FAIL_INSUFFICIENT_CF_POLL = 0x8f,
1292 TX_STATUS_FAIL_PASSIVE_NO_RX = 0x90,
1293 TX_STATUS_FAIL_NO_BEACON_ON_RADAR = 0x91,
1294};
1295
1296#define TX_PACKET_MODE_REGULAR 0x0000
1297#define TX_PACKET_MODE_BURST_SEQ 0x0100
1298#define TX_PACKET_MODE_BURST_FIRST 0x0200
1299
1300enum {
1301 TX_POWER_PA_NOT_ACTIVE = 0x0,
1302};
1303
1304enum {
1305 TX_STATUS_MSK = 0x000000ff,
1306 TX_STATUS_DELAY_MSK = 0x00000040,
1307 TX_STATUS_ABORT_MSK = 0x00000080,
1308 TX_PACKET_MODE_MSK = 0x0000ff00,
1309 TX_FIFO_NUMBER_MSK = 0x00070000,
1310 TX_RESERVED = 0x00780000,
1311 TX_POWER_PA_DETECT_MSK = 0x7f800000,
1312 TX_ABORT_REQUIRED_MSK = 0x80000000,
1313};
1314
1315
1316
1317
1318
1319enum {
1320 AGG_TX_STATE_TRANSMITTED = 0x00,
1321 AGG_TX_STATE_UNDERRUN_MSK = 0x01,
1322 AGG_TX_STATE_BT_PRIO_MSK = 0x02,
1323 AGG_TX_STATE_FEW_BYTES_MSK = 0x04,
1324 AGG_TX_STATE_ABORT_MSK = 0x08,
1325 AGG_TX_STATE_LAST_SENT_TTL_MSK = 0x10,
1326 AGG_TX_STATE_LAST_SENT_TRY_CNT_MSK = 0x20,
1327 AGG_TX_STATE_LAST_SENT_BT_KILL_MSK = 0x40,
1328 AGG_TX_STATE_SCD_QUERY_MSK = 0x80,
1329 AGG_TX_STATE_TEST_BAD_CRC32_MSK = 0x100,
1330 AGG_TX_STATE_RESPONSE_MSK = 0x1ff,
1331 AGG_TX_STATE_DUMP_TX_MSK = 0x200,
1332 AGG_TX_STATE_DELAY_TX_MSK = 0x400
1333};
1334
1335#define AGG_TX_STATUS_MSK 0x00000fff
1336#define AGG_TX_TRY_MSK 0x0000f000
1337#define AGG_TX_TRY_POS 12
1338
1339#define AGG_TX_STATE_LAST_SENT_MSK (AGG_TX_STATE_LAST_SENT_TTL_MSK | \
1340 AGG_TX_STATE_LAST_SENT_TRY_CNT_MSK | \
1341 AGG_TX_STATE_LAST_SENT_BT_KILL_MSK)
1342
1343
1344#define AGG_TX_STATE_TRY_CNT_POS 12
1345#define AGG_TX_STATE_TRY_CNT_MSK 0xf000
1346
1347
1348#define AGG_TX_STATE_SEQ_NUM_POS 16
1349#define AGG_TX_STATE_SEQ_NUM_MSK 0xffff0000
1350
1351
1352
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1355
1356
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1367
1368
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1370
1371
1372
1373struct agg_tx_status {
1374 __le16 status;
1375 __le16 sequence;
1376} __packed;
1377
1378
1379#define IWLAGN_TX_RES_TID_POS 0
1380#define IWLAGN_TX_RES_TID_MSK 0x0f
1381#define IWLAGN_TX_RES_RA_POS 4
1382#define IWLAGN_TX_RES_RA_MSK 0xf0
1383
1384struct iwlagn_tx_resp {
1385 u8 frame_count;
1386 u8 bt_kill_count;
1387 u8 failure_rts;
1388 u8 failure_frame;
1389
1390
1391
1392 __le32 rate_n_flags;
1393
1394
1395
1396 __le16 wireless_media_time;
1397
1398 u8 pa_status;
1399 u8 pa_integ_res_a[3];
1400 u8 pa_integ_res_b[3];
1401 u8 pa_integ_res_C[3];
1402
1403 __le32 tfd_info;
1404 __le16 seq_ctl;
1405 __le16 byte_cnt;
1406 u8 tlc_info;
1407 u8 ra_tid;
1408 __le16 frame_ctrl;
1409
1410
1411
1412
1413
1414
1415
1416
1417
1418
1419
1420
1421
1422 struct agg_tx_status status;
1423
1424} __packed;
1425
1426
1427
1428
1429
1430struct iwl_compressed_ba_resp {
1431 __le32 sta_addr_lo32;
1432 __le16 sta_addr_hi16;
1433 __le16 reserved;
1434
1435
1436 u8 sta_id;
1437 u8 tid;
1438 __le16 seq_ctl;
1439 __le64 bitmap;
1440 __le16 scd_flow;
1441 __le16 scd_ssn;
1442 u8 txed;
1443 u8 txed_2_done;
1444 __le16 reserved1;
1445} __packed;
1446
1447
1448
1449
1450
1451
1452
1453#define LINK_QUAL_FLAGS_SET_STA_TLC_RTS_MSK (1 << 0)
1454
1455
1456#define LINK_QUAL_AC_NUM AC_NUM
1457
1458
1459#define LINK_QUAL_MAX_RETRY_NUM 16
1460
1461
1462#define LINK_QUAL_ANT_A_MSK (1 << 0)
1463#define LINK_QUAL_ANT_B_MSK (1 << 1)
1464#define LINK_QUAL_ANT_MSK (LINK_QUAL_ANT_A_MSK|LINK_QUAL_ANT_B_MSK)
1465
1466
1467
1468
1469
1470
1471
1472struct iwl_link_qual_general_params {
1473 u8 flags;
1474
1475
1476 u8 mimo_delimiter;
1477
1478
1479 u8 single_stream_ant_msk;
1480
1481
1482 u8 dual_stream_ant_msk;
1483
1484
1485
1486
1487
1488
1489
1490
1491
1492
1493
1494
1495 u8 start_rate_index[LINK_QUAL_AC_NUM];
1496} __packed;
1497
1498#define LINK_QUAL_AGG_TIME_LIMIT_DEF (4000)
1499#define LINK_QUAL_AGG_TIME_LIMIT_MAX (8000)
1500#define LINK_QUAL_AGG_TIME_LIMIT_MIN (100)
1501
1502#define LINK_QUAL_AGG_DISABLE_START_DEF (3)
1503#define LINK_QUAL_AGG_DISABLE_START_MAX (255)
1504#define LINK_QUAL_AGG_DISABLE_START_MIN (0)
1505
1506#define LINK_QUAL_AGG_FRAME_LIMIT_DEF (63)
1507#define LINK_QUAL_AGG_FRAME_LIMIT_MAX (63)
1508#define LINK_QUAL_AGG_FRAME_LIMIT_MIN (0)
1509
1510
1511
1512
1513
1514
1515struct iwl_link_qual_agg_params {
1516
1517
1518
1519
1520
1521 __le16 agg_time_limit;
1522
1523
1524
1525
1526
1527
1528
1529 u8 agg_dis_start_th;
1530
1531
1532
1533
1534
1535
1536 u8 agg_frame_cnt_limit;
1537
1538 __le32 reserved;
1539} __packed;
1540
1541
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1726
1727
1728
1729struct iwl_link_quality_cmd {
1730
1731
1732 u8 sta_id;
1733 u8 reserved1;
1734 __le16 control;
1735 struct iwl_link_qual_general_params general_params;
1736 struct iwl_link_qual_agg_params agg_params;
1737
1738
1739
1740
1741
1742
1743 struct {
1744 __le32 rate_n_flags;
1745 } rs_table[LINK_QUAL_MAX_RETRY_NUM];
1746 __le32 reserved2;
1747} __packed;
1748
1749
1750
1751
1752
1753
1754
1755
1756
1757
1758#define BT_COEX_DISABLE (0x0)
1759#define BT_ENABLE_CHANNEL_ANNOUNCE BIT(0)
1760#define BT_ENABLE_PRIORITY BIT(1)
1761#define BT_ENABLE_2_WIRE BIT(2)
1762
1763#define BT_COEX_DISABLE (0x0)
1764#define BT_COEX_ENABLE (BT_ENABLE_CHANNEL_ANNOUNCE | BT_ENABLE_PRIORITY)
1765
1766#define BT_LEAD_TIME_MIN (0x0)
1767#define BT_LEAD_TIME_DEF (0x1E)
1768#define BT_LEAD_TIME_MAX (0xFF)
1769
1770#define BT_MAX_KILL_MIN (0x1)
1771#define BT_MAX_KILL_DEF (0x5)
1772#define BT_MAX_KILL_MAX (0xFF)
1773
1774#define BT_DURATION_LIMIT_DEF 625
1775#define BT_DURATION_LIMIT_MAX 1250
1776#define BT_DURATION_LIMIT_MIN 625
1777
1778#define BT_ON_THRESHOLD_DEF 4
1779#define BT_ON_THRESHOLD_MAX 1000
1780#define BT_ON_THRESHOLD_MIN 1
1781
1782#define BT_FRAG_THRESHOLD_DEF 0
1783#define BT_FRAG_THRESHOLD_MAX 0
1784#define BT_FRAG_THRESHOLD_MIN 0
1785
1786#define BT_AGG_THRESHOLD_DEF 1200
1787#define BT_AGG_THRESHOLD_MAX 8000
1788#define BT_AGG_THRESHOLD_MIN 400
1789
1790
1791
1792
1793
1794
1795
1796
1797struct iwl_bt_cmd {
1798 u8 flags;
1799 u8 lead_time;
1800 u8 max_kill;
1801 u8 reserved;
1802 __le32 kill_ack_mask;
1803 __le32 kill_cts_mask;
1804} __packed;
1805
1806#define IWLAGN_BT_FLAG_CHANNEL_INHIBITION BIT(0)
1807
1808#define IWLAGN_BT_FLAG_COEX_MODE_MASK (BIT(3)|BIT(4)|BIT(5))
1809#define IWLAGN_BT_FLAG_COEX_MODE_SHIFT 3
1810#define IWLAGN_BT_FLAG_COEX_MODE_DISABLED 0
1811#define IWLAGN_BT_FLAG_COEX_MODE_LEGACY_2W 1
1812#define IWLAGN_BT_FLAG_COEX_MODE_3W 2
1813#define IWLAGN_BT_FLAG_COEX_MODE_4W 3
1814
1815#define IWLAGN_BT_FLAG_UCODE_DEFAULT BIT(6)
1816
1817#define IWLAGN_BT_FLAG_SYNC_2_BT_DISABLE BIT(7)
1818
1819#define IWLAGN_BT_PSP_MIN_RSSI_THRESHOLD -75
1820#define IWLAGN_BT_PSP_MAX_RSSI_THRESHOLD -65
1821
1822#define IWLAGN_BT_PRIO_BOOST_MAX 0xFF
1823#define IWLAGN_BT_PRIO_BOOST_MIN 0x00
1824#define IWLAGN_BT_PRIO_BOOST_DEFAULT 0xF0
1825#define IWLAGN_BT_PRIO_BOOST_DEFAULT32 0xF0F0F0F0
1826
1827#define IWLAGN_BT_MAX_KILL_DEFAULT 5
1828
1829#define IWLAGN_BT3_T7_DEFAULT 1
1830
1831enum iwl_bt_kill_idx {
1832 IWL_BT_KILL_DEFAULT = 0,
1833 IWL_BT_KILL_OVERRIDE = 1,
1834 IWL_BT_KILL_REDUCE = 2,
1835};
1836
1837#define IWLAGN_BT_KILL_ACK_MASK_DEFAULT cpu_to_le32(0xffff0000)
1838#define IWLAGN_BT_KILL_CTS_MASK_DEFAULT cpu_to_le32(0xffff0000)
1839#define IWLAGN_BT_KILL_ACK_CTS_MASK_SCO cpu_to_le32(0xffffffff)
1840#define IWLAGN_BT_KILL_ACK_CTS_MASK_REDUCE cpu_to_le32(0)
1841
1842#define IWLAGN_BT3_PRIO_SAMPLE_DEFAULT 2
1843
1844#define IWLAGN_BT3_T2_DEFAULT 0xc
1845
1846#define IWLAGN_BT_VALID_ENABLE_FLAGS cpu_to_le16(BIT(0))
1847#define IWLAGN_BT_VALID_BOOST cpu_to_le16(BIT(1))
1848#define IWLAGN_BT_VALID_MAX_KILL cpu_to_le16(BIT(2))
1849#define IWLAGN_BT_VALID_3W_TIMERS cpu_to_le16(BIT(3))
1850#define IWLAGN_BT_VALID_KILL_ACK_MASK cpu_to_le16(BIT(4))
1851#define IWLAGN_BT_VALID_KILL_CTS_MASK cpu_to_le16(BIT(5))
1852#define IWLAGN_BT_VALID_REDUCED_TX_PWR cpu_to_le16(BIT(6))
1853#define IWLAGN_BT_VALID_3W_LUT cpu_to_le16(BIT(7))
1854
1855#define IWLAGN_BT_ALL_VALID_MSK (IWLAGN_BT_VALID_ENABLE_FLAGS | \
1856 IWLAGN_BT_VALID_BOOST | \
1857 IWLAGN_BT_VALID_MAX_KILL | \
1858 IWLAGN_BT_VALID_3W_TIMERS | \
1859 IWLAGN_BT_VALID_KILL_ACK_MASK | \
1860 IWLAGN_BT_VALID_KILL_CTS_MASK | \
1861 IWLAGN_BT_VALID_REDUCED_TX_PWR | \
1862 IWLAGN_BT_VALID_3W_LUT)
1863
1864#define IWLAGN_BT_REDUCED_TX_PWR BIT(0)
1865
1866#define IWLAGN_BT_DECISION_LUT_SIZE 12
1867
1868struct iwl_basic_bt_cmd {
1869 u8 flags;
1870 u8 ledtime;
1871 u8 max_kill;
1872 u8 bt3_timer_t7_value;
1873 __le32 kill_ack_mask;
1874 __le32 kill_cts_mask;
1875 u8 bt3_prio_sample_time;
1876 u8 bt3_timer_t2_value;
1877 __le16 bt4_reaction_time;
1878 __le32 bt3_lookup_table[IWLAGN_BT_DECISION_LUT_SIZE];
1879
1880
1881
1882
1883 u8 reduce_txpower;
1884 u8 reserved;
1885 __le16 valid;
1886};
1887
1888struct iwl_bt_cmd_v1 {
1889 struct iwl_basic_bt_cmd basic;
1890 u8 prio_boost;
1891
1892
1893
1894
1895 u8 tx_prio_boost;
1896 __le16 rx_prio_boost;
1897};
1898
1899struct iwl_bt_cmd_v2 {
1900 struct iwl_basic_bt_cmd basic;
1901 __le32 prio_boost;
1902
1903
1904
1905
1906 u8 reserved;
1907 u8 tx_prio_boost;
1908 __le16 rx_prio_boost;
1909};
1910
1911#define IWLAGN_BT_SCO_ACTIVE cpu_to_le32(BIT(0))
1912
1913struct iwlagn_bt_sco_cmd {
1914 __le32 flags;
1915};
1916
1917
1918
1919
1920
1921
1922
1923
1924
1925
1926#define MEASUREMENT_FILTER_FLAG (RXON_FILTER_PROMISC_MSK | \
1927 RXON_FILTER_CTL2HOST_MSK | \
1928 RXON_FILTER_ACCEPT_GRP_MSK | \
1929 RXON_FILTER_DIS_DECRYPT_MSK | \
1930 RXON_FILTER_DIS_GRP_DECRYPT_MSK | \
1931 RXON_FILTER_ASSOC_MSK | \
1932 RXON_FILTER_BCON_AWARE_MSK)
1933
1934struct iwl_measure_channel {
1935 __le32 duration;
1936
1937 u8 channel;
1938 u8 type;
1939 __le16 reserved;
1940} __packed;
1941
1942
1943
1944
1945struct iwl_spectrum_cmd {
1946 __le16 len;
1947 u8 token;
1948 u8 id;
1949 u8 origin;
1950 u8 periodic;
1951 __le16 path_loss_timeout;
1952 __le32 start_time;
1953 __le32 reserved2;
1954 __le32 flags;
1955 __le32 filter_flags;
1956 __le16 channel_count;
1957 __le16 reserved3;
1958 struct iwl_measure_channel channels[10];
1959} __packed;
1960
1961
1962
1963
1964struct iwl_spectrum_resp {
1965 u8 token;
1966 u8 id;
1967 __le16 status;
1968
1969
1970} __packed;
1971
1972enum iwl_measurement_state {
1973 IWL_MEASUREMENT_START = 0,
1974 IWL_MEASUREMENT_STOP = 1,
1975};
1976
1977enum iwl_measurement_status {
1978 IWL_MEASUREMENT_OK = 0,
1979 IWL_MEASUREMENT_CONCURRENT = 1,
1980 IWL_MEASUREMENT_CSA_CONFLICT = 2,
1981 IWL_MEASUREMENT_TGH_CONFLICT = 3,
1982
1983 IWL_MEASUREMENT_STOPPED = 6,
1984 IWL_MEASUREMENT_TIMEOUT = 7,
1985 IWL_MEASUREMENT_PERIODIC_FAILED = 8,
1986};
1987
1988#define NUM_ELEMENTS_IN_HISTOGRAM 8
1989
1990struct iwl_measurement_histogram {
1991 __le32 ofdm[NUM_ELEMENTS_IN_HISTOGRAM];
1992 __le32 cck[NUM_ELEMENTS_IN_HISTOGRAM];
1993} __packed;
1994
1995
1996struct iwl_measurement_cca_counters {
1997 __le32 ofdm;
1998 __le32 cck;
1999} __packed;
2000
2001enum iwl_measure_type {
2002 IWL_MEASURE_BASIC = (1 << 0),
2003 IWL_MEASURE_CHANNEL_LOAD = (1 << 1),
2004 IWL_MEASURE_HISTOGRAM_RPI = (1 << 2),
2005 IWL_MEASURE_HISTOGRAM_NOISE = (1 << 3),
2006 IWL_MEASURE_FRAME = (1 << 4),
2007
2008 IWL_MEASURE_IDLE = (1 << 7),
2009};
2010
2011
2012
2013
2014struct iwl_spectrum_notification {
2015 u8 id;
2016 u8 token;
2017 u8 channel_index;
2018 u8 state;
2019 __le32 start_time;
2020 u8 band;
2021 u8 channel;
2022 u8 type;
2023 u8 reserved1;
2024
2025
2026 __le32 cca_ofdm;
2027 __le32 cca_cck;
2028 __le32 cca_time;
2029 u8 basic_type;
2030
2031 u8 reserved2[3];
2032 struct iwl_measurement_histogram histogram;
2033 __le32 stop_time;
2034 __le32 status;
2035} __packed;
2036
2037
2038
2039
2040
2041
2042
2043
2044
2045
2046
2047
2048
2049
2050
2051
2052
2053
2054
2055
2056
2057
2058
2059
2060
2061
2062
2063
2064
2065
2066
2067
2068
2069
2070
2071
2072
2073
2074
2075
2076
2077
2078#define IWL_POWER_VEC_SIZE 5
2079
2080#define IWL_POWER_DRIVER_ALLOW_SLEEP_MSK cpu_to_le16(BIT(0))
2081#define IWL_POWER_POWER_SAVE_ENA_MSK cpu_to_le16(BIT(0))
2082#define IWL_POWER_POWER_MANAGEMENT_ENA_MSK cpu_to_le16(BIT(1))
2083#define IWL_POWER_SLEEP_OVER_DTIM_MSK cpu_to_le16(BIT(2))
2084#define IWL_POWER_PCI_PM_MSK cpu_to_le16(BIT(3))
2085#define IWL_POWER_FAST_PD cpu_to_le16(BIT(4))
2086#define IWL_POWER_BEACON_FILTERING cpu_to_le16(BIT(5))
2087#define IWL_POWER_SHADOW_REG_ENA cpu_to_le16(BIT(6))
2088#define IWL_POWER_CT_KILL_SET cpu_to_le16(BIT(7))
2089#define IWL_POWER_BT_SCO_ENA cpu_to_le16(BIT(8))
2090#define IWL_POWER_ADVANCE_PM_ENA_MSK cpu_to_le16(BIT(9))
2091
2092struct iwl_powertable_cmd {
2093 __le16 flags;
2094 u8 keep_alive_seconds;
2095 u8 debug_flags;
2096 __le32 rx_data_timeout;
2097 __le32 tx_data_timeout;
2098 __le32 sleep_interval[IWL_POWER_VEC_SIZE];
2099 __le32 keep_alive_beacons;
2100} __packed;
2101
2102
2103
2104
2105
2106struct iwl_sleep_notification {
2107 u8 pm_sleep_mode;
2108 u8 pm_wakeup_src;
2109 __le16 reserved;
2110 __le32 sleep_time;
2111 __le32 tsf_low;
2112 __le32 bcon_timer;
2113} __packed;
2114
2115
2116enum {
2117 IWL_PM_NO_SLEEP = 0,
2118 IWL_PM_SLP_MAC = 1,
2119 IWL_PM_SLP_FULL_MAC_UNASSOCIATE = 2,
2120 IWL_PM_SLP_FULL_MAC_CARD_STATE = 3,
2121 IWL_PM_SLP_PHY = 4,
2122 IWL_PM_SLP_REPENT = 5,
2123 IWL_PM_WAKEUP_BY_TIMER = 6,
2124 IWL_PM_WAKEUP_BY_DRIVER = 7,
2125 IWL_PM_WAKEUP_BY_RFKILL = 8,
2126
2127 IWL_PM_NUM_OF_MODES = 12,
2128};
2129
2130
2131
2132
2133#define CARD_STATE_CMD_DISABLE 0x00
2134#define CARD_STATE_CMD_ENABLE 0x01
2135#define CARD_STATE_CMD_HALT 0x02
2136struct iwl_card_state_cmd {
2137 __le32 status;
2138} __packed;
2139
2140
2141
2142
2143struct iwl_card_state_notif {
2144 __le32 flags;
2145} __packed;
2146
2147#define HW_CARD_DISABLED 0x01
2148#define SW_CARD_DISABLED 0x02
2149#define CT_CARD_DISABLED 0x04
2150#define RXON_CARD_DISABLED 0x10
2151
2152struct iwl_ct_kill_config {
2153 __le32 reserved;
2154 __le32 critical_temperature_M;
2155 __le32 critical_temperature_R;
2156} __packed;
2157
2158
2159struct iwl_ct_kill_throttling_config {
2160 __le32 critical_temperature_exit;
2161 __le32 reserved;
2162 __le32 critical_temperature_enter;
2163} __packed;
2164
2165
2166
2167
2168
2169
2170
2171#define SCAN_CHANNEL_TYPE_PASSIVE cpu_to_le32(0)
2172#define SCAN_CHANNEL_TYPE_ACTIVE cpu_to_le32(1)
2173
2174
2175
2176
2177
2178
2179
2180
2181
2182
2183
2184
2185
2186
2187
2188
2189
2190
2191
2192
2193
2194struct iwl_scan_channel {
2195
2196
2197
2198
2199
2200
2201
2202 __le32 type;
2203 __le16 channel;
2204 u8 tx_gain;
2205 u8 dsp_atten;
2206 __le16 active_dwell;
2207 __le16 passive_dwell;
2208} __packed;
2209
2210
2211#define IWL_SCAN_PROBE_MASK(n) cpu_to_le32((BIT(n) | (BIT(n) - BIT(1))))
2212
2213
2214
2215
2216
2217
2218
2219
2220
2221struct iwl_ssid_ie {
2222 u8 id;
2223 u8 len;
2224 u8 ssid[32];
2225} __packed;
2226
2227#define PROBE_OPTION_MAX 20
2228#define TX_CMD_LIFE_TIME_INFINITE cpu_to_le32(0xFFFFFFFF)
2229#define IWL_GOOD_CRC_TH_DISABLED 0
2230#define IWL_GOOD_CRC_TH_DEFAULT cpu_to_le16(1)
2231#define IWL_GOOD_CRC_TH_NEVER cpu_to_le16(0xffff)
2232#define IWL_MAX_CMD_SIZE 4096
2233
2234
2235
2236
2237
2238
2239
2240
2241
2242
2243
2244
2245
2246
2247
2248
2249
2250
2251
2252
2253
2254
2255
2256
2257
2258
2259
2260
2261
2262
2263
2264
2265
2266
2267
2268
2269
2270
2271
2272
2273
2274
2275
2276
2277
2278
2279
2280
2281
2282
2283
2284
2285
2286
2287enum iwl_scan_flags {
2288
2289 IWL_SCAN_FLAGS_ACTION_FRAME_TX = BIT(1),
2290
2291};
2292
2293struct iwl_scan_cmd {
2294 __le16 len;
2295 u8 scan_flags;
2296 u8 channel_count;
2297 __le16 quiet_time;
2298
2299 __le16 quiet_plcp_th;
2300 __le16 good_CRC_th;
2301 __le16 rx_chain;
2302 __le32 max_out_time;
2303
2304 __le32 suspend_time;
2305
2306
2307 __le32 flags;
2308 __le32 filter_flags;
2309
2310
2311
2312 struct iwl_tx_cmd tx_cmd;
2313
2314
2315 struct iwl_ssid_ie direct_scan[PROBE_OPTION_MAX];
2316
2317
2318
2319
2320
2321
2322
2323
2324
2325
2326
2327
2328
2329
2330
2331
2332 u8 data[];
2333} __packed;
2334
2335
2336#define CAN_ABORT_STATUS cpu_to_le32(0x1)
2337
2338#define ABORT_STATUS 0x2
2339
2340
2341
2342
2343struct iwl_scanreq_notification {
2344 __le32 status;
2345} __packed;
2346
2347
2348
2349
2350struct iwl_scanstart_notification {
2351 __le32 tsf_low;
2352 __le32 tsf_high;
2353 __le32 beacon_timer;
2354 u8 channel;
2355 u8 band;
2356 u8 reserved[2];
2357 __le32 status;
2358} __packed;
2359
2360#define SCAN_OWNER_STATUS 0x1
2361#define MEASURE_OWNER_STATUS 0x2
2362
2363#define IWL_PROBE_STATUS_OK 0
2364#define IWL_PROBE_STATUS_TX_FAILED BIT(0)
2365
2366#define IWL_PROBE_STATUS_FAIL_TTL BIT(1)
2367#define IWL_PROBE_STATUS_FAIL_BT BIT(2)
2368
2369#define NUMBER_OF_STATISTICS 1
2370
2371
2372
2373struct iwl_scanresults_notification {
2374 u8 channel;
2375 u8 band;
2376 u8 probe_status;
2377 u8 num_probe_not_sent;
2378 __le32 tsf_low;
2379 __le32 tsf_high;
2380 __le32 statistics[NUMBER_OF_STATISTICS];
2381} __packed;
2382
2383
2384
2385
2386struct iwl_scancomplete_notification {
2387 u8 scanned_channels;
2388 u8 status;
2389 u8 bt_status;
2390 u8 last_channel;
2391 __le32 tsf_low;
2392 __le32 tsf_high;
2393} __packed;
2394
2395
2396
2397
2398
2399
2400
2401
2402enum iwl_ibss_manager {
2403 IWL_NOT_IBSS_MANAGER = 0,
2404 IWL_IBSS_MANAGER = 1,
2405};
2406
2407
2408
2409
2410
2411struct iwlagn_beacon_notif {
2412 struct iwlagn_tx_resp beacon_notify_hdr;
2413 __le32 low_tsf;
2414 __le32 high_tsf;
2415 __le32 ibss_mgr_status;
2416} __packed;
2417
2418
2419
2420
2421
2422struct iwl_tx_beacon_cmd {
2423 struct iwl_tx_cmd tx;
2424 __le16 tim_idx;
2425 u8 tim_size;
2426 u8 reserved1;
2427 struct ieee80211_hdr frame[];
2428} __packed;
2429
2430
2431
2432
2433
2434
2435
2436#define IWL_TEMP_CONVERT 260
2437
2438#define SUP_RATE_11A_MAX_NUM_CHANNELS 8
2439#define SUP_RATE_11B_MAX_NUM_CHANNELS 4
2440#define SUP_RATE_11G_MAX_NUM_CHANNELS 12
2441
2442
2443struct rate_histogram {
2444 union {
2445 __le32 a[SUP_RATE_11A_MAX_NUM_CHANNELS];
2446 __le32 b[SUP_RATE_11B_MAX_NUM_CHANNELS];
2447 __le32 g[SUP_RATE_11G_MAX_NUM_CHANNELS];
2448 } success;
2449 union {
2450 __le32 a[SUP_RATE_11A_MAX_NUM_CHANNELS];
2451 __le32 b[SUP_RATE_11B_MAX_NUM_CHANNELS];
2452 __le32 g[SUP_RATE_11G_MAX_NUM_CHANNELS];
2453 } failed;
2454} __packed;
2455
2456
2457
2458struct statistics_dbg {
2459 __le32 burst_check;
2460 __le32 burst_count;
2461 __le32 wait_for_silence_timeout_cnt;
2462 __le32 reserved[3];
2463} __packed;
2464
2465struct statistics_rx_phy {
2466 __le32 ina_cnt;
2467 __le32 fina_cnt;
2468 __le32 plcp_err;
2469 __le32 crc32_err;
2470 __le32 overrun_err;
2471 __le32 early_overrun_err;
2472 __le32 crc32_good;
2473 __le32 false_alarm_cnt;
2474 __le32 fina_sync_err_cnt;
2475 __le32 sfd_timeout;
2476 __le32 fina_timeout;
2477 __le32 unresponded_rts;
2478 __le32 rxe_frame_limit_overrun;
2479 __le32 sent_ack_cnt;
2480 __le32 sent_cts_cnt;
2481 __le32 sent_ba_rsp_cnt;
2482 __le32 dsp_self_kill;
2483 __le32 mh_format_err;
2484 __le32 re_acq_main_rssi_sum;
2485 __le32 reserved3;
2486} __packed;
2487
2488struct statistics_rx_ht_phy {
2489 __le32 plcp_err;
2490 __le32 overrun_err;
2491 __le32 early_overrun_err;
2492 __le32 crc32_good;
2493 __le32 crc32_err;
2494 __le32 mh_format_err;
2495 __le32 agg_crc32_good;
2496 __le32 agg_mpdu_cnt;
2497 __le32 agg_cnt;
2498 __le32 unsupport_mcs;
2499} __packed;
2500
2501#define INTERFERENCE_DATA_AVAILABLE cpu_to_le32(1)
2502
2503struct statistics_rx_non_phy {
2504 __le32 bogus_cts;
2505 __le32 bogus_ack;
2506 __le32 non_bssid_frames;
2507
2508 __le32 filtered_frames;
2509
2510 __le32 non_channel_beacons;
2511
2512 __le32 channel_beacons;
2513
2514 __le32 num_missed_bcon;
2515 __le32 adc_rx_saturation_time;
2516
2517 __le32 ina_detection_search_time;
2518
2519 __le32 beacon_silence_rssi_a;
2520 __le32 beacon_silence_rssi_b;
2521 __le32 beacon_silence_rssi_c;
2522 __le32 interference_data_flag;
2523
2524
2525 __le32 channel_load;
2526 __le32 dsp_false_alarms;
2527
2528 __le32 beacon_rssi_a;
2529 __le32 beacon_rssi_b;
2530 __le32 beacon_rssi_c;
2531 __le32 beacon_energy_a;
2532 __le32 beacon_energy_b;
2533 __le32 beacon_energy_c;
2534} __packed;
2535
2536struct statistics_rx_non_phy_bt {
2537 struct statistics_rx_non_phy common;
2538
2539 __le32 num_bt_kills;
2540 __le32 reserved[2];
2541} __packed;
2542
2543struct statistics_rx {
2544 struct statistics_rx_phy ofdm;
2545 struct statistics_rx_phy cck;
2546 struct statistics_rx_non_phy general;
2547 struct statistics_rx_ht_phy ofdm_ht;
2548} __packed;
2549
2550struct statistics_rx_bt {
2551 struct statistics_rx_phy ofdm;
2552 struct statistics_rx_phy cck;
2553 struct statistics_rx_non_phy_bt general;
2554 struct statistics_rx_ht_phy ofdm_ht;
2555} __packed;
2556
2557
2558
2559
2560
2561
2562
2563
2564struct statistics_tx_power {
2565 u8 ant_a;
2566 u8 ant_b;
2567 u8 ant_c;
2568 u8 reserved;
2569} __packed;
2570
2571struct statistics_tx_non_phy_agg {
2572 __le32 ba_timeout;
2573 __le32 ba_reschedule_frames;
2574 __le32 scd_query_agg_frame_cnt;
2575 __le32 scd_query_no_agg;
2576 __le32 scd_query_agg;
2577 __le32 scd_query_mismatch;
2578 __le32 frame_not_ready;
2579 __le32 underrun;
2580 __le32 bt_prio_kill;
2581 __le32 rx_ba_rsp_cnt;
2582} __packed;
2583
2584struct statistics_tx {
2585 __le32 preamble_cnt;
2586 __le32 rx_detected_cnt;
2587 __le32 bt_prio_defer_cnt;
2588 __le32 bt_prio_kill_cnt;
2589 __le32 few_bytes_cnt;
2590 __le32 cts_timeout;
2591 __le32 ack_timeout;
2592 __le32 expected_ack_cnt;
2593 __le32 actual_ack_cnt;
2594 __le32 dump_msdu_cnt;
2595 __le32 burst_abort_next_frame_mismatch_cnt;
2596 __le32 burst_abort_missing_next_frame_cnt;
2597 __le32 cts_timeout_collision;
2598 __le32 ack_or_ba_timeout_collision;
2599 struct statistics_tx_non_phy_agg agg;
2600
2601
2602
2603
2604
2605 struct statistics_tx_power tx_power;
2606 __le32 reserved1;
2607} __packed;
2608
2609
2610struct statistics_div {
2611 __le32 tx_on_a;
2612 __le32 tx_on_b;
2613 __le32 exec_time;
2614 __le32 probe_time;
2615 __le32 reserved1;
2616 __le32 reserved2;
2617} __packed;
2618
2619struct statistics_general_common {
2620 __le32 temperature;
2621 __le32 temperature_m;
2622 struct statistics_dbg dbg;
2623 __le32 sleep_time;
2624 __le32 slots_out;
2625 __le32 slots_idle;
2626 __le32 ttl_timestamp;
2627 struct statistics_div div;
2628 __le32 rx_enable_counter;
2629
2630
2631
2632
2633
2634 __le32 num_of_sos_states;
2635} __packed;
2636
2637struct statistics_bt_activity {
2638
2639 __le32 hi_priority_tx_req_cnt;
2640 __le32 hi_priority_tx_denied_cnt;
2641 __le32 lo_priority_tx_req_cnt;
2642 __le32 lo_priority_tx_denied_cnt;
2643
2644 __le32 hi_priority_rx_req_cnt;
2645 __le32 hi_priority_rx_denied_cnt;
2646 __le32 lo_priority_rx_req_cnt;
2647 __le32 lo_priority_rx_denied_cnt;
2648} __packed;
2649
2650struct statistics_general {
2651 struct statistics_general_common common;
2652 __le32 reserved2;
2653 __le32 reserved3;
2654} __packed;
2655
2656struct statistics_general_bt {
2657 struct statistics_general_common common;
2658 struct statistics_bt_activity activity;
2659 __le32 reserved2;
2660 __le32 reserved3;
2661} __packed;
2662
2663#define UCODE_STATISTICS_CLEAR_MSK (0x1 << 0)
2664#define UCODE_STATISTICS_FREQUENCY_MSK (0x1 << 1)
2665#define UCODE_STATISTICS_NARROW_BAND_MSK (0x1 << 2)
2666
2667
2668
2669
2670
2671
2672
2673
2674
2675
2676
2677
2678
2679
2680
2681
2682#define IWL_STATS_CONF_CLEAR_STATS cpu_to_le32(0x1)
2683#define IWL_STATS_CONF_DISABLE_NOTIF cpu_to_le32(0x2)
2684struct iwl_statistics_cmd {
2685 __le32 configuration_flags;
2686} __packed;
2687
2688
2689
2690
2691
2692
2693
2694
2695
2696
2697
2698
2699
2700
2701
2702
2703#define STATISTICS_REPLY_FLG_BAND_24G_MSK cpu_to_le32(0x2)
2704#define STATISTICS_REPLY_FLG_HT40_MODE_MSK cpu_to_le32(0x8)
2705
2706struct iwl_notif_statistics {
2707 __le32 flag;
2708 struct statistics_rx rx;
2709 struct statistics_tx tx;
2710 struct statistics_general general;
2711} __packed;
2712
2713struct iwl_bt_notif_statistics {
2714 __le32 flag;
2715 struct statistics_rx_bt rx;
2716 struct statistics_tx tx;
2717 struct statistics_general_bt general;
2718} __packed;
2719
2720
2721
2722
2723
2724
2725
2726
2727
2728
2729
2730
2731
2732
2733
2734
2735
2736
2737
2738
2739
2740#define IWL_MISSED_BEACON_THRESHOLD_MIN (1)
2741#define IWL_MISSED_BEACON_THRESHOLD_DEF (5)
2742#define IWL_MISSED_BEACON_THRESHOLD_MAX IWL_MISSED_BEACON_THRESHOLD_DEF
2743
2744struct iwl_missed_beacon_notif {
2745 __le32 consecutive_missed_beacons;
2746 __le32 total_missed_becons;
2747 __le32 num_expected_beacons;
2748 __le32 num_recvd_beacons;
2749} __packed;
2750
2751
2752
2753
2754
2755
2756
2757
2758
2759
2760
2761
2762
2763
2764
2765
2766
2767
2768
2769
2770
2771
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2773
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2776
2777
2778
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2780
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2785
2786
2787
2788
2789
2790
2791
2792
2793
2794
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2796
2797
2798
2799
2800
2801
2802
2803
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2805
2806
2807
2808
2809
2810
2811
2812
2813
2814
2815
2816
2817
2818
2819
2820
2821
2822
2823
2824
2825
2826
2827
2828
2829
2830
2831
2832
2833
2834
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2837
2838
2839
2840
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2850
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2852
2853
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2862
2863
2864
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2866
2867
2868
2869
2870
2871
2872
2873
2874
2875
2876
2877
2878
2879
2880
2881
2882
2883
2884
2885
2886
2887
2888
2889
2890
2891
2892
2893
2894
2895
2896
2897
2898
2899
2900
2901
2902
2903
2904
2905
2906
2907
2908
2909
2910
2911
2912
2913
2914
2915
2916
2917
2918
2919
2920
2921
2922
2923
2924#define HD_TABLE_SIZE (11)
2925#define HD_MIN_ENERGY_CCK_DET_INDEX (0)
2926#define HD_MIN_ENERGY_OFDM_DET_INDEX (1)
2927#define HD_AUTO_CORR32_X1_TH_ADD_MIN_INDEX (2)
2928#define HD_AUTO_CORR32_X1_TH_ADD_MIN_MRC_INDEX (3)
2929#define HD_AUTO_CORR40_X4_TH_ADD_MIN_MRC_INDEX (4)
2930#define HD_AUTO_CORR32_X4_TH_ADD_MIN_INDEX (5)
2931#define HD_AUTO_CORR32_X4_TH_ADD_MIN_MRC_INDEX (6)
2932#define HD_BARKER_CORR_TH_ADD_MIN_INDEX (7)
2933#define HD_BARKER_CORR_TH_ADD_MIN_MRC_INDEX (8)
2934#define HD_AUTO_CORR40_X4_TH_ADD_MIN_INDEX (9)
2935#define HD_OFDM_ENERGY_TH_IN_INDEX (10)
2936
2937
2938
2939
2940#define HD_INA_NON_SQUARE_DET_OFDM_INDEX (11)
2941#define HD_INA_NON_SQUARE_DET_CCK_INDEX (12)
2942#define HD_CORR_11_INSTEAD_OF_CORR_9_EN_INDEX (13)
2943#define HD_OFDM_NON_SQUARE_DET_SLOPE_MRC_INDEX (14)
2944#define HD_OFDM_NON_SQUARE_DET_INTERCEPT_MRC_INDEX (15)
2945#define HD_OFDM_NON_SQUARE_DET_SLOPE_INDEX (16)
2946#define HD_OFDM_NON_SQUARE_DET_INTERCEPT_INDEX (17)
2947#define HD_CCK_NON_SQUARE_DET_SLOPE_MRC_INDEX (18)
2948#define HD_CCK_NON_SQUARE_DET_INTERCEPT_MRC_INDEX (19)
2949#define HD_CCK_NON_SQUARE_DET_SLOPE_INDEX (20)
2950#define HD_CCK_NON_SQUARE_DET_INTERCEPT_INDEX (21)
2951#define HD_RESERVED (22)
2952
2953
2954#define ENHANCE_HD_TABLE_SIZE (23)
2955
2956
2957#define ENHANCE_HD_TABLE_ENTRIES (ENHANCE_HD_TABLE_SIZE - HD_TABLE_SIZE)
2958
2959#define HD_INA_NON_SQUARE_DET_OFDM_DATA_V1 cpu_to_le16(0)
2960#define HD_INA_NON_SQUARE_DET_CCK_DATA_V1 cpu_to_le16(0)
2961#define HD_CORR_11_INSTEAD_OF_CORR_9_EN_DATA_V1 cpu_to_le16(0)
2962#define HD_OFDM_NON_SQUARE_DET_SLOPE_MRC_DATA_V1 cpu_to_le16(668)
2963#define HD_OFDM_NON_SQUARE_DET_INTERCEPT_MRC_DATA_V1 cpu_to_le16(4)
2964#define HD_OFDM_NON_SQUARE_DET_SLOPE_DATA_V1 cpu_to_le16(486)
2965#define HD_OFDM_NON_SQUARE_DET_INTERCEPT_DATA_V1 cpu_to_le16(37)
2966#define HD_CCK_NON_SQUARE_DET_SLOPE_MRC_DATA_V1 cpu_to_le16(853)
2967#define HD_CCK_NON_SQUARE_DET_INTERCEPT_MRC_DATA_V1 cpu_to_le16(4)
2968#define HD_CCK_NON_SQUARE_DET_SLOPE_DATA_V1 cpu_to_le16(476)
2969#define HD_CCK_NON_SQUARE_DET_INTERCEPT_DATA_V1 cpu_to_le16(99)
2970
2971#define HD_INA_NON_SQUARE_DET_OFDM_DATA_V2 cpu_to_le16(1)
2972#define HD_INA_NON_SQUARE_DET_CCK_DATA_V2 cpu_to_le16(1)
2973#define HD_CORR_11_INSTEAD_OF_CORR_9_EN_DATA_V2 cpu_to_le16(1)
2974#define HD_OFDM_NON_SQUARE_DET_SLOPE_MRC_DATA_V2 cpu_to_le16(600)
2975#define HD_OFDM_NON_SQUARE_DET_INTERCEPT_MRC_DATA_V2 cpu_to_le16(40)
2976#define HD_OFDM_NON_SQUARE_DET_SLOPE_DATA_V2 cpu_to_le16(486)
2977#define HD_OFDM_NON_SQUARE_DET_INTERCEPT_DATA_V2 cpu_to_le16(45)
2978#define HD_CCK_NON_SQUARE_DET_SLOPE_MRC_DATA_V2 cpu_to_le16(853)
2979#define HD_CCK_NON_SQUARE_DET_INTERCEPT_MRC_DATA_V2 cpu_to_le16(60)
2980#define HD_CCK_NON_SQUARE_DET_SLOPE_DATA_V2 cpu_to_le16(476)
2981#define HD_CCK_NON_SQUARE_DET_INTERCEPT_DATA_V2 cpu_to_le16(99)
2982
2983
2984
2985#define SENSITIVITY_CMD_CONTROL_DEFAULT_TABLE cpu_to_le16(0)
2986#define SENSITIVITY_CMD_CONTROL_WORK_TABLE cpu_to_le16(1)
2987
2988
2989
2990
2991
2992
2993
2994
2995struct iwl_sensitivity_cmd {
2996 __le16 control;
2997 __le16 table[HD_TABLE_SIZE];
2998} __packed;
2999
3000
3001
3002
3003struct iwl_enhance_sensitivity_cmd {
3004 __le16 control;
3005 __le16 enhance_table[ENHANCE_HD_TABLE_SIZE];
3006} __packed;
3007
3008
3009
3010
3011
3012
3013
3014
3015
3016
3017
3018
3019
3020
3021
3022
3023
3024
3025
3026
3027
3028
3029
3030
3031
3032
3033
3034
3035
3036
3037
3038
3039
3040
3041
3042
3043
3044
3045
3046
3047
3048
3049
3050
3051
3052
3053
3054
3055
3056
3057
3058
3059
3060
3061
3062
3063
3064
3065enum {
3066 IWL_PHY_CALIBRATE_DC_CMD = 8,
3067 IWL_PHY_CALIBRATE_LO_CMD = 9,
3068 IWL_PHY_CALIBRATE_TX_IQ_CMD = 11,
3069 IWL_PHY_CALIBRATE_CRYSTAL_FRQ_CMD = 15,
3070 IWL_PHY_CALIBRATE_BASE_BAND_CMD = 16,
3071 IWL_PHY_CALIBRATE_TX_IQ_PERD_CMD = 17,
3072 IWL_PHY_CALIBRATE_TEMP_OFFSET_CMD = 18,
3073};
3074
3075
3076
3077
3078enum iwl_ucode_calib_cfg {
3079 IWL_CALIB_CFG_RX_BB_IDX = BIT(0),
3080 IWL_CALIB_CFG_DC_IDX = BIT(1),
3081 IWL_CALIB_CFG_LO_IDX = BIT(2),
3082 IWL_CALIB_CFG_TX_IQ_IDX = BIT(3),
3083 IWL_CALIB_CFG_RX_IQ_IDX = BIT(4),
3084 IWL_CALIB_CFG_NOISE_IDX = BIT(5),
3085 IWL_CALIB_CFG_CRYSTAL_IDX = BIT(6),
3086 IWL_CALIB_CFG_TEMPERATURE_IDX = BIT(7),
3087 IWL_CALIB_CFG_PAPD_IDX = BIT(8),
3088 IWL_CALIB_CFG_SENSITIVITY_IDX = BIT(9),
3089 IWL_CALIB_CFG_TX_PWR_IDX = BIT(10),
3090};
3091
3092#define IWL_CALIB_INIT_CFG_ALL cpu_to_le32(IWL_CALIB_CFG_RX_BB_IDX | \
3093 IWL_CALIB_CFG_DC_IDX | \
3094 IWL_CALIB_CFG_LO_IDX | \
3095 IWL_CALIB_CFG_TX_IQ_IDX | \
3096 IWL_CALIB_CFG_RX_IQ_IDX | \
3097 IWL_CALIB_CFG_CRYSTAL_IDX)
3098
3099#define IWL_CALIB_RT_CFG_ALL cpu_to_le32(IWL_CALIB_CFG_RX_BB_IDX | \
3100 IWL_CALIB_CFG_DC_IDX | \
3101 IWL_CALIB_CFG_LO_IDX | \
3102 IWL_CALIB_CFG_TX_IQ_IDX | \
3103 IWL_CALIB_CFG_RX_IQ_IDX | \
3104 IWL_CALIB_CFG_TEMPERATURE_IDX | \
3105 IWL_CALIB_CFG_PAPD_IDX | \
3106 IWL_CALIB_CFG_TX_PWR_IDX | \
3107 IWL_CALIB_CFG_CRYSTAL_IDX)
3108
3109#define IWL_CALIB_CFG_FLAG_SEND_COMPLETE_NTFY_MSK cpu_to_le32(BIT(0))
3110
3111struct iwl_calib_cfg_elmnt_s {
3112 __le32 is_enable;
3113 __le32 start;
3114 __le32 send_res;
3115 __le32 apply_res;
3116 __le32 reserved;
3117} __packed;
3118
3119struct iwl_calib_cfg_status_s {
3120 struct iwl_calib_cfg_elmnt_s once;
3121 struct iwl_calib_cfg_elmnt_s perd;
3122 __le32 flags;
3123} __packed;
3124
3125struct iwl_calib_cfg_cmd {
3126 struct iwl_calib_cfg_status_s ucd_calib_cfg;
3127 struct iwl_calib_cfg_status_s drv_calib_cfg;
3128 __le32 reserved1;
3129} __packed;
3130
3131struct iwl_calib_hdr {
3132 u8 op_code;
3133 u8 first_group;
3134 u8 groups_num;
3135 u8 data_valid;
3136} __packed;
3137
3138struct iwl_calib_cmd {
3139 struct iwl_calib_hdr hdr;
3140 u8 data[];
3141} __packed;
3142
3143struct iwl_calib_xtal_freq_cmd {
3144 struct iwl_calib_hdr hdr;
3145 u8 cap_pin1;
3146 u8 cap_pin2;
3147 u8 pad[2];
3148} __packed;
3149
3150#define DEFAULT_RADIO_SENSOR_OFFSET cpu_to_le16(2700)
3151struct iwl_calib_temperature_offset_cmd {
3152 struct iwl_calib_hdr hdr;
3153 __le16 radio_sensor_offset;
3154 __le16 reserved;
3155} __packed;
3156
3157struct iwl_calib_temperature_offset_v2_cmd {
3158 struct iwl_calib_hdr hdr;
3159 __le16 radio_sensor_offset_high;
3160 __le16 radio_sensor_offset_low;
3161 __le16 burntVoltageRef;
3162 __le16 reserved;
3163} __packed;
3164
3165
3166struct iwl_calib_chain_noise_reset_cmd {
3167 struct iwl_calib_hdr hdr;
3168 u8 data[];
3169};
3170
3171
3172struct iwl_calib_chain_noise_gain_cmd {
3173 struct iwl_calib_hdr hdr;
3174 u8 delta_gain_1;
3175 u8 delta_gain_2;
3176 u8 pad[2];
3177} __packed;
3178
3179
3180
3181
3182
3183
3184
3185
3186
3187
3188
3189
3190
3191
3192struct iwl_led_cmd {
3193 __le32 interval;
3194 u8 id;
3195 u8 off;
3196
3197 u8 on;
3198
3199 u8 reserved;
3200} __packed;
3201
3202
3203
3204
3205
3206
3207
3208
3209
3210
3211
3212
3213#define COEX_EVT_FLAG_MEDIUM_FREE_NTFY_FLG (0x1)
3214#define COEX_EVT_FLAG_MEDIUM_ACTV_NTFY_FLG (0x2)
3215#define COEX_EVT_FLAG_DELAY_MEDIUM_FREE_NTFY_FLG (0x4)
3216
3217#define COEX_CU_UNASSOC_IDLE_RP 4
3218#define COEX_CU_UNASSOC_MANUAL_SCAN_RP 4
3219#define COEX_CU_UNASSOC_AUTO_SCAN_RP 4
3220#define COEX_CU_CALIBRATION_RP 4
3221#define COEX_CU_PERIODIC_CALIBRATION_RP 4
3222#define COEX_CU_CONNECTION_ESTAB_RP 4
3223#define COEX_CU_ASSOCIATED_IDLE_RP 4
3224#define COEX_CU_ASSOC_MANUAL_SCAN_RP 4
3225#define COEX_CU_ASSOC_AUTO_SCAN_RP 4
3226#define COEX_CU_ASSOC_ACTIVE_LEVEL_RP 4
3227#define COEX_CU_RF_ON_RP 6
3228#define COEX_CU_RF_OFF_RP 4
3229#define COEX_CU_STAND_ALONE_DEBUG_RP 6
3230#define COEX_CU_IPAN_ASSOC_LEVEL_RP 4
3231#define COEX_CU_RSRVD1_RP 4
3232#define COEX_CU_RSRVD2_RP 4
3233
3234#define COEX_CU_UNASSOC_IDLE_WP 3
3235#define COEX_CU_UNASSOC_MANUAL_SCAN_WP 3
3236#define COEX_CU_UNASSOC_AUTO_SCAN_WP 3
3237#define COEX_CU_CALIBRATION_WP 3
3238#define COEX_CU_PERIODIC_CALIBRATION_WP 3
3239#define COEX_CU_CONNECTION_ESTAB_WP 3
3240#define COEX_CU_ASSOCIATED_IDLE_WP 3
3241#define COEX_CU_ASSOC_MANUAL_SCAN_WP 3
3242#define COEX_CU_ASSOC_AUTO_SCAN_WP 3
3243#define COEX_CU_ASSOC_ACTIVE_LEVEL_WP 3
3244#define COEX_CU_RF_ON_WP 3
3245#define COEX_CU_RF_OFF_WP 3
3246#define COEX_CU_STAND_ALONE_DEBUG_WP 6
3247#define COEX_CU_IPAN_ASSOC_LEVEL_WP 3
3248#define COEX_CU_RSRVD1_WP 3
3249#define COEX_CU_RSRVD2_WP 3
3250
3251#define COEX_UNASSOC_IDLE_FLAGS 0
3252#define COEX_UNASSOC_MANUAL_SCAN_FLAGS \
3253 (COEX_EVT_FLAG_MEDIUM_FREE_NTFY_FLG | \
3254 COEX_EVT_FLAG_MEDIUM_ACTV_NTFY_FLG)
3255#define COEX_UNASSOC_AUTO_SCAN_FLAGS \
3256 (COEX_EVT_FLAG_MEDIUM_FREE_NTFY_FLG | \
3257 COEX_EVT_FLAG_MEDIUM_ACTV_NTFY_FLG)
3258#define COEX_CALIBRATION_FLAGS \
3259 (COEX_EVT_FLAG_MEDIUM_FREE_NTFY_FLG | \
3260 COEX_EVT_FLAG_MEDIUM_ACTV_NTFY_FLG)
3261#define COEX_PERIODIC_CALIBRATION_FLAGS 0
3262
3263
3264
3265
3266#define COEX_CONNECTION_ESTAB_FLAGS \
3267 (COEX_EVT_FLAG_MEDIUM_FREE_NTFY_FLG | \
3268 COEX_EVT_FLAG_MEDIUM_ACTV_NTFY_FLG | \
3269 COEX_EVT_FLAG_DELAY_MEDIUM_FREE_NTFY_FLG)
3270#define COEX_ASSOCIATED_IDLE_FLAGS 0
3271#define COEX_ASSOC_MANUAL_SCAN_FLAGS \
3272 (COEX_EVT_FLAG_MEDIUM_FREE_NTFY_FLG | \
3273 COEX_EVT_FLAG_MEDIUM_ACTV_NTFY_FLG)
3274#define COEX_ASSOC_AUTO_SCAN_FLAGS \
3275 (COEX_EVT_FLAG_MEDIUM_FREE_NTFY_FLG | \
3276 COEX_EVT_FLAG_MEDIUM_ACTV_NTFY_FLG)
3277#define COEX_ASSOC_ACTIVE_LEVEL_FLAGS 0
3278#define COEX_RF_ON_FLAGS 0
3279#define COEX_RF_OFF_FLAGS 0
3280#define COEX_STAND_ALONE_DEBUG_FLAGS \
3281 (COEX_EVT_FLAG_MEDIUM_FREE_NTFY_FLG | \
3282 COEX_EVT_FLAG_MEDIUM_ACTV_NTFY_FLG)
3283#define COEX_IPAN_ASSOC_LEVEL_FLAGS \
3284 (COEX_EVT_FLAG_MEDIUM_FREE_NTFY_FLG | \
3285 COEX_EVT_FLAG_MEDIUM_ACTV_NTFY_FLG | \
3286 COEX_EVT_FLAG_DELAY_MEDIUM_FREE_NTFY_FLG)
3287#define COEX_RSRVD1_FLAGS 0
3288#define COEX_RSRVD2_FLAGS 0
3289
3290
3291
3292
3293#define COEX_CU_RF_ON_FLAGS \
3294 (COEX_EVT_FLAG_MEDIUM_FREE_NTFY_FLG | \
3295 COEX_EVT_FLAG_MEDIUM_ACTV_NTFY_FLG | \
3296 COEX_EVT_FLAG_DELAY_MEDIUM_FREE_NTFY_FLG)
3297
3298
3299enum {
3300
3301 COEX_UNASSOC_IDLE = 0,
3302 COEX_UNASSOC_MANUAL_SCAN = 1,
3303 COEX_UNASSOC_AUTO_SCAN = 2,
3304
3305 COEX_CALIBRATION = 3,
3306 COEX_PERIODIC_CALIBRATION = 4,
3307
3308 COEX_CONNECTION_ESTAB = 5,
3309
3310 COEX_ASSOCIATED_IDLE = 6,
3311 COEX_ASSOC_MANUAL_SCAN = 7,
3312 COEX_ASSOC_AUTO_SCAN = 8,
3313 COEX_ASSOC_ACTIVE_LEVEL = 9,
3314
3315 COEX_RF_ON = 10,
3316 COEX_RF_OFF = 11,
3317 COEX_STAND_ALONE_DEBUG = 12,
3318
3319 COEX_IPAN_ASSOC_LEVEL = 13,
3320
3321 COEX_RSRVD1 = 14,
3322 COEX_RSRVD2 = 15,
3323 COEX_NUM_OF_EVENTS = 16
3324};
3325
3326
3327
3328
3329
3330
3331struct iwl_wimax_coex_event_entry {
3332 u8 request_prio;
3333 u8 win_medium_prio;
3334 u8 reserved;
3335 u8 flags;
3336} __packed;
3337
3338
3339
3340
3341#define COEX_FLAGS_STA_TABLE_VALID_MSK (0x1)
3342
3343#define COEX_FLAGS_UNASSOC_WA_UNMASK_MSK (0x4)
3344
3345#define COEX_FLAGS_ASSOC_WA_UNMASK_MSK (0x8)
3346
3347#define COEX_FLAGS_COEX_ENABLE_MSK (0x80)
3348
3349struct iwl_wimax_coex_cmd {
3350 u8 flags;
3351 u8 reserved[3];
3352 struct iwl_wimax_coex_event_entry sta_prio[COEX_NUM_OF_EVENTS];
3353} __packed;
3354
3355
3356
3357
3358
3359
3360
3361
3362
3363
3364
3365
3366
3367
3368
3369#define COEX_MEDIUM_BUSY (0x0)
3370#define COEX_MEDIUM_ACTIVE (0x1)
3371#define COEX_MEDIUM_PRE_RELEASE (0x2)
3372#define COEX_MEDIUM_MSK (0x7)
3373
3374
3375#define COEX_MEDIUM_CHANGED (0x8)
3376#define COEX_MEDIUM_CHANGED_MSK (0x8)
3377#define COEX_MEDIUM_SHIFT (3)
3378
3379struct iwl_coex_medium_notification {
3380 __le32 status;
3381 __le32 events;
3382} __packed;
3383
3384
3385
3386
3387
3388
3389
3390
3391#define COEX_EVENT_REQUEST_MSK (0x1)
3392
3393struct iwl_coex_event_cmd {
3394 u8 flags;
3395 u8 event;
3396 __le16 reserved;
3397} __packed;
3398
3399struct iwl_coex_event_resp {
3400 __le32 status;
3401} __packed;
3402
3403
3404
3405
3406
3407
3408
3409
3410
3411
3412
3413enum iwl_bt_coex_profile_traffic_load {
3414 IWL_BT_COEX_TRAFFIC_LOAD_NONE = 0,
3415 IWL_BT_COEX_TRAFFIC_LOAD_LOW = 1,
3416 IWL_BT_COEX_TRAFFIC_LOAD_HIGH = 2,
3417 IWL_BT_COEX_TRAFFIC_LOAD_CONTINUOUS = 3,
3418
3419
3420
3421
3422};
3423
3424#define BT_SESSION_ACTIVITY_1_UART_MSG 0x1
3425#define BT_SESSION_ACTIVITY_2_UART_MSG 0x2
3426
3427
3428#define BT_UART_MSG_FRAME1MSGTYPE_POS (0)
3429#define BT_UART_MSG_FRAME1MSGTYPE_MSK \
3430 (0x7 << BT_UART_MSG_FRAME1MSGTYPE_POS)
3431#define BT_UART_MSG_FRAME1SSN_POS (3)
3432#define BT_UART_MSG_FRAME1SSN_MSK \
3433 (0x3 << BT_UART_MSG_FRAME1SSN_POS)
3434#define BT_UART_MSG_FRAME1UPDATEREQ_POS (5)
3435#define BT_UART_MSG_FRAME1UPDATEREQ_MSK \
3436 (0x1 << BT_UART_MSG_FRAME1UPDATEREQ_POS)
3437#define BT_UART_MSG_FRAME1RESERVED_POS (6)
3438#define BT_UART_MSG_FRAME1RESERVED_MSK \
3439 (0x3 << BT_UART_MSG_FRAME1RESERVED_POS)
3440
3441#define BT_UART_MSG_FRAME2OPENCONNECTIONS_POS (0)
3442#define BT_UART_MSG_FRAME2OPENCONNECTIONS_MSK \
3443 (0x3 << BT_UART_MSG_FRAME2OPENCONNECTIONS_POS)
3444#define BT_UART_MSG_FRAME2TRAFFICLOAD_POS (2)
3445#define BT_UART_MSG_FRAME2TRAFFICLOAD_MSK \
3446 (0x3 << BT_UART_MSG_FRAME2TRAFFICLOAD_POS)
3447#define BT_UART_MSG_FRAME2CHLSEQN_POS (4)
3448#define BT_UART_MSG_FRAME2CHLSEQN_MSK \
3449 (0x1 << BT_UART_MSG_FRAME2CHLSEQN_POS)
3450#define BT_UART_MSG_FRAME2INBAND_POS (5)
3451#define BT_UART_MSG_FRAME2INBAND_MSK \
3452 (0x1 << BT_UART_MSG_FRAME2INBAND_POS)
3453#define BT_UART_MSG_FRAME2RESERVED_POS (6)
3454#define BT_UART_MSG_FRAME2RESERVED_MSK \
3455 (0x3 << BT_UART_MSG_FRAME2RESERVED_POS)
3456
3457#define BT_UART_MSG_FRAME3SCOESCO_POS (0)
3458#define BT_UART_MSG_FRAME3SCOESCO_MSK \
3459 (0x1 << BT_UART_MSG_FRAME3SCOESCO_POS)
3460#define BT_UART_MSG_FRAME3SNIFF_POS (1)
3461#define BT_UART_MSG_FRAME3SNIFF_MSK \
3462 (0x1 << BT_UART_MSG_FRAME3SNIFF_POS)
3463#define BT_UART_MSG_FRAME3A2DP_POS (2)
3464#define BT_UART_MSG_FRAME3A2DP_MSK \
3465 (0x1 << BT_UART_MSG_FRAME3A2DP_POS)
3466#define BT_UART_MSG_FRAME3ACL_POS (3)
3467#define BT_UART_MSG_FRAME3ACL_MSK \
3468 (0x1 << BT_UART_MSG_FRAME3ACL_POS)
3469#define BT_UART_MSG_FRAME3MASTER_POS (4)
3470#define BT_UART_MSG_FRAME3MASTER_MSK \
3471 (0x1 << BT_UART_MSG_FRAME3MASTER_POS)
3472#define BT_UART_MSG_FRAME3OBEX_POS (5)
3473#define BT_UART_MSG_FRAME3OBEX_MSK \
3474 (0x1 << BT_UART_MSG_FRAME3OBEX_POS)
3475#define BT_UART_MSG_FRAME3RESERVED_POS (6)
3476#define BT_UART_MSG_FRAME3RESERVED_MSK \
3477 (0x3 << BT_UART_MSG_FRAME3RESERVED_POS)
3478
3479#define BT_UART_MSG_FRAME4IDLEDURATION_POS (0)
3480#define BT_UART_MSG_FRAME4IDLEDURATION_MSK \
3481 (0x3F << BT_UART_MSG_FRAME4IDLEDURATION_POS)
3482#define BT_UART_MSG_FRAME4RESERVED_POS (6)
3483#define BT_UART_MSG_FRAME4RESERVED_MSK \
3484 (0x3 << BT_UART_MSG_FRAME4RESERVED_POS)
3485
3486#define BT_UART_MSG_FRAME5TXACTIVITY_POS (0)
3487#define BT_UART_MSG_FRAME5TXACTIVITY_MSK \
3488 (0x3 << BT_UART_MSG_FRAME5TXACTIVITY_POS)
3489#define BT_UART_MSG_FRAME5RXACTIVITY_POS (2)
3490#define BT_UART_MSG_FRAME5RXACTIVITY_MSK \
3491 (0x3 << BT_UART_MSG_FRAME5RXACTIVITY_POS)
3492#define BT_UART_MSG_FRAME5ESCORETRANSMIT_POS (4)
3493#define BT_UART_MSG_FRAME5ESCORETRANSMIT_MSK \
3494 (0x3 << BT_UART_MSG_FRAME5ESCORETRANSMIT_POS)
3495#define BT_UART_MSG_FRAME5RESERVED_POS (6)
3496#define BT_UART_MSG_FRAME5RESERVED_MSK \
3497 (0x3 << BT_UART_MSG_FRAME5RESERVED_POS)
3498
3499#define BT_UART_MSG_FRAME6SNIFFINTERVAL_POS (0)
3500#define BT_UART_MSG_FRAME6SNIFFINTERVAL_MSK \
3501 (0x1F << BT_UART_MSG_FRAME6SNIFFINTERVAL_POS)
3502#define BT_UART_MSG_FRAME6DISCOVERABLE_POS (5)
3503#define BT_UART_MSG_FRAME6DISCOVERABLE_MSK \
3504 (0x1 << BT_UART_MSG_FRAME6DISCOVERABLE_POS)
3505#define BT_UART_MSG_FRAME6RESERVED_POS (6)
3506#define BT_UART_MSG_FRAME6RESERVED_MSK \
3507 (0x3 << BT_UART_MSG_FRAME6RESERVED_POS)
3508
3509#define BT_UART_MSG_FRAME7SNIFFACTIVITY_POS (0)
3510#define BT_UART_MSG_FRAME7SNIFFACTIVITY_MSK \
3511 (0x7 << BT_UART_MSG_FRAME7SNIFFACTIVITY_POS)
3512#define BT_UART_MSG_FRAME7PAGE_POS (3)
3513#define BT_UART_MSG_FRAME7PAGE_MSK \
3514 (0x1 << BT_UART_MSG_FRAME7PAGE_POS)
3515#define BT_UART_MSG_FRAME7INQUIRY_POS (4)
3516#define BT_UART_MSG_FRAME7INQUIRY_MSK \
3517 (0x1 << BT_UART_MSG_FRAME7INQUIRY_POS)
3518#define BT_UART_MSG_FRAME7CONNECTABLE_POS (5)
3519#define BT_UART_MSG_FRAME7CONNECTABLE_MSK \
3520 (0x1 << BT_UART_MSG_FRAME7CONNECTABLE_POS)
3521#define BT_UART_MSG_FRAME7RESERVED_POS (6)
3522#define BT_UART_MSG_FRAME7RESERVED_MSK \
3523 (0x3 << BT_UART_MSG_FRAME7RESERVED_POS)
3524
3525
3526#define BT_UART_MSG_2_FRAME1RESERVED1_POS (5)
3527#define BT_UART_MSG_2_FRAME1RESERVED1_MSK \
3528 (0x1<<BT_UART_MSG_2_FRAME1RESERVED1_POS)
3529#define BT_UART_MSG_2_FRAME1RESERVED2_POS (6)
3530#define BT_UART_MSG_2_FRAME1RESERVED2_MSK \
3531 (0x3<<BT_UART_MSG_2_FRAME1RESERVED2_POS)
3532
3533#define BT_UART_MSG_2_FRAME2AGGTRAFFICLOAD_POS (0)
3534#define BT_UART_MSG_2_FRAME2AGGTRAFFICLOAD_MSK \
3535 (0x3F<<BT_UART_MSG_2_FRAME2AGGTRAFFICLOAD_POS)
3536#define BT_UART_MSG_2_FRAME2RESERVED_POS (6)
3537#define BT_UART_MSG_2_FRAME2RESERVED_MSK \
3538 (0x3<<BT_UART_MSG_2_FRAME2RESERVED_POS)
3539
3540#define BT_UART_MSG_2_FRAME3BRLASTTXPOWER_POS (0)
3541#define BT_UART_MSG_2_FRAME3BRLASTTXPOWER_MSK \
3542 (0xF<<BT_UART_MSG_2_FRAME3BRLASTTXPOWER_POS)
3543#define BT_UART_MSG_2_FRAME3INQPAGESRMODE_POS (4)
3544#define BT_UART_MSG_2_FRAME3INQPAGESRMODE_MSK \
3545 (0x1<<BT_UART_MSG_2_FRAME3INQPAGESRMODE_POS)
3546#define BT_UART_MSG_2_FRAME3LEMASTER_POS (5)
3547#define BT_UART_MSG_2_FRAME3LEMASTER_MSK \
3548 (0x1<<BT_UART_MSG_2_FRAME3LEMASTER_POS)
3549#define BT_UART_MSG_2_FRAME3RESERVED_POS (6)
3550#define BT_UART_MSG_2_FRAME3RESERVED_MSK \
3551 (0x3<<BT_UART_MSG_2_FRAME3RESERVED_POS)
3552
3553#define BT_UART_MSG_2_FRAME4LELASTTXPOWER_POS (0)
3554#define BT_UART_MSG_2_FRAME4LELASTTXPOWER_MSK \
3555 (0xF<<BT_UART_MSG_2_FRAME4LELASTTXPOWER_POS)
3556#define BT_UART_MSG_2_FRAME4NUMLECONN_POS (4)
3557#define BT_UART_MSG_2_FRAME4NUMLECONN_MSK \
3558 (0x3<<BT_UART_MSG_2_FRAME4NUMLECONN_POS)
3559#define BT_UART_MSG_2_FRAME4RESERVED_POS (6)
3560#define BT_UART_MSG_2_FRAME4RESERVED_MSK \
3561 (0x3<<BT_UART_MSG_2_FRAME4RESERVED_POS)
3562
3563#define BT_UART_MSG_2_FRAME5BTMINRSSI_POS (0)
3564#define BT_UART_MSG_2_FRAME5BTMINRSSI_MSK \
3565 (0xF<<BT_UART_MSG_2_FRAME5BTMINRSSI_POS)
3566#define BT_UART_MSG_2_FRAME5LESCANINITMODE_POS (4)
3567#define BT_UART_MSG_2_FRAME5LESCANINITMODE_MSK \
3568 (0x1<<BT_UART_MSG_2_FRAME5LESCANINITMODE_POS)
3569#define BT_UART_MSG_2_FRAME5LEADVERMODE_POS (5)
3570#define BT_UART_MSG_2_FRAME5LEADVERMODE_MSK \
3571 (0x1<<BT_UART_MSG_2_FRAME5LEADVERMODE_POS)
3572#define BT_UART_MSG_2_FRAME5RESERVED_POS (6)
3573#define BT_UART_MSG_2_FRAME5RESERVED_MSK \
3574 (0x3<<BT_UART_MSG_2_FRAME5RESERVED_POS)
3575
3576#define BT_UART_MSG_2_FRAME6LECONNINTERVAL_POS (0)
3577#define BT_UART_MSG_2_FRAME6LECONNINTERVAL_MSK \
3578 (0x1F<<BT_UART_MSG_2_FRAME6LECONNINTERVAL_POS)
3579#define BT_UART_MSG_2_FRAME6RFU_POS (5)
3580#define BT_UART_MSG_2_FRAME6RFU_MSK \
3581 (0x1<<BT_UART_MSG_2_FRAME6RFU_POS)
3582#define BT_UART_MSG_2_FRAME6RESERVED_POS (6)
3583#define BT_UART_MSG_2_FRAME6RESERVED_MSK \
3584 (0x3<<BT_UART_MSG_2_FRAME6RESERVED_POS)
3585
3586#define BT_UART_MSG_2_FRAME7LECONNSLAVELAT_POS (0)
3587#define BT_UART_MSG_2_FRAME7LECONNSLAVELAT_MSK \
3588 (0x7<<BT_UART_MSG_2_FRAME7LECONNSLAVELAT_POS)
3589#define BT_UART_MSG_2_FRAME7LEPROFILE1_POS (3)
3590#define BT_UART_MSG_2_FRAME7LEPROFILE1_MSK \
3591 (0x1<<BT_UART_MSG_2_FRAME7LEPROFILE1_POS)
3592#define BT_UART_MSG_2_FRAME7LEPROFILE2_POS (4)
3593#define BT_UART_MSG_2_FRAME7LEPROFILE2_MSK \
3594 (0x1<<BT_UART_MSG_2_FRAME7LEPROFILE2_POS)
3595#define BT_UART_MSG_2_FRAME7LEPROFILEOTHER_POS (5)
3596#define BT_UART_MSG_2_FRAME7LEPROFILEOTHER_MSK \
3597 (0x1<<BT_UART_MSG_2_FRAME7LEPROFILEOTHER_POS)
3598#define BT_UART_MSG_2_FRAME7RESERVED_POS (6)
3599#define BT_UART_MSG_2_FRAME7RESERVED_MSK \
3600 (0x3<<BT_UART_MSG_2_FRAME7RESERVED_POS)
3601
3602
3603#define BT_ENABLE_REDUCED_TXPOWER_THRESHOLD (-62)
3604#define BT_DISABLE_REDUCED_TXPOWER_THRESHOLD (-65)
3605
3606struct iwl_bt_uart_msg {
3607 u8 header;
3608 u8 frame1;
3609 u8 frame2;
3610 u8 frame3;
3611 u8 frame4;
3612 u8 frame5;
3613 u8 frame6;
3614 u8 frame7;
3615} __packed;
3616
3617struct iwl_bt_coex_profile_notif {
3618 struct iwl_bt_uart_msg last_bt_uart_msg;
3619 u8 bt_status;
3620 u8 bt_traffic_load;
3621 u8 bt_ci_compliance;
3622 u8 reserved;
3623} __packed;
3624
3625#define IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS 0
3626#define IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_MSK 0x1
3627#define IWL_BT_COEX_PRIO_TBL_PRIO_POS 1
3628#define IWL_BT_COEX_PRIO_TBL_PRIO_MASK 0x0e
3629#define IWL_BT_COEX_PRIO_TBL_RESERVED_POS 4
3630#define IWL_BT_COEX_PRIO_TBL_RESERVED_MASK 0xf0
3631#define IWL_BT_COEX_PRIO_TBL_PRIO_SHIFT 1
3632
3633
3634
3635
3636
3637enum bt_coex_prio_table_events {
3638 BT_COEX_PRIO_TBL_EVT_INIT_CALIB1 = 0,
3639 BT_COEX_PRIO_TBL_EVT_INIT_CALIB2 = 1,
3640 BT_COEX_PRIO_TBL_EVT_PERIODIC_CALIB_LOW1 = 2,
3641 BT_COEX_PRIO_TBL_EVT_PERIODIC_CALIB_LOW2 = 3,
3642 BT_COEX_PRIO_TBL_EVT_PERIODIC_CALIB_HIGH1 = 4,
3643 BT_COEX_PRIO_TBL_EVT_PERIODIC_CALIB_HIGH2 = 5,
3644 BT_COEX_PRIO_TBL_EVT_DTIM = 6,
3645 BT_COEX_PRIO_TBL_EVT_SCAN52 = 7,
3646 BT_COEX_PRIO_TBL_EVT_SCAN24 = 8,
3647 BT_COEX_PRIO_TBL_EVT_RESERVED0 = 9,
3648 BT_COEX_PRIO_TBL_EVT_RESERVED1 = 10,
3649 BT_COEX_PRIO_TBL_EVT_RESERVED2 = 11,
3650 BT_COEX_PRIO_TBL_EVT_RESERVED3 = 12,
3651 BT_COEX_PRIO_TBL_EVT_RESERVED4 = 13,
3652 BT_COEX_PRIO_TBL_EVT_RESERVED5 = 14,
3653 BT_COEX_PRIO_TBL_EVT_RESERVED6 = 15,
3654
3655 BT_COEX_PRIO_TBL_EVT_MAX,
3656};
3657
3658enum bt_coex_prio_table_priorities {
3659 BT_COEX_PRIO_TBL_DISABLED = 0,
3660 BT_COEX_PRIO_TBL_PRIO_LOW = 1,
3661 BT_COEX_PRIO_TBL_PRIO_HIGH = 2,
3662 BT_COEX_PRIO_TBL_PRIO_BYPASS = 3,
3663 BT_COEX_PRIO_TBL_PRIO_COEX_OFF = 4,
3664 BT_COEX_PRIO_TBL_PRIO_COEX_ON = 5,
3665 BT_COEX_PRIO_TBL_PRIO_RSRVD1 = 6,
3666 BT_COEX_PRIO_TBL_PRIO_RSRVD2 = 7,
3667 BT_COEX_PRIO_TBL_MAX,
3668};
3669
3670struct iwl_bt_coex_prio_table_cmd {
3671 u8 prio_tbl[BT_COEX_PRIO_TBL_EVT_MAX];
3672} __packed;
3673
3674#define IWL_BT_COEX_ENV_CLOSE 0
3675#define IWL_BT_COEX_ENV_OPEN 1
3676
3677
3678
3679
3680struct iwl_bt_coex_prot_env_cmd {
3681 u8 action;
3682 u8 type;
3683 u8 reserved[2];
3684} __packed;
3685
3686
3687
3688
3689enum iwlagn_d3_wakeup_filters {
3690 IWLAGN_D3_WAKEUP_RFKILL = BIT(0),
3691 IWLAGN_D3_WAKEUP_SYSASSERT = BIT(1),
3692};
3693
3694struct iwlagn_d3_config_cmd {
3695 __le32 min_sleep_time;
3696 __le32 wakeup_flags;
3697} __packed;
3698
3699
3700
3701
3702#define IWLAGN_WOWLAN_MIN_PATTERN_LEN 16
3703#define IWLAGN_WOWLAN_MAX_PATTERN_LEN 128
3704
3705struct iwlagn_wowlan_pattern {
3706 u8 mask[IWLAGN_WOWLAN_MAX_PATTERN_LEN / 8];
3707 u8 pattern[IWLAGN_WOWLAN_MAX_PATTERN_LEN];
3708 u8 mask_size;
3709 u8 pattern_size;
3710 __le16 reserved;
3711} __packed;
3712
3713#define IWLAGN_WOWLAN_MAX_PATTERNS 20
3714
3715struct iwlagn_wowlan_patterns_cmd {
3716 __le32 n_patterns;
3717 struct iwlagn_wowlan_pattern patterns[];
3718} __packed;
3719
3720
3721
3722
3723enum iwlagn_wowlan_wakeup_filters {
3724 IWLAGN_WOWLAN_WAKEUP_MAGIC_PACKET = BIT(0),
3725 IWLAGN_WOWLAN_WAKEUP_PATTERN_MATCH = BIT(1),
3726 IWLAGN_WOWLAN_WAKEUP_BEACON_MISS = BIT(2),
3727 IWLAGN_WOWLAN_WAKEUP_LINK_CHANGE = BIT(3),
3728 IWLAGN_WOWLAN_WAKEUP_GTK_REKEY_FAIL = BIT(4),
3729 IWLAGN_WOWLAN_WAKEUP_EAP_IDENT_REQ = BIT(5),
3730 IWLAGN_WOWLAN_WAKEUP_4WAY_HANDSHAKE = BIT(6),
3731 IWLAGN_WOWLAN_WAKEUP_ALWAYS = BIT(7),
3732 IWLAGN_WOWLAN_WAKEUP_ENABLE_NET_DETECT = BIT(8),
3733};
3734
3735struct iwlagn_wowlan_wakeup_filter_cmd {
3736 __le32 enabled;
3737 __le16 non_qos_seq;
3738 __le16 reserved;
3739 __le16 qos_seq[8];
3740};
3741
3742
3743
3744
3745#define IWLAGN_NUM_RSC 16
3746
3747struct tkip_sc {
3748 __le16 iv16;
3749 __le16 pad;
3750 __le32 iv32;
3751} __packed;
3752
3753struct iwlagn_tkip_rsc_tsc {
3754 struct tkip_sc unicast_rsc[IWLAGN_NUM_RSC];
3755 struct tkip_sc multicast_rsc[IWLAGN_NUM_RSC];
3756 struct tkip_sc tsc;
3757} __packed;
3758
3759struct aes_sc {
3760 __le64 pn;
3761} __packed;
3762
3763struct iwlagn_aes_rsc_tsc {
3764 struct aes_sc unicast_rsc[IWLAGN_NUM_RSC];
3765 struct aes_sc multicast_rsc[IWLAGN_NUM_RSC];
3766 struct aes_sc tsc;
3767} __packed;
3768
3769union iwlagn_all_tsc_rsc {
3770 struct iwlagn_tkip_rsc_tsc tkip;
3771 struct iwlagn_aes_rsc_tsc aes;
3772};
3773
3774struct iwlagn_wowlan_rsc_tsc_params_cmd {
3775 union iwlagn_all_tsc_rsc all_tsc_rsc;
3776} __packed;
3777
3778
3779
3780
3781#define IWLAGN_MIC_KEY_SIZE 8
3782#define IWLAGN_P1K_SIZE 5
3783struct iwlagn_mic_keys {
3784 u8 tx[IWLAGN_MIC_KEY_SIZE];
3785 u8 rx_unicast[IWLAGN_MIC_KEY_SIZE];
3786 u8 rx_mcast[IWLAGN_MIC_KEY_SIZE];
3787} __packed;
3788
3789struct iwlagn_p1k_cache {
3790 __le16 p1k[IWLAGN_P1K_SIZE];
3791} __packed;
3792
3793#define IWLAGN_NUM_RX_P1K_CACHE 2
3794
3795struct iwlagn_wowlan_tkip_params_cmd {
3796 struct iwlagn_mic_keys mic_keys;
3797 struct iwlagn_p1k_cache tx;
3798 struct iwlagn_p1k_cache rx_uni[IWLAGN_NUM_RX_P1K_CACHE];
3799 struct iwlagn_p1k_cache rx_multi[IWLAGN_NUM_RX_P1K_CACHE];
3800} __packed;
3801
3802
3803
3804
3805
3806#define IWLAGN_KCK_MAX_SIZE 32
3807#define IWLAGN_KEK_MAX_SIZE 32
3808
3809struct iwlagn_wowlan_kek_kck_material_cmd {
3810 u8 kck[IWLAGN_KCK_MAX_SIZE];
3811 u8 kek[IWLAGN_KEK_MAX_SIZE];
3812 __le16 kck_len;
3813 __le16 kek_len;
3814 __le64 replay_ctr;
3815} __packed;
3816
3817#define RF_KILL_INDICATOR_FOR_WOWLAN 0x87
3818
3819
3820
3821
3822struct iwlagn_wowlan_status {
3823 __le64 replay_ctr;
3824 __le32 rekey_status;
3825 __le32 wakeup_reason;
3826 u8 pattern_number;
3827 u8 reserved1;
3828 __le16 qos_seq_ctr[8];
3829 __le16 non_qos_seq_ctr;
3830 __le16 reserved2;
3831 union iwlagn_all_tsc_rsc tsc_rsc;
3832 __le16 reserved3;
3833} __packed;
3834
3835
3836
3837
3838
3839
3840
3841
3842#define IWL_MIN_SLOT_TIME 20
3843
3844
3845
3846
3847
3848
3849
3850
3851struct iwl_wipan_slot {
3852 __le16 width;
3853 u8 type;
3854 u8 reserved;
3855} __packed;
3856
3857#define IWL_WIPAN_PARAMS_FLG_LEAVE_CHANNEL_CTS BIT(1)
3858#define IWL_WIPAN_PARAMS_FLG_LEAVE_CHANNEL_QUIET BIT(2)
3859#define IWL_WIPAN_PARAMS_FLG_SLOTTED_MODE BIT(3)
3860#define IWL_WIPAN_PARAMS_FLG_FILTER_BEACON_NOTIF BIT(4)
3861#define IWL_WIPAN_PARAMS_FLG_FULL_SLOTTED_MODE BIT(5)
3862
3863
3864
3865
3866
3867
3868
3869
3870
3871
3872
3873
3874
3875
3876
3877
3878struct iwl_wipan_params_cmd {
3879 __le16 flags;
3880 u8 reserved;
3881 u8 num_slots;
3882 struct iwl_wipan_slot slots[10];
3883} __packed;
3884
3885
3886
3887
3888
3889
3890
3891
3892
3893struct iwl_wipan_p2p_channel_switch_cmd {
3894 __le16 channel;
3895 __le16 reserved;
3896};
3897
3898
3899
3900
3901
3902
3903
3904
3905
3906
3907
3908
3909struct iwl_wipan_noa_descriptor {
3910 u8 count;
3911 __le32 duration;
3912 __le32 interval;
3913 __le32 starttime;
3914} __packed;
3915
3916struct iwl_wipan_noa_attribute {
3917 u8 id;
3918 __le16 length;
3919 u8 index;
3920 u8 ct_window;
3921 struct iwl_wipan_noa_descriptor descr0, descr1;
3922 u8 reserved;
3923} __packed;
3924
3925struct iwl_wipan_noa_notification {
3926 u32 noa_active;
3927 struct iwl_wipan_noa_attribute noa_attribute;
3928} __packed;
3929
3930#endif
3931