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20#include <linux/firmware.h>
21
22#include "decl.h"
23#include "ioctl.h"
24#include "util.h"
25#include "fw.h"
26#include "main.h"
27#include "wmm.h"
28#include "11n.h"
29#include "sdio.h"
30
31
32#define SDIO_VERSION "1.0"
33
34static void mwifiex_sdio_work(struct work_struct *work);
35
36static struct mwifiex_if_ops sdio_ops;
37
38static const struct mwifiex_sdio_card_reg mwifiex_reg_sd87xx = {
39 .start_rd_port = 1,
40 .start_wr_port = 1,
41 .base_0_reg = 0x0040,
42 .base_1_reg = 0x0041,
43 .poll_reg = 0x30,
44 .host_int_enable = UP_LD_HOST_INT_MASK | DN_LD_HOST_INT_MASK,
45 .host_int_rsr_reg = 0x1,
46 .host_int_mask_reg = 0x02,
47 .host_int_status_reg = 0x03,
48 .status_reg_0 = 0x60,
49 .status_reg_1 = 0x61,
50 .sdio_int_mask = 0x3f,
51 .data_port_mask = 0x0000fffe,
52 .io_port_0_reg = 0x78,
53 .io_port_1_reg = 0x79,
54 .io_port_2_reg = 0x7A,
55 .max_mp_regs = 64,
56 .rd_bitmap_l = 0x04,
57 .rd_bitmap_u = 0x05,
58 .wr_bitmap_l = 0x06,
59 .wr_bitmap_u = 0x07,
60 .rd_len_p0_l = 0x08,
61 .rd_len_p0_u = 0x09,
62 .card_misc_cfg_reg = 0x6c,
63 .func1_dump_reg_start = 0x0,
64 .func1_dump_reg_end = 0x9,
65 .func1_scratch_reg = 0x60,
66 .func1_spec_reg_num = 5,
67 .func1_spec_reg_table = {0x28, 0x30, 0x34, 0x38, 0x3c},
68};
69
70static const struct mwifiex_sdio_card_reg mwifiex_reg_sd8897 = {
71 .start_rd_port = 0,
72 .start_wr_port = 0,
73 .base_0_reg = 0x60,
74 .base_1_reg = 0x61,
75 .poll_reg = 0x50,
76 .host_int_enable = UP_LD_HOST_INT_MASK | DN_LD_HOST_INT_MASK |
77 CMD_PORT_UPLD_INT_MASK | CMD_PORT_DNLD_INT_MASK,
78 .host_int_rsr_reg = 0x1,
79 .host_int_status_reg = 0x03,
80 .host_int_mask_reg = 0x02,
81 .status_reg_0 = 0xc0,
82 .status_reg_1 = 0xc1,
83 .sdio_int_mask = 0xff,
84 .data_port_mask = 0xffffffff,
85 .io_port_0_reg = 0xD8,
86 .io_port_1_reg = 0xD9,
87 .io_port_2_reg = 0xDA,
88 .max_mp_regs = 184,
89 .rd_bitmap_l = 0x04,
90 .rd_bitmap_u = 0x05,
91 .rd_bitmap_1l = 0x06,
92 .rd_bitmap_1u = 0x07,
93 .wr_bitmap_l = 0x08,
94 .wr_bitmap_u = 0x09,
95 .wr_bitmap_1l = 0x0a,
96 .wr_bitmap_1u = 0x0b,
97 .rd_len_p0_l = 0x0c,
98 .rd_len_p0_u = 0x0d,
99 .card_misc_cfg_reg = 0xcc,
100 .card_cfg_2_1_reg = 0xcd,
101 .cmd_rd_len_0 = 0xb4,
102 .cmd_rd_len_1 = 0xb5,
103 .cmd_rd_len_2 = 0xb6,
104 .cmd_rd_len_3 = 0xb7,
105 .cmd_cfg_0 = 0xb8,
106 .cmd_cfg_1 = 0xb9,
107 .cmd_cfg_2 = 0xba,
108 .cmd_cfg_3 = 0xbb,
109 .fw_dump_host_ready = 0xee,
110 .fw_dump_ctrl = 0xe2,
111 .fw_dump_start = 0xe3,
112 .fw_dump_end = 0xea,
113 .func1_dump_reg_start = 0x0,
114 .func1_dump_reg_end = 0xb,
115 .func1_scratch_reg = 0xc0,
116 .func1_spec_reg_num = 8,
117 .func1_spec_reg_table = {0x4C, 0x50, 0x54, 0x55, 0x58,
118 0x59, 0x5c, 0x5d},
119};
120
121static const struct mwifiex_sdio_card_reg mwifiex_reg_sd8977 = {
122 .start_rd_port = 0,
123 .start_wr_port = 0,
124 .base_0_reg = 0xF8,
125 .base_1_reg = 0xF9,
126 .poll_reg = 0x5C,
127 .host_int_enable = UP_LD_HOST_INT_MASK | DN_LD_HOST_INT_MASK |
128 CMD_PORT_UPLD_INT_MASK | CMD_PORT_DNLD_INT_MASK,
129 .host_int_rsr_reg = 0x4,
130 .host_int_status_reg = 0x0C,
131 .host_int_mask_reg = 0x08,
132 .status_reg_0 = 0xE8,
133 .status_reg_1 = 0xE9,
134 .sdio_int_mask = 0xff,
135 .data_port_mask = 0xffffffff,
136 .io_port_0_reg = 0xE4,
137 .io_port_1_reg = 0xE5,
138 .io_port_2_reg = 0xE6,
139 .max_mp_regs = 196,
140 .rd_bitmap_l = 0x10,
141 .rd_bitmap_u = 0x11,
142 .rd_bitmap_1l = 0x12,
143 .rd_bitmap_1u = 0x13,
144 .wr_bitmap_l = 0x14,
145 .wr_bitmap_u = 0x15,
146 .wr_bitmap_1l = 0x16,
147 .wr_bitmap_1u = 0x17,
148 .rd_len_p0_l = 0x18,
149 .rd_len_p0_u = 0x19,
150 .card_misc_cfg_reg = 0xd8,
151 .card_cfg_2_1_reg = 0xd9,
152 .cmd_rd_len_0 = 0xc0,
153 .cmd_rd_len_1 = 0xc1,
154 .cmd_rd_len_2 = 0xc2,
155 .cmd_rd_len_3 = 0xc3,
156 .cmd_cfg_0 = 0xc4,
157 .cmd_cfg_1 = 0xc5,
158 .cmd_cfg_2 = 0xc6,
159 .cmd_cfg_3 = 0xc7,
160 .fw_dump_host_ready = 0xcc,
161 .fw_dump_ctrl = 0xf0,
162 .fw_dump_start = 0xf1,
163 .fw_dump_end = 0xf8,
164 .func1_dump_reg_start = 0x10,
165 .func1_dump_reg_end = 0x17,
166 .func1_scratch_reg = 0xe8,
167 .func1_spec_reg_num = 13,
168 .func1_spec_reg_table = {0x08, 0x58, 0x5C, 0x5D,
169 0x60, 0x61, 0x62, 0x64,
170 0x65, 0x66, 0x68, 0x69,
171 0x6a},
172};
173
174static const struct mwifiex_sdio_card_reg mwifiex_reg_sd8997 = {
175 .start_rd_port = 0,
176 .start_wr_port = 0,
177 .base_0_reg = 0xF8,
178 .base_1_reg = 0xF9,
179 .poll_reg = 0x5C,
180 .host_int_enable = UP_LD_HOST_INT_MASK | DN_LD_HOST_INT_MASK |
181 CMD_PORT_UPLD_INT_MASK | CMD_PORT_DNLD_INT_MASK,
182 .host_int_rsr_reg = 0x4,
183 .host_int_status_reg = 0x0C,
184 .host_int_mask_reg = 0x08,
185 .host_strap_reg = 0xF4,
186 .host_strap_mask = 0x01,
187 .host_strap_value = 0x00,
188 .status_reg_0 = 0xE8,
189 .status_reg_1 = 0xE9,
190 .sdio_int_mask = 0xff,
191 .data_port_mask = 0xffffffff,
192 .io_port_0_reg = 0xE4,
193 .io_port_1_reg = 0xE5,
194 .io_port_2_reg = 0xE6,
195 .max_mp_regs = 196,
196 .rd_bitmap_l = 0x10,
197 .rd_bitmap_u = 0x11,
198 .rd_bitmap_1l = 0x12,
199 .rd_bitmap_1u = 0x13,
200 .wr_bitmap_l = 0x14,
201 .wr_bitmap_u = 0x15,
202 .wr_bitmap_1l = 0x16,
203 .wr_bitmap_1u = 0x17,
204 .rd_len_p0_l = 0x18,
205 .rd_len_p0_u = 0x19,
206 .card_misc_cfg_reg = 0xd8,
207 .card_cfg_2_1_reg = 0xd9,
208 .cmd_rd_len_0 = 0xc0,
209 .cmd_rd_len_1 = 0xc1,
210 .cmd_rd_len_2 = 0xc2,
211 .cmd_rd_len_3 = 0xc3,
212 .cmd_cfg_0 = 0xc4,
213 .cmd_cfg_1 = 0xc5,
214 .cmd_cfg_2 = 0xc6,
215 .cmd_cfg_3 = 0xc7,
216 .fw_dump_host_ready = 0xcc,
217 .fw_dump_ctrl = 0xf0,
218 .fw_dump_start = 0xf1,
219 .fw_dump_end = 0xf8,
220 .func1_dump_reg_start = 0x10,
221 .func1_dump_reg_end = 0x17,
222 .func1_scratch_reg = 0xe8,
223 .func1_spec_reg_num = 13,
224 .func1_spec_reg_table = {0x08, 0x58, 0x5C, 0x5D,
225 0x60, 0x61, 0x62, 0x64,
226 0x65, 0x66, 0x68, 0x69,
227 0x6a},
228};
229
230static const struct mwifiex_sdio_card_reg mwifiex_reg_sd8887 = {
231 .start_rd_port = 0,
232 .start_wr_port = 0,
233 .base_0_reg = 0x6C,
234 .base_1_reg = 0x6D,
235 .poll_reg = 0x5C,
236 .host_int_enable = UP_LD_HOST_INT_MASK | DN_LD_HOST_INT_MASK |
237 CMD_PORT_UPLD_INT_MASK | CMD_PORT_DNLD_INT_MASK,
238 .host_int_rsr_reg = 0x4,
239 .host_int_status_reg = 0x0C,
240 .host_int_mask_reg = 0x08,
241 .status_reg_0 = 0x90,
242 .status_reg_1 = 0x91,
243 .sdio_int_mask = 0xff,
244 .data_port_mask = 0xffffffff,
245 .io_port_0_reg = 0xE4,
246 .io_port_1_reg = 0xE5,
247 .io_port_2_reg = 0xE6,
248 .max_mp_regs = 196,
249 .rd_bitmap_l = 0x10,
250 .rd_bitmap_u = 0x11,
251 .rd_bitmap_1l = 0x12,
252 .rd_bitmap_1u = 0x13,
253 .wr_bitmap_l = 0x14,
254 .wr_bitmap_u = 0x15,
255 .wr_bitmap_1l = 0x16,
256 .wr_bitmap_1u = 0x17,
257 .rd_len_p0_l = 0x18,
258 .rd_len_p0_u = 0x19,
259 .card_misc_cfg_reg = 0xd8,
260 .card_cfg_2_1_reg = 0xd9,
261 .cmd_rd_len_0 = 0xc0,
262 .cmd_rd_len_1 = 0xc1,
263 .cmd_rd_len_2 = 0xc2,
264 .cmd_rd_len_3 = 0xc3,
265 .cmd_cfg_0 = 0xc4,
266 .cmd_cfg_1 = 0xc5,
267 .cmd_cfg_2 = 0xc6,
268 .cmd_cfg_3 = 0xc7,
269 .func1_dump_reg_start = 0x10,
270 .func1_dump_reg_end = 0x17,
271 .func1_scratch_reg = 0x90,
272 .func1_spec_reg_num = 13,
273 .func1_spec_reg_table = {0x08, 0x58, 0x5C, 0x5D, 0x60,
274 0x61, 0x62, 0x64, 0x65, 0x66,
275 0x68, 0x69, 0x6a},
276};
277
278static const struct mwifiex_sdio_card_reg mwifiex_reg_sd8987 = {
279 .start_rd_port = 0,
280 .start_wr_port = 0,
281 .base_0_reg = 0xF8,
282 .base_1_reg = 0xF9,
283 .poll_reg = 0x5C,
284 .host_int_enable = UP_LD_HOST_INT_MASK | DN_LD_HOST_INT_MASK |
285 CMD_PORT_UPLD_INT_MASK | CMD_PORT_DNLD_INT_MASK,
286 .host_int_rsr_reg = 0x4,
287 .host_int_status_reg = 0x0C,
288 .host_int_mask_reg = 0x08,
289 .host_strap_reg = 0xF4,
290 .host_strap_mask = 0x01,
291 .host_strap_value = 0x00,
292 .status_reg_0 = 0xE8,
293 .status_reg_1 = 0xE9,
294 .sdio_int_mask = 0xff,
295 .data_port_mask = 0xffffffff,
296 .io_port_0_reg = 0xE4,
297 .io_port_1_reg = 0xE5,
298 .io_port_2_reg = 0xE6,
299 .max_mp_regs = 196,
300 .rd_bitmap_l = 0x10,
301 .rd_bitmap_u = 0x11,
302 .rd_bitmap_1l = 0x12,
303 .rd_bitmap_1u = 0x13,
304 .wr_bitmap_l = 0x14,
305 .wr_bitmap_u = 0x15,
306 .wr_bitmap_1l = 0x16,
307 .wr_bitmap_1u = 0x17,
308 .rd_len_p0_l = 0x18,
309 .rd_len_p0_u = 0x19,
310 .card_misc_cfg_reg = 0xd8,
311 .card_cfg_2_1_reg = 0xd9,
312 .cmd_rd_len_0 = 0xc0,
313 .cmd_rd_len_1 = 0xc1,
314 .cmd_rd_len_2 = 0xc2,
315 .cmd_rd_len_3 = 0xc3,
316 .cmd_cfg_0 = 0xc4,
317 .cmd_cfg_1 = 0xc5,
318 .cmd_cfg_2 = 0xc6,
319 .cmd_cfg_3 = 0xc7,
320 .fw_dump_host_ready = 0xcc,
321 .fw_dump_ctrl = 0xf9,
322 .fw_dump_start = 0xf1,
323 .fw_dump_end = 0xf8,
324 .func1_dump_reg_start = 0x10,
325 .func1_dump_reg_end = 0x17,
326 .func1_scratch_reg = 0xE8,
327 .func1_spec_reg_num = 13,
328 .func1_spec_reg_table = {0x08, 0x58, 0x5C, 0x5D, 0x60,
329 0x61, 0x62, 0x64, 0x65, 0x66,
330 0x68, 0x69, 0x6a},
331};
332
333static const struct mwifiex_sdio_device mwifiex_sdio_sd8786 = {
334 .firmware = SD8786_DEFAULT_FW_NAME,
335 .reg = &mwifiex_reg_sd87xx,
336 .max_ports = 16,
337 .mp_agg_pkt_limit = 8,
338 .tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_2K,
339 .mp_tx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_16K,
340 .mp_rx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_16K,
341 .supports_sdio_new_mode = false,
342 .has_control_mask = true,
343 .can_dump_fw = false,
344 .can_auto_tdls = false,
345 .can_ext_scan = false,
346};
347
348static const struct mwifiex_sdio_device mwifiex_sdio_sd8787 = {
349 .firmware = SD8787_DEFAULT_FW_NAME,
350 .reg = &mwifiex_reg_sd87xx,
351 .max_ports = 16,
352 .mp_agg_pkt_limit = 8,
353 .tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_2K,
354 .mp_tx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_16K,
355 .mp_rx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_16K,
356 .supports_sdio_new_mode = false,
357 .has_control_mask = true,
358 .can_dump_fw = false,
359 .can_auto_tdls = false,
360 .can_ext_scan = true,
361};
362
363static const struct mwifiex_sdio_device mwifiex_sdio_sd8797 = {
364 .firmware = SD8797_DEFAULT_FW_NAME,
365 .reg = &mwifiex_reg_sd87xx,
366 .max_ports = 16,
367 .mp_agg_pkt_limit = 8,
368 .tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_2K,
369 .mp_tx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_16K,
370 .mp_rx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_16K,
371 .supports_sdio_new_mode = false,
372 .has_control_mask = true,
373 .can_dump_fw = false,
374 .can_auto_tdls = false,
375 .can_ext_scan = true,
376};
377
378static const struct mwifiex_sdio_device mwifiex_sdio_sd8897 = {
379 .firmware = SD8897_DEFAULT_FW_NAME,
380 .reg = &mwifiex_reg_sd8897,
381 .max_ports = 32,
382 .mp_agg_pkt_limit = 16,
383 .tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_4K,
384 .mp_tx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_MAX,
385 .mp_rx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_MAX,
386 .supports_sdio_new_mode = true,
387 .has_control_mask = false,
388 .can_dump_fw = true,
389 .can_auto_tdls = false,
390 .can_ext_scan = true,
391};
392
393static const struct mwifiex_sdio_device mwifiex_sdio_sd8977 = {
394 .firmware = SD8977_DEFAULT_FW_NAME,
395 .reg = &mwifiex_reg_sd8977,
396 .max_ports = 32,
397 .mp_agg_pkt_limit = 16,
398 .tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_4K,
399 .mp_tx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_MAX,
400 .mp_rx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_MAX,
401 .supports_sdio_new_mode = true,
402 .has_control_mask = false,
403 .can_dump_fw = true,
404 .fw_dump_enh = true,
405 .can_auto_tdls = false,
406 .can_ext_scan = true,
407};
408
409static const struct mwifiex_sdio_device mwifiex_sdio_sd8997 = {
410 .firmware = SD8997_DEFAULT_FW_NAME,
411 .firmware_sdiouart = SD8997_SDIOUART_FW_NAME,
412 .reg = &mwifiex_reg_sd8997,
413 .max_ports = 32,
414 .mp_agg_pkt_limit = 16,
415 .tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_4K,
416 .mp_tx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_MAX,
417 .mp_rx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_MAX,
418 .supports_sdio_new_mode = true,
419 .has_control_mask = false,
420 .can_dump_fw = true,
421 .fw_dump_enh = true,
422 .can_auto_tdls = false,
423 .can_ext_scan = true,
424};
425
426static const struct mwifiex_sdio_device mwifiex_sdio_sd8887 = {
427 .firmware = SD8887_DEFAULT_FW_NAME,
428 .reg = &mwifiex_reg_sd8887,
429 .max_ports = 32,
430 .mp_agg_pkt_limit = 16,
431 .tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_2K,
432 .mp_tx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_32K,
433 .mp_rx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_32K,
434 .supports_sdio_new_mode = true,
435 .has_control_mask = false,
436 .can_dump_fw = false,
437 .can_auto_tdls = true,
438 .can_ext_scan = true,
439};
440
441static const struct mwifiex_sdio_device mwifiex_sdio_sd8987 = {
442 .firmware = SD8987_DEFAULT_FW_NAME,
443 .reg = &mwifiex_reg_sd8987,
444 .max_ports = 32,
445 .mp_agg_pkt_limit = 16,
446 .tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_2K,
447 .mp_tx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_MAX,
448 .mp_rx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_MAX,
449 .supports_sdio_new_mode = true,
450 .has_control_mask = false,
451 .can_dump_fw = true,
452 .fw_dump_enh = true,
453 .can_auto_tdls = true,
454 .can_ext_scan = true,
455};
456
457static const struct mwifiex_sdio_device mwifiex_sdio_sd8801 = {
458 .firmware = SD8801_DEFAULT_FW_NAME,
459 .reg = &mwifiex_reg_sd87xx,
460 .max_ports = 16,
461 .mp_agg_pkt_limit = 8,
462 .supports_sdio_new_mode = false,
463 .has_control_mask = true,
464 .tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_2K,
465 .mp_tx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_16K,
466 .mp_rx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_16K,
467 .can_dump_fw = false,
468 .can_auto_tdls = false,
469 .can_ext_scan = true,
470};
471
472static struct memory_type_mapping generic_mem_type_map[] = {
473 {"DUMP", NULL, 0, 0xDD},
474};
475
476static struct memory_type_mapping mem_type_mapping_tbl[] = {
477 {"ITCM", NULL, 0, 0xF0},
478 {"DTCM", NULL, 0, 0xF1},
479 {"SQRAM", NULL, 0, 0xF2},
480 {"APU", NULL, 0, 0xF3},
481 {"CIU", NULL, 0, 0xF4},
482 {"ICU", NULL, 0, 0xF5},
483 {"MAC", NULL, 0, 0xF6},
484 {"EXT7", NULL, 0, 0xF7},
485 {"EXT8", NULL, 0, 0xF8},
486 {"EXT9", NULL, 0, 0xF9},
487 {"EXT10", NULL, 0, 0xFA},
488 {"EXT11", NULL, 0, 0xFB},
489 {"EXT12", NULL, 0, 0xFC},
490 {"EXT13", NULL, 0, 0xFD},
491 {"EXTLAST", NULL, 0, 0xFE},
492};
493
494static const struct of_device_id mwifiex_sdio_of_match_table[] = {
495 { .compatible = "marvell,sd8897" },
496 { .compatible = "marvell,sd8997" },
497 { }
498};
499
500
501
502
503
504
505static int mwifiex_sdio_probe_of(struct device *dev)
506{
507 if (!of_match_node(mwifiex_sdio_of_match_table, dev->of_node)) {
508 dev_err(dev, "required compatible string missing\n");
509 return -EINVAL;
510 }
511
512 return 0;
513}
514
515
516
517
518
519
520
521
522
523static int
524mwifiex_sdio_probe(struct sdio_func *func, const struct sdio_device_id *id)
525{
526 int ret;
527 struct sdio_mmc_card *card = NULL;
528
529 pr_debug("info: vendor=0x%4.04X device=0x%4.04X class=%d function=%d\n",
530 func->vendor, func->device, func->class, func->num);
531
532 card = devm_kzalloc(&func->dev, sizeof(*card), GFP_KERNEL);
533 if (!card)
534 return -ENOMEM;
535
536 init_completion(&card->fw_done);
537
538 card->func = func;
539
540 func->card->quirks |= MMC_QUIRK_BLKSZ_FOR_BYTE_MODE;
541
542 if (id->driver_data) {
543 struct mwifiex_sdio_device *data = (void *)id->driver_data;
544
545 card->firmware = data->firmware;
546 card->firmware_sdiouart = data->firmware_sdiouart;
547 card->reg = data->reg;
548 card->max_ports = data->max_ports;
549 card->mp_agg_pkt_limit = data->mp_agg_pkt_limit;
550 card->supports_sdio_new_mode = data->supports_sdio_new_mode;
551 card->has_control_mask = data->has_control_mask;
552 card->tx_buf_size = data->tx_buf_size;
553 card->mp_tx_agg_buf_size = data->mp_tx_agg_buf_size;
554 card->mp_rx_agg_buf_size = data->mp_rx_agg_buf_size;
555 card->can_dump_fw = data->can_dump_fw;
556 card->fw_dump_enh = data->fw_dump_enh;
557 card->can_auto_tdls = data->can_auto_tdls;
558 card->can_ext_scan = data->can_ext_scan;
559 INIT_WORK(&card->work, mwifiex_sdio_work);
560 }
561
562 sdio_claim_host(func);
563 ret = sdio_enable_func(func);
564 sdio_release_host(func);
565
566 if (ret) {
567 dev_err(&func->dev, "failed to enable function\n");
568 return ret;
569 }
570
571
572 if (func->dev.of_node) {
573 ret = mwifiex_sdio_probe_of(&func->dev);
574 if (ret)
575 goto err_disable;
576 }
577
578 ret = mwifiex_add_card(card, &card->fw_done, &sdio_ops,
579 MWIFIEX_SDIO, &func->dev);
580 if (ret) {
581 dev_err(&func->dev, "add card failed\n");
582 goto err_disable;
583 }
584
585 return 0;
586
587err_disable:
588 sdio_claim_host(func);
589 sdio_disable_func(func);
590 sdio_release_host(func);
591
592 return ret;
593}
594
595
596
597
598
599
600
601
602
603
604
605static int mwifiex_sdio_resume(struct device *dev)
606{
607 struct sdio_func *func = dev_to_sdio_func(dev);
608 struct sdio_mmc_card *card;
609 struct mwifiex_adapter *adapter;
610
611 card = sdio_get_drvdata(func);
612 if (!card || !card->adapter) {
613 dev_err(dev, "resume: invalid card or adapter\n");
614 return 0;
615 }
616
617 adapter = card->adapter;
618
619 if (!test_bit(MWIFIEX_IS_SUSPENDED, &adapter->work_flags)) {
620 mwifiex_dbg(adapter, WARN,
621 "device already resumed\n");
622 return 0;
623 }
624
625 clear_bit(MWIFIEX_IS_SUSPENDED, &adapter->work_flags);
626
627
628 mwifiex_cancel_hs(mwifiex_get_priv(adapter, MWIFIEX_BSS_ROLE_STA),
629 MWIFIEX_SYNC_CMD);
630
631 mwifiex_disable_wake(adapter);
632
633 return 0;
634}
635
636
637static int
638mwifiex_write_reg_locked(struct sdio_func *func, u32 reg, u8 data)
639{
640 int ret = -1;
641
642 sdio_writeb(func, data, reg, &ret);
643 return ret;
644}
645
646
647
648static int
649mwifiex_write_reg(struct mwifiex_adapter *adapter, u32 reg, u8 data)
650{
651 struct sdio_mmc_card *card = adapter->card;
652 int ret;
653
654 sdio_claim_host(card->func);
655 ret = mwifiex_write_reg_locked(card->func, reg, data);
656 sdio_release_host(card->func);
657
658 return ret;
659}
660
661
662
663static int
664mwifiex_read_reg(struct mwifiex_adapter *adapter, u32 reg, u8 *data)
665{
666 struct sdio_mmc_card *card = adapter->card;
667 int ret = -1;
668 u8 val;
669
670 sdio_claim_host(card->func);
671 val = sdio_readb(card->func, reg, &ret);
672 sdio_release_host(card->func);
673
674 *data = val;
675
676 return ret;
677}
678
679
680
681
682
683static int
684mwifiex_write_data_sync(struct mwifiex_adapter *adapter,
685 u8 *buffer, u32 pkt_len, u32 port)
686{
687 struct sdio_mmc_card *card = adapter->card;
688 int ret;
689 u8 blk_mode =
690 (port & MWIFIEX_SDIO_BYTE_MODE_MASK) ? BYTE_MODE : BLOCK_MODE;
691 u32 blk_size = (blk_mode == BLOCK_MODE) ? MWIFIEX_SDIO_BLOCK_SIZE : 1;
692 u32 blk_cnt =
693 (blk_mode ==
694 BLOCK_MODE) ? (pkt_len /
695 MWIFIEX_SDIO_BLOCK_SIZE) : pkt_len;
696 u32 ioport = (port & MWIFIEX_SDIO_IO_PORT_MASK);
697
698 if (test_bit(MWIFIEX_IS_SUSPENDED, &adapter->work_flags)) {
699 mwifiex_dbg(adapter, ERROR,
700 "%s: not allowed while suspended\n", __func__);
701 return -1;
702 }
703
704 sdio_claim_host(card->func);
705
706 ret = sdio_writesb(card->func, ioport, buffer, blk_cnt * blk_size);
707
708 sdio_release_host(card->func);
709
710 return ret;
711}
712
713
714
715static int mwifiex_read_data_sync(struct mwifiex_adapter *adapter, u8 *buffer,
716 u32 len, u32 port, u8 claim)
717{
718 struct sdio_mmc_card *card = adapter->card;
719 int ret;
720 u8 blk_mode = (port & MWIFIEX_SDIO_BYTE_MODE_MASK) ? BYTE_MODE
721 : BLOCK_MODE;
722 u32 blk_size = (blk_mode == BLOCK_MODE) ? MWIFIEX_SDIO_BLOCK_SIZE : 1;
723 u32 blk_cnt = (blk_mode == BLOCK_MODE) ? (len / MWIFIEX_SDIO_BLOCK_SIZE)
724 : len;
725 u32 ioport = (port & MWIFIEX_SDIO_IO_PORT_MASK);
726
727 if (claim)
728 sdio_claim_host(card->func);
729
730 ret = sdio_readsb(card->func, buffer, ioport, blk_cnt * blk_size);
731
732 if (claim)
733 sdio_release_host(card->func);
734
735 return ret;
736}
737
738
739
740static int
741mwifiex_sdio_read_fw_status(struct mwifiex_adapter *adapter, u16 *dat)
742{
743 struct sdio_mmc_card *card = adapter->card;
744 const struct mwifiex_sdio_card_reg *reg = card->reg;
745 u8 fws0, fws1;
746
747 if (mwifiex_read_reg(adapter, reg->status_reg_0, &fws0))
748 return -1;
749
750 if (mwifiex_read_reg(adapter, reg->status_reg_1, &fws1))
751 return -1;
752
753 *dat = (u16)((fws1 << 8) | fws0);
754 return 0;
755}
756
757
758
759static int mwifiex_check_fw_status(struct mwifiex_adapter *adapter,
760 u32 poll_num)
761{
762 int ret = 0;
763 u16 firmware_stat;
764 u32 tries;
765
766 for (tries = 0; tries < poll_num; tries++) {
767 ret = mwifiex_sdio_read_fw_status(adapter, &firmware_stat);
768 if (ret)
769 continue;
770 if (firmware_stat == FIRMWARE_READY_SDIO) {
771 ret = 0;
772 break;
773 }
774
775 msleep(100);
776 ret = -1;
777 }
778
779 return ret;
780}
781
782
783
784static int mwifiex_check_winner_status(struct mwifiex_adapter *adapter)
785{
786 int ret = 0;
787 u8 winner = 0;
788 struct sdio_mmc_card *card = adapter->card;
789
790 if (mwifiex_read_reg(adapter, card->reg->status_reg_0, &winner))
791 return -1;
792
793 if (winner)
794 adapter->winner = 0;
795 else
796 adapter->winner = 1;
797
798 return ret;
799}
800
801
802
803
804
805
806static void
807mwifiex_sdio_remove(struct sdio_func *func)
808{
809 struct sdio_mmc_card *card;
810 struct mwifiex_adapter *adapter;
811 struct mwifiex_private *priv;
812 int ret = 0;
813 u16 firmware_stat;
814
815 card = sdio_get_drvdata(func);
816 if (!card)
817 return;
818
819 wait_for_completion(&card->fw_done);
820
821 adapter = card->adapter;
822 if (!adapter || !adapter->priv_num)
823 return;
824
825 mwifiex_dbg(adapter, INFO, "info: SDIO func num=%d\n", func->num);
826
827 ret = mwifiex_sdio_read_fw_status(adapter, &firmware_stat);
828 if (!ret && firmware_stat == FIRMWARE_READY_SDIO &&
829 !adapter->mfg_mode) {
830 mwifiex_deauthenticate_all(adapter);
831
832 priv = mwifiex_get_priv(adapter, MWIFIEX_BSS_ROLE_ANY);
833 mwifiex_disable_auto_ds(priv);
834 mwifiex_init_shutdown_fw(priv, MWIFIEX_FUNC_SHUTDOWN);
835 }
836
837 mwifiex_remove_card(adapter);
838}
839
840
841
842
843
844
845
846
847
848
849
850static int mwifiex_sdio_suspend(struct device *dev)
851{
852 struct sdio_func *func = dev_to_sdio_func(dev);
853 struct sdio_mmc_card *card;
854 struct mwifiex_adapter *adapter;
855 mmc_pm_flag_t pm_flag = 0;
856 int ret = 0;
857
858 pm_flag = sdio_get_host_pm_caps(func);
859 pr_debug("cmd: %s: suspend: PM flag = 0x%x\n",
860 sdio_func_id(func), pm_flag);
861 if (!(pm_flag & MMC_PM_KEEP_POWER)) {
862 dev_err(dev, "%s: cannot remain alive while host is"
863 " suspended\n", sdio_func_id(func));
864 return -ENOSYS;
865 }
866
867 card = sdio_get_drvdata(func);
868 if (!card) {
869 dev_err(dev, "suspend: invalid card\n");
870 return 0;
871 }
872
873
874 wait_for_completion(&card->fw_done);
875
876 adapter = card->adapter;
877 if (!adapter) {
878 dev_err(dev, "adapter is not valid\n");
879 return 0;
880 }
881
882 if (!adapter->is_up)
883 return -EBUSY;
884
885 mwifiex_enable_wake(adapter);
886
887
888 if (!mwifiex_enable_hs(adapter)) {
889 mwifiex_dbg(adapter, ERROR,
890 "cmd: failed to suspend\n");
891 clear_bit(MWIFIEX_IS_HS_ENABLING, &adapter->work_flags);
892 mwifiex_disable_wake(adapter);
893 return -EFAULT;
894 }
895
896 mwifiex_dbg(adapter, INFO,
897 "cmd: suspend with MMC_PM_KEEP_POWER\n");
898 ret = sdio_set_host_pm_flags(func, MMC_PM_KEEP_POWER);
899
900
901 set_bit(MWIFIEX_IS_SUSPENDED, &adapter->work_flags);
902 clear_bit(MWIFIEX_IS_HS_ENABLING, &adapter->work_flags);
903
904 return ret;
905}
906
907static void mwifiex_sdio_coredump(struct device *dev)
908{
909 struct sdio_func *func = dev_to_sdio_func(dev);
910 struct sdio_mmc_card *card;
911
912 card = sdio_get_drvdata(func);
913 if (!test_and_set_bit(MWIFIEX_IFACE_WORK_DEVICE_DUMP,
914 &card->work_flags))
915 schedule_work(&card->work);
916}
917
918
919static const struct sdio_device_id mwifiex_ids[] = {
920 {SDIO_DEVICE(SDIO_VENDOR_ID_MARVELL, SDIO_DEVICE_ID_MARVELL_8786_WLAN),
921 .driver_data = (unsigned long) &mwifiex_sdio_sd8786},
922 {SDIO_DEVICE(SDIO_VENDOR_ID_MARVELL, SDIO_DEVICE_ID_MARVELL_8787_WLAN),
923 .driver_data = (unsigned long) &mwifiex_sdio_sd8787},
924 {SDIO_DEVICE(SDIO_VENDOR_ID_MARVELL, SDIO_DEVICE_ID_MARVELL_8797_WLAN),
925 .driver_data = (unsigned long) &mwifiex_sdio_sd8797},
926 {SDIO_DEVICE(SDIO_VENDOR_ID_MARVELL, SDIO_DEVICE_ID_MARVELL_8897_WLAN),
927 .driver_data = (unsigned long) &mwifiex_sdio_sd8897},
928 {SDIO_DEVICE(SDIO_VENDOR_ID_MARVELL, SDIO_DEVICE_ID_MARVELL_8887_WLAN),
929 .driver_data = (unsigned long)&mwifiex_sdio_sd8887},
930 {SDIO_DEVICE(SDIO_VENDOR_ID_MARVELL, SDIO_DEVICE_ID_MARVELL_8801_WLAN),
931 .driver_data = (unsigned long)&mwifiex_sdio_sd8801},
932 {SDIO_DEVICE(SDIO_VENDOR_ID_MARVELL, SDIO_DEVICE_ID_MARVELL_8977_WLAN),
933 .driver_data = (unsigned long)&mwifiex_sdio_sd8977},
934 {SDIO_DEVICE(SDIO_VENDOR_ID_MARVELL, SDIO_DEVICE_ID_MARVELL_8987_WLAN),
935 .driver_data = (unsigned long)&mwifiex_sdio_sd8987},
936 {SDIO_DEVICE(SDIO_VENDOR_ID_MARVELL, SDIO_DEVICE_ID_MARVELL_8997_WLAN),
937 .driver_data = (unsigned long)&mwifiex_sdio_sd8997},
938 {},
939};
940
941MODULE_DEVICE_TABLE(sdio, mwifiex_ids);
942
943static const struct dev_pm_ops mwifiex_sdio_pm_ops = {
944 .suspend = mwifiex_sdio_suspend,
945 .resume = mwifiex_sdio_resume,
946};
947
948static struct sdio_driver mwifiex_sdio = {
949 .name = "mwifiex_sdio",
950 .id_table = mwifiex_ids,
951 .probe = mwifiex_sdio_probe,
952 .remove = mwifiex_sdio_remove,
953 .drv = {
954 .owner = THIS_MODULE,
955 .coredump = mwifiex_sdio_coredump,
956 .pm = &mwifiex_sdio_pm_ops,
957 }
958};
959
960
961
962
963
964
965
966static int mwifiex_pm_wakeup_card(struct mwifiex_adapter *adapter)
967{
968 mwifiex_dbg(adapter, EVENT,
969 "event: wakeup device...\n");
970
971 return mwifiex_write_reg(adapter, CONFIGURATION_REG, HOST_POWER_UP);
972}
973
974
975
976
977
978
979static int mwifiex_pm_wakeup_card_complete(struct mwifiex_adapter *adapter)
980{
981 mwifiex_dbg(adapter, EVENT,
982 "cmd: wakeup device completed\n");
983
984 return mwifiex_write_reg(adapter, CONFIGURATION_REG, 0);
985}
986
987static int mwifiex_sdio_dnld_fw(struct mwifiex_adapter *adapter,
988 struct mwifiex_fw_image *fw)
989{
990 struct sdio_mmc_card *card = adapter->card;
991 int ret;
992
993 sdio_claim_host(card->func);
994 ret = mwifiex_dnld_fw(adapter, fw);
995 sdio_release_host(card->func);
996
997 return ret;
998}
999
1000
1001
1002
1003
1004static int mwifiex_init_sdio_new_mode(struct mwifiex_adapter *adapter)
1005{
1006 u8 reg;
1007 struct sdio_mmc_card *card = adapter->card;
1008
1009 adapter->ioport = MEM_PORT;
1010
1011
1012 if (mwifiex_read_reg(adapter, card->reg->card_cfg_2_1_reg, ®))
1013 return -1;
1014 if (mwifiex_write_reg(adapter, card->reg->card_cfg_2_1_reg,
1015 reg | CMD53_NEW_MODE))
1016 return -1;
1017
1018
1019 if (mwifiex_read_reg(adapter, card->reg->cmd_cfg_0, ®))
1020 return -1;
1021 if (mwifiex_write_reg(adapter, card->reg->cmd_cfg_0,
1022 reg | CMD_PORT_RD_LEN_EN))
1023 return -1;
1024
1025
1026
1027
1028 if (mwifiex_read_reg(adapter, card->reg->cmd_cfg_1, ®))
1029 return -1;
1030 if (mwifiex_write_reg(adapter, card->reg->cmd_cfg_1,
1031 reg | CMD_PORT_AUTO_EN))
1032 return -1;
1033
1034 return 0;
1035}
1036
1037
1038
1039
1040
1041
1042
1043
1044static int mwifiex_init_sdio_ioport(struct mwifiex_adapter *adapter)
1045{
1046 u8 reg;
1047 struct sdio_mmc_card *card = adapter->card;
1048
1049 adapter->ioport = 0;
1050
1051 if (card->supports_sdio_new_mode) {
1052 if (mwifiex_init_sdio_new_mode(adapter))
1053 return -1;
1054 goto cont;
1055 }
1056
1057
1058 if (!mwifiex_read_reg(adapter, card->reg->io_port_0_reg, ®))
1059 adapter->ioport |= (reg & 0xff);
1060 else
1061 return -1;
1062
1063 if (!mwifiex_read_reg(adapter, card->reg->io_port_1_reg, ®))
1064 adapter->ioport |= ((reg & 0xff) << 8);
1065 else
1066 return -1;
1067
1068 if (!mwifiex_read_reg(adapter, card->reg->io_port_2_reg, ®))
1069 adapter->ioport |= ((reg & 0xff) << 16);
1070 else
1071 return -1;
1072cont:
1073 mwifiex_dbg(adapter, INFO,
1074 "info: SDIO FUNC1 IO port: %#x\n", adapter->ioport);
1075
1076
1077 if (!mwifiex_read_reg(adapter, card->reg->host_int_rsr_reg, ®))
1078 mwifiex_write_reg(adapter, card->reg->host_int_rsr_reg,
1079 reg | card->reg->sdio_int_mask);
1080 else
1081 return -1;
1082
1083
1084 if (!mwifiex_read_reg(adapter, card->reg->card_misc_cfg_reg, ®))
1085 mwifiex_write_reg(adapter, card->reg->card_misc_cfg_reg,
1086 reg | AUTO_RE_ENABLE_INT);
1087 else
1088 return -1;
1089
1090 return 0;
1091}
1092
1093
1094
1095
1096static int mwifiex_write_data_to_card(struct mwifiex_adapter *adapter,
1097 u8 *payload, u32 pkt_len, u32 port)
1098{
1099 u32 i = 0;
1100 int ret;
1101
1102 do {
1103 ret = mwifiex_write_data_sync(adapter, payload, pkt_len, port);
1104 if (ret) {
1105 i++;
1106 mwifiex_dbg(adapter, ERROR,
1107 "host_to_card, write iomem\t"
1108 "(%d) failed: %d\n", i, ret);
1109 if (mwifiex_write_reg(adapter, CONFIGURATION_REG, 0x04))
1110 mwifiex_dbg(adapter, ERROR,
1111 "write CFG reg failed\n");
1112
1113 ret = -1;
1114 if (i > MAX_WRITE_IOMEM_RETRY)
1115 return ret;
1116 }
1117 } while (ret == -1);
1118
1119 return ret;
1120}
1121
1122
1123
1124
1125
1126
1127
1128
1129
1130static int mwifiex_get_rd_port(struct mwifiex_adapter *adapter, u8 *port)
1131{
1132 struct sdio_mmc_card *card = adapter->card;
1133 const struct mwifiex_sdio_card_reg *reg = card->reg;
1134 u32 rd_bitmap = card->mp_rd_bitmap;
1135
1136 mwifiex_dbg(adapter, DATA,
1137 "data: mp_rd_bitmap=0x%08x\n", rd_bitmap);
1138
1139 if (card->supports_sdio_new_mode) {
1140 if (!(rd_bitmap & reg->data_port_mask))
1141 return -1;
1142 } else {
1143 if (!(rd_bitmap & (CTRL_PORT_MASK | reg->data_port_mask)))
1144 return -1;
1145 }
1146
1147 if ((card->has_control_mask) &&
1148 (card->mp_rd_bitmap & CTRL_PORT_MASK)) {
1149 card->mp_rd_bitmap &= (u32) (~CTRL_PORT_MASK);
1150 *port = CTRL_PORT;
1151 mwifiex_dbg(adapter, DATA,
1152 "data: port=%d mp_rd_bitmap=0x%08x\n",
1153 *port, card->mp_rd_bitmap);
1154 return 0;
1155 }
1156
1157 if (!(card->mp_rd_bitmap & (1 << card->curr_rd_port)))
1158 return -1;
1159
1160
1161 card->mp_rd_bitmap &= (u32)(~(1 << card->curr_rd_port));
1162 *port = card->curr_rd_port;
1163
1164 if (++card->curr_rd_port == card->max_ports)
1165 card->curr_rd_port = reg->start_rd_port;
1166
1167 mwifiex_dbg(adapter, DATA,
1168 "data: port=%d mp_rd_bitmap=0x%08x -> 0x%08x\n",
1169 *port, rd_bitmap, card->mp_rd_bitmap);
1170
1171 return 0;
1172}
1173
1174
1175
1176
1177
1178
1179
1180
1181static int mwifiex_get_wr_port_data(struct mwifiex_adapter *adapter, u32 *port)
1182{
1183 struct sdio_mmc_card *card = adapter->card;
1184 const struct mwifiex_sdio_card_reg *reg = card->reg;
1185 u32 wr_bitmap = card->mp_wr_bitmap;
1186
1187 mwifiex_dbg(adapter, DATA,
1188 "data: mp_wr_bitmap=0x%08x\n", wr_bitmap);
1189
1190 if (!(wr_bitmap & card->mp_data_port_mask)) {
1191 adapter->data_sent = true;
1192 return -EBUSY;
1193 }
1194
1195 if (card->mp_wr_bitmap & (1 << card->curr_wr_port)) {
1196 card->mp_wr_bitmap &= (u32) (~(1 << card->curr_wr_port));
1197 *port = card->curr_wr_port;
1198 if (++card->curr_wr_port == card->mp_end_port)
1199 card->curr_wr_port = reg->start_wr_port;
1200 } else {
1201 adapter->data_sent = true;
1202 return -EBUSY;
1203 }
1204
1205 if ((card->has_control_mask) && (*port == CTRL_PORT)) {
1206 mwifiex_dbg(adapter, ERROR,
1207 "invalid data port=%d cur port=%d mp_wr_bitmap=0x%08x -> 0x%08x\n",
1208 *port, card->curr_wr_port, wr_bitmap,
1209 card->mp_wr_bitmap);
1210 return -1;
1211 }
1212
1213 mwifiex_dbg(adapter, DATA,
1214 "data: port=%d mp_wr_bitmap=0x%08x -> 0x%08x\n",
1215 *port, wr_bitmap, card->mp_wr_bitmap);
1216
1217 return 0;
1218}
1219
1220
1221
1222
1223static int
1224mwifiex_sdio_poll_card_status(struct mwifiex_adapter *adapter, u8 bits)
1225{
1226 struct sdio_mmc_card *card = adapter->card;
1227 u32 tries;
1228 u8 cs;
1229
1230 for (tries = 0; tries < MAX_POLL_TRIES; tries++) {
1231 if (mwifiex_read_reg(adapter, card->reg->poll_reg, &cs))
1232 break;
1233 else if ((cs & bits) == bits)
1234 return 0;
1235
1236 usleep_range(10, 20);
1237 }
1238
1239 mwifiex_dbg(adapter, ERROR,
1240 "poll card status failed, tries = %d\n", tries);
1241
1242 return -1;
1243}
1244
1245
1246
1247
1248
1249
1250
1251static void mwifiex_sdio_disable_host_int(struct mwifiex_adapter *adapter)
1252{
1253 struct sdio_mmc_card *card = adapter->card;
1254 struct sdio_func *func = card->func;
1255
1256 sdio_claim_host(func);
1257 mwifiex_write_reg_locked(func, card->reg->host_int_mask_reg, 0);
1258 sdio_release_irq(func);
1259 sdio_release_host(func);
1260}
1261
1262
1263
1264
1265static void mwifiex_interrupt_status(struct mwifiex_adapter *adapter)
1266{
1267 struct sdio_mmc_card *card = adapter->card;
1268 u8 sdio_ireg;
1269 unsigned long flags;
1270
1271 if (mwifiex_read_data_sync(adapter, card->mp_regs,
1272 card->reg->max_mp_regs,
1273 REG_PORT | MWIFIEX_SDIO_BYTE_MODE_MASK, 0)) {
1274 mwifiex_dbg(adapter, ERROR, "read mp_regs failed\n");
1275 return;
1276 }
1277
1278 sdio_ireg = card->mp_regs[card->reg->host_int_status_reg];
1279 if (sdio_ireg) {
1280
1281
1282
1283
1284
1285
1286
1287 mwifiex_dbg(adapter, INTR,
1288 "int: sdio_ireg = %#x\n", sdio_ireg);
1289 spin_lock_irqsave(&adapter->int_lock, flags);
1290 adapter->int_status |= sdio_ireg;
1291 spin_unlock_irqrestore(&adapter->int_lock, flags);
1292 }
1293}
1294
1295
1296
1297
1298
1299
1300
1301static void
1302mwifiex_sdio_interrupt(struct sdio_func *func)
1303{
1304 struct mwifiex_adapter *adapter;
1305 struct sdio_mmc_card *card;
1306
1307 card = sdio_get_drvdata(func);
1308 if (!card || !card->adapter) {
1309 pr_err("int: func=%p card=%p adapter=%p\n",
1310 func, card, card ? card->adapter : NULL);
1311 return;
1312 }
1313 adapter = card->adapter;
1314
1315 if (!adapter->pps_uapsd_mode && adapter->ps_state == PS_STATE_SLEEP)
1316 adapter->ps_state = PS_STATE_AWAKE;
1317
1318 mwifiex_interrupt_status(adapter);
1319 mwifiex_main_process(adapter);
1320}
1321
1322
1323
1324
1325
1326
1327
1328static int mwifiex_sdio_enable_host_int(struct mwifiex_adapter *adapter)
1329{
1330 struct sdio_mmc_card *card = adapter->card;
1331 struct sdio_func *func = card->func;
1332 int ret;
1333
1334 sdio_claim_host(func);
1335
1336
1337 ret = sdio_claim_irq(func, mwifiex_sdio_interrupt);
1338 if (ret) {
1339 mwifiex_dbg(adapter, ERROR,
1340 "claim irq failed: ret=%d\n", ret);
1341 goto out;
1342 }
1343
1344
1345 ret = mwifiex_write_reg_locked(func, card->reg->host_int_mask_reg,
1346 card->reg->host_int_enable);
1347 if (ret) {
1348 mwifiex_dbg(adapter, ERROR,
1349 "enable host interrupt failed\n");
1350 sdio_release_irq(func);
1351 }
1352
1353out:
1354 sdio_release_host(func);
1355 return ret;
1356}
1357
1358
1359
1360
1361static int mwifiex_sdio_card_to_host(struct mwifiex_adapter *adapter,
1362 u32 *type, u8 *buffer,
1363 u32 npayload, u32 ioport)
1364{
1365 int ret;
1366 u32 nb;
1367
1368 if (!buffer) {
1369 mwifiex_dbg(adapter, ERROR,
1370 "%s: buffer is NULL\n", __func__);
1371 return -1;
1372 }
1373
1374 ret = mwifiex_read_data_sync(adapter, buffer, npayload, ioport, 1);
1375
1376 if (ret) {
1377 mwifiex_dbg(adapter, ERROR,
1378 "%s: read iomem failed: %d\n", __func__,
1379 ret);
1380 return -1;
1381 }
1382
1383 nb = get_unaligned_le16((buffer));
1384 if (nb > npayload) {
1385 mwifiex_dbg(adapter, ERROR,
1386 "%s: invalid packet, nb=%d npayload=%d\n",
1387 __func__, nb, npayload);
1388 return -1;
1389 }
1390
1391 *type = get_unaligned_le16((buffer + 2));
1392
1393 return ret;
1394}
1395
1396
1397
1398
1399
1400
1401
1402
1403static int mwifiex_prog_fw_w_helper(struct mwifiex_adapter *adapter,
1404 struct mwifiex_fw_image *fw)
1405{
1406 struct sdio_mmc_card *card = adapter->card;
1407 const struct mwifiex_sdio_card_reg *reg = card->reg;
1408 int ret;
1409 u8 *firmware = fw->fw_buf;
1410 u32 firmware_len = fw->fw_len;
1411 u32 offset = 0;
1412 u8 base0, base1;
1413 u8 *fwbuf;
1414 u16 len = 0;
1415 u32 txlen, tx_blocks = 0, tries;
1416 u32 i = 0;
1417
1418 if (!firmware_len) {
1419 mwifiex_dbg(adapter, ERROR,
1420 "firmware image not found! Terminating download\n");
1421 return -1;
1422 }
1423
1424 mwifiex_dbg(adapter, INFO,
1425 "info: downloading FW image (%d bytes)\n",
1426 firmware_len);
1427
1428
1429 fwbuf = kzalloc(MWIFIEX_UPLD_SIZE, GFP_KERNEL);
1430 if (!fwbuf)
1431 return -ENOMEM;
1432
1433 sdio_claim_host(card->func);
1434
1435
1436 do {
1437
1438
1439 ret = mwifiex_sdio_poll_card_status(adapter, CARD_IO_READY |
1440 DN_LD_CARD_RDY);
1441 if (ret) {
1442 mwifiex_dbg(adapter, ERROR,
1443 "FW download with helper:\t"
1444 "poll status timeout @ %d\n", offset);
1445 goto done;
1446 }
1447
1448
1449 if (offset >= firmware_len)
1450 break;
1451
1452 for (tries = 0; tries < MAX_POLL_TRIES; tries++) {
1453 ret = mwifiex_read_reg(adapter, reg->base_0_reg,
1454 &base0);
1455 if (ret) {
1456 mwifiex_dbg(adapter, ERROR,
1457 "dev BASE0 register read failed:\t"
1458 "base0=%#04X(%d). Terminating dnld\n",
1459 base0, base0);
1460 goto done;
1461 }
1462 ret = mwifiex_read_reg(adapter, reg->base_1_reg,
1463 &base1);
1464 if (ret) {
1465 mwifiex_dbg(adapter, ERROR,
1466 "dev BASE1 register read failed:\t"
1467 "base1=%#04X(%d). Terminating dnld\n",
1468 base1, base1);
1469 goto done;
1470 }
1471 len = (u16) (((base1 & 0xff) << 8) | (base0 & 0xff));
1472
1473 if (len)
1474 break;
1475
1476 usleep_range(10, 20);
1477 }
1478
1479 if (!len) {
1480 break;
1481 } else if (len > MWIFIEX_UPLD_SIZE) {
1482 mwifiex_dbg(adapter, ERROR,
1483 "FW dnld failed @ %d, invalid length %d\n",
1484 offset, len);
1485 ret = -1;
1486 goto done;
1487 }
1488
1489 txlen = len;
1490
1491 if (len & BIT(0)) {
1492 i++;
1493 if (i > MAX_WRITE_IOMEM_RETRY) {
1494 mwifiex_dbg(adapter, ERROR,
1495 "FW dnld failed @ %d, over max retry\n",
1496 offset);
1497 ret = -1;
1498 goto done;
1499 }
1500 mwifiex_dbg(adapter, ERROR,
1501 "CRC indicated by the helper:\t"
1502 "len = 0x%04X, txlen = %d\n", len, txlen);
1503 len &= ~BIT(0);
1504
1505 txlen = 0;
1506 } else {
1507 i = 0;
1508
1509
1510
1511 if (firmware_len - offset < txlen)
1512 txlen = firmware_len - offset;
1513
1514 tx_blocks = (txlen + MWIFIEX_SDIO_BLOCK_SIZE - 1)
1515 / MWIFIEX_SDIO_BLOCK_SIZE;
1516
1517
1518 memmove(fwbuf, &firmware[offset], txlen);
1519 }
1520
1521 ret = mwifiex_write_data_sync(adapter, fwbuf, tx_blocks *
1522 MWIFIEX_SDIO_BLOCK_SIZE,
1523 adapter->ioport);
1524 if (ret) {
1525 mwifiex_dbg(adapter, ERROR,
1526 "FW download, write iomem (%d) failed @ %d\n",
1527 i, offset);
1528 if (mwifiex_write_reg(adapter, CONFIGURATION_REG, 0x04))
1529 mwifiex_dbg(adapter, ERROR,
1530 "write CFG reg failed\n");
1531
1532 ret = -1;
1533 goto done;
1534 }
1535
1536 offset += txlen;
1537 } while (true);
1538
1539 mwifiex_dbg(adapter, MSG,
1540 "info: FW download over, size %d bytes\n", offset);
1541
1542 ret = 0;
1543done:
1544 sdio_release_host(card->func);
1545 kfree(fwbuf);
1546 return ret;
1547}
1548
1549
1550
1551
1552
1553
1554
1555static void mwifiex_deaggr_sdio_pkt(struct mwifiex_adapter *adapter,
1556 struct sk_buff *skb)
1557{
1558 u32 total_pkt_len, pkt_len;
1559 struct sk_buff *skb_deaggr;
1560 u16 blk_size;
1561 u8 blk_num;
1562 u8 *data;
1563
1564 data = skb->data;
1565 total_pkt_len = skb->len;
1566
1567 while (total_pkt_len >= (SDIO_HEADER_OFFSET + adapter->intf_hdr_len)) {
1568 if (total_pkt_len < adapter->sdio_rx_block_size)
1569 break;
1570 blk_num = *(data + BLOCK_NUMBER_OFFSET);
1571 blk_size = adapter->sdio_rx_block_size * blk_num;
1572 if (blk_size > total_pkt_len) {
1573 mwifiex_dbg(adapter, ERROR,
1574 "%s: error in blk_size,\t"
1575 "blk_num=%d, blk_size=%d, total_pkt_len=%d\n",
1576 __func__, blk_num, blk_size, total_pkt_len);
1577 break;
1578 }
1579 pkt_len = get_unaligned_le16((data +
1580 SDIO_HEADER_OFFSET));
1581 if ((pkt_len + SDIO_HEADER_OFFSET) > blk_size) {
1582 mwifiex_dbg(adapter, ERROR,
1583 "%s: error in pkt_len,\t"
1584 "pkt_len=%d, blk_size=%d\n",
1585 __func__, pkt_len, blk_size);
1586 break;
1587 }
1588
1589 skb_deaggr = mwifiex_alloc_dma_align_buf(pkt_len, GFP_KERNEL);
1590 if (!skb_deaggr)
1591 break;
1592 skb_put(skb_deaggr, pkt_len);
1593 memcpy(skb_deaggr->data, data + SDIO_HEADER_OFFSET, pkt_len);
1594 skb_pull(skb_deaggr, adapter->intf_hdr_len);
1595
1596 mwifiex_handle_rx_packet(adapter, skb_deaggr);
1597 data += blk_size;
1598 total_pkt_len -= blk_size;
1599 }
1600}
1601
1602
1603
1604
1605
1606
1607
1608
1609static int mwifiex_decode_rx_packet(struct mwifiex_adapter *adapter,
1610 struct sk_buff *skb, u32 upld_typ)
1611{
1612 u8 *cmd_buf;
1613 u16 pkt_len;
1614 struct mwifiex_rxinfo *rx_info;
1615
1616 pkt_len = get_unaligned_le16(skb->data);
1617
1618 if (upld_typ != MWIFIEX_TYPE_AGGR_DATA) {
1619 skb_trim(skb, pkt_len);
1620 skb_pull(skb, adapter->intf_hdr_len);
1621 }
1622
1623 switch (upld_typ) {
1624 case MWIFIEX_TYPE_AGGR_DATA:
1625 mwifiex_dbg(adapter, INFO,
1626 "info: --- Rx: Aggr Data packet ---\n");
1627 rx_info = MWIFIEX_SKB_RXCB(skb);
1628 rx_info->buf_type = MWIFIEX_TYPE_AGGR_DATA;
1629 if (adapter->rx_work_enabled) {
1630 skb_queue_tail(&adapter->rx_data_q, skb);
1631 atomic_inc(&adapter->rx_pending);
1632 adapter->data_received = true;
1633 } else {
1634 mwifiex_deaggr_sdio_pkt(adapter, skb);
1635 dev_kfree_skb_any(skb);
1636 }
1637 break;
1638
1639 case MWIFIEX_TYPE_DATA:
1640 mwifiex_dbg(adapter, DATA,
1641 "info: --- Rx: Data packet ---\n");
1642 if (adapter->rx_work_enabled) {
1643 skb_queue_tail(&adapter->rx_data_q, skb);
1644 adapter->data_received = true;
1645 atomic_inc(&adapter->rx_pending);
1646 } else {
1647 mwifiex_handle_rx_packet(adapter, skb);
1648 }
1649 break;
1650
1651 case MWIFIEX_TYPE_CMD:
1652 mwifiex_dbg(adapter, CMD,
1653 "info: --- Rx: Cmd Response ---\n");
1654
1655 if (!adapter->curr_cmd) {
1656 cmd_buf = adapter->upld_buf;
1657
1658 if (adapter->ps_state == PS_STATE_SLEEP_CFM)
1659 mwifiex_process_sleep_confirm_resp(adapter,
1660 skb->data,
1661 skb->len);
1662
1663 memcpy(cmd_buf, skb->data,
1664 min_t(u32, MWIFIEX_SIZE_OF_CMD_BUFFER,
1665 skb->len));
1666
1667 dev_kfree_skb_any(skb);
1668 } else {
1669 adapter->cmd_resp_received = true;
1670 adapter->curr_cmd->resp_skb = skb;
1671 }
1672 break;
1673
1674 case MWIFIEX_TYPE_EVENT:
1675 mwifiex_dbg(adapter, EVENT,
1676 "info: --- Rx: Event ---\n");
1677 adapter->event_cause = get_unaligned_le32(skb->data);
1678
1679 if ((skb->len > 0) && (skb->len < MAX_EVENT_SIZE))
1680 memcpy(adapter->event_body,
1681 skb->data + MWIFIEX_EVENT_HEADER_LEN,
1682 skb->len);
1683
1684
1685 adapter->event_received = true;
1686 adapter->event_skb = skb;
1687
1688 break;
1689
1690 default:
1691 mwifiex_dbg(adapter, ERROR,
1692 "unknown upload type %#x\n", upld_typ);
1693 dev_kfree_skb_any(skb);
1694 break;
1695 }
1696
1697 return 0;
1698}
1699
1700
1701
1702
1703
1704
1705
1706
1707
1708
1709static int mwifiex_sdio_card_to_host_mp_aggr(struct mwifiex_adapter *adapter,
1710 u16 rx_len, u8 port)
1711{
1712 struct sdio_mmc_card *card = adapter->card;
1713 s32 f_do_rx_aggr = 0;
1714 s32 f_do_rx_cur = 0;
1715 s32 f_aggr_cur = 0;
1716 s32 f_post_aggr_cur = 0;
1717 struct sk_buff *skb_deaggr;
1718 struct sk_buff *skb = NULL;
1719 u32 pkt_len, pkt_type, mport, pind;
1720 u8 *curr_ptr;
1721
1722 if ((card->has_control_mask) && (port == CTRL_PORT)) {
1723
1724 mwifiex_dbg(adapter, CMD,
1725 "info: %s: no aggregation for cmd\t"
1726 "response\n", __func__);
1727
1728 f_do_rx_cur = 1;
1729 goto rx_curr_single;
1730 }
1731
1732 if (!card->mpa_rx.enabled) {
1733 mwifiex_dbg(adapter, WARN,
1734 "info: %s: rx aggregation disabled\n",
1735 __func__);
1736
1737 f_do_rx_cur = 1;
1738 goto rx_curr_single;
1739 }
1740
1741 if ((!card->has_control_mask && (card->mp_rd_bitmap &
1742 card->reg->data_port_mask)) ||
1743 (card->has_control_mask && (card->mp_rd_bitmap &
1744 (~((u32) CTRL_PORT_MASK))))) {
1745
1746 mwifiex_dbg(adapter, INFO,
1747 "info: %s: not last packet\n", __func__);
1748
1749 if (MP_RX_AGGR_IN_PROGRESS(card)) {
1750 if (MP_RX_AGGR_BUF_HAS_ROOM(card, rx_len)) {
1751 f_aggr_cur = 1;
1752 } else {
1753
1754 f_do_rx_aggr = 1;
1755 f_post_aggr_cur = 1;
1756 }
1757 } else {
1758
1759 f_aggr_cur = 1;
1760 }
1761
1762 } else {
1763
1764 mwifiex_dbg(adapter, INFO,
1765 "info: %s: last packet\n", __func__);
1766
1767 if (MP_RX_AGGR_IN_PROGRESS(card)) {
1768 f_do_rx_aggr = 1;
1769 if (MP_RX_AGGR_BUF_HAS_ROOM(card, rx_len))
1770 f_aggr_cur = 1;
1771 else
1772
1773 f_do_rx_cur = 1;
1774 } else {
1775 f_do_rx_cur = 1;
1776 }
1777 }
1778
1779 if (f_aggr_cur) {
1780 mwifiex_dbg(adapter, INFO,
1781 "info: current packet aggregation\n");
1782
1783 mp_rx_aggr_setup(card, rx_len, port);
1784
1785 if (MP_RX_AGGR_PKT_LIMIT_REACHED(card) ||
1786 mp_rx_aggr_port_limit_reached(card)) {
1787 mwifiex_dbg(adapter, INFO,
1788 "info: %s: aggregated packet\t"
1789 "limit reached\n", __func__);
1790
1791 f_do_rx_aggr = 1;
1792 }
1793 }
1794
1795 if (f_do_rx_aggr) {
1796
1797 mwifiex_dbg(adapter, DATA,
1798 "info: do_rx_aggr: num of packets: %d\n",
1799 card->mpa_rx.pkt_cnt);
1800
1801 if (card->supports_sdio_new_mode) {
1802 int i;
1803 u32 port_count;
1804
1805 for (i = 0, port_count = 0; i < card->max_ports; i++)
1806 if (card->mpa_rx.ports & BIT(i))
1807 port_count++;
1808
1809
1810
1811
1812 port_count--;
1813 mport = (adapter->ioport | SDIO_MPA_ADDR_BASE |
1814 (port_count << 8)) + card->mpa_rx.start_port;
1815 } else {
1816 mport = (adapter->ioport | SDIO_MPA_ADDR_BASE |
1817 (card->mpa_rx.ports << 4)) +
1818 card->mpa_rx.start_port;
1819 }
1820
1821 if (card->mpa_rx.pkt_cnt == 1)
1822 mport = adapter->ioport + card->mpa_rx.start_port;
1823
1824 if (mwifiex_read_data_sync(adapter, card->mpa_rx.buf,
1825 card->mpa_rx.buf_len, mport, 1))
1826 goto error;
1827
1828 curr_ptr = card->mpa_rx.buf;
1829
1830 for (pind = 0; pind < card->mpa_rx.pkt_cnt; pind++) {
1831 u32 *len_arr = card->mpa_rx.len_arr;
1832
1833
1834 pkt_len = get_unaligned_le16(&curr_ptr[0]);
1835 pkt_type = get_unaligned_le16(&curr_ptr[2]);
1836
1837
1838 skb_deaggr = mwifiex_alloc_dma_align_buf(len_arr[pind],
1839 GFP_KERNEL);
1840 if (!skb_deaggr) {
1841 mwifiex_dbg(adapter, ERROR, "skb allocation failure\t"
1842 "drop pkt len=%d type=%d\n",
1843 pkt_len, pkt_type);
1844 curr_ptr += len_arr[pind];
1845 continue;
1846 }
1847
1848 skb_put(skb_deaggr, len_arr[pind]);
1849
1850 if ((pkt_type == MWIFIEX_TYPE_DATA ||
1851 (pkt_type == MWIFIEX_TYPE_AGGR_DATA &&
1852 adapter->sdio_rx_aggr_enable)) &&
1853 (pkt_len <= len_arr[pind])) {
1854
1855 memcpy(skb_deaggr->data, curr_ptr, pkt_len);
1856
1857 skb_trim(skb_deaggr, pkt_len);
1858
1859
1860 mwifiex_decode_rx_packet(adapter, skb_deaggr,
1861 pkt_type);
1862 } else {
1863 mwifiex_dbg(adapter, ERROR,
1864 "drop wrong aggr pkt:\t"
1865 "sdio_single_port_rx_aggr=%d\t"
1866 "type=%d len=%d max_len=%d\n",
1867 adapter->sdio_rx_aggr_enable,
1868 pkt_type, pkt_len, len_arr[pind]);
1869 dev_kfree_skb_any(skb_deaggr);
1870 }
1871 curr_ptr += len_arr[pind];
1872 }
1873 MP_RX_AGGR_BUF_RESET(card);
1874 }
1875
1876rx_curr_single:
1877 if (f_do_rx_cur) {
1878 mwifiex_dbg(adapter, INFO, "info: RX: port: %d, rx_len: %d\n",
1879 port, rx_len);
1880
1881 skb = mwifiex_alloc_dma_align_buf(rx_len, GFP_KERNEL);
1882 if (!skb) {
1883 mwifiex_dbg(adapter, ERROR,
1884 "single skb allocated fail,\t"
1885 "drop pkt port=%d len=%d\n", port, rx_len);
1886 if (mwifiex_sdio_card_to_host(adapter, &pkt_type,
1887 card->mpa_rx.buf, rx_len,
1888 adapter->ioport + port))
1889 goto error;
1890 return 0;
1891 }
1892
1893 skb_put(skb, rx_len);
1894
1895 if (mwifiex_sdio_card_to_host(adapter, &pkt_type,
1896 skb->data, skb->len,
1897 adapter->ioport + port))
1898 goto error;
1899 if (!adapter->sdio_rx_aggr_enable &&
1900 pkt_type == MWIFIEX_TYPE_AGGR_DATA) {
1901 mwifiex_dbg(adapter, ERROR, "drop wrong pkt type %d\t"
1902 "current SDIO RX Aggr not enabled\n",
1903 pkt_type);
1904 dev_kfree_skb_any(skb);
1905 return 0;
1906 }
1907
1908 mwifiex_decode_rx_packet(adapter, skb, pkt_type);
1909 }
1910 if (f_post_aggr_cur) {
1911 mwifiex_dbg(adapter, INFO,
1912 "info: current packet aggregation\n");
1913
1914 mp_rx_aggr_setup(card, rx_len, port);
1915 }
1916
1917 return 0;
1918error:
1919 if (MP_RX_AGGR_IN_PROGRESS(card))
1920 MP_RX_AGGR_BUF_RESET(card);
1921
1922 if (f_do_rx_cur && skb)
1923
1924 dev_kfree_skb_any(skb);
1925
1926 return -1;
1927}
1928
1929
1930
1931
1932
1933
1934
1935
1936
1937
1938
1939
1940
1941
1942
1943
1944static int mwifiex_process_int_status(struct mwifiex_adapter *adapter)
1945{
1946 struct sdio_mmc_card *card = adapter->card;
1947 const struct mwifiex_sdio_card_reg *reg = card->reg;
1948 int ret = 0;
1949 u8 sdio_ireg;
1950 struct sk_buff *skb;
1951 u8 port = CTRL_PORT;
1952 u32 len_reg_l, len_reg_u;
1953 u32 rx_blocks;
1954 u16 rx_len;
1955 unsigned long flags;
1956 u32 bitmap;
1957 u8 cr;
1958
1959 spin_lock_irqsave(&adapter->int_lock, flags);
1960 sdio_ireg = adapter->int_status;
1961 adapter->int_status = 0;
1962 spin_unlock_irqrestore(&adapter->int_lock, flags);
1963
1964 if (!sdio_ireg)
1965 return ret;
1966
1967
1968 if (sdio_ireg & DN_LD_CMD_PORT_HOST_INT_STATUS && adapter->cmd_sent)
1969 adapter->cmd_sent = false;
1970
1971
1972 if (sdio_ireg & UP_LD_CMD_PORT_HOST_INT_STATUS) {
1973 u32 pkt_type;
1974
1975
1976 rx_len = card->mp_regs[reg->cmd_rd_len_1] << 8;
1977 rx_len |= (u16)card->mp_regs[reg->cmd_rd_len_0];
1978 rx_blocks = DIV_ROUND_UP(rx_len, MWIFIEX_SDIO_BLOCK_SIZE);
1979 if (rx_len <= adapter->intf_hdr_len ||
1980 (rx_blocks * MWIFIEX_SDIO_BLOCK_SIZE) >
1981 MWIFIEX_RX_DATA_BUF_SIZE)
1982 return -1;
1983 rx_len = (u16) (rx_blocks * MWIFIEX_SDIO_BLOCK_SIZE);
1984 mwifiex_dbg(adapter, INFO, "info: rx_len = %d\n", rx_len);
1985
1986 skb = mwifiex_alloc_dma_align_buf(rx_len, GFP_KERNEL);
1987 if (!skb)
1988 return -1;
1989
1990 skb_put(skb, rx_len);
1991
1992 if (mwifiex_sdio_card_to_host(adapter, &pkt_type, skb->data,
1993 skb->len, adapter->ioport |
1994 CMD_PORT_SLCT)) {
1995 mwifiex_dbg(adapter, ERROR,
1996 "%s: failed to card_to_host", __func__);
1997 dev_kfree_skb_any(skb);
1998 goto term_cmd;
1999 }
2000
2001 if ((pkt_type != MWIFIEX_TYPE_CMD) &&
2002 (pkt_type != MWIFIEX_TYPE_EVENT))
2003 mwifiex_dbg(adapter, ERROR,
2004 "%s:Received wrong packet on cmd port",
2005 __func__);
2006
2007 mwifiex_decode_rx_packet(adapter, skb, pkt_type);
2008 }
2009
2010 if (sdio_ireg & DN_LD_HOST_INT_STATUS) {
2011 bitmap = (u32) card->mp_regs[reg->wr_bitmap_l];
2012 bitmap |= ((u32) card->mp_regs[reg->wr_bitmap_u]) << 8;
2013 if (card->supports_sdio_new_mode) {
2014 bitmap |=
2015 ((u32) card->mp_regs[reg->wr_bitmap_1l]) << 16;
2016 bitmap |=
2017 ((u32) card->mp_regs[reg->wr_bitmap_1u]) << 24;
2018 }
2019 card->mp_wr_bitmap = bitmap;
2020
2021 mwifiex_dbg(adapter, INTR,
2022 "int: DNLD: wr_bitmap=0x%x\n",
2023 card->mp_wr_bitmap);
2024 if (adapter->data_sent &&
2025 (card->mp_wr_bitmap & card->mp_data_port_mask)) {
2026 mwifiex_dbg(adapter, INTR,
2027 "info: <--- Tx DONE Interrupt --->\n");
2028 adapter->data_sent = false;
2029 }
2030 }
2031
2032
2033
2034
2035 if (card->has_control_mask && adapter->cmd_sent) {
2036
2037
2038 card->mp_wr_bitmap |=
2039 (u32) card->mp_regs[reg->wr_bitmap_l] & CTRL_PORT_MASK;
2040 if (card->mp_wr_bitmap & CTRL_PORT_MASK)
2041 adapter->cmd_sent = false;
2042 }
2043
2044 mwifiex_dbg(adapter, INTR, "info: cmd_sent=%d data_sent=%d\n",
2045 adapter->cmd_sent, adapter->data_sent);
2046 if (sdio_ireg & UP_LD_HOST_INT_STATUS) {
2047 bitmap = (u32) card->mp_regs[reg->rd_bitmap_l];
2048 bitmap |= ((u32) card->mp_regs[reg->rd_bitmap_u]) << 8;
2049 if (card->supports_sdio_new_mode) {
2050 bitmap |=
2051 ((u32) card->mp_regs[reg->rd_bitmap_1l]) << 16;
2052 bitmap |=
2053 ((u32) card->mp_regs[reg->rd_bitmap_1u]) << 24;
2054 }
2055 card->mp_rd_bitmap = bitmap;
2056 mwifiex_dbg(adapter, INTR,
2057 "int: UPLD: rd_bitmap=0x%x\n",
2058 card->mp_rd_bitmap);
2059
2060 while (true) {
2061 ret = mwifiex_get_rd_port(adapter, &port);
2062 if (ret) {
2063 mwifiex_dbg(adapter, INFO,
2064 "info: no more rd_port available\n");
2065 break;
2066 }
2067 len_reg_l = reg->rd_len_p0_l + (port << 1);
2068 len_reg_u = reg->rd_len_p0_u + (port << 1);
2069 rx_len = ((u16) card->mp_regs[len_reg_u]) << 8;
2070 rx_len |= (u16) card->mp_regs[len_reg_l];
2071 mwifiex_dbg(adapter, INFO,
2072 "info: RX: port=%d rx_len=%u\n",
2073 port, rx_len);
2074 rx_blocks =
2075 (rx_len + MWIFIEX_SDIO_BLOCK_SIZE -
2076 1) / MWIFIEX_SDIO_BLOCK_SIZE;
2077 if (rx_len <= adapter->intf_hdr_len ||
2078 (card->mpa_rx.enabled &&
2079 ((rx_blocks * MWIFIEX_SDIO_BLOCK_SIZE) >
2080 card->mpa_rx.buf_size))) {
2081 mwifiex_dbg(adapter, ERROR,
2082 "invalid rx_len=%d\n",
2083 rx_len);
2084 return -1;
2085 }
2086
2087 rx_len = (u16) (rx_blocks * MWIFIEX_SDIO_BLOCK_SIZE);
2088 mwifiex_dbg(adapter, INFO, "info: rx_len = %d\n",
2089 rx_len);
2090
2091 if (mwifiex_sdio_card_to_host_mp_aggr(adapter, rx_len,
2092 port)) {
2093 mwifiex_dbg(adapter, ERROR,
2094 "card_to_host_mpa failed: int status=%#x\n",
2095 sdio_ireg);
2096 goto term_cmd;
2097 }
2098 }
2099 }
2100
2101 return 0;
2102
2103term_cmd:
2104
2105 if (mwifiex_read_reg(adapter, CONFIGURATION_REG, &cr))
2106 mwifiex_dbg(adapter, ERROR, "read CFG reg failed\n");
2107 else
2108 mwifiex_dbg(adapter, INFO,
2109 "info: CFG reg val = %d\n", cr);
2110
2111 if (mwifiex_write_reg(adapter, CONFIGURATION_REG, (cr | 0x04)))
2112 mwifiex_dbg(adapter, ERROR,
2113 "write CFG reg failed\n");
2114 else
2115 mwifiex_dbg(adapter, INFO, "info: write success\n");
2116
2117 if (mwifiex_read_reg(adapter, CONFIGURATION_REG, &cr))
2118 mwifiex_dbg(adapter, ERROR,
2119 "read CFG reg failed\n");
2120 else
2121 mwifiex_dbg(adapter, INFO,
2122 "info: CFG reg val =%x\n", cr);
2123
2124 return -1;
2125}
2126
2127
2128
2129
2130
2131
2132
2133
2134
2135
2136
2137
2138
2139
2140
2141static int mwifiex_host_to_card_mp_aggr(struct mwifiex_adapter *adapter,
2142 u8 *payload, u32 pkt_len, u32 port,
2143 u32 next_pkt_len)
2144{
2145 struct sdio_mmc_card *card = adapter->card;
2146 int ret = 0;
2147 s32 f_send_aggr_buf = 0;
2148 s32 f_send_cur_buf = 0;
2149 s32 f_precopy_cur_buf = 0;
2150 s32 f_postcopy_cur_buf = 0;
2151 u32 mport;
2152 int index;
2153
2154 if (!card->mpa_tx.enabled ||
2155 (card->has_control_mask && (port == CTRL_PORT)) ||
2156 (card->supports_sdio_new_mode && (port == CMD_PORT_SLCT))) {
2157 mwifiex_dbg(adapter, WARN,
2158 "info: %s: tx aggregation disabled\n",
2159 __func__);
2160
2161 f_send_cur_buf = 1;
2162 goto tx_curr_single;
2163 }
2164
2165 if (next_pkt_len) {
2166
2167 mwifiex_dbg(adapter, INFO,
2168 "info: %s: more packets in queue.\n",
2169 __func__);
2170
2171 if (MP_TX_AGGR_IN_PROGRESS(card)) {
2172 if (MP_TX_AGGR_BUF_HAS_ROOM(card, pkt_len)) {
2173 f_precopy_cur_buf = 1;
2174
2175 if (!(card->mp_wr_bitmap &
2176 (1 << card->curr_wr_port)) ||
2177 !MP_TX_AGGR_BUF_HAS_ROOM(
2178 card, pkt_len + next_pkt_len))
2179 f_send_aggr_buf = 1;
2180 } else {
2181
2182 f_send_aggr_buf = 1;
2183
2184 if (!(card->mp_wr_bitmap &
2185 (1 << card->curr_wr_port)))
2186 f_send_cur_buf = 1;
2187 else
2188 f_postcopy_cur_buf = 1;
2189 }
2190 } else {
2191 if (MP_TX_AGGR_BUF_HAS_ROOM(card, pkt_len) &&
2192 (card->mp_wr_bitmap & (1 << card->curr_wr_port)))
2193 f_precopy_cur_buf = 1;
2194 else
2195 f_send_cur_buf = 1;
2196 }
2197 } else {
2198
2199 mwifiex_dbg(adapter, INFO,
2200 "info: %s: Last packet in Tx Queue.\n",
2201 __func__);
2202
2203 if (MP_TX_AGGR_IN_PROGRESS(card)) {
2204
2205 f_send_aggr_buf = 1;
2206
2207 if (MP_TX_AGGR_BUF_HAS_ROOM(card, pkt_len))
2208 f_precopy_cur_buf = 1;
2209 else
2210
2211 f_send_cur_buf = 1;
2212 } else {
2213 f_send_cur_buf = 1;
2214 }
2215 }
2216
2217 if (f_precopy_cur_buf) {
2218 mwifiex_dbg(adapter, DATA,
2219 "data: %s: precopy current buffer\n",
2220 __func__);
2221 MP_TX_AGGR_BUF_PUT(card, payload, pkt_len, port);
2222
2223 if (MP_TX_AGGR_PKT_LIMIT_REACHED(card) ||
2224 mp_tx_aggr_port_limit_reached(card))
2225
2226 f_send_aggr_buf = 1;
2227 }
2228
2229 if (f_send_aggr_buf) {
2230 mwifiex_dbg(adapter, DATA,
2231 "data: %s: send aggr buffer: %d %d\n",
2232 __func__, card->mpa_tx.start_port,
2233 card->mpa_tx.ports);
2234 if (card->supports_sdio_new_mode) {
2235 u32 port_count;
2236 int i;
2237
2238 for (i = 0, port_count = 0; i < card->max_ports; i++)
2239 if (card->mpa_tx.ports & BIT(i))
2240 port_count++;
2241
2242
2243
2244
2245 port_count--;
2246 mport = (adapter->ioport | SDIO_MPA_ADDR_BASE |
2247 (port_count << 8)) + card->mpa_tx.start_port;
2248 } else {
2249 mport = (adapter->ioport | SDIO_MPA_ADDR_BASE |
2250 (card->mpa_tx.ports << 4)) +
2251 card->mpa_tx.start_port;
2252 }
2253
2254 if (card->mpa_tx.pkt_cnt == 1)
2255 mport = adapter->ioport + card->mpa_tx.start_port;
2256
2257 ret = mwifiex_write_data_to_card(adapter, card->mpa_tx.buf,
2258 card->mpa_tx.buf_len, mport);
2259
2260
2261 index = adapter->dbg.last_sdio_mp_index;
2262 index = (index + 1) % MWIFIEX_DBG_SDIO_MP_NUM;
2263 adapter->dbg.last_sdio_mp_index = index;
2264 adapter->dbg.last_mp_wr_ports[index] = mport;
2265 adapter->dbg.last_mp_wr_bitmap[index] = card->mp_wr_bitmap;
2266 adapter->dbg.last_mp_wr_len[index] = card->mpa_tx.buf_len;
2267 adapter->dbg.last_mp_curr_wr_port[index] = card->curr_wr_port;
2268
2269 MP_TX_AGGR_BUF_RESET(card);
2270 }
2271
2272tx_curr_single:
2273 if (f_send_cur_buf) {
2274 mwifiex_dbg(adapter, DATA,
2275 "data: %s: send current buffer %d\n",
2276 __func__, port);
2277 ret = mwifiex_write_data_to_card(adapter, payload, pkt_len,
2278 adapter->ioport + port);
2279 }
2280
2281 if (f_postcopy_cur_buf) {
2282 mwifiex_dbg(adapter, DATA,
2283 "data: %s: postcopy current buffer\n",
2284 __func__);
2285 MP_TX_AGGR_BUF_PUT(card, payload, pkt_len, port);
2286 }
2287
2288 return ret;
2289}
2290
2291
2292
2293
2294
2295
2296
2297
2298
2299
2300
2301static int mwifiex_sdio_host_to_card(struct mwifiex_adapter *adapter,
2302 u8 type, struct sk_buff *skb,
2303 struct mwifiex_tx_param *tx_param)
2304{
2305 struct sdio_mmc_card *card = adapter->card;
2306 int ret;
2307 u32 buf_block_len;
2308 u32 blk_size;
2309 u32 port = CTRL_PORT;
2310 u8 *payload = (u8 *)skb->data;
2311 u32 pkt_len = skb->len;
2312
2313
2314 blk_size = MWIFIEX_SDIO_BLOCK_SIZE;
2315 buf_block_len = (pkt_len + blk_size - 1) / blk_size;
2316 put_unaligned_le16((u16)pkt_len, payload + 0);
2317 put_unaligned_le16((u32)type, payload + 2);
2318
2319
2320
2321
2322
2323
2324
2325
2326 if (type == MWIFIEX_TYPE_DATA) {
2327 ret = mwifiex_get_wr_port_data(adapter, &port);
2328 if (ret) {
2329 mwifiex_dbg(adapter, ERROR,
2330 "%s: no wr_port available\n",
2331 __func__);
2332 return ret;
2333 }
2334 } else {
2335 adapter->cmd_sent = true;
2336
2337
2338 if (pkt_len <= adapter->intf_hdr_len ||
2339 pkt_len > MWIFIEX_UPLD_SIZE)
2340 mwifiex_dbg(adapter, ERROR,
2341 "%s: payload=%p, nb=%d\n",
2342 __func__, payload, pkt_len);
2343
2344 if (card->supports_sdio_new_mode)
2345 port = CMD_PORT_SLCT;
2346 }
2347
2348
2349 pkt_len = buf_block_len * blk_size;
2350
2351 if (tx_param)
2352 ret = mwifiex_host_to_card_mp_aggr(adapter, payload, pkt_len,
2353 port, tx_param->next_pkt_len
2354 );
2355 else
2356 ret = mwifiex_host_to_card_mp_aggr(adapter, payload, pkt_len,
2357 port, 0);
2358
2359 if (ret) {
2360 if (type == MWIFIEX_TYPE_CMD)
2361 adapter->cmd_sent = false;
2362 if (type == MWIFIEX_TYPE_DATA) {
2363 adapter->data_sent = false;
2364
2365 card->curr_wr_port = port;
2366 card->mp_wr_bitmap |= (u32)(1 << card->curr_wr_port);
2367 }
2368 } else {
2369 if (type == MWIFIEX_TYPE_DATA) {
2370 if (!(card->mp_wr_bitmap & (1 << card->curr_wr_port)))
2371 adapter->data_sent = true;
2372 else
2373 adapter->data_sent = false;
2374 }
2375 }
2376
2377 return ret;
2378}
2379
2380
2381
2382
2383static int mwifiex_alloc_sdio_mpa_buffers(struct mwifiex_adapter *adapter,
2384 u32 mpa_tx_buf_size, u32 mpa_rx_buf_size)
2385{
2386 struct sdio_mmc_card *card = adapter->card;
2387 u32 rx_buf_size;
2388 int ret = 0;
2389
2390 card->mpa_tx.buf = kzalloc(mpa_tx_buf_size, GFP_KERNEL);
2391 if (!card->mpa_tx.buf) {
2392 ret = -1;
2393 goto error;
2394 }
2395
2396 card->mpa_tx.buf_size = mpa_tx_buf_size;
2397
2398 rx_buf_size = max_t(u32, mpa_rx_buf_size,
2399 (u32)SDIO_MAX_AGGR_BUF_SIZE);
2400 card->mpa_rx.buf = kzalloc(rx_buf_size, GFP_KERNEL);
2401 if (!card->mpa_rx.buf) {
2402 ret = -1;
2403 goto error;
2404 }
2405
2406 card->mpa_rx.buf_size = rx_buf_size;
2407
2408error:
2409 if (ret) {
2410 kfree(card->mpa_tx.buf);
2411 kfree(card->mpa_rx.buf);
2412 card->mpa_tx.buf_size = 0;
2413 card->mpa_rx.buf_size = 0;
2414 card->mpa_tx.buf = NULL;
2415 card->mpa_rx.buf = NULL;
2416 }
2417
2418 return ret;
2419}
2420
2421
2422
2423
2424
2425
2426
2427static void
2428mwifiex_unregister_dev(struct mwifiex_adapter *adapter)
2429{
2430 struct sdio_mmc_card *card = adapter->card;
2431
2432 if (adapter->card) {
2433 card->adapter = NULL;
2434 sdio_claim_host(card->func);
2435 sdio_disable_func(card->func);
2436 sdio_release_host(card->func);
2437 }
2438}
2439
2440
2441
2442
2443
2444
2445static int mwifiex_register_dev(struct mwifiex_adapter *adapter)
2446{
2447 int ret;
2448 struct sdio_mmc_card *card = adapter->card;
2449 struct sdio_func *func = card->func;
2450 const char *firmware = card->firmware;
2451
2452
2453 card->adapter = adapter;
2454 adapter->tx_buf_size = card->tx_buf_size;
2455
2456 sdio_claim_host(func);
2457
2458
2459 ret = sdio_set_block_size(card->func, MWIFIEX_SDIO_BLOCK_SIZE);
2460 sdio_release_host(func);
2461 if (ret) {
2462 mwifiex_dbg(adapter, ERROR,
2463 "cannot set SDIO block size\n");
2464 return ret;
2465 }
2466
2467
2468
2469
2470 if (card->firmware_sdiouart) {
2471 u8 val;
2472
2473 mwifiex_read_reg(adapter, card->reg->host_strap_reg, &val);
2474 if ((val & card->reg->host_strap_mask) == card->reg->host_strap_value)
2475 firmware = card->firmware_sdiouart;
2476 }
2477 strcpy(adapter->fw_name, firmware);
2478
2479 if (card->fw_dump_enh) {
2480 adapter->mem_type_mapping_tbl = generic_mem_type_map;
2481 adapter->num_mem_types = 1;
2482 } else {
2483 adapter->mem_type_mapping_tbl = mem_type_mapping_tbl;
2484 adapter->num_mem_types = ARRAY_SIZE(mem_type_mapping_tbl);
2485 }
2486
2487 return 0;
2488}
2489
2490
2491
2492
2493
2494
2495
2496
2497
2498
2499
2500
2501
2502static int mwifiex_init_sdio(struct mwifiex_adapter *adapter)
2503{
2504 struct sdio_mmc_card *card = adapter->card;
2505 const struct mwifiex_sdio_card_reg *reg = card->reg;
2506 int ret;
2507 u8 sdio_ireg;
2508
2509 sdio_set_drvdata(card->func, card);
2510
2511
2512
2513
2514
2515
2516 mwifiex_read_reg(adapter, card->reg->host_int_status_reg, &sdio_ireg);
2517
2518
2519 mwifiex_init_sdio_ioport(adapter);
2520
2521
2522 card->mp_rd_bitmap = 0;
2523 card->mp_wr_bitmap = 0;
2524 card->curr_rd_port = reg->start_rd_port;
2525 card->curr_wr_port = reg->start_wr_port;
2526
2527 card->mp_data_port_mask = reg->data_port_mask;
2528
2529 card->mpa_tx.buf_len = 0;
2530 card->mpa_tx.pkt_cnt = 0;
2531 card->mpa_tx.start_port = 0;
2532
2533 card->mpa_tx.enabled = 1;
2534 card->mpa_tx.pkt_aggr_limit = card->mp_agg_pkt_limit;
2535
2536 card->mpa_rx.buf_len = 0;
2537 card->mpa_rx.pkt_cnt = 0;
2538 card->mpa_rx.start_port = 0;
2539
2540 card->mpa_rx.enabled = 1;
2541 card->mpa_rx.pkt_aggr_limit = card->mp_agg_pkt_limit;
2542
2543
2544 card->mp_regs = kzalloc(reg->max_mp_regs, GFP_KERNEL);
2545 if (!card->mp_regs)
2546 return -ENOMEM;
2547
2548
2549 card->mpa_rx.skb_arr = kcalloc(card->mp_agg_pkt_limit, sizeof(void *),
2550 GFP_KERNEL);
2551 if (!card->mpa_rx.skb_arr) {
2552 kfree(card->mp_regs);
2553 return -ENOMEM;
2554 }
2555
2556 card->mpa_rx.len_arr = kcalloc(card->mp_agg_pkt_limit,
2557 sizeof(*card->mpa_rx.len_arr),
2558 GFP_KERNEL);
2559 if (!card->mpa_rx.len_arr) {
2560 kfree(card->mp_regs);
2561 kfree(card->mpa_rx.skb_arr);
2562 return -ENOMEM;
2563 }
2564
2565 ret = mwifiex_alloc_sdio_mpa_buffers(adapter,
2566 card->mp_tx_agg_buf_size,
2567 card->mp_rx_agg_buf_size);
2568
2569
2570 if (ret && (card->mp_tx_agg_buf_size == MWIFIEX_MP_AGGR_BUF_SIZE_MAX ||
2571 card->mp_rx_agg_buf_size == MWIFIEX_MP_AGGR_BUF_SIZE_MAX)) {
2572
2573 adapter->host_disable_sdio_rx_aggr = true;
2574
2575 ret = mwifiex_alloc_sdio_mpa_buffers
2576 (adapter, MWIFIEX_MP_AGGR_BUF_SIZE_32K,
2577 MWIFIEX_MP_AGGR_BUF_SIZE_32K);
2578 if (ret) {
2579
2580 card->mpa_tx.enabled = 0;
2581 card->mpa_rx.enabled = 0;
2582 }
2583 }
2584
2585 adapter->auto_tdls = card->can_auto_tdls;
2586 adapter->ext_scan = card->can_ext_scan;
2587 return 0;
2588}
2589
2590
2591
2592
2593static void mwifiex_cleanup_mpa_buf(struct mwifiex_adapter *adapter)
2594{
2595 struct sdio_mmc_card *card = adapter->card;
2596
2597 MP_TX_AGGR_BUF_RESET(card);
2598 MP_RX_AGGR_BUF_RESET(card);
2599}
2600
2601
2602
2603
2604
2605
2606
2607
2608
2609static void mwifiex_cleanup_sdio(struct mwifiex_adapter *adapter)
2610{
2611 struct sdio_mmc_card *card = adapter->card;
2612
2613 cancel_work_sync(&card->work);
2614
2615 kfree(card->mp_regs);
2616 kfree(card->mpa_rx.skb_arr);
2617 kfree(card->mpa_rx.len_arr);
2618 kfree(card->mpa_tx.buf);
2619 kfree(card->mpa_rx.buf);
2620}
2621
2622
2623
2624
2625static void
2626mwifiex_update_mp_end_port(struct mwifiex_adapter *adapter, u16 port)
2627{
2628 struct sdio_mmc_card *card = adapter->card;
2629 const struct mwifiex_sdio_card_reg *reg = card->reg;
2630 int i;
2631
2632 card->mp_end_port = port;
2633
2634 card->mp_data_port_mask = reg->data_port_mask;
2635
2636 if (reg->start_wr_port) {
2637 for (i = 1; i <= card->max_ports - card->mp_end_port; i++)
2638 card->mp_data_port_mask &=
2639 ~(1 << (card->max_ports - i));
2640 }
2641
2642 card->curr_wr_port = reg->start_wr_port;
2643
2644 mwifiex_dbg(adapter, CMD,
2645 "cmd: mp_end_port %d, data port mask 0x%x\n",
2646 port, card->mp_data_port_mask);
2647}
2648
2649static void mwifiex_sdio_card_reset_work(struct mwifiex_adapter *adapter)
2650{
2651 struct sdio_mmc_card *card = adapter->card;
2652 struct sdio_func *func = card->func;
2653 int ret;
2654
2655
2656 mwifiex_shutdown_sw(adapter);
2657 clear_bit(MWIFIEX_IFACE_WORK_DEVICE_DUMP, &card->work_flags);
2658 clear_bit(MWIFIEX_IFACE_WORK_CARD_RESET, &card->work_flags);
2659
2660
2661 sdio_claim_host(func);
2662 ret = mmc_hw_reset(func->card);
2663 sdio_release_host(func);
2664
2665 switch (ret) {
2666 case 1:
2667 dev_dbg(&func->dev, "SDIO HW reset asynchronous\n");
2668 complete_all(adapter->fw_done);
2669 break;
2670 case 0:
2671 ret = mwifiex_reinit_sw(adapter);
2672 if (ret)
2673 dev_err(&func->dev, "reinit failed: %d\n", ret);
2674 break;
2675 default:
2676 dev_err(&func->dev, "SDIO HW reset failed: %d\n", ret);
2677 break;
2678 }
2679}
2680
2681
2682static enum
2683rdwr_status mwifiex_sdio_rdwr_firmware(struct mwifiex_adapter *adapter,
2684 u8 doneflag)
2685{
2686 struct sdio_mmc_card *card = adapter->card;
2687 int ret, tries;
2688 u8 ctrl_data = 0;
2689
2690 sdio_writeb(card->func, card->reg->fw_dump_host_ready,
2691 card->reg->fw_dump_ctrl, &ret);
2692 if (ret) {
2693 mwifiex_dbg(adapter, ERROR, "SDIO Write ERR\n");
2694 return RDWR_STATUS_FAILURE;
2695 }
2696 for (tries = 0; tries < MAX_POLL_TRIES; tries++) {
2697 ctrl_data = sdio_readb(card->func, card->reg->fw_dump_ctrl,
2698 &ret);
2699 if (ret) {
2700 mwifiex_dbg(adapter, ERROR, "SDIO read err\n");
2701 return RDWR_STATUS_FAILURE;
2702 }
2703 if (ctrl_data == FW_DUMP_DONE)
2704 break;
2705 if (doneflag && ctrl_data == doneflag)
2706 return RDWR_STATUS_DONE;
2707 if (ctrl_data != card->reg->fw_dump_host_ready) {
2708 mwifiex_dbg(adapter, WARN,
2709 "The ctrl reg was changed, re-try again\n");
2710 sdio_writeb(card->func, card->reg->fw_dump_host_ready,
2711 card->reg->fw_dump_ctrl, &ret);
2712 if (ret) {
2713 mwifiex_dbg(adapter, ERROR, "SDIO write err\n");
2714 return RDWR_STATUS_FAILURE;
2715 }
2716 }
2717 usleep_range(100, 200);
2718 }
2719 if (ctrl_data == card->reg->fw_dump_host_ready) {
2720 mwifiex_dbg(adapter, ERROR,
2721 "Fail to pull ctrl_data\n");
2722 return RDWR_STATUS_FAILURE;
2723 }
2724
2725 return RDWR_STATUS_SUCCESS;
2726}
2727
2728
2729static void mwifiex_sdio_fw_dump(struct mwifiex_adapter *adapter)
2730{
2731 struct sdio_mmc_card *card = adapter->card;
2732 int ret = 0;
2733 unsigned int reg, reg_start, reg_end;
2734 u8 *dbg_ptr, *end_ptr, dump_num, idx, i, read_reg, doneflag = 0;
2735 enum rdwr_status stat;
2736 u32 memory_size;
2737
2738 if (!card->can_dump_fw)
2739 return;
2740
2741 for (idx = 0; idx < ARRAY_SIZE(mem_type_mapping_tbl); idx++) {
2742 struct memory_type_mapping *entry = &mem_type_mapping_tbl[idx];
2743
2744 if (entry->mem_ptr) {
2745 vfree(entry->mem_ptr);
2746 entry->mem_ptr = NULL;
2747 }
2748 entry->mem_size = 0;
2749 }
2750
2751 mwifiex_pm_wakeup_card(adapter);
2752 sdio_claim_host(card->func);
2753
2754 mwifiex_dbg(adapter, MSG, "== mwifiex firmware dump start ==\n");
2755
2756 stat = mwifiex_sdio_rdwr_firmware(adapter, doneflag);
2757 if (stat == RDWR_STATUS_FAILURE)
2758 goto done;
2759
2760 reg = card->reg->fw_dump_start;
2761
2762 dump_num = sdio_readb(card->func, reg, &ret);
2763 if (ret) {
2764 mwifiex_dbg(adapter, ERROR, "SDIO read memory length err\n");
2765 goto done;
2766 }
2767
2768
2769 for (idx = 0; idx < dump_num; idx++) {
2770 struct memory_type_mapping *entry = &mem_type_mapping_tbl[idx];
2771
2772 stat = mwifiex_sdio_rdwr_firmware(adapter, doneflag);
2773 if (stat == RDWR_STATUS_FAILURE)
2774 goto done;
2775
2776 memory_size = 0;
2777 reg = card->reg->fw_dump_start;
2778 for (i = 0; i < 4; i++) {
2779 read_reg = sdio_readb(card->func, reg, &ret);
2780 if (ret) {
2781 mwifiex_dbg(adapter, ERROR, "SDIO read err\n");
2782 goto done;
2783 }
2784 memory_size |= (read_reg << i*8);
2785 reg++;
2786 }
2787
2788 if (memory_size == 0) {
2789 mwifiex_dbg(adapter, DUMP, "Firmware dump Finished!\n");
2790 ret = mwifiex_write_reg(adapter,
2791 card->reg->fw_dump_ctrl,
2792 FW_DUMP_READ_DONE);
2793 if (ret) {
2794 mwifiex_dbg(adapter, ERROR, "SDIO write err\n");
2795 return;
2796 }
2797 break;
2798 }
2799
2800 mwifiex_dbg(adapter, DUMP,
2801 "%s_SIZE=0x%x\n", entry->mem_name, memory_size);
2802 entry->mem_ptr = vmalloc(memory_size + 1);
2803 entry->mem_size = memory_size;
2804 if (!entry->mem_ptr) {
2805 mwifiex_dbg(adapter, ERROR, "Vmalloc %s failed\n",
2806 entry->mem_name);
2807 goto done;
2808 }
2809 dbg_ptr = entry->mem_ptr;
2810 end_ptr = dbg_ptr + memory_size;
2811
2812 doneflag = entry->done_flag;
2813 mwifiex_dbg(adapter, DUMP,
2814 "Start %s output, please wait...\n",
2815 entry->mem_name);
2816
2817 do {
2818 stat = mwifiex_sdio_rdwr_firmware(adapter, doneflag);
2819 if (stat == RDWR_STATUS_FAILURE)
2820 goto done;
2821
2822 reg_start = card->reg->fw_dump_start;
2823 reg_end = card->reg->fw_dump_end;
2824 for (reg = reg_start; reg <= reg_end; reg++) {
2825 *dbg_ptr = sdio_readb(card->func, reg, &ret);
2826 if (ret) {
2827 mwifiex_dbg(adapter, ERROR,
2828 "SDIO read err\n");
2829 goto done;
2830 }
2831 if (dbg_ptr < end_ptr)
2832 dbg_ptr++;
2833 else
2834 mwifiex_dbg(adapter, ERROR,
2835 "Allocated buf not enough\n");
2836 }
2837
2838 if (stat != RDWR_STATUS_DONE)
2839 continue;
2840
2841 mwifiex_dbg(adapter, DUMP, "%s done: size=0x%tx\n",
2842 entry->mem_name, dbg_ptr - entry->mem_ptr);
2843 break;
2844 } while (1);
2845 }
2846 mwifiex_dbg(adapter, MSG, "== mwifiex firmware dump end ==\n");
2847
2848done:
2849 sdio_release_host(card->func);
2850}
2851
2852static void mwifiex_sdio_generic_fw_dump(struct mwifiex_adapter *adapter)
2853{
2854 struct sdio_mmc_card *card = adapter->card;
2855 struct memory_type_mapping *entry = &generic_mem_type_map[0];
2856 unsigned int reg, reg_start, reg_end;
2857 u8 start_flag = 0, done_flag = 0;
2858 u8 *dbg_ptr, *end_ptr;
2859 enum rdwr_status stat;
2860 int ret = -1, tries;
2861
2862 if (!card->fw_dump_enh)
2863 return;
2864
2865 if (entry->mem_ptr) {
2866 vfree(entry->mem_ptr);
2867 entry->mem_ptr = NULL;
2868 }
2869 entry->mem_size = 0;
2870
2871 mwifiex_pm_wakeup_card(adapter);
2872 sdio_claim_host(card->func);
2873
2874 mwifiex_dbg(adapter, MSG, "== mwifiex firmware dump start ==\n");
2875
2876 stat = mwifiex_sdio_rdwr_firmware(adapter, done_flag);
2877 if (stat == RDWR_STATUS_FAILURE)
2878 goto done;
2879
2880 reg_start = card->reg->fw_dump_start;
2881 reg_end = card->reg->fw_dump_end;
2882 for (reg = reg_start; reg <= reg_end; reg++) {
2883 for (tries = 0; tries < MAX_POLL_TRIES; tries++) {
2884 start_flag = sdio_readb(card->func, reg, &ret);
2885 if (ret) {
2886 mwifiex_dbg(adapter, ERROR,
2887 "SDIO read err\n");
2888 goto done;
2889 }
2890 if (start_flag == 0)
2891 break;
2892 if (tries == MAX_POLL_TRIES) {
2893 mwifiex_dbg(adapter, ERROR,
2894 "FW not ready to dump\n");
2895 ret = -1;
2896 goto done;
2897 }
2898 }
2899 usleep_range(100, 200);
2900 }
2901
2902 entry->mem_ptr = vmalloc(0xf0000 + 1);
2903 if (!entry->mem_ptr) {
2904 ret = -1;
2905 goto done;
2906 }
2907 dbg_ptr = entry->mem_ptr;
2908 entry->mem_size = 0xf0000;
2909 end_ptr = dbg_ptr + entry->mem_size;
2910
2911 done_flag = entry->done_flag;
2912 mwifiex_dbg(adapter, DUMP,
2913 "Start %s output, please wait...\n", entry->mem_name);
2914
2915 while (true) {
2916 stat = mwifiex_sdio_rdwr_firmware(adapter, done_flag);
2917 if (stat == RDWR_STATUS_FAILURE)
2918 goto done;
2919 for (reg = reg_start; reg <= reg_end; reg++) {
2920 *dbg_ptr = sdio_readb(card->func, reg, &ret);
2921 if (ret) {
2922 mwifiex_dbg(adapter, ERROR,
2923 "SDIO read err\n");
2924 goto done;
2925 }
2926 dbg_ptr++;
2927 if (dbg_ptr >= end_ptr) {
2928 u8 *tmp_ptr;
2929
2930 tmp_ptr = vmalloc(entry->mem_size + 0x4000 + 1);
2931 if (!tmp_ptr)
2932 goto done;
2933
2934 memcpy(tmp_ptr, entry->mem_ptr,
2935 entry->mem_size);
2936 vfree(entry->mem_ptr);
2937 entry->mem_ptr = tmp_ptr;
2938 tmp_ptr = NULL;
2939 dbg_ptr = entry->mem_ptr + entry->mem_size;
2940 entry->mem_size += 0x4000;
2941 end_ptr = entry->mem_ptr + entry->mem_size;
2942 }
2943 }
2944 if (stat == RDWR_STATUS_DONE) {
2945 entry->mem_size = dbg_ptr - entry->mem_ptr;
2946 mwifiex_dbg(adapter, DUMP, "dump %s done size=0x%x\n",
2947 entry->mem_name, entry->mem_size);
2948 ret = 0;
2949 break;
2950 }
2951 }
2952 mwifiex_dbg(adapter, MSG, "== mwifiex firmware dump end ==\n");
2953
2954done:
2955 if (ret) {
2956 mwifiex_dbg(adapter, ERROR, "firmware dump failed\n");
2957 if (entry->mem_ptr) {
2958 vfree(entry->mem_ptr);
2959 entry->mem_ptr = NULL;
2960 }
2961 entry->mem_size = 0;
2962 }
2963 sdio_release_host(card->func);
2964}
2965
2966static void mwifiex_sdio_device_dump_work(struct mwifiex_adapter *adapter)
2967{
2968 struct sdio_mmc_card *card = adapter->card;
2969
2970 adapter->devdump_data = vzalloc(MWIFIEX_FW_DUMP_SIZE);
2971 if (!adapter->devdump_data) {
2972 mwifiex_dbg(adapter, ERROR,
2973 "vzalloc devdump data failure!\n");
2974 return;
2975 }
2976
2977 mwifiex_drv_info_dump(adapter);
2978 if (card->fw_dump_enh)
2979 mwifiex_sdio_generic_fw_dump(adapter);
2980 else
2981 mwifiex_sdio_fw_dump(adapter);
2982 mwifiex_prepare_fw_dump_info(adapter);
2983 mwifiex_upload_device_dump(adapter);
2984}
2985
2986static void mwifiex_sdio_work(struct work_struct *work)
2987{
2988 struct sdio_mmc_card *card =
2989 container_of(work, struct sdio_mmc_card, work);
2990
2991 if (test_and_clear_bit(MWIFIEX_IFACE_WORK_DEVICE_DUMP,
2992 &card->work_flags))
2993 mwifiex_sdio_device_dump_work(card->adapter);
2994 if (test_and_clear_bit(MWIFIEX_IFACE_WORK_CARD_RESET,
2995 &card->work_flags))
2996 mwifiex_sdio_card_reset_work(card->adapter);
2997}
2998
2999
3000static void mwifiex_sdio_card_reset(struct mwifiex_adapter *adapter)
3001{
3002 struct sdio_mmc_card *card = adapter->card;
3003
3004 if (!test_and_set_bit(MWIFIEX_IFACE_WORK_CARD_RESET, &card->work_flags))
3005 schedule_work(&card->work);
3006}
3007
3008
3009static void mwifiex_sdio_device_dump(struct mwifiex_adapter *adapter)
3010{
3011 struct sdio_mmc_card *card = adapter->card;
3012
3013 if (!test_and_set_bit(MWIFIEX_IFACE_WORK_DEVICE_DUMP,
3014 &card->work_flags))
3015 schedule_work(&card->work);
3016}
3017
3018
3019
3020
3021static int
3022mwifiex_sdio_reg_dump(struct mwifiex_adapter *adapter, char *drv_buf)
3023{
3024 char *p = drv_buf;
3025 struct sdio_mmc_card *cardp = adapter->card;
3026 int ret = 0;
3027 u8 count, func, data, index = 0, size = 0;
3028 u8 reg, reg_start, reg_end;
3029 char buf[256], *ptr;
3030
3031 if (!p)
3032 return 0;
3033
3034 mwifiex_dbg(adapter, MSG, "SDIO register dump start\n");
3035
3036 mwifiex_pm_wakeup_card(adapter);
3037
3038 sdio_claim_host(cardp->func);
3039
3040 for (count = 0; count < 5; count++) {
3041 memset(buf, 0, sizeof(buf));
3042 ptr = buf;
3043
3044 switch (count) {
3045 case 0:
3046
3047 func = count;
3048 reg_start = 0;
3049 reg_end = 9;
3050 break;
3051 case 1:
3052
3053 func = count;
3054 reg_start = cardp->reg->func1_dump_reg_start;
3055 reg_end = cardp->reg->func1_dump_reg_end;
3056 break;
3057 case 2:
3058 index = 0;
3059 func = 1;
3060 reg_start = cardp->reg->func1_spec_reg_table[index++];
3061 size = cardp->reg->func1_spec_reg_num;
3062 reg_end = cardp->reg->func1_spec_reg_table[size-1];
3063 break;
3064 default:
3065
3066 if (count == 4)
3067 mdelay(100);
3068 func = 1;
3069 reg_start = cardp->reg->func1_scratch_reg;
3070 reg_end = reg_start + MWIFIEX_SDIO_SCRATCH_SIZE;
3071 }
3072
3073 if (count != 2)
3074 ptr += sprintf(ptr, "SDIO Func%d (%#x-%#x): ",
3075 func, reg_start, reg_end);
3076 else
3077 ptr += sprintf(ptr, "SDIO Func%d: ", func);
3078
3079 for (reg = reg_start; reg <= reg_end;) {
3080 if (func == 0)
3081 data = sdio_f0_readb(cardp->func, reg, &ret);
3082 else
3083 data = sdio_readb(cardp->func, reg, &ret);
3084
3085 if (count == 2)
3086 ptr += sprintf(ptr, "(%#x) ", reg);
3087 if (!ret) {
3088 ptr += sprintf(ptr, "%02x ", data);
3089 } else {
3090 ptr += sprintf(ptr, "ERR");
3091 break;
3092 }
3093
3094 if (count == 2 && reg < reg_end)
3095 reg = cardp->reg->func1_spec_reg_table[index++];
3096 else
3097 reg++;
3098 }
3099
3100 mwifiex_dbg(adapter, MSG, "%s\n", buf);
3101 p += sprintf(p, "%s\n", buf);
3102 }
3103
3104 sdio_release_host(cardp->func);
3105
3106 mwifiex_dbg(adapter, MSG, "SDIO register dump end\n");
3107
3108 return p - drv_buf;
3109}
3110
3111
3112
3113
3114static void mwifiex_sdio_up_dev(struct mwifiex_adapter *adapter)
3115{
3116 struct sdio_mmc_card *card = adapter->card;
3117 u8 sdio_ireg;
3118
3119 sdio_claim_host(card->func);
3120 sdio_enable_func(card->func);
3121 sdio_set_block_size(card->func, MWIFIEX_SDIO_BLOCK_SIZE);
3122 sdio_release_host(card->func);
3123
3124
3125
3126
3127 adapter->tx_buf_size = card->tx_buf_size;
3128
3129
3130
3131
3132
3133 mwifiex_read_reg(adapter, card->reg->host_int_status_reg, &sdio_ireg);
3134
3135 mwifiex_init_sdio_ioport(adapter);
3136}
3137
3138static struct mwifiex_if_ops sdio_ops = {
3139 .init_if = mwifiex_init_sdio,
3140 .cleanup_if = mwifiex_cleanup_sdio,
3141 .check_fw_status = mwifiex_check_fw_status,
3142 .check_winner_status = mwifiex_check_winner_status,
3143 .prog_fw = mwifiex_prog_fw_w_helper,
3144 .register_dev = mwifiex_register_dev,
3145 .unregister_dev = mwifiex_unregister_dev,
3146 .enable_int = mwifiex_sdio_enable_host_int,
3147 .disable_int = mwifiex_sdio_disable_host_int,
3148 .process_int_status = mwifiex_process_int_status,
3149 .host_to_card = mwifiex_sdio_host_to_card,
3150 .wakeup = mwifiex_pm_wakeup_card,
3151 .wakeup_complete = mwifiex_pm_wakeup_card_complete,
3152
3153
3154 .update_mp_end_port = mwifiex_update_mp_end_port,
3155 .cleanup_mpa_buf = mwifiex_cleanup_mpa_buf,
3156 .cmdrsp_complete = mwifiex_sdio_cmdrsp_complete,
3157 .event_complete = mwifiex_sdio_event_complete,
3158 .dnld_fw = mwifiex_sdio_dnld_fw,
3159 .card_reset = mwifiex_sdio_card_reset,
3160 .reg_dump = mwifiex_sdio_reg_dump,
3161 .device_dump = mwifiex_sdio_device_dump,
3162 .deaggr_pkt = mwifiex_deaggr_sdio_pkt,
3163 .up_dev = mwifiex_sdio_up_dev,
3164};
3165
3166module_driver(mwifiex_sdio, sdio_register_driver, sdio_unregister_driver);
3167
3168MODULE_AUTHOR("Marvell International Ltd.");
3169MODULE_DESCRIPTION("Marvell WiFi-Ex SDIO Driver version " SDIO_VERSION);
3170MODULE_VERSION(SDIO_VERSION);
3171MODULE_LICENSE("GPL v2");
3172MODULE_FIRMWARE(SD8786_DEFAULT_FW_NAME);
3173MODULE_FIRMWARE(SD8787_DEFAULT_FW_NAME);
3174MODULE_FIRMWARE(SD8797_DEFAULT_FW_NAME);
3175MODULE_FIRMWARE(SD8897_DEFAULT_FW_NAME);
3176MODULE_FIRMWARE(SD8887_DEFAULT_FW_NAME);
3177MODULE_FIRMWARE(SD8977_DEFAULT_FW_NAME);
3178MODULE_FIRMWARE(SD8987_DEFAULT_FW_NAME);
3179MODULE_FIRMWARE(SD8997_DEFAULT_FW_NAME);
3180MODULE_FIRMWARE(SD8997_SDIOUART_FW_NAME);
3181