LXR linux/drivers/net/wwan/t7xx/t7xx_hif_dpmaif

   1/* SPDX-License-Identifier: GPL-2.0-only
   2 *
   3 * Copyright (c) 2021, MediaTek Inc.
   4 * Copyright (c) 2021-2022, Intel Corporation.
   5 *
   6 * Authors:
   7 *  Haijun Liu <haijun.liu@mediatek.com>
   8 *  Eliot Lee <eliot.lee@intel.com>
   9 *  Ricardo Martinez <ricardo.martinez@linux.intel.com>
  10 *
  11 * Contributors:
  12 *  Amir Hanania <amir.hanania@intel.com>
  13 *  Moises Veleta <moises.veleta@intel.com>
  14 *  Sreehari Kancharla <sreehari.kancharla@intel.com>
  15 */
  16
  17#ifndef __T7XX_HIF_DPMA_RX_H__
  18#define __T7XX_HIF_DPMA_RX_H__
  19
  20#include <linux/bits.h>
  21#include <linux/types.h>
  22
  23#include "t7xx_hif_dpmaif.h"
  24
  25#define NETIF_MASK              GENMASK(4, 0)
  26
  27#define PKT_TYPE_IP4            0
  28#define PKT_TYPE_IP6            1
  29
  30/* Structure of DL PIT */
  31struct dpmaif_pit {
  32        __le32 header;
  33        union {
  34                struct {
  35                        __le32 data_addr_l;
  36                        __le32 data_addr_h;
  37                        __le32 footer;
  38                } pd;
  39                struct {
  40                        __le32 params_1;
  41                        __le32 params_2;
  42                        __le32 params_3;
  43                } msg;
  44        };
  45};
  46
  47/* PIT header fields */
  48#define PD_PIT_DATA_LEN         GENMASK(31, 16)
  49#define PD_PIT_BUFFER_ID        GENMASK(15, 3)
  50#define PD_PIT_BUFFER_TYPE      BIT(2)
  51#define PD_PIT_CONT             BIT(1)
  52#define PD_PIT_PACKET_TYPE      BIT(0)
  53/* PIT footer fields */
  54#define PD_PIT_DLQ_DONE         GENMASK(31, 30)
  55#define PD_PIT_ULQ_DONE         GENMASK(29, 24)
  56#define PD_PIT_HEADER_OFFSET    GENMASK(23, 19)
  57#define PD_PIT_BI_F             GENMASK(18, 17)
  58#define PD_PIT_IG               BIT(16)
  59#define PD_PIT_RES              GENMASK(15, 11)
  60#define PD_PIT_H_BID            GENMASK(10, 8)
  61#define PD_PIT_PIT_SEQ          GENMASK(7, 0)
  62
  63#define MSG_PIT_DP              BIT(31)
  64#define MSG_PIT_RES             GENMASK(30, 27)
  65#define MSG_PIT_NETWORK_TYPE    GENMASK(26, 24)
  66#define MSG_PIT_CHANNEL_ID      GENMASK(23, 16)
  67#define MSG_PIT_RES2            GENMASK(15, 12)
  68#define MSG_PIT_HPC_IDX         GENMASK(11, 8)
  69#define MSG_PIT_SRC_QID         GENMASK(7, 5)
  70#define MSG_PIT_ERROR_BIT       BIT(4)
  71#define MSG_PIT_CHECKSUM        GENMASK(3, 2)
  72#define MSG_PIT_CONT            BIT(1)
  73#define MSG_PIT_PACKET_TYPE     BIT(0)
  74
  75#define MSG_PIT_HP_IDX          GENMASK(31, 27)
  76#define MSG_PIT_CMD             GENMASK(26, 24)
  77#define MSG_PIT_RES3            GENMASK(23, 21)
  78#define MSG_PIT_FLOW            GENMASK(20, 16)
  79#define MSG_PIT_COUNT           GENMASK(15, 0)
  80
  81#define MSG_PIT_HASH            GENMASK(31, 24)
  82#define MSG_PIT_RES4            GENMASK(23, 18)
  83#define MSG_PIT_PRO             GENMASK(17, 16)
  84#define MSG_PIT_VBID            GENMASK(15, 3)
  85#define MSG_PIT_RES5            GENMASK(2, 0)
  86
  87#define MSG_PIT_DLQ_DONE        GENMASK(31, 30)
  88#define MSG_PIT_ULQ_DONE        GENMASK(29, 24)
  89#define MSG_PIT_IP              BIT(23)
  90#define MSG_PIT_RES6            BIT(22)
  91#define MSG_PIT_MR              GENMASK(21, 20)
  92#define MSG_PIT_RES7            GENMASK(19, 17)
  93#define MSG_PIT_IG              BIT(16)
  94#define MSG_PIT_RES8            GENMASK(15, 11)
  95#define MSG_PIT_H_BID           GENMASK(10, 8)
  96#define MSG_PIT_PIT_SEQ         GENMASK(7, 0)
  97
  98int t7xx_dpmaif_rxq_init(struct dpmaif_rx_queue *queue);
  99void t7xx_dpmaif_rx_clear(struct dpmaif_ctrl *dpmaif_ctrl);
 100int t7xx_dpmaif_bat_rel_wq_alloc(struct dpmaif_ctrl *dpmaif_ctrl);
 101int t7xx_dpmaif_rx_buf_alloc(struct dpmaif_ctrl *dpmaif_ctrl,
 102                             const struct dpmaif_bat_request *bat_req,
 103                             const unsigned int q_num, const unsigned int buf_cnt,
 104                             const bool initial);
 105int t7xx_dpmaif_rx_frag_alloc(struct dpmaif_ctrl *dpmaif_ctrl, struct dpmaif_bat_request *bat_req,
 106                              const unsigned int buf_cnt, const bool first_time);
 107void t7xx_dpmaif_rx_stop(struct dpmaif_ctrl *dpmaif_ctrl);
 108void t7xx_dpmaif_irq_rx_done(struct dpmaif_ctrl *dpmaif_ctrl, const unsigned int que_mask);
 109void t7xx_dpmaif_rxq_free(struct dpmaif_rx_queue *queue);
 110void t7xx_dpmaif_bat_wq_rel(struct dpmaif_ctrl *dpmaif_ctrl);
 111int t7xx_dpmaif_bat_alloc(const struct dpmaif_ctrl *dpmaif_ctrl, struct dpmaif_bat_request *bat_req,
 112                          const enum bat_type buf_type);
 113void t7xx_dpmaif_bat_free(const struct dpmaif_ctrl *dpmaif_ctrl,
 114                          struct dpmaif_bat_request *bat_req);
 115
 116#endif /* __T7XX_HIF_DPMA_RX_H__ */
 117