LXR linux/drivers/phy/qualcomm/phy-qcom-qmp.c

   1// SPDX-License-Identifier: GPL-2.0
   2/*
   3 * Copyright (c) 2017, The Linux Foundation. All rights reserved.
   4 */
   5
   6#include <linux/clk.h>
   7#include <linux/clk-provider.h>
   8#include <linux/delay.h>
   9#include <linux/err.h>
  10#include <linux/io.h>
  11#include <linux/iopoll.h>
  12#include <linux/kernel.h>
  13#include <linux/module.h>
  14#include <linux/of.h>
  15#include <linux/of_device.h>
  16#include <linux/of_address.h>
  17#include <linux/phy/phy.h>
  18#include <linux/platform_device.h>
  19#include <linux/regulator/consumer.h>
  20#include <linux/reset.h>
  21#include <linux/slab.h>
  22
  23#include <dt-bindings/phy/phy.h>
  24
  25#include "phy-qcom-qmp.h"
  26
  27/* QPHY_SW_RESET bit */
  28#define SW_RESET                                BIT(0)
  29/* QPHY_POWER_DOWN_CONTROL */
  30#define SW_PWRDN                                BIT(0)
  31#define REFCLK_DRV_DSBL                         BIT(1)
  32/* QPHY_START_CONTROL bits */
  33#define SERDES_START                            BIT(0)
  34#define PCS_START                               BIT(1)
  35#define PLL_READY_GATE_EN                       BIT(3)
  36/* QPHY_PCS_STATUS bit */
  37#define PHYSTATUS                               BIT(6)
  38#define PHYSTATUS_4_20                          BIT(7)
  39/* QPHY_PCS_READY_STATUS & QPHY_COM_PCS_READY_STATUS bit */
  40#define PCS_READY                               BIT(0)
  41
  42/* QPHY_V3_DP_COM_RESET_OVRD_CTRL register bits */
  43/* DP PHY soft reset */
  44#define SW_DPPHY_RESET                          BIT(0)
  45/* mux to select DP PHY reset control, 0:HW control, 1: software reset */
  46#define SW_DPPHY_RESET_MUX                      BIT(1)
  47/* USB3 PHY soft reset */
  48#define SW_USB3PHY_RESET                        BIT(2)
  49/* mux to select USB3 PHY reset control, 0:HW control, 1: software reset */
  50#define SW_USB3PHY_RESET_MUX                    BIT(3)
  51
  52/* QPHY_V3_DP_COM_PHY_MODE_CTRL register bits */
  53#define USB3_MODE                               BIT(0) /* enables USB3 mode */
  54#define DP_MODE                                 BIT(1) /* enables DP mode */
  55
  56/* QPHY_PCS_AUTONOMOUS_MODE_CTRL register bits */
  57#define ARCVR_DTCT_EN                           BIT(0)
  58#define ALFPS_DTCT_EN                           BIT(1)
  59#define ARCVR_DTCT_EVENT_SEL                    BIT(4)
  60
  61/* QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR register bits */
  62#define IRQ_CLEAR                               BIT(0)
  63
  64/* QPHY_PCS_LFPS_RXTERM_IRQ_STATUS register bits */
  65#define RCVR_DETECT                             BIT(0)
  66
  67/* QPHY_V3_PCS_MISC_CLAMP_ENABLE register bits */
  68#define CLAMP_EN                                BIT(0) /* enables i/o clamp_n */
  69
  70#define PHY_INIT_COMPLETE_TIMEOUT               10000
  71#define POWER_DOWN_DELAY_US_MIN                 10
  72#define POWER_DOWN_DELAY_US_MAX                 11
  73
  74#define MAX_PROP_NAME                           32
  75
  76/* Define the assumed distance between lanes for underspecified device trees. */
  77#define QMP_PHY_LEGACY_LANE_STRIDE              0x400
  78
  79struct qmp_phy_init_tbl {
  80        unsigned int offset;
  81        unsigned int val;
  82        /*
  83         * register part of layout ?
  84         * if yes, then offset gives index in the reg-layout
  85         */
  86        bool in_layout;
  87        /*
  88         * mask of lanes for which this register is written
  89         * for cases when second lane needs different values
  90         */
  91        u8 lane_mask;
  92};
  93
  94#define QMP_PHY_INIT_CFG(o, v)          \
  95        {                               \
  96                .offset = o,            \
  97                .val = v,               \
  98                .lane_mask = 0xff,      \
  99        }
 100
 101#define QMP_PHY_INIT_CFG_L(o, v)        \
 102        {                               \
 103                .offset = o,            \
 104                .val = v,               \
 105                .in_layout = true,      \
 106                .lane_mask = 0xff,      \
 107        }
 108
 109#define QMP_PHY_INIT_CFG_LANE(o, v, l)  \
 110        {                               \
 111                .offset = o,            \
 112                .val = v,               \
 113                .lane_mask = l,         \
 114        }
 115
 116/* set of registers with offsets different per-PHY */
 117enum qphy_reg_layout {
 118        /* Common block control registers */
 119        QPHY_COM_SW_RESET,
 120        QPHY_COM_POWER_DOWN_CONTROL,
 121        QPHY_COM_START_CONTROL,
 122        QPHY_COM_PCS_READY_STATUS,
 123        /* PCS registers */
 124        QPHY_PLL_LOCK_CHK_DLY_TIME,
 125        QPHY_FLL_CNTRL1,
 126        QPHY_FLL_CNTRL2,
 127        QPHY_FLL_CNT_VAL_L,
 128        QPHY_FLL_CNT_VAL_H_TOL,
 129        QPHY_FLL_MAN_CODE,
 130        QPHY_SW_RESET,
 131        QPHY_START_CTRL,
 132        QPHY_PCS_READY_STATUS,
 133        QPHY_PCS_STATUS,
 134        QPHY_PCS_AUTONOMOUS_MODE_CTRL,
 135        QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR,
 136        QPHY_PCS_LFPS_RXTERM_IRQ_STATUS,
 137        QPHY_PCS_POWER_DOWN_CONTROL,
 138        /* PCS_MISC registers */
 139        QPHY_PCS_MISC_TYPEC_CTRL,
 140        /* Keep last to ensure regs_layout arrays are properly initialized */
 141        QPHY_LAYOUT_SIZE
 142};
 143
 144static const unsigned int msm8996_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
 145        [QPHY_START_CTRL]               = 0x00,
 146        [QPHY_PCS_READY_STATUS]         = 0x168,
 147};
 148
 149static const unsigned int ipq_pciephy_gen3_regs_layout[QPHY_LAYOUT_SIZE] = {
 150        [QPHY_SW_RESET]                         = 0x00,
 151        [QPHY_START_CTRL]                       = 0x44,
 152        [QPHY_PCS_STATUS]                       = 0x14,
 153        [QPHY_PCS_POWER_DOWN_CONTROL]           = 0x40,
 154};
 155
 156static const unsigned int pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
 157        [QPHY_COM_SW_RESET]             = 0x400,
 158        [QPHY_COM_POWER_DOWN_CONTROL]   = 0x404,
 159        [QPHY_COM_START_CONTROL]        = 0x408,
 160        [QPHY_COM_PCS_READY_STATUS]     = 0x448,
 161        [QPHY_PLL_LOCK_CHK_DLY_TIME]    = 0xa8,
 162        [QPHY_FLL_CNTRL1]               = 0xc4,
 163        [QPHY_FLL_CNTRL2]               = 0xc8,
 164        [QPHY_FLL_CNT_VAL_L]            = 0xcc,
 165        [QPHY_FLL_CNT_VAL_H_TOL]        = 0xd0,
 166        [QPHY_FLL_MAN_CODE]             = 0xd4,
 167        [QPHY_SW_RESET]                 = 0x00,
 168        [QPHY_START_CTRL]               = 0x08,
 169        [QPHY_PCS_STATUS]               = 0x174,
 170};
 171
 172static const unsigned int usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
 173        [QPHY_FLL_CNTRL1]               = 0xc0,
 174        [QPHY_FLL_CNTRL2]               = 0xc4,
 175        [QPHY_FLL_CNT_VAL_L]            = 0xc8,
 176        [QPHY_FLL_CNT_VAL_H_TOL]        = 0xcc,
 177        [QPHY_FLL_MAN_CODE]             = 0xd0,
 178        [QPHY_SW_RESET]                 = 0x00,
 179        [QPHY_START_CTRL]               = 0x08,
 180        [QPHY_PCS_STATUS]               = 0x17c,
 181        [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d4,
 182        [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR]  = 0x0d8,
 183        [QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x178,
 184};
 185
 186static const unsigned int qmp_v3_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
 187        [QPHY_SW_RESET]                 = 0x00,
 188        [QPHY_START_CTRL]               = 0x08,
 189        [QPHY_PCS_STATUS]               = 0x174,
 190        [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d8,
 191        [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR]  = 0x0dc,
 192        [QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x170,
 193};
 194
 195static const unsigned int sdm845_qmp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
 196        [QPHY_SW_RESET]                 = 0x00,
 197        [QPHY_START_CTRL]               = 0x08,
 198        [QPHY_PCS_STATUS]               = 0x174,
 199};
 200
 201static const unsigned int sdm845_qhp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
 202        [QPHY_SW_RESET]                 = 0x00,
 203        [QPHY_START_CTRL]               = 0x08,
 204        [QPHY_PCS_STATUS]               = 0x2ac,
 205};
 206
 207static const unsigned int qmp_v4_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
 208        [QPHY_SW_RESET]                 = 0x00,
 209        [QPHY_START_CTRL]               = 0x44,
 210        [QPHY_PCS_STATUS]               = 0x14,
 211        [QPHY_PCS_POWER_DOWN_CONTROL]   = 0x40,
 212        [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x308,
 213        [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x314,
 214};
 215
 216static const unsigned int qmp_v4_usb3_uniphy_regs_layout[QPHY_LAYOUT_SIZE] = {
 217        [QPHY_SW_RESET]                 = 0x00,
 218        [QPHY_START_CTRL]               = 0x44,
 219        [QPHY_PCS_STATUS]               = 0x14,
 220        [QPHY_PCS_POWER_DOWN_CONTROL]   = 0x40,
 221        [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x608,
 222        [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR]  = 0x614,
 223};
 224
 225static const unsigned int sm8350_usb3_uniphy_regs_layout[QPHY_LAYOUT_SIZE] = {
 226        [QPHY_SW_RESET]                 = 0x00,
 227        [QPHY_START_CTRL]               = 0x44,
 228        [QPHY_PCS_STATUS]               = 0x14,
 229        [QPHY_PCS_POWER_DOWN_CONTROL]   = 0x40,
 230        [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x1008,
 231        [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR]  = 0x1014,
 232};
 233
 234static const unsigned int qcm2290_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
 235        [QPHY_SW_RESET]                 = 0x00,
 236        [QPHY_PCS_POWER_DOWN_CONTROL]   = 0x04,
 237        [QPHY_START_CTRL]               = 0x08,
 238        [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0xd8,
 239        [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0xdc,
 240        [QPHY_PCS_STATUS]               = 0x174,
 241        [QPHY_PCS_MISC_TYPEC_CTRL]      = 0x00,
 242};
 243
 244static const unsigned int sdm845_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
 245        [QPHY_START_CTRL]               = 0x00,
 246        [QPHY_PCS_READY_STATUS]         = 0x160,
 247};
 248
 249static const unsigned int sm6115_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
 250        [QPHY_START_CTRL]               = 0x00,
 251        [QPHY_PCS_READY_STATUS]         = 0x168,
 252};
 253
 254static const unsigned int sm8250_pcie_regs_layout[QPHY_LAYOUT_SIZE] = {
 255        [QPHY_SW_RESET]                 = 0x00,
 256        [QPHY_START_CTRL]               = 0x44,
 257        [QPHY_PCS_STATUS]               = 0x14,
 258        [QPHY_PCS_POWER_DOWN_CONTROL]   = 0x40,
 259};
 260
 261static const unsigned int sm8150_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
 262        [QPHY_START_CTRL]               = QPHY_V4_PCS_UFS_PHY_START,
 263        [QPHY_PCS_READY_STATUS]         = QPHY_V4_PCS_UFS_READY_STATUS,
 264        [QPHY_SW_RESET]                 = QPHY_V4_PCS_UFS_SW_RESET,
 265};
 266
 267static const struct qmp_phy_init_tbl ipq8074_usb3_serdes_tbl[] = {
 268        QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x1a),
 269        QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
 270        QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
 271        QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
 272        QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
 273        QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
 274        QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
 275        QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
 276        QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
 277        QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
 278        /* PLL and Loop filter settings */
 279        QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
 280        QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
 281        QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
 282        QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
 283        QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
 284        QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
 285        QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
 286        QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
 287        QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),
 288        QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),
 289        QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
 290        QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
 291        QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
 292        QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
 293        QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
 294        /* SSC settings */
 295        QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
 296        QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
 297        QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
 298        QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
 299        QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
 300        QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),
 301        QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),
 302};
 303
 304static const struct qmp_phy_init_tbl ipq8074_usb3_rx_tbl[] = {
 305        QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x06),
 306        QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
 307        QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c),
 308        QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xb8),
 309        QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
 310        QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
 311        QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03),
 312        QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
 313        QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x0),
 314};
 315
 316static const struct qmp_phy_init_tbl ipq8074_usb3_pcs_tbl[] = {
 317        QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
 318        QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0e),
 319        QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
 320        QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
 321        QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
 322        QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
 323        QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85),
 324        QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
 325        QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
 326        QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
 327        QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
 328        QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
 329        QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
 330        QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
 331        QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
 332        QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
 333        QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
 334        QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
 335        QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
 336        QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
 337        QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88),
 338        QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17),
 339        QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f),
 340};
 341
 342static const struct qmp_phy_init_tbl msm8996_pcie_serdes_tbl[] = {
 343        QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x1c),
 344        QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
 345        QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
 346        QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
 347        QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x42),
 348        QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
 349        QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
 350        QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x1f),
 351        QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x01),
 352        QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
 353        QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
 354        QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
 355        QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x09),
 356        QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
 357        QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
 358        QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
 359        QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
 360        QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
 361        QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x1a),
 362        QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x0a),
 363        QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
 364        QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x02),
 365        QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f),
 366        QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x04),
 367        QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
 368        QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
 369        QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
 370        QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
 371        QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
 372        QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
 373        QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
 374        QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
 375        QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x02),
 376        QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
 377        QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f),
 378        QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19),
 379        QMP_PHY_INIT_CFG(QSERDES_COM_RESCODE_DIV_NUM, 0x15),
 380        QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
 381        QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
 382        QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19),
 383        QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
 384        QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
 385        QMP_PHY_INIT_CFG(QSERDES_COM_RESCODE_DIV_NUM, 0x40),
 386};
 387
 388static const struct qmp_phy_init_tbl msm8996_pcie_tx_tbl[] = {
 389        QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
 390        QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
 391};
 392
 393static const struct qmp_phy_init_tbl msm8996_pcie_rx_tbl[] = {
 394        QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c),
 395        QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x01),
 396        QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x00),
 397        QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb),
 398        QMP_PHY_INIT_CFG(QSERDES_RX_RX_BAND, 0x18),
 399        QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x04),
 400        QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN_HALF, 0x04),
 401        QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
 402        QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
 403        QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x19),
 404};
 405
 406static const struct qmp_phy_init_tbl msm8996_pcie_pcs_tbl[] = {
 407        QMP_PHY_INIT_CFG(QPHY_RX_IDLE_DTCT_CNTRL, 0x4c),
 408        QMP_PHY_INIT_CFG(QPHY_PWRUP_RESET_DLY_TIME_AUXCLK, 0x00),
 409        QMP_PHY_INIT_CFG(QPHY_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
 410
 411        QMP_PHY_INIT_CFG_L(QPHY_PLL_LOCK_CHK_DLY_TIME, 0x05),
 412
 413        QMP_PHY_INIT_CFG(QPHY_ENDPOINT_REFCLK_DRIVE, 0x05),
 414        QMP_PHY_INIT_CFG(QPHY_POWER_DOWN_CONTROL, 0x02),
 415        QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG4, 0x00),
 416        QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG1, 0xa3),
 417        QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M3P5DB_V0, 0x0e),
 418};
 419
 420static const struct qmp_phy_init_tbl msm8998_pcie_serdes_tbl[] = {
 421        QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
 422        QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
 423        QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x0f),
 424        QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
 425        QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
 426        QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
 427        QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
 428        QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
 429        QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
 430        QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff),
 431        QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f),
 432        QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
 433        QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
 434        QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
 435        QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19),
 436        QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90),
 437        QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
 438        QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x03),
 439        QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x55),
 440        QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x55),
 441        QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
 442        QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d),
 443        QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04),
 444        QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
 445        QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x08),
 446        QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
 447        QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x34),
 448        QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
 449        QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33),
 450        QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
 451        QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x07),
 452        QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04),
 453        QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
 454        QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
 455        QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09),
 456        QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
 457        QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40),
 458        QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
 459        QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02),
 460        QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
 461        QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e),
 462        QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15),
 463};
 464
 465static const struct qmp_phy_init_tbl msm8998_pcie_tx_tbl[] = {
 466        QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02),
 467        QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
 468        QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
 469        QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
 470};
 471
 472static const struct qmp_phy_init_tbl msm8998_pcie_rx_tbl[] = {
 473        QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
 474        QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x1c),
 475        QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
 476        QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0a),
 477        QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
 478        QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a),
 479        QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
 480        QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04),
 481        QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04),
 482        QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x00),
 483        QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
 484        QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
 485        QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71),
 486        QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40),
 487};
 488
 489static const struct qmp_phy_init_tbl msm8998_pcie_pcs_tbl[] = {
 490        QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04),
 491        QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00),
 492        QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01),
 493        QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
 494        QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20),
 495        QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
 496        QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
 497        QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73),
 498        QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x99),
 499        QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03),
 500};
 501
 502static const struct qmp_phy_init_tbl msm8996_ufs_serdes_tbl[] = {
 503        QMP_PHY_INIT_CFG(QPHY_POWER_DOWN_CONTROL, 0x01),
 504        QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e),
 505        QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xd7),
 506        QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
 507        QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
 508        QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
 509        QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
 510        QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x05),
 511        QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
 512        QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV_MODE1, 0x0a),
 513        QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x01),
 514        QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x10),
 515        QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
 516        QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
 517        QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
 518        QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
 519        QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x3f),
 520        QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x54),
 521        QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x05),
 522        QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
 523        QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00),
 524        QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x00),
 525        QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x00),
 526        QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
 527        QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
 528        QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
 529        QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
 530        QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
 531        QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE0, 0x28),
 532        QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE0, 0x02),
 533        QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xff),
 534        QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x0c),
 535        QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
 536        QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE1, 0x98),
 537        QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE1, 0x00),
 538        QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE1, 0x00),
 539        QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE1, 0x00),
 540        QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE1, 0x0b),
 541        QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE1, 0x16),
 542        QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE1, 0x28),
 543        QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE1, 0x80),
 544        QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
 545        QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE1, 0xd6),
 546        QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE1, 0x00),
 547        QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE1, 0x32),
 548        QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE1, 0x0f),
 549        QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE1, 0x00),
 550};
 551
 552static const struct qmp_phy_init_tbl msm8996_ufs_tx_tbl[] = {
 553        QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
 554        QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x02),
 555};
 556
 557static const struct qmp_phy_init_tbl msm8996_ufs_rx_tbl[] = {
 558        QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x24),
 559        QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x02),
 560        QMP_PHY_INIT_CFG(QSERDES_RX_RX_INTERFACE_MODE, 0x00),
 561        QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x18),
 562        QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0B),
 563        QMP_PHY_INIT_CFG(QSERDES_RX_RX_TERM_BW, 0x5b),
 564        QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_LSB, 0xff),
 565        QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_MSB, 0x3f),
 566        QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_LSB, 0xff),
 567        QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_MSB, 0x0f),
 568        QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0E),
 569};
 570
 571static const struct qmp_phy_init_tbl msm8996_usb3_serdes_tbl[] = {
 572        QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
 573        QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
 574        QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
 575        QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
 576        QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
 577        QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
 578        QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
 579        QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
 580        QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x04),
 581        /* PLL and Loop filter settings */
 582        QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
 583        QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
 584        QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
 585        QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
 586        QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
 587        QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
 588        QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
 589        QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
 590        QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x00),
 591        QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),
 592        QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),
 593        QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
 594        QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
 595        QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
 596        QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
 597        QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
 598        /* SSC settings */
 599        QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
 600        QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
 601        QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
 602        QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
 603        QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
 604        QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),
 605        QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),
 606};
 607
 608static const struct qmp_phy_init_tbl msm8996_usb3_tx_tbl[] = {
 609        QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
 610        QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),
 611        QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
 612};
 613
 614static const struct qmp_phy_init_tbl msm8996_usb3_rx_tbl[] = {
 615        QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
 616        QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x04),
 617        QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
 618        QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c),
 619        QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xbb),
 620        QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
 621        QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
 622        QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03),
 623        QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x18),
 624        QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
 625};
 626
 627static const struct qmp_phy_init_tbl msm8996_usb3_pcs_tbl[] = {
 628        /* FLL settings */
 629        QMP_PHY_INIT_CFG_L(QPHY_FLL_CNTRL2, 0x03),
 630        QMP_PHY_INIT_CFG_L(QPHY_FLL_CNTRL1, 0x02),
 631        QMP_PHY_INIT_CFG_L(QPHY_FLL_CNT_VAL_L, 0x09),
 632        QMP_PHY_INIT_CFG_L(QPHY_FLL_CNT_VAL_H_TOL, 0x42),
 633        QMP_PHY_INIT_CFG_L(QPHY_FLL_MAN_CODE, 0x85),
 634
 635        /* Lock Det settings */
 636        QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG1, 0xd1),
 637        QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG2, 0x1f),
 638        QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG3, 0x47),
 639        QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG2, 0x08),
 640};
 641
 642static const struct qmp_phy_init_tbl ipq6018_pcie_serdes_tbl[] = {
 643        QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER1, 0x7d),
 644        QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER2, 0x01),
 645        QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE0, 0x0a),
 646        QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE0, 0x05),
 647        QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE1, 0x08),
 648        QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE1, 0x04),
 649        QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CLKBUFLR_EN, 0x18),
 650        QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90),
 651        QMP_PHY_INIT_CFG(QSERDES_PLL_SYS_CLK_CTRL, 0x02),
 652        QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_BUF_ENABLE, 0x07),
 653        QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_IVCO, 0x0f),
 654        QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE0, 0xd4),
 655        QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE0, 0x14),
 656        QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE1, 0xaa),
 657        QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE1, 0x29),
 658        QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TRIM, 0x0f),
 659        QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE0, 0x09),
 660        QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE1, 0x09),
 661        QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE0, 0x16),
 662        QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE1, 0x16),
 663        QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE0, 0x28),
 664        QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE1, 0x28),
 665        QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CTRL_BY_PSM, 0x01),
 666        QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_EN_SEL, 0x08),
 667        QMP_PHY_INIT_CFG(QSERDES_PLL_RESETSM_CNTRL, 0x20),
 668        QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP_EN, 0x42),
 669        QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE0, 0x68),
 670        QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE1, 0x53),
 671        QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE0, 0xab),
 672        QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE0, 0xaa),
 673        QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE0, 0x02),
 674        QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE1, 0x55),
 675        QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE1, 0x55),
 676        QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE1, 0x05),
 677        QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE0, 0xa0),
 678        QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE1, 0xa0),
 679        QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE0, 0x24),
 680        QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE0, 0x02),
 681        QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE1, 0xb4),
 682        QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE1, 0x03),
 683        QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x32),
 684        QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x01),
 685        QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x00),
 686        QMP_PHY_INIT_CFG(QSERDES_PLL_CMN_CONFIG, 0x06),
 687        QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05),
 688        QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV_MODE1, 0x08),
 689};
 690
 691static const struct qmp_phy_init_tbl ipq6018_pcie_tx_tbl[] = {
 692        QMP_PHY_INIT_CFG(QSERDES_TX0_RES_CODE_LANE_OFFSET_TX, 0x02),
 693        QMP_PHY_INIT_CFG(QSERDES_TX0_LANE_MODE_1, 0x06),
 694        QMP_PHY_INIT_CFG(QSERDES_TX0_RCV_DETECT_LVL_2, 0x12),
 695};
 696
 697static const struct qmp_phy_init_tbl ipq6018_pcie_rx_tbl[] = {
 698        QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_FO_GAIN, 0x0c),
 699        QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_SO_GAIN, 0x02),
 700        QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
 701        QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_PI_CONTROLS, 0x70),
 702        QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL2, 0x61),
 703        QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL3, 0x04),
 704        QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL4, 0x1e),
 705        QMP_PHY_INIT_CFG(QSERDES_RX0_RX_IDAC_TSETTLE_LOW, 0xc0),
 706        QMP_PHY_INIT_CFG(QSERDES_RX0_RX_IDAC_TSETTLE_HIGH, 0x00),
 707        QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x73),
 708        QMP_PHY_INIT_CFG(QSERDES_RX0_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
 709        QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_ENABLES, 0x1c),
 710        QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_CNTRL, 0x03),
 711        QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_DEGLITCH_CNTRL, 0x14),
 712        QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_LOW, 0xf0),
 713        QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH, 0x01),
 714        QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH2, 0x2f),
 715        QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH3, 0xd3),
 716        QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH4, 0x40),
 717        QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_LOW, 0x01),
 718        QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH, 0x02),
 719        QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH2, 0xc8),
 720        QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH3, 0x09),
 721        QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH4, 0xb1),
 722        QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_LOW, 0x00),
 723        QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH, 0x02),
 724        QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH2, 0xc8),
 725        QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH3, 0x09),
 726        QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH4, 0xb1),
 727        QMP_PHY_INIT_CFG(QSERDES_RX0_DFE_EN_TIMER, 0x04),
 728};
 729
 730static const struct qmp_phy_init_tbl ipq6018_pcie_pcs_tbl[] = {
 731        QMP_PHY_INIT_CFG(PCS_COM_FLL_CNTRL1, 0x01),
 732        QMP_PHY_INIT_CFG(PCS_COM_REFGEN_REQ_CONFIG1, 0x0d),
 733        QMP_PHY_INIT_CFG(PCS_COM_G12S1_TXDEEMPH_M3P5DB, 0x10),
 734        QMP_PHY_INIT_CFG(PCS_COM_RX_SIGDET_LVL, 0xaa),
 735        QMP_PHY_INIT_CFG(PCS_COM_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
 736        QMP_PHY_INIT_CFG(PCS_COM_RX_DCC_CAL_CONFIG, 0x01),
 737        QMP_PHY_INIT_CFG(PCS_COM_EQ_CONFIG5, 0x01),
 738        QMP_PHY_INIT_CFG(PCS_PCIE_POWER_STATE_CONFIG2, 0x0d),
 739        QMP_PHY_INIT_CFG(PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
 740        QMP_PHY_INIT_CFG(PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
 741        QMP_PHY_INIT_CFG(PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
 742        QMP_PHY_INIT_CFG(PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
 743        QMP_PHY_INIT_CFG(PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
 744        QMP_PHY_INIT_CFG(PCS_PCIE_EQ_CONFIG1, 0x11),
 745        QMP_PHY_INIT_CFG(PCS_PCIE_PRESET_P10_PRE, 0x00),
 746        QMP_PHY_INIT_CFG(PCS_PCIE_PRESET_P10_POST, 0x58),
 747};
 748
 749static const struct qmp_phy_init_tbl ipq8074_pcie_serdes_tbl[] = {
 750        QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x18),
 751        QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
 752        QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0xf),
 753        QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x1),
 754        QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x0),
 755        QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
 756        QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x1f),
 757        QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x6),
 758        QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0xf),
 759        QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x0),
 760        QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x1),
 761        QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x20),
 762        QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0xa),
 763        QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
 764        QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0xa),
 765        QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xa),
 766        QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
 767        QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x3),
 768        QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
 769        QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
 770        QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x0),
 771        QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0xD),
 772        QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xD04),
 773        QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
 774        QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x2),
 775        QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f),
 776        QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0xb),
 777        QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
 778        QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
 779        QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x0),
 780        QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
 781        QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x1),
 782        QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x1),
 783        QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
 784        QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x1),
 785        QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x2),
 786        QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x0),
 787        QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f),
 788        QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19),
 789        QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19),
 790};
 791
 792static const struct qmp_phy_init_tbl ipq8074_pcie_tx_tbl[] = {
 793        QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
 794        QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x6),
 795        QMP_PHY_INIT_CFG(QSERDES_TX_RES_CODE_LANE_OFFSET, 0x2),
 796        QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),
 797        QMP_PHY_INIT_CFG(QSERDES_TX_EMP_POST1_LVL, 0x36),
 798        QMP_PHY_INIT_CFG(QSERDES_TX_SLEW_CNTL, 0x0a),
 799};
 800
 801static const struct qmp_phy_init_tbl ipq8074_pcie_rx_tbl[] = {
 802        QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c),
 803        QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
 804        QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x1),
 805        QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x0),
 806        QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb),
 807        QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
 808        QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x4),
 809};
 810
 811static const struct qmp_phy_init_tbl ipq8074_pcie_pcs_tbl[] = {
 812        QMP_PHY_INIT_CFG(QPHY_ENDPOINT_REFCLK_DRIVE, 0x4),
 813        QMP_PHY_INIT_CFG(QPHY_OSC_DTCT_ACTIONS, 0x0),
 814        QMP_PHY_INIT_CFG(QPHY_PWRUP_RESET_DLY_TIME_AUXCLK, 0x40),
 815        QMP_PHY_INIT_CFG(QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x0),
 816        QMP_PHY_INIT_CFG(QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x40),
 817        QMP_PHY_INIT_CFG(QPHY_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB, 0x0),
 818        QMP_PHY_INIT_CFG(QPHY_LP_WAKEUP_DLY_TIME_AUXCLK, 0x40),
 819        QMP_PHY_INIT_CFG_L(QPHY_PLL_LOCK_CHK_DLY_TIME, 0x73),
 820        QMP_PHY_INIT_CFG(QPHY_RX_SIGDET_LVL, 0x99),
 821        QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M6DB_V0, 0x15),
 822        QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M3P5DB_V0, 0xe),
 823        QMP_PHY_INIT_CFG_L(QPHY_SW_RESET, 0x0),
 824        QMP_PHY_INIT_CFG_L(QPHY_START_CTRL, 0x3),
 825};
 826
 827static const struct qmp_phy_init_tbl sdm845_qmp_pcie_serdes_tbl[] = {
 828        QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
 829        QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
 830        QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x007),
 831        QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
 832        QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
 833        QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
 834        QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
 835        QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
 836        QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
 837        QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff),
 838        QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f),
 839        QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
 840        QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
 841        QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
 842        QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19),
 843        QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90),
 844        QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
 845        QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
 846        QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
 847        QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
 848        QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
 849        QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d),
 850        QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04),
 851        QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
 852        QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
 853        QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
 854        QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
 855        QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_MODE, 0x01),
 856        QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33),
 857        QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
 858        QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06),
 859        QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04),
 860        QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
 861        QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
 862        QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09),
 863        QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
 864        QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40),
 865        QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
 866        QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02),
 867        QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
 868        QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e),
 869        QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15),
 870};
 871
 872static const struct qmp_phy_init_tbl sdm845_qmp_pcie_tx_tbl[] = {
 873        QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02),
 874        QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
 875        QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
 876        QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
 877};
 878
 879static const struct qmp_phy_init_tbl sdm845_qmp_pcie_rx_tbl[] = {
 880        QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
 881        QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x10),
 882        QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
 883        QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
 884        QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
 885        QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a),
 886        QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
 887        QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04),
 888        QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04),
 889        QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x71),
 890        QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59),
 891        QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_01, 0x59),
 892        QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
 893        QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
 894        QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71),
 895        QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40),
 896};
 897
 898static const struct qmp_phy_init_tbl sdm845_qmp_pcie_pcs_tbl[] = {
 899        QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04),
 900
 901        QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
 902        QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
 903        QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
 904        QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
 905        QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
 906
 907        QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00),
 908        QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01),
 909        QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
 910        QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20),
 911        QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
 912        QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
 913        QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73),
 914
 915        QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xbb),
 916        QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03),
 917        QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x0d),
 918
 919        QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG4, 0x00),
 920};
 921
 922static const struct qmp_phy_init_tbl sdm845_qmp_pcie_pcs_misc_tbl[] = {
 923        QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_CONFIG2, 0x52),
 924        QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG2, 0x10),
 925        QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG4, 0x1a),
 926        QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG5, 0x06),
 927        QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
 928};
 929
 930static const struct qmp_phy_init_tbl sdm845_qhp_pcie_serdes_tbl[] = {
 931        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SYSCLK_EN_SEL, 0x27),
 932        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_EN_CENTER, 0x01),
 933        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_PER1, 0x31),
 934        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_PER2, 0x01),
 935        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1, 0xde),
 936        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2, 0x07),
 937        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
 938        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2_MODE1, 0x06),
 939        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BIAS_EN_CKBUFLR_EN, 0x18),
 940        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CLK_ENABLE1, 0xb0),
 941        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE0, 0x8c),
 942        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE0, 0x20),
 943        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE1, 0x14),
 944        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE1, 0x34),
 945        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CP_CTRL_MODE0, 0x06),
 946        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CP_CTRL_MODE1, 0x06),
 947        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE0, 0x16),
 948        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE1, 0x16),
 949        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE0, 0x36),
 950        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE1, 0x36),
 951        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_RESTRIM_CTRL2, 0x05),
 952        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP_EN, 0x42),
 953        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DEC_START_MODE0, 0x82),
 954        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DEC_START_MODE1, 0x68),
 955        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE0, 0x55),
 956        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE0, 0x55),
 957        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE0, 0x03),
 958        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE1, 0xab),
 959        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE1, 0xaa),
 960        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE1, 0x02),
 961        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
 962        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE1, 0x3f),
 963        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VCO_TUNE_MAP, 0x10),
 964        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CLK_SELECT, 0x04),
 965        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_HSCLK_SEL1, 0x30),
 966        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORECLK_DIV, 0x04),
 967        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORE_CLK_EN, 0x73),
 968        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CMN_CONFIG, 0x0c),
 969        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SVS_MODE_CLK_SEL, 0x15),
 970        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORECLK_DIV_MODE1, 0x04),
 971        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CMN_MODE, 0x01),
 972        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VREGCLK_DIV1, 0x22),
 973        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VREGCLK_DIV2, 0x00),
 974        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BGV_TRIM, 0x20),
 975        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BG_CTRL, 0x07),
 976};
 977
 978static const struct qmp_phy_init_tbl sdm845_qhp_pcie_tx_tbl[] = {
 979        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL0, 0x00),
 980        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_TAP_EN, 0x0d),
 981        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_TX_BAND_MODE, 0x01),
 982        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_LANE_MODE, 0x1a),
 983        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PARALLEL_RATE, 0x2f),
 984        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE0, 0x09),
 985        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE1, 0x09),
 986        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE2, 0x1b),
 987        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE1, 0x01),
 988        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE2, 0x07),
 989        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE0, 0x31),
 990        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE1, 0x31),
 991        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE2, 0x03),
 992        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_THRESH_DFE, 0x02),
 993        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CGA_THRESH_DFE, 0x00),
 994        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXENGINE_EN0, 0x12),
 995        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_TRAIN_TIME, 0x25),
 996        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_DFE_OVRLP_TIME, 0x00),
 997        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_REFRESH_TIME, 0x05),
 998        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_ENABLE_TIME, 0x01),
 999        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_VGA_GAIN, 0x26),
1000        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_GAIN, 0x12),

1001        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EQ_GAIN, 0x04),
1002        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_OFFSET_GAIN, 0x04),
1003        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PRE_GAIN, 0x09),
1004        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EQ_INTVAL, 0x15),
1005        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EDAC_INITVAL, 0x28),
1006        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_INITB0, 0x7f),
1007        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_INITB1, 0x07),
1008        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RCVRDONE_THRESH1, 0x04),
1009        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_CTRL, 0x70),
1010        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE0, 0x8b),
1011        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE1, 0x08),
1012        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE2, 0x0a),
1013        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE0, 0x03),
1014        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE1, 0x04),
1015        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE2, 0x04),
1016        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_CONFIG, 0x0c),
1017        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_BAND, 0x02),
1018        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE0, 0x5c),
1019        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE1, 0x3e),
1020        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE2, 0x3f),
1021        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_ENABLES, 0x01),
1022        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_CNTRL, 0xa0),
1023        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_DEGLITCH_CNTRL, 0x08),
1024        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DCC_GAIN, 0x01),
1025        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_EN_SIGNAL, 0xc3),
1026        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PSM_RX_EN_CAL, 0x00),
1027        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_MISC_CNTRL0, 0xbc),
1028        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_TS0_TIMER, 0x7f),
1029        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DLL_HIGHDATARATE, 0x15),
1030        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL1, 0x0c),
1031        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL2, 0x0f),
1032        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RESETCODE_OFFSET, 0x04),
1033        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_VGA_INITVAL, 0x20),
1034        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RSM_START, 0x01),
1035};
1036
1037static const struct qmp_phy_init_tbl sdm845_qhp_pcie_rx_tbl[] = {
1038};
1039
1040static const struct qmp_phy_init_tbl sdm845_qhp_pcie_pcs_tbl[] = {
1041        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG, 0x3f),
1042        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_PCS_TX_RX_CONFIG, 0x50),
1043        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M3P5DB, 0x19),
1044        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M3P5DB, 0x07),
1045        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M6DB, 0x17),
1046        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M6DB, 0x09),
1047        QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG5, 0x9f),
1048};
1049
1050static const struct qmp_phy_init_tbl qmp_v3_usb3_serdes_tbl[] = {
1051        QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
1052        QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
1053        QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
1054        QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
1055        QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
1056        QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
1057        QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x16),
1058        QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
1059        QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
1060        QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
1061        QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
1062        QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
1063        QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
1064        QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
1065        QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
1066        QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
1067        QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
1068        QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
1069        QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
1070        QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
1071        QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
1072        QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
1073        QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
1074        QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
1075        QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
1076        QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
1077        QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
1078        QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
1079        QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a),
1080        QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
1081        QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
1082        QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
1083        QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
1084        QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
1085        QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
1086        QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
1087};
1088
1089static const struct qmp_phy_init_tbl qmp_v3_usb3_tx_tbl[] = {
1090        QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
1091        QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
1092        QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16),
1093        QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x09),
1094        QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
1095};
1096
1097static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl[] = {
1098        QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
1099        QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x37),
1100        QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
1101        QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x0e),
1102        QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06),
1103        QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
1104        QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x02),
1105        QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x00),
1106        QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
1107        QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
1108        QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
1109        QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
1110        QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
1111        QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
1112        QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_CTRL, 0x00),
1113        QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x3f),
1114        QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x1f),
1115        QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
1116        QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
1117        QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
1118        QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
1119};
1120
1121static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_rbr[] = {
1122        QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x0c),
1123        QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69),
1124        QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80),
1125        QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07),
1126        QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x6f),
1127        QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x08),
1128        QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00),
1129};
1130
1131static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr[] = {
1132        QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x04),
1133        QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69),
1134        QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80),
1135        QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07),
1136        QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x0f),
1137        QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0e),
1138        QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00),
1139};
1140
1141static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr2[] = {
1142        QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
1143        QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x8c),
1144        QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x00),
1145        QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x0a),
1146        QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x1f),
1147        QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x1c),
1148        QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00),
1149};
1150
1151static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr3[] = {
1152        QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x03),
1153        QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69),
1154        QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80),
1155        QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07),
1156        QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x2f),
1157        QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x2a),
1158        QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x08),
1159};
1160
1161static const struct qmp_phy_init_tbl qmp_v3_dp_tx_tbl[] = {
1162        QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRANSCEIVER_BIAS_EN, 0x1a),
1163        QMP_PHY_INIT_CFG(QSERDES_V3_TX_VMODE_CTRL1, 0x40),
1164        QMP_PHY_INIT_CFG(QSERDES_V3_TX_PRE_STALL_LDO_BOOST_EN, 0x30),
1165        QMP_PHY_INIT_CFG(QSERDES_V3_TX_INTERFACE_SELECT, 0x3d),
1166        QMP_PHY_INIT_CFG(QSERDES_V3_TX_CLKBUF_ENABLE, 0x0f),
1167        QMP_PHY_INIT_CFG(QSERDES_V3_TX_RESET_TSYNC_EN, 0x03),
1168        QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRAN_DRVR_EMP_EN, 0x03),
1169        QMP_PHY_INIT_CFG(QSERDES_V3_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00),
1170        QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_INTERFACE_MODE, 0x00),
1171        QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_BAND, 0x4),
1172        QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_POL_INV, 0x0a),
1173        QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_DRV_LVL, 0x38),
1174        QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_EMP_POST1_LVL, 0x20),
1175        QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
1176        QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x07),
1177};
1178
1179static const struct qmp_phy_init_tbl qmp_v3_usb3_rx_tbl[] = {
1180        QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
1181        QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
1182        QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
1183        QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
1184        QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
1185        QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
1186        QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
1187        QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
1188        QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
1189};
1190
1191static const struct qmp_phy_init_tbl qmp_v3_usb3_pcs_tbl[] = {
1192        /* FLL settings */
1193        QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
1194        QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
1195        QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
1196        QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
1197        QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
1198
1199        /* Lock Det settings */
1200        QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
1201        QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
1202        QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
1203        QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
1204
1205        QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba),
1206        QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
1207        QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
1208        QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7),
1209        QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e),
1210        QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65),
1211        QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b),
1212        QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
1213        QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
1214        QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15),
1215        QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
1216        QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
1217        QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
1218        QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
1219        QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d),
1220        QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
1221        QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
1222        QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
1223        QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
1224
1225        QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
1226        QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
1227        QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
1228        QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
1229        QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
1230        QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
1231        QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
1232        QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
1233        QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
1234        QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
1235        QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
1236};
1237
1238static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_serdes_tbl[] = {
1239        QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
1240        QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
1241        QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
1242        QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
1243        QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
1244        QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
1245        QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
1246        QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
1247        QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
1248        QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
1249        QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
1250        QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
1251        QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
1252        QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
1253        QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
1254        QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
1255        QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
1256        QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
1257        QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
1258        QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
1259        QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
1260        QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
1261        QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
1262        QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
1263        QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
1264        QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
1265        QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
1266        QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
1267        QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a),
1268        QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
1269        QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
1270        QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
1271        QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
1272        QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
1273        QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
1274        QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
1275};
1276
1277static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_tx_tbl[] = {
1278        QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
1279        QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
1280        QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0xc6),
1281        QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x06),
1282        QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
1283};
1284
1285static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_rx_tbl[] = {
1286        QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x0c),
1287        QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x50),
1288        QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
1289        QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
1290        QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
1291        QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
1292        QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
1293        QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
1294        QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
1295        QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1c),
1296        QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
1297};
1298
1299static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_pcs_tbl[] = {
1300        /* FLL settings */
1301        QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
1302        QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
1303        QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
1304        QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
1305        QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
1306
1307        /* Lock Det settings */
1308        QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
1309        QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
1310        QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
1311        QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
1312
1313        QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba),
1314        QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
1315        QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
1316        QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb5),
1317        QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4c),
1318        QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x64),
1319        QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6a),
1320        QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
1321        QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
1322        QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15),
1323        QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
1324        QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
1325        QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
1326        QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
1327        QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d),
1328        QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
1329        QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
1330        QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
1331        QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
1332
1333        QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
1334        QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
1335        QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
1336        QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
1337        QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
1338        QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
1339        QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
1340        QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
1341        QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
1342        QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
1343        QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
1344
1345        QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x21),
1346        QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG2, 0x60),
1347};
1348
1349static const struct qmp_phy_init_tbl sm6115_ufsphy_serdes_tbl[] = {
1350        QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e),
1351        QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
1352        QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
1353        QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x02),
1354        QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
1355        QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
1356        QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
1357        QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
1358        QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV_MODE1, 0x0a),
1359        QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x01),
1360        QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x00),
1361        QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
1362        QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
1363        QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
1364        QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
1365        QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x3f),
1366        QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x04),
1367        QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x05),
1368        QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
1369        QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00),
1370        QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x00),
1371        QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x00),
1372        QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
1373        QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
1374        QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
1375        QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
1376        QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
1377        QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE0, 0x28),
1378        QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE0, 0x02),
1379        QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xff),
1380        QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x0c),
1381        QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
1382        QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE1, 0x98),
1383        QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE1, 0x00),
1384        QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE1, 0x00),
1385        QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE1, 0x00),
1386        QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE1, 0x0b),
1387        QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE1, 0x16),
1388        QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE1, 0x28),
1389        QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE1, 0x80),
1390        QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
1391        QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE1, 0xd6),
1392        QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE1, 0x00),
1393        QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE1, 0x32),
1394        QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE1, 0x0f),
1395        QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE1, 0x00),
1396        QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
1397        QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
1398        QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_INITVAL1, 0xff),
1399        QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_INITVAL2, 0x00),
1400
1401        /* Rate B */
1402        QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x44),
1403};
1404
1405static const struct qmp_phy_init_tbl sm6115_ufsphy_tx_tbl[] = {
1406        QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
1407        QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
1408};
1409
1410static const struct qmp_phy_init_tbl sm6115_ufsphy_rx_tbl[] = {
1411        QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x24),
1412        QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x0F),
1413        QMP_PHY_INIT_CFG(QSERDES_RX_RX_INTERFACE_MODE, 0x40),
1414        QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x1E),
1415        QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0B),
1416        QMP_PHY_INIT_CFG(QSERDES_RX_RX_TERM_BW, 0x5B),
1417        QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_LSB, 0xFF),
1418        QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_MSB, 0x3F),
1419        QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_LSB, 0xFF),
1420        QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_MSB, 0x3F),
1421        QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0D),
1422        QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN_HALF, 0x04),
1423        QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN_QUARTER, 0x04),
1424        QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN, 0x04),
1425        QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5B),
1426};
1427
1428static const struct qmp_phy_init_tbl sm6115_ufsphy_pcs_tbl[] = {
1429        QMP_PHY_INIT_CFG(QPHY_RX_PWM_GEAR_BAND, 0x15),
1430        QMP_PHY_INIT_CFG(QPHY_RX_SIGDET_CTRL2, 0x6d),
1431        QMP_PHY_INIT_CFG(QPHY_TX_LARGE_AMP_DRV_LVL, 0x0f),
1432        QMP_PHY_INIT_CFG(QPHY_TX_SMALL_AMP_DRV_LVL, 0x02),
1433        QMP_PHY_INIT_CFG(QPHY_RX_MIN_STALL_NOCONFIG_TIME_CAP, 0x28),
1434        QMP_PHY_INIT_CFG(QPHY_RX_SYM_RESYNC_CTRL, 0x03),
1435        QMP_PHY_INIT_CFG(QPHY_TX_LARGE_AMP_POST_EMP_LVL, 0x12),
1436        QMP_PHY_INIT_CFG(QPHY_TX_SMALL_AMP_POST_EMP_LVL, 0x0f),
1437        QMP_PHY_INIT_CFG(QPHY_RX_MIN_HIBERN8_TIME, 0x9a), /* 8 us */
1438};
1439
1440static const struct qmp_phy_init_tbl sdm845_ufsphy_serdes_tbl[] = {
1441        QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
1442        QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
1443        QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
1444        QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
1445        QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
1446        QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0xd5),
1447        QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
1448        QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
1449        QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
1450        QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
1451        QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_CTRL, 0x00),
1452        QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
1453        QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x04),
1454        QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x05),
1455        QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_INITVAL1, 0xff),
1456        QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_INITVAL2, 0x00),
1457        QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
1458        QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
1459        QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
1460        QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
1461        QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
1462        QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
1463        QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xda),
1464        QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
1465        QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0xff),
1466        QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0c),
1467        QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE1, 0x98),
1468        QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE1, 0x06),
1469        QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE1, 0x16),
1470        QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE1, 0x36),
1471        QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE1, 0x3f),
1472        QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
1473        QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE1, 0xc1),
1474        QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE1, 0x00),
1475        QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE1, 0x32),
1476        QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE1, 0x0f),
1477
1478        /* Rate B */
1479        QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x44),
1480};
1481
1482static const struct qmp_phy_init_tbl sdm845_ufsphy_tx_tbl[] = {
1483        QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
1484        QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x04),
1485        QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x07),
1486};
1487
1488static const struct qmp_phy_init_tbl sdm845_ufsphy_rx_tbl[] = {
1489        QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_LVL, 0x24),
1490        QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x0f),
1491        QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
1492        QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
1493        QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
1494        QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_TERM_BW, 0x5b),
1495        QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
1496        QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
1497        QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1b),
1498        QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_HALF, 0x04),
1499        QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_QUARTER, 0x04),
1500        QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN, 0x04),
1501        QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
1502        QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x81),
1503        QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
1504        QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59),
1505};
1506
1507static const struct qmp_phy_init_tbl sdm845_ufsphy_pcs_tbl[] = {
1508        QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_CTRL2, 0x6e),
1509        QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL, 0x0a),
1510        QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_SMALL_AMP_DRV_LVL, 0x02),
1511        QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SYM_RESYNC_CTRL, 0x03),
1512        QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_MID_TERM_CTRL1, 0x43),
1513        QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_CTRL1, 0x0f),
1514        QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_MIN_HIBERN8_TIME, 0x9a),
1515        QMP_PHY_INIT_CFG(QPHY_V3_PCS_MULTI_LANE_CTRL1, 0x02),
1516};
1517
1518static const struct qmp_phy_init_tbl msm8998_usb3_serdes_tbl[] = {
1519        QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
1520        QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
1521        QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
1522        QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x06),
1523        QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
1524        QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
1525        QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
1526        QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
1527        QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
1528        QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
1529        QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
1530        QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
1531        QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
1532        QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
1533        QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
1534        QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
1535        QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
1536        QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
1537        QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
1538        QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
1539        QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
1540        QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
1541        QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
1542        QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
1543        QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
1544        QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
1545        QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
1546        QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
1547        QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
1548        QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_INITVAL, 0x80),
1549        QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_MODE, 0x01),
1550        QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
1551        QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
1552        QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
1553        QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
1554        QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
1555        QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
1556        QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
1557};
1558
1559static const struct qmp_phy_init_tbl msm8998_usb3_tx_tbl[] = {
1560        QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
1561        QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
1562        QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16),
1563        QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x00),
1564};
1565
1566static const struct qmp_phy_init_tbl msm8998_usb3_rx_tbl[] = {
1567        QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
1568        QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
1569        QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
1570        QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
1571        QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x07),
1572        QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
1573        QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x43),
1574        QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1c),
1575        QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
1576        QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00),
1577        QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x00),
1578        QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x80),
1579        QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FO_GAIN, 0x0a),
1580        QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x06),
1581        QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x00),
1582        QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x03),
1583        QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x05),
1584};
1585
1586static const struct qmp_phy_init_tbl msm8998_usb3_pcs_tbl[] = {
1587        QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
1588        QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
1589        QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
1590        QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
1591        QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
1592        QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
1593        QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
1594        QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
1595        QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
1596        QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
1597        QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
1598        QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7),
1599        QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e),
1600        QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65),
1601        QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b),
1602        QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
1603        QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
1604        QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL, 0x15),
1605        QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
1606        QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
1607        QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
1608        QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
1609        QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x0d),
1610        QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
1611        QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
1612        QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
1613        QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
1614        QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
1615        QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
1616        QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
1617        QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
1618        QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
1619        QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
1620        QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
1621        QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x8a),
1622        QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
1623        QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
1624        QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
1625};
1626
1627static const struct qmp_phy_init_tbl sm8150_ufsphy_serdes_tbl[] = {
1628        QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0xd9),
1629        QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x11),
1630        QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00),
1631        QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x01),
1632        QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
1633        QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
1634        QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_INITVAL2, 0x00),
1635        QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
1636        QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
1637        QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
1638        QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
1639        QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
1640        QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0xff),
1641        QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x0c),
1642        QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xac),
1643        QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
1644        QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x98),
1645        QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
1646        QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
1647        QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
1648        QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x32),
1649        QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x0f),
1650        QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xdd),
1651        QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23),
1652
1653        /* Rate B */
1654        QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x06),
1655};
1656
1657static const struct qmp_phy_init_tbl sm8150_ufsphy_tx_tbl[] = {
1658        QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06),
1659        QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03),
1660        QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01),
1661        QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00),
1662        QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x05),
1663        QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0c),
1664};
1665
1666static const struct qmp_phy_init_tbl sm8150_ufsphy_rx_tbl[] = {
1667        QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_LVL, 0x24),
1668        QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x0f),
1669        QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
1670        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_BAND, 0x18),
1671        QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a),
1672        QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
1673        QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0xf1),
1674        QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
1675        QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CTRL2, 0x80),
1676        QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
1677        QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04),
1678        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_TERM_BW, 0x1b),
1679        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
1680        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
1681        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1d),
1682        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00),
1683        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_MEASURE_TIME, 0x10),
1684        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
1685        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
1686        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x36),
1687        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x36),
1688        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xf6),
1689        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x3b),
1690        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x3d),
1691        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xe0),
1692        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xc8),
1693        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xc8),
1694        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b),
1695        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb1),
1696        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xe0),
1697        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0xc8),
1698        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8),
1699        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b),
1700        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1),
1701
1702};
1703
1704static const struct qmp_phy_init_tbl sm8150_ufsphy_pcs_tbl[] = {
1705        QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_SIGDET_CTRL2, 0x6d),
1706        QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a),
1707        QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02),
1708        QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
1709        QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_DEBUG_BUS_CLKSEL, 0x1f),
1710        QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff),
1711        QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
1712};
1713
1714static const struct qmp_phy_init_tbl sm8150_usb3_serdes_tbl[] = {
1715        QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
1716        QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
1717        QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
1718        QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
1719        QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
1720        QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0xde),
1721        QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x07),
1722        QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x0a),
1723        QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_IPTRIM, 0x20),
1724        QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
1725        QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
1726        QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
1727        QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
1728        QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
1729        QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
1730        QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x1a),
1731        QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04),
1732        QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x14),
1733        QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x34),
1734        QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x34),
1735        QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x82),
1736        QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
1737        QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x82),
1738        QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0xab),
1739        QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0xea),
1740        QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x02),
1741        QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
1742        QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
1743        QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xea),
1744        QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
1745        QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
1746        QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0x24),
1747        QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x02),
1748        QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
1749        QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
1750        QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
1751        QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
1752        QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca),
1753        QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e),
1754        QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
1755};
1756
1757static const struct qmp_phy_init_tbl sm8150_usb3_tx_tbl[] = {
1758        QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_TX, 0x00),
1759        QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_RX, 0x00),
1760        QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
1761        QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
1762        QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20),
1763};
1764
1765static const struct qmp_phy_init_tbl sm8150_usb3_rx_tbl[] = {
1766        QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x05),
1767        QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
1768        QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
1769        QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
1770        QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
1771        QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
1772        QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
1773        QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
1774        QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
1775        QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
1776        QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
1777        QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0e),
1778        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
1779        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
1780        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
1781        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
1782        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
1783        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
1784        QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
1785        QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
1786        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xbf),
1787        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xbf),
1788        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x3f),
1789        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
1790        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x94),
1791        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
1792        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
1793        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
1794        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x0b),
1795        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb3),
1796        QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
1797        QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
1798        QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
1799        QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
1800        QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
1801        QMP_PHY_INIT_CFG(QSERDES_V4_RX_VTH_CODE, 0x10),
1802};
1803
1804static const struct qmp_phy_init_tbl sm8150_usb3_pcs_tbl[] = {
1805        /* Lock Det settings */
1806        QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
1807        QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
1808        QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
1809
1810        QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
1811        QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
1812        QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
1813        QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
1814        QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
1815        QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
1816        QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
1817        QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
1818        QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
1819        QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
1820};
1821
1822static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_serdes_tbl[] = {
1823        QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x1a),
1824        QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
1825        QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
1826        QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
1827        QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0xab),
1828        QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0xea),
1829        QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x02),
1830        QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
1831        QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
1832        QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
1833        QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
1834        QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
1835        QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
1836        QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x34),
1837        QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x14),
1838        QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04),
1839        QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x0a),
1840        QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x02),
1841        QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0x24),
1842        QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
1843        QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x82),
1844        QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
1845        QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xea),
1846        QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
1847        QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x82),
1848        QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x34),
1849        QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
1850        QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
1851        QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
1852        QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca),
1853        QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e),
1854        QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_IPTRIM, 0x20),
1855        QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
1856        QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
1857        QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
1858        QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0xde),
1859        QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x07),
1860        QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
1861        QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
1862        QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
1863};
1864
1865static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_tx_tbl[] = {
1866        QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
1867        QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x95),
1868        QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x40),
1869        QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x05),
1870};
1871
1872static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_rx_tbl[] = {
1873        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0xb8),
1874        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
1875        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x37),
1876        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x2f),
1877        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xef),
1878        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb3),
1879        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x0b),
1880        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
1881        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
1882        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
1883        QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
1884        QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
1885        QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
1886        QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
1887        QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
1888        QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
1889        QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
1890        QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
1891        QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
1892        QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x08),
1893        QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
1894        QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
1895        QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
1896        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
1897        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
1898        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
1899        QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
1900        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
1901        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
1902        QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
1903        QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
1904        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
1905        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
1906        QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x20),
1907        QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04),
1908        QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
1909};
1910
1911static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_pcs_tbl[] = {
1912        QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
1913        QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
1914        QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
1915        QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
1916        QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
1917        QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
1918        QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
1919        QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2, 0x07),
1920        QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
1921        QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0f),
1922        QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
1923        QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
1924        QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
1925        QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
1926        QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
1927        QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
1928};
1929
1930static const struct qmp_phy_init_tbl sm8250_usb3_tx_tbl[] = {
1931        QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_TX, 0x60),
1932        QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_RX, 0x60),
1933        QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
1934        QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x02),
1935        QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
1936        QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
1937        QMP_PHY_INIT_CFG_LANE(QSERDES_V4_TX_PI_QEC_CTRL, 0x40, 1),
1938        QMP_PHY_INIT_CFG_LANE(QSERDES_V4_TX_PI_QEC_CTRL, 0x54, 2),
1939};
1940
1941static const struct qmp_phy_init_tbl sm8250_usb3_rx_tbl[] = {
1942        QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x06),
1943        QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
1944        QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
1945        QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
1946        QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
1947        QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
1948        QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
1949        QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
1950        QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
1951        QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
1952        QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
1953        QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
1954        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
1955        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
1956        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
1957        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
1958        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
1959        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
1960        QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
1961        QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
1962        QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_LOW, 0xff, 1),
1963        QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f, 2),
1964        QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f, 1),
1965        QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff, 2),
1966        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x7f),
1967        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
1968        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x97),
1969        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
1970        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
1971        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
1972        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b),
1973        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4),
1974        QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
1975        QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
1976        QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
1977        QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
1978        QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
1979        QMP_PHY_INIT_CFG(QSERDES_V4_RX_VTH_CODE, 0x10),
1980};
1981
1982static const struct qmp_phy_init_tbl sm8250_usb3_pcs_tbl[] = {
1983        QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
1984        QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
1985        QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
1986        QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
1987        QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
1988        QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xa9),
1989        QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
1990        QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
1991        QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
1992        QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
1993        QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
1994        QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
1995        QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
1996        QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
1997};
1998
1999static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_tx_tbl[] = {
2000        QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),

2001        QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
2002        QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_2, 0x82),
2003        QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x40),
2004        QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
2005        QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x02),
2006};
2007
2008static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_rx_tbl[] = {
2009        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0xb8),
2010        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xff),
2011        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xbf),
2012        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f),
2013        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f),
2014        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4),
2015        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b),
2016        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
2017        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
2018        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
2019        QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
2020        QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
2021        QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
2022        QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
2023        QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
2024        QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
2025        QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
2026        QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
2027        QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
2028        QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0a),
2029        QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
2030        QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
2031        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
2032        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
2033        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
2034        QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
2035        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
2036        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
2037        QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
2038        QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
2039        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
2040        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
2041        QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
2042        QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x06),
2043        QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
2044        QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
2045};
2046
2047static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_pcs_tbl[] = {
2048        QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
2049        QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
2050        QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
2051        QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
2052        QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
2053        QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
2054        QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xa9),
2055        QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
2056        QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2, 0x07),
2057        QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
2058        QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
2059        QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
2060        QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
2061        QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
2062        QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
2063        QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
2064};
2065
2066static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl[] = {
2067        QMP_PHY_INIT_CFG(QSERDES_V4_COM_SVS_MODE_CLK_SEL, 0x05),
2068        QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x3b),
2069        QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x02),
2070        QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x0c),
2071        QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x06),
2072        QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x30),
2073        QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
2074        QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
2075        QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
2076        QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
2077        QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x02),
2078        QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
2079        QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
2080        QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x00),
2081        QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x00),
2082        QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x0a),
2083        QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x0a),
2084        QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_CTRL, 0x00),
2085        QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x17),
2086        QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORE_CLK_EN, 0x1f),
2087};
2088
2089static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_rbr[] = {
2090        QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x05),
2091        QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69),
2092        QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80),
2093        QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07),
2094        QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x6f),
2095        QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x08),
2096        QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04),
2097};
2098
2099static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr[] = {
2100        QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x03),
2101        QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69),
2102        QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80),
2103        QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07),
2104        QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0f),
2105        QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x0e),
2106        QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08),
2107};
2108
2109static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr2[] = {
2110        QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
2111        QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x8c),
2112        QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x00),
2113        QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x0a),
2114        QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x1f),
2115        QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1c),
2116        QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08),
2117};
2118
2119static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr3[] = {
2120        QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x00),
2121        QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69),
2122        QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80),
2123        QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07),
2124        QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x2f),
2125        QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x2a),
2126        QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08),
2127};
2128
2129static const struct qmp_phy_init_tbl qmp_v4_dp_tx_tbl[] = {
2130        QMP_PHY_INIT_CFG(QSERDES_V4_TX_VMODE_CTRL1, 0x40),
2131        QMP_PHY_INIT_CFG(QSERDES_V4_TX_PRE_STALL_LDO_BOOST_EN, 0x30),
2132        QMP_PHY_INIT_CFG(QSERDES_V4_TX_INTERFACE_SELECT, 0x3b),
2133        QMP_PHY_INIT_CFG(QSERDES_V4_TX_CLKBUF_ENABLE, 0x0f),
2134        QMP_PHY_INIT_CFG(QSERDES_V4_TX_RESET_TSYNC_EN, 0x03),
2135        QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0f),
2136        QMP_PHY_INIT_CFG(QSERDES_V4_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00),
2137        QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_INTERFACE_MODE, 0x00),
2138        QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
2139        QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x11),
2140        QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_BAND, 0x4),
2141        QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_POL_INV, 0x0a),
2142        QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_DRV_LVL, 0x2a),
2143        QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_EMP_POST1_LVL, 0x20),
2144};
2145
2146static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_serdes_tbl[] = {
2147        QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08),
2148        QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34),
2149        QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
2150        QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
2151        QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x42),
2152        QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
2153        QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x03),
2154        QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0xb4),
2155        QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
2156        QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
2157        QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
2158        QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x03),
2159        QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x55),
2160        QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x55),
2161        QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1a),
2162        QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0a),
2163        QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x68),
2164        QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
2165        QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xaa),
2166        QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
2167        QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x34),
2168        QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x14),
2169        QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
2170        QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
2171        QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
2172        QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
2173        QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
2174        QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
2175        QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
2176        QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
2177        QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
2178        QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18),
2179        QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2),
2180        QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x07),
2181        QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
2182        QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
2183        QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
2184        QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
2185        QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
2186        QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
2187        QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x06),
2188        QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90),
2189};
2190
2191static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_tx_tbl[] = {
2192        QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
2193        QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x5),
2194};
2195
2196static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_rx_tbl[] = {
2197        QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03),
2198        QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c),
2199        QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
2200        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x07),
2201        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x6e),
2202        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x6e),
2203        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x4a),
2204        QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
2205        QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
2206        QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70),
2207        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
2208        QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
2209        QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x37),
2210        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xd4),
2211        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x54),
2212        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xdb),
2213        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x39),
2214        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0x31),
2215        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x24),
2216        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xe4),
2217        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xec),
2218        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x39),
2219        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x36),
2220        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f),
2221        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff),
2222        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff),
2223        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xdb),
2224        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x75),
2225        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
2226        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
2227        QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
2228        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RCLK_AUXDATA_SEL, 0xc0),
2229        QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
2230        QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x05),
2231        QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
2232        QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x03),
2233};
2234
2235static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_pcs_tbl[] = {
2236        QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
2237        QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
2238        QMP_PHY_INIT_CFG(QPHY_V4_PCS_RATE_SLEW_CNTRL1, 0x0b),
2239        QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d),
2240        QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x01),
2241};
2242
2243static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_pcs_misc_tbl[] = {
2244        QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
2245        QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
2246        QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
2247        QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
2248        QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00),
2249        QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58),
2250        QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
2251};
2252
2253static const struct qmp_phy_init_tbl sm8250_qmp_pcie_serdes_tbl[] = {
2254        QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08),
2255        QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34),
2256        QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
2257        QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
2258        QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x42),
2259        QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
2260        QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x03),
2261        QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0xb4),
2262        QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
2263        QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
2264        QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
2265        QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x03),
2266        QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x55),
2267        QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x55),
2268        QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1a),
2269        QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0a),
2270        QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x68),
2271        QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
2272        QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xaa),
2273        QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
2274        QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x34),
2275        QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x14),
2276        QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
2277        QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
2278        QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
2279        QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
2280        QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
2281        QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
2282        QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
2283        QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
2284        QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
2285        QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18),
2286        QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2),
2287        QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
2288        QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
2289        QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
2290        QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
2291        QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
2292        QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
2293        QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x06),
2294        QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90),
2295};
2296
2297static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_serdes_tbl[] = {
2298        QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x07),
2299};
2300
2301static const struct qmp_phy_init_tbl sm8250_qmp_pcie_tx_tbl[] = {
2302        QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
2303        QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x35),
2304        QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
2305};
2306
2307static const struct qmp_phy_init_tbl sm8250_qmp_pcie_rx_tbl[] = {
2308        QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
2309        QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x03),
2310        QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1b),
2311        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
2312        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
2313        QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0x30),
2314        QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x04),
2315        QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x07),
2316        QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
2317        QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70),
2318        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
2319        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
2320        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0f),
2321        QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03),
2322        QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c),
2323        QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
2324        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
2325        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xd4),
2326        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x54),
2327        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xdb),
2328        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b),
2329        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0x31),
2330        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x24),
2331        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff),
2332        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
2333        QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
2334        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xe4),
2335        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xec),
2336        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b),
2337        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x36),
2338};
2339
2340static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_rx_tbl[] = {
2341        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RCLK_AUXDATA_SEL, 0x00),
2342        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x00),
2343        QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
2344        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x3f),
2345        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x14),
2346        QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x30),
2347};
2348
2349static const struct qmp_phy_init_tbl sm8250_qmp_pcie_pcs_tbl[] = {
2350        QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
2351        QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0x77),
2352        QMP_PHY_INIT_CFG(QPHY_V4_PCS_RATE_SLEW_CNTRL1, 0x0b),
2353};
2354
2355static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_pcs_tbl[] = {
2356        QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d),
2357        QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x12),
2358};
2359
2360static const struct qmp_phy_init_tbl sm8250_qmp_pcie_pcs_misc_tbl[] = {
2361        QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
2362        QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
2363        QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
2364        QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P6_P7_PRE, 0x33),
2365        QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00),
2366        QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58),
2367        QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
2368};
2369
2370static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_pcs_misc_tbl[] = {
2371        QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
2372        QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG2, 0x0f),
2373};
2374
2375static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_tx_tbl[] = {
2376        QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20),
2377};
2378
2379static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_rx_tbl[] = {
2380        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04),
2381        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xbf),
2382        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x15),
2383        QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
2384};
2385
2386static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_pcs_tbl[] = {
2387        QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x05),
2388        QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG2, 0x0f),
2389};
2390
2391static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_pcs_misc_tbl[] = {
2392        QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG2, 0x0d),
2393        QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
2394};
2395
2396static const struct qmp_phy_init_tbl sdx55_usb3_uniphy_tx_tbl[] = {
2397        QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
2398        QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
2399        QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_2, 0x80),
2400        QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20),
2401        QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x08),
2402};
2403
2404static const struct qmp_phy_init_tbl sdx55_usb3_uniphy_rx_tbl[] = {
2405        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x26),
2406        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
2407        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xbf),
2408        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f),
2409        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f),
2410        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4),
2411        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b),
2412        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
2413        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
2414        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
2415        QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
2416        QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x048),
2417        QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
2418        QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x00),
2419        QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x04),
2420        QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
2421        QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
2422        QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
2423        QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
2424        QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x09),
2425        QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
2426        QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
2427        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
2428        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
2429        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
2430        QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
2431        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
2432        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
2433        QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
2434        QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
2435        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
2436        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
2437        QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
2438        QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x05),
2439        QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
2440        QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
2441};
2442
2443static const struct qmp_phy_init_tbl sdx55_qmp_pcie_serdes_tbl[] = {
2444        QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x02),
2445        QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x18),
2446        QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x07),
2447        QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
2448        QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x0a),
2449        QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x0a),
2450        QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x19),
2451        QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x19),
2452        QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x03),
2453        QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x03),
2454        QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x00),
2455        QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x46),
2456        QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_CFG, 0x04),
2457        QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x7f),
2458        QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x02),
2459        QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0xff),
2460        QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x04),
2461        QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x4b),
2462        QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x50),
2463        QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x00),
2464        QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0xfb),
2465        QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x01),
2466        QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE1, 0xfb),
2467        QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE1, 0x01),
2468        QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
2469        QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x12),
2470        QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00),
2471        QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x05),
2472        QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x04),
2473        QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x04),
2474        QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MISC1, 0x88),
2475        QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTERNAL_DIG_CORECLK_DIV, 0x03),
2476        QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MODE, 0x17),
2477        QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_DC_LEVEL_CTRL, 0x0b),
2478        QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x56),
2479        QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1d),
2480        QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0x4b),
2481        QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1f),
2482        QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x22),
2483};
2484
2485static const struct qmp_phy_init_tbl sdx55_qmp_pcie_tx_tbl[] = {
2486        QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_1, 0x05),
2487        QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_2, 0xf6),
2488        QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_3, 0x13),
2489        QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_VMODE_CTRL1, 0x00),
2490        QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_PI_QEC_CTRL, 0x00),
2491};
2492
2493static const struct qmp_phy_init_tbl sdx55_qmp_pcie_rx_tbl[] = {
2494        QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_FO_GAIN_RATE2, 0x0c),
2495        QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_UCDR_PI_CONTROLS, 0x16),
2496        QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_AUX_DATA_TCOARSE_TFINE, 0x7f),
2497        QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_3, 0x55),
2498        QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_DAC_ENABLE1, 0x0c),
2499        QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_DAC_ENABLE2, 0x00),
2500        QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_VGA_CAL_CNTRL2, 0x08),
2501        QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x27),
2502        QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B1, 0x1a),
2503        QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B2, 0x5a),
2504        QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B3, 0x09),
2505        QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B4, 0x37),
2506        QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B0, 0xbd),
2507        QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B1, 0xf9),
2508        QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B2, 0xbf),
2509        QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B3, 0xce),
2510        QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B4, 0x62),
2511        QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B0, 0xbf),
2512        QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B1, 0x7d),
2513        QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B2, 0xbf),
2514        QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B3, 0xcf),
2515        QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B4, 0xd6),
2516        QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_PHPRE_CTRL, 0xa0),
2517        QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
2518        QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_MARG_COARSE_CTRL2, 0x12),
2519};
2520
2521static const struct qmp_phy_init_tbl sdx55_qmp_pcie_pcs_tbl[] = {
2522        QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_RX_SIGDET_LVL, 0x77),
2523        QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG2, 0x01),
2524        QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG4, 0x16),
2525        QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG5, 0x02),
2526};
2527
2528static const struct qmp_phy_init_tbl sdx55_qmp_pcie_pcs_misc_tbl[] = {
2529        QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_EQ_CONFIG1, 0x17),
2530        QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G3_RXEQEVAL_TIME, 0x13),
2531        QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_RXEQEVAL_TIME, 0x13),
2532        QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG2, 0x01),
2533        QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02),
2534        QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_SW_CTRL2, 0x00),
2535        QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_MX_CTRL2, 0x00),
2536};
2537
2538static const struct qmp_phy_init_tbl sdx65_usb3_uniphy_tx_tbl[] = {
2539        QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xa5),
2540        QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_2, 0x82),
2541        QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
2542        QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
2543        QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21),
2544        QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x1f),
2545        QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0b),
2546};
2547
2548static const struct qmp_phy_init_tbl sdx65_usb3_uniphy_rx_tbl[] = {
2549        QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdb),
2550        QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0xbd),
2551        QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xff),
2552        QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7f),
2553        QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xff),
2554        QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9),
2555        QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x7b),
2556        QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xe4),
2557        QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24),
2558        QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64),
2559        QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99),
2560        QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
2561        QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
2562        QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00),
2563        QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04),
2564        QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
2565        QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
2566        QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
2567        QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a),
2568        QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54),
2569        QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
2570        QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
2571        QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
2572        QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
2573        QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
2574        QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04),
2575        QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
2576        QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
2577        QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
2578        QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
2579        QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_ENABLES, 0x00),
2580};
2581
2582static const struct qmp_phy_init_tbl sm8350_ufsphy_serdes_tbl[] = {
2583        QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0xd9),
2584        QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x11),
2585        QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00),
2586        QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x42),
2587        QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
2588        QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
2589        QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_INITVAL2, 0x00),
2590        QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
2591        QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),
2592        QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x14),
2593        QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x18),
2594        QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x18),
2595        QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0xff),
2596        QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x19),
2597        QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xac),
2598        QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
2599        QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x98),
2600        QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x14),
2601        QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x18),
2602        QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x18),
2603        QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x65),
2604        QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x1e),
2605        QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xdd),
2606        QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23),
2607
2608        /* Rate B */
2609        QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x06),
2610};
2611
2612static const struct qmp_phy_init_tbl sm8350_ufsphy_tx_tbl[] = {
2613        QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06),
2614        QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03),
2615        QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01),
2616        QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00),
2617        QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xf5),
2618        QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
2619        QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x09),
2620        QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x09),
2621        QMP_PHY_INIT_CFG(QSERDES_V5_TX_TRAN_DRVR_EMP_EN, 0x0c),
2622};
2623
2624static const struct qmp_phy_init_tbl sm8350_ufsphy_rx_tbl[] = {
2625        QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_LVL, 0x24),
2626        QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x0f),
2627        QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
2628        QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_BAND, 0x18),
2629        QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a),
2630        QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5a),
2631        QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf1),
2632        QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
2633        QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CTRL2, 0x80),
2634        QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0e),
2635        QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x04),
2636        QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_TERM_BW, 0x1b),
2637        QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04),
2638        QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
2639        QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
2640        QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a),
2641        QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
2642        QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00),
2643        QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_MEASURE_TIME, 0x10),
2644        QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
2645        QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
2646        QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x6d),
2647        QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x6d),
2648        QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xed),
2649        QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3b),
2650        QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0x3c),
2651        QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xe0),
2652        QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xc8),
2653        QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xc8),
2654        QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x3b),
2655        QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xb7),
2656        QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_LOW, 0xe0),
2657        QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH, 0xc8),
2658        QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH2, 0xc8),
2659        QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x3b),
2660        QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH4, 0xb7),
2661        QMP_PHY_INIT_CFG(QSERDES_V5_RX_DCC_CTRL1, 0x0c),
2662};
2663
2664static const struct qmp_phy_init_tbl sm8350_ufsphy_pcs_tbl[] = {
2665        QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_SIGDET_CTRL2, 0x6d),
2666        QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a),
2667        QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02),
2668        QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
2669        QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_DEBUG_BUS_CLKSEL, 0x1f),
2670        QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff),
2671        QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_PLL_CNTL, 0x03),
2672        QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB, 0x16),
2673        QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB, 0xd8),
2674        QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_PWM_GEAR_BAND, 0xaa),
2675        QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_HS_GEAR_BAND, 0x06),
2676        QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x03),
2677        QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x03),
2678        QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_SIGDET_CTRL1, 0x0e),
2679        QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
2680};
2681
2682static const struct qmp_phy_init_tbl sm8350_usb3_tx_tbl[] = {
2683        QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_TX, 0x00),
2684        QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_RX, 0x00),
2685        QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x16),
2686        QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0e),
2687        QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x35),
2688        QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
2689        QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x7f),
2690        QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_5, 0x3f),
2691        QMP_PHY_INIT_CFG(QSERDES_V5_TX_RCV_DETECT_LVL_2, 0x12),
2692        QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21),
2693};
2694
2695static const struct qmp_phy_init_tbl sm8350_usb3_rx_tbl[] = {
2696        QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a),
2697        QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
2698        QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
2699        QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
2700        QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
2701        QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
2702        QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99),
2703        QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
2704        QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
2705        QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00),
2706        QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04),
2707        QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54),
2708        QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
2709        QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
2710        QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
2711        QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
2712        QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
2713        QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
2714        QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
2715        QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04),
2716        QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
2717        QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xbb),
2718        QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7b),
2719        QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbb),
2720        QMP_PHY_INIT_CFG_LANE(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3d, 1),
2721        QMP_PHY_INIT_CFG_LANE(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3c, 2),
2722        QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdb),
2723        QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64),
2724        QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24),
2725        QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xd2),
2726        QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x13),
2727        QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9),
2728        QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_EN_TIMER, 0x04),
2729        QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
2730        QMP_PHY_INIT_CFG(QSERDES_V5_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
2731        QMP_PHY_INIT_CFG(QSERDES_V5_RX_DCC_CTRL1, 0x0c),
2732        QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
2733        QMP_PHY_INIT_CFG(QSERDES_V5_RX_VTH_CODE, 0x10),
2734};
2735
2736static const struct qmp_phy_init_tbl sm8350_usb3_pcs_tbl[] = {
2737        QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_L, 0x40),
2738        QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_H, 0x00),
2739        QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
2740        QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
2741        QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
2742        QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
2743        QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
2744        QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
2745        QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
2746        QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
2747        QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
2748        QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
2749        QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
2750        QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
2751        QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
2752        QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
2753        QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
2754        QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
2755};
2756
2757static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_tx_tbl[] = {
2758        QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xa5),
2759        QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_2, 0x82),
2760        QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
2761        QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
2762        QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21),
2763        QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x10),
2764        QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0e),
2765};
2766
2767static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_rx_tbl[] = {
2768        QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdc),
2769        QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0xbd),
2770        QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xff),
2771        QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7f),
2772        QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xff),
2773        QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9),
2774        QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x7b),
2775        QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xe4),
2776        QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24),
2777        QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64),
2778        QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99),
2779        QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
2780        QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
2781        QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00),
2782        QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04),
2783        QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
2784        QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
2785        QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
2786        QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a),
2787        QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54),
2788        QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
2789        QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
2790        QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
2791        QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
2792        QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
2793        QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04),
2794        QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
2795        QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
2796        QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
2797        QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
2798        QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_ENABLES, 0x00),
2799};
2800
2801static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_pcs_tbl[] = {
2802        QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
2803        QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
2804        QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
2805        QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
2806        QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
2807        QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
2808        QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
2809        QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
2810        QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2, 0x07),
2811        QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
2812        QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
2813        QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
2814        QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
2815        QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
2816        QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
2817        QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
2818};
2819
2820static const struct qmp_phy_init_tbl qcm2290_usb3_serdes_tbl[] = {
2821        QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
2822        QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
2823        QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
2824        QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
2825        QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x00),
2826        QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL2, 0x08),
2827        QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
2828        QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
2829        QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
2830        QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
2831        QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
2832        QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
2833        QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
2834        QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
2835        QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
2836        QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
2837        QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
2838        QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
2839        QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
2840        QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),
2841        QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),
2842        QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
2843        QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x00),
2844        QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
2845        QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
2846        QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
2847        QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
2848        QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
2849        QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
2850        QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
2851        QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
2852        QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
2853        QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),
2854        QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),
2855        QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
2856        QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
2857        QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_INITVAL, 0x80),
2858        QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x01),
2859};
2860
2861static const struct qmp_phy_init_tbl qcm2290_usb3_tx_tbl[] = {
2862        QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
2863        QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
2864        QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0xc6),
2865        QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x00),
2866        QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x00),
2867};
2868
2869static const struct qmp_phy_init_tbl qcm2290_usb3_rx_tbl[] = {
2870        QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
2871        QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x00),
2872        QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00),
2873        QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x00),
2874        QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FO_GAIN, 0x0a),
2875        QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x06),
2876        QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
2877        QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
2878        QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
2879        QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
2880        QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
2881        QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
2882        QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x0a),
2883        QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
2884        QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
2885        QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x00),
2886        QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x00),
2887};
2888
2889static const struct qmp_phy_init_tbl qcm2290_usb3_pcs_tbl[] = {
2890        QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
2891        QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17),
2892        QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f),
2893        QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
2894        QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
2895        QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
2896        QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
2897        QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85),
2898        QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
2899        QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
2900        QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
2901        QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
2902        QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
2903        QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
2904        QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
2905        QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
2906        QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
2907        QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
2908        QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
2909        QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
2910        QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88),
2911};
2912
2913static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_serdes_tbl[] = {
2914        QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08),
2915        QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34),
2916        QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x08),
2917        QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
2918        QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x42),
2919        QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE0, 0x24),
2920        QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE2_MODE1, 0x03),
2921        QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE1, 0xb4),
2922        QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
2923        QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
2924        QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),
2925        QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03),
2926        QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55),
2927        QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55),
2928        QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a),
2929        QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a),
2930        QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x68),
2931        QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x02),
2932        QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0xaa),
2933        QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0xab),
2934        QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34),
2935        QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14),
2936        QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x01),
2937        QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06),
2938        QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16),
2939        QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36),
2940        QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06),
2941        QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16),
2942        QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36),
2943        QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
2944        QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
2945        QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18),
2946        QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2),
2947        QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_BUF_ENABLE, 0x07),
2948        QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x01),
2949        QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31),
2950        QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01),
2951        QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde),
2952        QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07),
2953        QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
2954        QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x06),
2955        QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90),
2956};
2957
2958static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_tx_tbl[] = {
2959        QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x20),
2960        QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x75),
2961        QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
2962        QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x16),
2963        QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x04),
2964};
2965
2966static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_rx_tbl[] = {
2967        QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x7f),
2968        QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0xff),
2969        QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbf),
2970        QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3f),
2971        QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xd8),
2972        QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xdc),
2973        QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xdc),
2974        QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0x5c),
2975        QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x34),
2976        QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa6),
2977        QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x34),
2978        QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH4, 0x38),
2979        QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x07),
2980        QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
2981        QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
2982        QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
2983        QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf0),
2984        QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
2985        QMP_PHY_INIT_CFG(QSERDES_V5_RX_TX_ADAPT_POST_THRESH, 0xf0),
2986        QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x07),
2987        QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x09),
2988        QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
2989};
2990
2991static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_pcs_tbl[] = {
2992        QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x77),
2993        QMP_PHY_INIT_CFG(QPHY_V5_PCS_RATE_SLEW_CNTRL1, 0x0b),
2994        QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x05),
2995};
2996
2997static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_pcs_misc_tbl[] = {
2998        QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
2999        QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
3000        QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_EQ_CONFIG2, 0x0f),

3001        QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
3002};
3003
3004static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_serdes_tbl[] = {
3005        QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31),
3006        QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01),
3007        QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde),
3008        QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07),
3009        QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x97),
3010        QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x0c),
3011        QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
3012        QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90),
3013        QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
3014        QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06),
3015        QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06),
3016        QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16),
3017        QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16),
3018        QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36),
3019        QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36),
3020        QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08),
3021        QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x46),
3022        QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_CFG, 0x04),
3023        QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a),
3024        QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a),
3025        QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14),
3026        QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34),
3027        QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),
3028        QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0xd0),
3029        QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55),
3030        QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55),
3031        QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03),
3032        QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0x55),
3033        QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0x55),
3034        QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x05),
3035        QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
3036        QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34),
3037        QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x12),
3038        QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00),
3039        QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE0, 0x0a),
3040        QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x04),
3041        QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MISC1, 0x88),
3042        QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORE_CLK_EN, 0x20),
3043        QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_CONFIG, 0x06),
3044        QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MODE, 0x14),
3045        QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_DC_LEVEL_CTRL, 0x0f),
3046};
3047
3048static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_tx_tbl[] = {
3049        QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_1, 0x05),
3050        QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_2, 0xf6),
3051        QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_TX, 0x1a),
3052        QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_RX, 0x0c),
3053};
3054
3055static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_rx_tbl[] = {
3056        QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_PI_CONTROLS, 0x16),
3057        QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
3058        QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B1, 0xcc),
3059        QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B2, 0x12),
3060        QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B3, 0xcc),
3061        QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B5, 0x4a),
3062        QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B6, 0x29),
3063        QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B0, 0xc5),
3064        QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B1, 0xad),
3065        QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B2, 0xb6),
3066        QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B3, 0xc0),
3067        QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B4, 0x1f),
3068        QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B5, 0xfb),
3069        QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B6, 0x0f),
3070        QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B0, 0xc7),
3071        QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B1, 0xef),
3072        QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B2, 0xbf),
3073        QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B3, 0xa0),
3074        QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B4, 0x81),
3075        QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B5, 0xde),
3076        QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B6, 0x7f),
3077        QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_PHPRE_CTRL, 0x20),
3078        QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_0_1, 0x3f),
3079        QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_2_3, 0x37),
3080
3081        QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_3, 0x05),
3082
3083        QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE3, 0x1f),
3084
3085        QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE3, 0x1f),
3086        QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE3, 0x1f),
3087        QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH4_RATE3, 0x1f),
3088        QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH5_RATE3, 0x1f),
3089        QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH6_RATE3, 0x1f),
3090        QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE210, 0x1f),
3091        QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE210, 0x1f),
3092        QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE210, 0x1f),
3093
3094        QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2, 0x0c),
3095        QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3, 0x0a),
3096        QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_MAN_VAL, 0x0a),
3097        QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0b),
3098        QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_IDAC_SAOFFSET, 0x10),
3099        QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_DAC_ENABLE1, 0x00),
3100        QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_GM_CAL, 0x0f),
3101        QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH1, 0x00),
3102        QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH2, 0x1f),
3103};
3104
3105/* Register names should be validated, they might be different for this PHY */
3106static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_pcs_tbl[] = {
3107        QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG2, 0x16),
3108        QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG3, 0x22),
3109        QMP_PHY_INIT_CFG(QPHY_V5_PCS_G3S2_PRE_GAIN, 0x2e),
3110        QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x99),
3111};
3112
3113static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_pcs_misc_tbl[] = {
3114        QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
3115        QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
3116        QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02),
3117        QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_EQ_CONFIG1, 0x16),
3118        QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_RX_MARGINING_CONFIG3, 0x28),
3119        QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_PRE_GAIN, 0x2e),
3120};
3121
3122struct qmp_phy;
3123
3124/* struct qmp_phy_cfg - per-PHY initialization config */
3125struct qmp_phy_cfg {
3126        /* phy-type - PCIE/UFS/USB */
3127        unsigned int type;
3128        /* number of lanes provided by phy */
3129        int nlanes;
3130
3131        /* Init sequence for PHY blocks - serdes, tx, rx, pcs */
3132        const struct qmp_phy_init_tbl *serdes_tbl;
3133        int serdes_tbl_num;
3134        const struct qmp_phy_init_tbl *serdes_tbl_sec;
3135        int serdes_tbl_num_sec;
3136        const struct qmp_phy_init_tbl *tx_tbl;
3137        int tx_tbl_num;
3138        const struct qmp_phy_init_tbl *tx_tbl_sec;
3139        int tx_tbl_num_sec;
3140        const struct qmp_phy_init_tbl *rx_tbl;
3141        int rx_tbl_num;
3142        const struct qmp_phy_init_tbl *rx_tbl_sec;
3143        int rx_tbl_num_sec;
3144        const struct qmp_phy_init_tbl *pcs_tbl;
3145        int pcs_tbl_num;
3146        const struct qmp_phy_init_tbl *pcs_tbl_sec;
3147        int pcs_tbl_num_sec;
3148        const struct qmp_phy_init_tbl *pcs_misc_tbl;
3149        int pcs_misc_tbl_num;
3150        const struct qmp_phy_init_tbl *pcs_misc_tbl_sec;
3151        int pcs_misc_tbl_num_sec;
3152
3153        /* Init sequence for DP PHY block link rates */
3154        const struct qmp_phy_init_tbl *serdes_tbl_rbr;
3155        int serdes_tbl_rbr_num;
3156        const struct qmp_phy_init_tbl *serdes_tbl_hbr;
3157        int serdes_tbl_hbr_num;
3158        const struct qmp_phy_init_tbl *serdes_tbl_hbr2;
3159        int serdes_tbl_hbr2_num;
3160        const struct qmp_phy_init_tbl *serdes_tbl_hbr3;
3161        int serdes_tbl_hbr3_num;
3162
3163        /* DP PHY callbacks */
3164        int (*configure_dp_phy)(struct qmp_phy *qphy);
3165        void (*configure_dp_tx)(struct qmp_phy *qphy);
3166        int (*calibrate_dp_phy)(struct qmp_phy *qphy);
3167        void (*dp_aux_init)(struct qmp_phy *qphy);
3168
3169        /* clock ids to be requested */
3170        const char * const *clk_list;
3171        int num_clks;
3172        /* resets to be requested */
3173        const char * const *reset_list;
3174        int num_resets;
3175        /* regulators to be requested */
3176        const char * const *vreg_list;
3177        int num_vregs;
3178
3179        /* array of registers with different offsets */
3180        const unsigned int *regs;
3181
3182        unsigned int start_ctrl;
3183        unsigned int pwrdn_ctrl;
3184        unsigned int mask_com_pcs_ready;
3185        /* bit offset of PHYSTATUS in QPHY_PCS_STATUS register */
3186        unsigned int phy_status;
3187
3188        /* true, if PHY has a separate PHY_COM control block */
3189        bool has_phy_com_ctrl;
3190        /* true, if PHY has a reset for individual lanes */
3191        bool has_lane_rst;
3192        /* true, if PHY needs delay after POWER_DOWN */
3193        bool has_pwrdn_delay;
3194        /* power_down delay in usec */
3195        int pwrdn_delay_min;
3196        int pwrdn_delay_max;
3197
3198        /* true, if PHY has a separate DP_COM control block */
3199        bool has_phy_dp_com_ctrl;
3200        /* true, if PHY has secondary tx/rx lanes to be configured */
3201        bool is_dual_lane_phy;
3202
3203        /* true, if PCS block has no separate SW_RESET register */
3204        bool no_pcs_sw_reset;
3205};
3206
3207struct qmp_phy_combo_cfg {
3208        const struct qmp_phy_cfg *usb_cfg;
3209        const struct qmp_phy_cfg *dp_cfg;
3210};
3211
3212/**
3213 * struct qmp_phy - per-lane phy descriptor
3214 *
3215 * @phy: generic phy
3216 * @cfg: phy specific configuration
3217 * @serdes: iomapped memory space for phy's serdes (i.e. PLL)
3218 * @tx: iomapped memory space for lane's tx
3219 * @rx: iomapped memory space for lane's rx
3220 * @pcs: iomapped memory space for lane's pcs
3221 * @tx2: iomapped memory space for second lane's tx (in dual lane PHYs)
3222 * @rx2: iomapped memory space for second lane's rx (in dual lane PHYs)
3223 * @pcs_misc: iomapped memory space for lane's pcs_misc
3224 * @pipe_clk: pipe clock
3225 * @index: lane index
3226 * @qmp: QMP phy to which this lane belongs
3227 * @lane_rst: lane's reset controller
3228 * @mode: current PHY mode
3229 * @dp_aux_cfg: Display port aux config
3230 * @dp_opts: Display port optional config
3231 * @dp_clks: Display port clocks
3232 */
3233struct qmp_phy {
3234        struct phy *phy;
3235        const struct qmp_phy_cfg *cfg;
3236        void __iomem *serdes;
3237        void __iomem *tx;
3238        void __iomem *rx;
3239        void __iomem *pcs;
3240        void __iomem *tx2;
3241        void __iomem *rx2;
3242        void __iomem *pcs_misc;
3243        struct clk *pipe_clk;
3244        unsigned int index;
3245        struct qcom_qmp *qmp;
3246        struct reset_control *lane_rst;
3247        enum phy_mode mode;
3248        unsigned int dp_aux_cfg;
3249        struct phy_configure_opts_dp dp_opts;
3250        struct qmp_phy_dp_clks *dp_clks;
3251};
3252
3253struct qmp_phy_dp_clks {
3254        struct qmp_phy *qphy;
3255        struct clk_hw dp_link_hw;
3256        struct clk_hw dp_pixel_hw;
3257};
3258
3259/**
3260 * struct qcom_qmp - structure holding QMP phy block attributes
3261 *
3262 * @dev: device
3263 * @dp_com: iomapped memory space for phy's dp_com control block
3264 *
3265 * @clks: array of clocks required by phy
3266 * @resets: array of resets required by phy
3267 * @vregs: regulator supplies bulk data
3268 *
3269 * @phys: array of per-lane phy descriptors
3270 * @phy_mutex: mutex lock for PHY common block initialization
3271 * @init_count: phy common block initialization count
3272 * @ufs_reset: optional UFS PHY reset handle
3273 */
3274struct qcom_qmp {
3275        struct device *dev;
3276        void __iomem *dp_com;
3277
3278        struct clk_bulk_data *clks;
3279        struct reset_control **resets;
3280        struct regulator_bulk_data *vregs;
3281
3282        struct qmp_phy **phys;
3283
3284        struct mutex phy_mutex;
3285        int init_count;
3286
3287        struct reset_control *ufs_reset;
3288};
3289
3290static void qcom_qmp_v3_phy_dp_aux_init(struct qmp_phy *qphy);
3291static void qcom_qmp_v3_phy_configure_dp_tx(struct qmp_phy *qphy);
3292static int qcom_qmp_v3_phy_configure_dp_phy(struct qmp_phy *qphy);
3293static int qcom_qmp_v3_dp_phy_calibrate(struct qmp_phy *qphy);
3294
3295static void qcom_qmp_v4_phy_dp_aux_init(struct qmp_phy *qphy);
3296static void qcom_qmp_v4_phy_configure_dp_tx(struct qmp_phy *qphy);
3297static int qcom_qmp_v4_phy_configure_dp_phy(struct qmp_phy *qphy);
3298static int qcom_qmp_v4_dp_phy_calibrate(struct qmp_phy *qphy);
3299
3300static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val)
3301{
3302        u32 reg;
3303
3304        reg = readl(base + offset);
3305        reg |= val;
3306        writel(reg, base + offset);
3307
3308        /* ensure that above write is through */
3309        readl(base + offset);
3310}
3311
3312static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val)
3313{
3314        u32 reg;
3315
3316        reg = readl(base + offset);
3317        reg &= ~val;
3318        writel(reg, base + offset);
3319
3320        /* ensure that above write is through */
3321        readl(base + offset);
3322}
3323
3324/* list of clocks required by phy */
3325static const char * const msm8996_phy_clk_l[] = {
3326        "aux", "cfg_ahb", "ref",
3327};
3328
3329static const char * const msm8996_ufs_phy_clk_l[] = {
3330        "ref",
3331};
3332
3333static const char * const qmp_v3_phy_clk_l[] = {
3334        "aux", "cfg_ahb", "ref", "com_aux",
3335};
3336
3337static const char * const sdm845_pciephy_clk_l[] = {
3338        "aux", "cfg_ahb", "ref", "refgen",
3339};
3340
3341static const char * const qmp_v4_phy_clk_l[] = {
3342        "aux", "ref_clk_src", "ref", "com_aux",
3343};
3344
3345/* the primary usb3 phy on sm8250 doesn't have a ref clock */
3346static const char * const qmp_v4_sm8250_usbphy_clk_l[] = {
3347        "aux", "ref_clk_src", "com_aux"
3348};
3349
3350static const char * const sm8450_ufs_phy_clk_l[] = {
3351        "qref", "ref", "ref_aux",
3352};
3353
3354static const char * const sdm845_ufs_phy_clk_l[] = {
3355        "ref", "ref_aux",
3356};
3357
3358/* usb3 phy on sdx55 doesn't have com_aux clock */
3359static const char * const qmp_v4_sdx55_usbphy_clk_l[] = {
3360        "aux", "cfg_ahb", "ref"
3361};
3362
3363static const char * const qcm2290_usb3phy_clk_l[] = {
3364        "cfg_ahb", "ref", "com_aux",
3365};
3366
3367/* list of resets */
3368static const char * const msm8996_pciephy_reset_l[] = {
3369        "phy", "common", "cfg",
3370};
3371
3372static const char * const msm8996_usb3phy_reset_l[] = {
3373        "phy", "common",
3374};
3375
3376static const char * const sc7180_usb3phy_reset_l[] = {
3377        "phy",
3378};
3379
3380static const char * const qcm2290_usb3phy_reset_l[] = {
3381        "phy_phy", "phy",
3382};
3383
3384static const char * const sdm845_pciephy_reset_l[] = {
3385        "phy",
3386};
3387
3388/* list of regulators */
3389static const char * const qmp_phy_vreg_l[] = {
3390        "vdda-phy", "vdda-pll",
3391};
3392
3393static const struct qmp_phy_cfg ipq8074_usb3phy_cfg = {
3394        .type                   = PHY_TYPE_USB3,
3395        .nlanes                 = 1,
3396
3397        .serdes_tbl             = ipq8074_usb3_serdes_tbl,
3398        .serdes_tbl_num         = ARRAY_SIZE(ipq8074_usb3_serdes_tbl),
3399        .tx_tbl                 = msm8996_usb3_tx_tbl,
3400        .tx_tbl_num             = ARRAY_SIZE(msm8996_usb3_tx_tbl),
3401        .rx_tbl                 = ipq8074_usb3_rx_tbl,
3402        .rx_tbl_num             = ARRAY_SIZE(ipq8074_usb3_rx_tbl),
3403        .pcs_tbl                = ipq8074_usb3_pcs_tbl,
3404        .pcs_tbl_num            = ARRAY_SIZE(ipq8074_usb3_pcs_tbl),
3405        .clk_list               = msm8996_phy_clk_l,
3406        .num_clks               = ARRAY_SIZE(msm8996_phy_clk_l),
3407        .reset_list             = msm8996_usb3phy_reset_l,
3408        .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
3409        .vreg_list              = qmp_phy_vreg_l,
3410        .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
3411        .regs                   = usb3phy_regs_layout,
3412
3413        .start_ctrl             = SERDES_START | PCS_START,
3414        .pwrdn_ctrl             = SW_PWRDN,
3415        .phy_status             = PHYSTATUS,
3416};
3417
3418static const struct qmp_phy_cfg msm8996_pciephy_cfg = {
3419        .type                   = PHY_TYPE_PCIE,
3420        .nlanes                 = 3,
3421
3422        .serdes_tbl             = msm8996_pcie_serdes_tbl,
3423        .serdes_tbl_num         = ARRAY_SIZE(msm8996_pcie_serdes_tbl),
3424        .tx_tbl                 = msm8996_pcie_tx_tbl,
3425        .tx_tbl_num             = ARRAY_SIZE(msm8996_pcie_tx_tbl),
3426        .rx_tbl                 = msm8996_pcie_rx_tbl,
3427        .rx_tbl_num             = ARRAY_SIZE(msm8996_pcie_rx_tbl),
3428        .pcs_tbl                = msm8996_pcie_pcs_tbl,
3429        .pcs_tbl_num            = ARRAY_SIZE(msm8996_pcie_pcs_tbl),
3430        .clk_list               = msm8996_phy_clk_l,
3431        .num_clks               = ARRAY_SIZE(msm8996_phy_clk_l),
3432        .reset_list             = msm8996_pciephy_reset_l,
3433        .num_resets             = ARRAY_SIZE(msm8996_pciephy_reset_l),
3434        .vreg_list              = qmp_phy_vreg_l,
3435        .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
3436        .regs                   = pciephy_regs_layout,
3437
3438        .start_ctrl             = PCS_START | PLL_READY_GATE_EN,
3439        .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
3440        .mask_com_pcs_ready     = PCS_READY,
3441        .phy_status             = PHYSTATUS,
3442
3443        .has_phy_com_ctrl       = true,
3444        .has_lane_rst           = true,
3445        .has_pwrdn_delay        = true,
3446        .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
3447        .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
3448};
3449
3450static const struct qmp_phy_cfg msm8996_ufs_cfg = {
3451        .type                   = PHY_TYPE_UFS,
3452        .nlanes                 = 1,
3453
3454        .serdes_tbl             = msm8996_ufs_serdes_tbl,
3455        .serdes_tbl_num         = ARRAY_SIZE(msm8996_ufs_serdes_tbl),
3456        .tx_tbl                 = msm8996_ufs_tx_tbl,
3457        .tx_tbl_num             = ARRAY_SIZE(msm8996_ufs_tx_tbl),
3458        .rx_tbl                 = msm8996_ufs_rx_tbl,
3459        .rx_tbl_num             = ARRAY_SIZE(msm8996_ufs_rx_tbl),
3460
3461        .clk_list               = msm8996_ufs_phy_clk_l,
3462        .num_clks               = ARRAY_SIZE(msm8996_ufs_phy_clk_l),
3463
3464        .vreg_list              = qmp_phy_vreg_l,
3465        .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
3466
3467        .regs                   = msm8996_ufsphy_regs_layout,
3468
3469        .start_ctrl             = SERDES_START,
3470        .pwrdn_ctrl             = SW_PWRDN,
3471        .phy_status             = PHYSTATUS,
3472
3473        .no_pcs_sw_reset        = true,
3474};
3475
3476static const struct qmp_phy_cfg msm8996_usb3phy_cfg = {
3477        .type                   = PHY_TYPE_USB3,
3478        .nlanes                 = 1,
3479
3480        .serdes_tbl             = msm8996_usb3_serdes_tbl,
3481        .serdes_tbl_num         = ARRAY_SIZE(msm8996_usb3_serdes_tbl),
3482        .tx_tbl                 = msm8996_usb3_tx_tbl,
3483        .tx_tbl_num             = ARRAY_SIZE(msm8996_usb3_tx_tbl),
3484        .rx_tbl                 = msm8996_usb3_rx_tbl,
3485        .rx_tbl_num             = ARRAY_SIZE(msm8996_usb3_rx_tbl),
3486        .pcs_tbl                = msm8996_usb3_pcs_tbl,
3487        .pcs_tbl_num            = ARRAY_SIZE(msm8996_usb3_pcs_tbl),
3488        .clk_list               = msm8996_phy_clk_l,
3489        .num_clks               = ARRAY_SIZE(msm8996_phy_clk_l),
3490        .reset_list             = msm8996_usb3phy_reset_l,
3491        .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
3492        .vreg_list              = qmp_phy_vreg_l,
3493        .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
3494        .regs                   = usb3phy_regs_layout,
3495
3496        .start_ctrl             = SERDES_START | PCS_START,
3497        .pwrdn_ctrl             = SW_PWRDN,
3498        .phy_status             = PHYSTATUS,
3499};
3500
3501static const char * const ipq8074_pciephy_clk_l[] = {
3502        "aux", "cfg_ahb",
3503};
3504/* list of resets */
3505static const char * const ipq8074_pciephy_reset_l[] = {
3506        "phy", "common",
3507};
3508
3509static const struct qmp_phy_cfg ipq8074_pciephy_cfg = {
3510        .type                   = PHY_TYPE_PCIE,
3511        .nlanes                 = 1,
3512
3513        .serdes_tbl             = ipq8074_pcie_serdes_tbl,
3514        .serdes_tbl_num         = ARRAY_SIZE(ipq8074_pcie_serdes_tbl),
3515        .tx_tbl                 = ipq8074_pcie_tx_tbl,
3516        .tx_tbl_num             = ARRAY_SIZE(ipq8074_pcie_tx_tbl),
3517        .rx_tbl                 = ipq8074_pcie_rx_tbl,
3518        .rx_tbl_num             = ARRAY_SIZE(ipq8074_pcie_rx_tbl),
3519        .pcs_tbl                = ipq8074_pcie_pcs_tbl,
3520        .pcs_tbl_num            = ARRAY_SIZE(ipq8074_pcie_pcs_tbl),
3521        .clk_list               = ipq8074_pciephy_clk_l,
3522        .num_clks               = ARRAY_SIZE(ipq8074_pciephy_clk_l),
3523        .reset_list             = ipq8074_pciephy_reset_l,
3524        .num_resets             = ARRAY_SIZE(ipq8074_pciephy_reset_l),
3525        .vreg_list              = NULL,
3526        .num_vregs              = 0,
3527        .regs                   = pciephy_regs_layout,
3528
3529        .start_ctrl             = SERDES_START | PCS_START,
3530        .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
3531        .phy_status             = PHYSTATUS,
3532
3533        .has_phy_com_ctrl       = false,
3534        .has_lane_rst           = false,
3535        .has_pwrdn_delay        = true,
3536        .pwrdn_delay_min        = 995,          /* us */
3537        .pwrdn_delay_max        = 1005,         /* us */
3538};
3539
3540static const struct qmp_phy_cfg ipq6018_pciephy_cfg = {
3541        .type                   = PHY_TYPE_PCIE,
3542        .nlanes                 = 1,
3543
3544        .serdes_tbl             = ipq6018_pcie_serdes_tbl,
3545        .serdes_tbl_num         = ARRAY_SIZE(ipq6018_pcie_serdes_tbl),
3546        .tx_tbl                 = ipq6018_pcie_tx_tbl,
3547        .tx_tbl_num             = ARRAY_SIZE(ipq6018_pcie_tx_tbl),
3548        .rx_tbl                 = ipq6018_pcie_rx_tbl,
3549        .rx_tbl_num             = ARRAY_SIZE(ipq6018_pcie_rx_tbl),
3550        .pcs_tbl                = ipq6018_pcie_pcs_tbl,
3551        .pcs_tbl_num            = ARRAY_SIZE(ipq6018_pcie_pcs_tbl),
3552        .clk_list               = ipq8074_pciephy_clk_l,
3553        .num_clks               = ARRAY_SIZE(ipq8074_pciephy_clk_l),
3554        .reset_list             = ipq8074_pciephy_reset_l,
3555        .num_resets             = ARRAY_SIZE(ipq8074_pciephy_reset_l),
3556        .vreg_list              = NULL,
3557        .num_vregs              = 0,
3558        .regs                   = ipq_pciephy_gen3_regs_layout,
3559
3560        .start_ctrl             = SERDES_START | PCS_START,
3561        .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
3562
3563        .has_phy_com_ctrl       = false,
3564        .has_lane_rst           = false,
3565        .has_pwrdn_delay        = true,
3566        .pwrdn_delay_min        = 995,          /* us */
3567        .pwrdn_delay_max        = 1005,         /* us */
3568};
3569
3570static const struct qmp_phy_cfg sdm845_qmp_pciephy_cfg = {
3571        .type = PHY_TYPE_PCIE,
3572        .nlanes = 1,
3573
3574        .serdes_tbl             = sdm845_qmp_pcie_serdes_tbl,
3575        .serdes_tbl_num         = ARRAY_SIZE(sdm845_qmp_pcie_serdes_tbl),
3576        .tx_tbl                 = sdm845_qmp_pcie_tx_tbl,
3577        .tx_tbl_num             = ARRAY_SIZE(sdm845_qmp_pcie_tx_tbl),
3578        .rx_tbl                 = sdm845_qmp_pcie_rx_tbl,
3579        .rx_tbl_num             = ARRAY_SIZE(sdm845_qmp_pcie_rx_tbl),
3580        .pcs_tbl                = sdm845_qmp_pcie_pcs_tbl,
3581        .pcs_tbl_num            = ARRAY_SIZE(sdm845_qmp_pcie_pcs_tbl),
3582        .pcs_misc_tbl           = sdm845_qmp_pcie_pcs_misc_tbl,
3583        .pcs_misc_tbl_num       = ARRAY_SIZE(sdm845_qmp_pcie_pcs_misc_tbl),
3584        .clk_list               = sdm845_pciephy_clk_l,
3585        .num_clks               = ARRAY_SIZE(sdm845_pciephy_clk_l),
3586        .reset_list             = sdm845_pciephy_reset_l,
3587        .num_resets             = ARRAY_SIZE(sdm845_pciephy_reset_l),
3588        .vreg_list              = qmp_phy_vreg_l,
3589        .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
3590        .regs                   = sdm845_qmp_pciephy_regs_layout,
3591
3592        .start_ctrl             = PCS_START | SERDES_START,
3593        .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
3594        .phy_status             = PHYSTATUS,
3595
3596        .has_pwrdn_delay        = true,
3597        .pwrdn_delay_min        = 995,          /* us */
3598        .pwrdn_delay_max        = 1005,         /* us */
3599};
3600
3601static const struct qmp_phy_cfg sdm845_qhp_pciephy_cfg = {
3602        .type = PHY_TYPE_PCIE,
3603        .nlanes = 1,
3604
3605        .serdes_tbl             = sdm845_qhp_pcie_serdes_tbl,
3606        .serdes_tbl_num         = ARRAY_SIZE(sdm845_qhp_pcie_serdes_tbl),
3607        .tx_tbl                 = sdm845_qhp_pcie_tx_tbl,
3608        .tx_tbl_num             = ARRAY_SIZE(sdm845_qhp_pcie_tx_tbl),
3609        .rx_tbl                 = sdm845_qhp_pcie_rx_tbl,
3610        .rx_tbl_num             = ARRAY_SIZE(sdm845_qhp_pcie_rx_tbl),
3611        .pcs_tbl                = sdm845_qhp_pcie_pcs_tbl,
3612        .pcs_tbl_num            = ARRAY_SIZE(sdm845_qhp_pcie_pcs_tbl),
3613        .clk_list               = sdm845_pciephy_clk_l,
3614        .num_clks               = ARRAY_SIZE(sdm845_pciephy_clk_l),
3615        .reset_list             = sdm845_pciephy_reset_l,
3616        .num_resets             = ARRAY_SIZE(sdm845_pciephy_reset_l),
3617        .vreg_list              = qmp_phy_vreg_l,
3618        .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
3619        .regs                   = sdm845_qhp_pciephy_regs_layout,
3620
3621        .start_ctrl             = PCS_START | SERDES_START,
3622        .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
3623        .phy_status             = PHYSTATUS,
3624
3625        .has_pwrdn_delay        = true,
3626        .pwrdn_delay_min        = 995,          /* us */
3627        .pwrdn_delay_max        = 1005,         /* us */
3628};
3629
3630static const struct qmp_phy_cfg sm8250_qmp_gen3x1_pciephy_cfg = {
3631        .type = PHY_TYPE_PCIE,
3632        .nlanes = 1,
3633
3634        .serdes_tbl             = sm8250_qmp_pcie_serdes_tbl,
3635        .serdes_tbl_num         = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl),
3636        .serdes_tbl_sec         = sm8250_qmp_gen3x1_pcie_serdes_tbl,
3637        .serdes_tbl_num_sec     = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_serdes_tbl),
3638        .tx_tbl                 = sm8250_qmp_pcie_tx_tbl,
3639        .tx_tbl_num             = ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl),
3640        .rx_tbl                 = sm8250_qmp_pcie_rx_tbl,
3641        .rx_tbl_num             = ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl),
3642        .rx_tbl_sec             = sm8250_qmp_gen3x1_pcie_rx_tbl,
3643        .rx_tbl_num_sec         = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_rx_tbl),
3644        .pcs_tbl                = sm8250_qmp_pcie_pcs_tbl,
3645        .pcs_tbl_num            = ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl),
3646        .pcs_tbl_sec            = sm8250_qmp_gen3x1_pcie_pcs_tbl,
3647        .pcs_tbl_num_sec                = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_tbl),
3648        .pcs_misc_tbl           = sm8250_qmp_pcie_pcs_misc_tbl,
3649        .pcs_misc_tbl_num       = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl),
3650        .pcs_misc_tbl_sec               = sm8250_qmp_gen3x1_pcie_pcs_misc_tbl,
3651        .pcs_misc_tbl_num_sec   = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_misc_tbl),
3652        .clk_list               = sdm845_pciephy_clk_l,
3653        .num_clks               = ARRAY_SIZE(sdm845_pciephy_clk_l),
3654        .reset_list             = sdm845_pciephy_reset_l,
3655        .num_resets             = ARRAY_SIZE(sdm845_pciephy_reset_l),
3656        .vreg_list              = qmp_phy_vreg_l,
3657        .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
3658        .regs                   = sm8250_pcie_regs_layout,
3659
3660        .start_ctrl             = PCS_START | SERDES_START,
3661        .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
3662        .phy_status             = PHYSTATUS,
3663
3664        .has_pwrdn_delay        = true,
3665        .pwrdn_delay_min        = 995,          /* us */
3666        .pwrdn_delay_max        = 1005,         /* us */
3667};
3668
3669static const struct qmp_phy_cfg sm8250_qmp_gen3x2_pciephy_cfg = {
3670        .type = PHY_TYPE_PCIE,
3671        .nlanes = 2,
3672
3673        .serdes_tbl             = sm8250_qmp_pcie_serdes_tbl,
3674        .serdes_tbl_num         = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl),
3675        .tx_tbl                 = sm8250_qmp_pcie_tx_tbl,
3676        .tx_tbl_num             = ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl),
3677        .tx_tbl_sec             = sm8250_qmp_gen3x2_pcie_tx_tbl,
3678        .tx_tbl_num_sec         = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_tx_tbl),
3679        .rx_tbl                 = sm8250_qmp_pcie_rx_tbl,
3680        .rx_tbl_num             = ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl),
3681        .rx_tbl_sec             = sm8250_qmp_gen3x2_pcie_rx_tbl,
3682        .rx_tbl_num_sec         = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_rx_tbl),
3683        .pcs_tbl                = sm8250_qmp_pcie_pcs_tbl,
3684        .pcs_tbl_num            = ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl),
3685        .pcs_tbl_sec            = sm8250_qmp_gen3x2_pcie_pcs_tbl,
3686        .pcs_tbl_num_sec                = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_tbl),
3687        .pcs_misc_tbl           = sm8250_qmp_pcie_pcs_misc_tbl,
3688        .pcs_misc_tbl_num       = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl),
3689        .pcs_misc_tbl_sec               = sm8250_qmp_gen3x2_pcie_pcs_misc_tbl,
3690        .pcs_misc_tbl_num_sec   = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_misc_tbl),
3691        .clk_list               = sdm845_pciephy_clk_l,
3692        .num_clks               = ARRAY_SIZE(sdm845_pciephy_clk_l),
3693        .reset_list             = sdm845_pciephy_reset_l,
3694        .num_resets             = ARRAY_SIZE(sdm845_pciephy_reset_l),
3695        .vreg_list              = qmp_phy_vreg_l,
3696        .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
3697        .regs                   = sm8250_pcie_regs_layout,
3698
3699        .start_ctrl             = PCS_START | SERDES_START,
3700        .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
3701        .phy_status             = PHYSTATUS,
3702
3703        .is_dual_lane_phy       = true,
3704        .has_pwrdn_delay        = true,
3705        .pwrdn_delay_min        = 995,          /* us */
3706        .pwrdn_delay_max        = 1005,         /* us */
3707};
3708
3709static const struct qmp_phy_cfg qmp_v3_usb3phy_cfg = {
3710        .type                   = PHY_TYPE_USB3,
3711        .nlanes                 = 1,
3712
3713        .serdes_tbl             = qmp_v3_usb3_serdes_tbl,
3714        .serdes_tbl_num         = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl),
3715        .tx_tbl                 = qmp_v3_usb3_tx_tbl,
3716        .tx_tbl_num             = ARRAY_SIZE(qmp_v3_usb3_tx_tbl),
3717        .rx_tbl                 = qmp_v3_usb3_rx_tbl,
3718        .rx_tbl_num             = ARRAY_SIZE(qmp_v3_usb3_rx_tbl),
3719        .pcs_tbl                = qmp_v3_usb3_pcs_tbl,
3720        .pcs_tbl_num            = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl),
3721        .clk_list               = qmp_v3_phy_clk_l,
3722        .num_clks               = ARRAY_SIZE(qmp_v3_phy_clk_l),
3723        .reset_list             = msm8996_usb3phy_reset_l,
3724        .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
3725        .vreg_list              = qmp_phy_vreg_l,
3726        .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
3727        .regs                   = qmp_v3_usb3phy_regs_layout,
3728
3729        .start_ctrl             = SERDES_START | PCS_START,
3730        .pwrdn_ctrl             = SW_PWRDN,
3731        .phy_status             = PHYSTATUS,
3732
3733        .has_pwrdn_delay        = true,
3734        .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
3735        .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
3736
3737        .has_phy_dp_com_ctrl    = true,
3738        .is_dual_lane_phy       = true,
3739};
3740
3741static const struct qmp_phy_cfg sc7180_usb3phy_cfg = {
3742        .type                   = PHY_TYPE_USB3,
3743        .nlanes                 = 1,
3744
3745        .serdes_tbl             = qmp_v3_usb3_serdes_tbl,
3746        .serdes_tbl_num         = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl),
3747        .tx_tbl                 = qmp_v3_usb3_tx_tbl,
3748        .tx_tbl_num             = ARRAY_SIZE(qmp_v3_usb3_tx_tbl),
3749        .rx_tbl                 = qmp_v3_usb3_rx_tbl,
3750        .rx_tbl_num             = ARRAY_SIZE(qmp_v3_usb3_rx_tbl),
3751        .pcs_tbl                = qmp_v3_usb3_pcs_tbl,
3752        .pcs_tbl_num            = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl),
3753        .clk_list               = qmp_v3_phy_clk_l,
3754        .num_clks               = ARRAY_SIZE(qmp_v3_phy_clk_l),
3755        .reset_list             = sc7180_usb3phy_reset_l,
3756        .num_resets             = ARRAY_SIZE(sc7180_usb3phy_reset_l),
3757        .vreg_list              = qmp_phy_vreg_l,
3758        .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
3759        .regs                   = qmp_v3_usb3phy_regs_layout,
3760
3761        .start_ctrl             = SERDES_START | PCS_START,
3762        .pwrdn_ctrl             = SW_PWRDN,
3763        .phy_status             = PHYSTATUS,
3764
3765        .has_pwrdn_delay        = true,
3766        .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
3767        .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
3768
3769        .has_phy_dp_com_ctrl    = true,
3770        .is_dual_lane_phy       = true,
3771};
3772
3773static const struct qmp_phy_cfg sc7180_dpphy_cfg = {
3774        .type                   = PHY_TYPE_DP,
3775        .nlanes                 = 1,
3776
3777        .serdes_tbl             = qmp_v3_dp_serdes_tbl,
3778        .serdes_tbl_num         = ARRAY_SIZE(qmp_v3_dp_serdes_tbl),
3779        .tx_tbl                 = qmp_v3_dp_tx_tbl,
3780        .tx_tbl_num             = ARRAY_SIZE(qmp_v3_dp_tx_tbl),
3781
3782        .serdes_tbl_rbr         = qmp_v3_dp_serdes_tbl_rbr,
3783        .serdes_tbl_rbr_num     = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_rbr),
3784        .serdes_tbl_hbr         = qmp_v3_dp_serdes_tbl_hbr,
3785        .serdes_tbl_hbr_num     = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr),
3786        .serdes_tbl_hbr2        = qmp_v3_dp_serdes_tbl_hbr2,
3787        .serdes_tbl_hbr2_num    = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr2),
3788        .serdes_tbl_hbr3        = qmp_v3_dp_serdes_tbl_hbr3,
3789        .serdes_tbl_hbr3_num    = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr3),
3790
3791        .clk_list               = qmp_v3_phy_clk_l,
3792        .num_clks               = ARRAY_SIZE(qmp_v3_phy_clk_l),
3793        .reset_list             = sc7180_usb3phy_reset_l,
3794        .num_resets             = ARRAY_SIZE(sc7180_usb3phy_reset_l),
3795        .vreg_list              = qmp_phy_vreg_l,
3796        .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
3797        .regs                   = qmp_v3_usb3phy_regs_layout,
3798
3799        .has_phy_dp_com_ctrl    = true,
3800        .is_dual_lane_phy       = true,
3801
3802        .dp_aux_init = qcom_qmp_v3_phy_dp_aux_init,
3803        .configure_dp_tx = qcom_qmp_v3_phy_configure_dp_tx,
3804        .configure_dp_phy = qcom_qmp_v3_phy_configure_dp_phy,
3805        .calibrate_dp_phy = qcom_qmp_v3_dp_phy_calibrate,
3806};
3807
3808static const struct qmp_phy_combo_cfg sc7180_usb3dpphy_cfg = {
3809        .usb_cfg                = &sc7180_usb3phy_cfg,
3810        .dp_cfg                 = &sc7180_dpphy_cfg,
3811};
3812
3813static const struct qmp_phy_cfg qmp_v3_usb3_uniphy_cfg = {
3814        .type                   = PHY_TYPE_USB3,
3815        .nlanes                 = 1,
3816
3817        .serdes_tbl             = qmp_v3_usb3_uniphy_serdes_tbl,
3818        .serdes_tbl_num         = ARRAY_SIZE(qmp_v3_usb3_uniphy_serdes_tbl),
3819        .tx_tbl                 = qmp_v3_usb3_uniphy_tx_tbl,
3820        .tx_tbl_num             = ARRAY_SIZE(qmp_v3_usb3_uniphy_tx_tbl),
3821        .rx_tbl                 = qmp_v3_usb3_uniphy_rx_tbl,
3822        .rx_tbl_num             = ARRAY_SIZE(qmp_v3_usb3_uniphy_rx_tbl),
3823        .pcs_tbl                = qmp_v3_usb3_uniphy_pcs_tbl,
3824        .pcs_tbl_num            = ARRAY_SIZE(qmp_v3_usb3_uniphy_pcs_tbl),
3825        .clk_list               = qmp_v3_phy_clk_l,
3826        .num_clks               = ARRAY_SIZE(qmp_v3_phy_clk_l),
3827        .reset_list             = msm8996_usb3phy_reset_l,
3828        .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
3829        .vreg_list              = qmp_phy_vreg_l,
3830        .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
3831        .regs                   = qmp_v3_usb3phy_regs_layout,
3832
3833        .start_ctrl             = SERDES_START | PCS_START,
3834        .pwrdn_ctrl             = SW_PWRDN,
3835        .phy_status             = PHYSTATUS,
3836
3837        .has_pwrdn_delay        = true,
3838        .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
3839        .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
3840};
3841
3842static const struct qmp_phy_cfg sdm845_ufsphy_cfg = {
3843        .type                   = PHY_TYPE_UFS,
3844        .nlanes                 = 2,
3845
3846        .serdes_tbl             = sdm845_ufsphy_serdes_tbl,
3847        .serdes_tbl_num         = ARRAY_SIZE(sdm845_ufsphy_serdes_tbl),
3848        .tx_tbl                 = sdm845_ufsphy_tx_tbl,
3849        .tx_tbl_num             = ARRAY_SIZE(sdm845_ufsphy_tx_tbl),
3850        .rx_tbl                 = sdm845_ufsphy_rx_tbl,
3851        .rx_tbl_num             = ARRAY_SIZE(sdm845_ufsphy_rx_tbl),
3852        .pcs_tbl                = sdm845_ufsphy_pcs_tbl,
3853        .pcs_tbl_num            = ARRAY_SIZE(sdm845_ufsphy_pcs_tbl),
3854        .clk_list               = sdm845_ufs_phy_clk_l,
3855        .num_clks               = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
3856        .vreg_list              = qmp_phy_vreg_l,
3857        .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
3858        .regs                   = sdm845_ufsphy_regs_layout,
3859
3860        .start_ctrl             = SERDES_START,
3861        .pwrdn_ctrl             = SW_PWRDN,
3862        .phy_status             = PHYSTATUS,
3863
3864        .is_dual_lane_phy       = true,
3865        .no_pcs_sw_reset        = true,
3866};
3867
3868static const struct qmp_phy_cfg sm6115_ufsphy_cfg = {
3869        .type                   = PHY_TYPE_UFS,
3870        .nlanes                 = 1,
3871
3872        .serdes_tbl             = sm6115_ufsphy_serdes_tbl,
3873        .serdes_tbl_num         = ARRAY_SIZE(sm6115_ufsphy_serdes_tbl),
3874        .tx_tbl                 = sm6115_ufsphy_tx_tbl,
3875        .tx_tbl_num             = ARRAY_SIZE(sm6115_ufsphy_tx_tbl),
3876        .rx_tbl                 = sm6115_ufsphy_rx_tbl,
3877        .rx_tbl_num             = ARRAY_SIZE(sm6115_ufsphy_rx_tbl),
3878        .pcs_tbl                = sm6115_ufsphy_pcs_tbl,
3879        .pcs_tbl_num            = ARRAY_SIZE(sm6115_ufsphy_pcs_tbl),
3880        .clk_list               = sdm845_ufs_phy_clk_l,
3881        .num_clks               = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
3882        .vreg_list              = qmp_phy_vreg_l,
3883        .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
3884        .regs                   = sm6115_ufsphy_regs_layout,
3885
3886        .start_ctrl             = SERDES_START,
3887        .pwrdn_ctrl             = SW_PWRDN,
3888
3889        .is_dual_lane_phy       = false,
3890        .no_pcs_sw_reset        = true,
3891};
3892
3893static const struct qmp_phy_cfg msm8998_pciephy_cfg = {
3894        .type                   = PHY_TYPE_PCIE,
3895        .nlanes                 = 1,
3896
3897        .serdes_tbl             = msm8998_pcie_serdes_tbl,
3898        .serdes_tbl_num         = ARRAY_SIZE(msm8998_pcie_serdes_tbl),
3899        .tx_tbl                 = msm8998_pcie_tx_tbl,
3900        .tx_tbl_num             = ARRAY_SIZE(msm8998_pcie_tx_tbl),
3901        .rx_tbl                 = msm8998_pcie_rx_tbl,
3902        .rx_tbl_num             = ARRAY_SIZE(msm8998_pcie_rx_tbl),
3903        .pcs_tbl                = msm8998_pcie_pcs_tbl,
3904        .pcs_tbl_num            = ARRAY_SIZE(msm8998_pcie_pcs_tbl),
3905        .clk_list               = msm8996_phy_clk_l,
3906        .num_clks               = ARRAY_SIZE(msm8996_phy_clk_l),
3907        .reset_list             = ipq8074_pciephy_reset_l,
3908        .num_resets             = ARRAY_SIZE(ipq8074_pciephy_reset_l),
3909        .vreg_list              = qmp_phy_vreg_l,
3910        .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
3911        .regs                   = pciephy_regs_layout,
3912
3913        .start_ctrl             = SERDES_START | PCS_START,
3914        .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
3915        .phy_status             = PHYSTATUS,
3916};
3917
3918static const struct qmp_phy_cfg msm8998_usb3phy_cfg = {
3919        .type                   = PHY_TYPE_USB3,
3920        .nlanes                 = 1,
3921
3922        .serdes_tbl             = msm8998_usb3_serdes_tbl,
3923        .serdes_tbl_num         = ARRAY_SIZE(msm8998_usb3_serdes_tbl),
3924        .tx_tbl                 = msm8998_usb3_tx_tbl,
3925        .tx_tbl_num             = ARRAY_SIZE(msm8998_usb3_tx_tbl),
3926        .rx_tbl                 = msm8998_usb3_rx_tbl,
3927        .rx_tbl_num             = ARRAY_SIZE(msm8998_usb3_rx_tbl),
3928        .pcs_tbl                = msm8998_usb3_pcs_tbl,
3929        .pcs_tbl_num            = ARRAY_SIZE(msm8998_usb3_pcs_tbl),
3930        .clk_list               = msm8996_phy_clk_l,
3931        .num_clks               = ARRAY_SIZE(msm8996_phy_clk_l),
3932        .reset_list             = msm8996_usb3phy_reset_l,
3933        .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
3934        .vreg_list              = qmp_phy_vreg_l,
3935        .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
3936        .regs                   = qmp_v3_usb3phy_regs_layout,
3937
3938        .start_ctrl             = SERDES_START | PCS_START,
3939        .pwrdn_ctrl             = SW_PWRDN,
3940        .phy_status             = PHYSTATUS,
3941
3942        .is_dual_lane_phy       = true,
3943};
3944
3945static const struct qmp_phy_cfg sm8150_ufsphy_cfg = {
3946        .type                   = PHY_TYPE_UFS,
3947        .nlanes                 = 2,
3948
3949        .serdes_tbl             = sm8150_ufsphy_serdes_tbl,
3950        .serdes_tbl_num         = ARRAY_SIZE(sm8150_ufsphy_serdes_tbl),
3951        .tx_tbl                 = sm8150_ufsphy_tx_tbl,
3952        .tx_tbl_num             = ARRAY_SIZE(sm8150_ufsphy_tx_tbl),
3953        .rx_tbl                 = sm8150_ufsphy_rx_tbl,
3954        .rx_tbl_num             = ARRAY_SIZE(sm8150_ufsphy_rx_tbl),
3955        .pcs_tbl                = sm8150_ufsphy_pcs_tbl,
3956        .pcs_tbl_num            = ARRAY_SIZE(sm8150_ufsphy_pcs_tbl),
3957        .clk_list               = sdm845_ufs_phy_clk_l,
3958        .num_clks               = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
3959        .vreg_list              = qmp_phy_vreg_l,
3960        .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
3961        .regs                   = sm8150_ufsphy_regs_layout,
3962
3963        .start_ctrl             = SERDES_START,
3964        .pwrdn_ctrl             = SW_PWRDN,
3965        .phy_status             = PHYSTATUS,
3966
3967        .is_dual_lane_phy       = true,
3968};
3969
3970static const struct qmp_phy_cfg sm8150_usb3phy_cfg = {
3971        .type                   = PHY_TYPE_USB3,
3972        .nlanes                 = 1,
3973
3974        .serdes_tbl             = sm8150_usb3_serdes_tbl,
3975        .serdes_tbl_num         = ARRAY_SIZE(sm8150_usb3_serdes_tbl),
3976        .tx_tbl                 = sm8150_usb3_tx_tbl,
3977        .tx_tbl_num             = ARRAY_SIZE(sm8150_usb3_tx_tbl),
3978        .rx_tbl                 = sm8150_usb3_rx_tbl,
3979        .rx_tbl_num             = ARRAY_SIZE(sm8150_usb3_rx_tbl),
3980        .pcs_tbl                = sm8150_usb3_pcs_tbl,
3981        .pcs_tbl_num            = ARRAY_SIZE(sm8150_usb3_pcs_tbl),
3982        .clk_list               = qmp_v4_phy_clk_l,
3983        .num_clks               = ARRAY_SIZE(qmp_v4_phy_clk_l),
3984        .reset_list             = msm8996_usb3phy_reset_l,
3985        .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
3986        .vreg_list              = qmp_phy_vreg_l,
3987        .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
3988        .regs                   = qmp_v4_usb3phy_regs_layout,
3989
3990        .start_ctrl             = SERDES_START | PCS_START,
3991        .pwrdn_ctrl             = SW_PWRDN,
3992        .phy_status             = PHYSTATUS,
3993
3994
3995        .has_pwrdn_delay        = true,
3996        .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
3997        .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
3998
3999        .has_phy_dp_com_ctrl    = true,
4000        .is_dual_lane_phy       = true,

4001};
4002
4003static const struct qmp_phy_cfg sc8180x_pciephy_cfg = {
4004        .type = PHY_TYPE_PCIE,
4005        .nlanes = 1,
4006
4007        .serdes_tbl             = sc8180x_qmp_pcie_serdes_tbl,
4008        .serdes_tbl_num         = ARRAY_SIZE(sc8180x_qmp_pcie_serdes_tbl),
4009        .tx_tbl                 = sc8180x_qmp_pcie_tx_tbl,
4010        .tx_tbl_num             = ARRAY_SIZE(sc8180x_qmp_pcie_tx_tbl),
4011        .rx_tbl                 = sc8180x_qmp_pcie_rx_tbl,
4012        .rx_tbl_num             = ARRAY_SIZE(sc8180x_qmp_pcie_rx_tbl),
4013        .pcs_tbl                = sc8180x_qmp_pcie_pcs_tbl,
4014        .pcs_tbl_num            = ARRAY_SIZE(sc8180x_qmp_pcie_pcs_tbl),
4015        .pcs_misc_tbl           = sc8180x_qmp_pcie_pcs_misc_tbl,
4016        .pcs_misc_tbl_num       = ARRAY_SIZE(sc8180x_qmp_pcie_pcs_misc_tbl),
4017        .clk_list               = sdm845_pciephy_clk_l,
4018        .num_clks               = ARRAY_SIZE(sdm845_pciephy_clk_l),
4019        .reset_list             = sdm845_pciephy_reset_l,
4020        .num_resets             = ARRAY_SIZE(sdm845_pciephy_reset_l),
4021        .vreg_list              = qmp_phy_vreg_l,
4022        .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
4023        .regs                   = sm8250_pcie_regs_layout,
4024
4025        .start_ctrl             = PCS_START | SERDES_START,
4026        .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
4027
4028        .has_pwrdn_delay        = true,
4029        .pwrdn_delay_min        = 995,          /* us */
4030        .pwrdn_delay_max        = 1005,         /* us */
4031};
4032
4033static const struct qmp_phy_cfg sc8180x_dpphy_cfg = {
4034        .type                   = PHY_TYPE_DP,
4035        .nlanes                 = 1,
4036
4037        .serdes_tbl             = qmp_v4_dp_serdes_tbl,
4038        .serdes_tbl_num         = ARRAY_SIZE(qmp_v4_dp_serdes_tbl),
4039        .tx_tbl                 = qmp_v4_dp_tx_tbl,
4040        .tx_tbl_num             = ARRAY_SIZE(qmp_v4_dp_tx_tbl),
4041
4042        .serdes_tbl_rbr         = qmp_v4_dp_serdes_tbl_rbr,
4043        .serdes_tbl_rbr_num     = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr),
4044        .serdes_tbl_hbr         = qmp_v4_dp_serdes_tbl_hbr,
4045        .serdes_tbl_hbr_num     = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr),
4046        .serdes_tbl_hbr2        = qmp_v4_dp_serdes_tbl_hbr2,
4047        .serdes_tbl_hbr2_num    = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2),
4048        .serdes_tbl_hbr3        = qmp_v4_dp_serdes_tbl_hbr3,
4049        .serdes_tbl_hbr3_num    = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3),
4050
4051        .clk_list               = qmp_v3_phy_clk_l,
4052        .num_clks               = ARRAY_SIZE(qmp_v3_phy_clk_l),
4053        .reset_list             = sc7180_usb3phy_reset_l,
4054        .num_resets             = ARRAY_SIZE(sc7180_usb3phy_reset_l),
4055        .vreg_list              = qmp_phy_vreg_l,
4056        .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
4057        .regs                   = qmp_v3_usb3phy_regs_layout,
4058
4059        .has_phy_dp_com_ctrl    = true,
4060        .is_dual_lane_phy       = true,
4061
4062        .dp_aux_init = qcom_qmp_v4_phy_dp_aux_init,
4063        .configure_dp_tx = qcom_qmp_v4_phy_configure_dp_tx,
4064        .configure_dp_phy = qcom_qmp_v4_phy_configure_dp_phy,
4065        .calibrate_dp_phy = qcom_qmp_v4_dp_phy_calibrate,
4066};
4067
4068static const struct qmp_phy_combo_cfg sc8180x_usb3dpphy_cfg = {
4069        .usb_cfg                = &sm8150_usb3phy_cfg,
4070        .dp_cfg                 = &sc8180x_dpphy_cfg,
4071};
4072
4073static const struct qmp_phy_cfg sm8150_usb3_uniphy_cfg = {
4074        .type                   = PHY_TYPE_USB3,
4075        .nlanes                 = 1,
4076
4077        .serdes_tbl             = sm8150_usb3_uniphy_serdes_tbl,
4078        .serdes_tbl_num         = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
4079        .tx_tbl                 = sm8150_usb3_uniphy_tx_tbl,
4080        .tx_tbl_num             = ARRAY_SIZE(sm8150_usb3_uniphy_tx_tbl),
4081        .rx_tbl                 = sm8150_usb3_uniphy_rx_tbl,
4082        .rx_tbl_num             = ARRAY_SIZE(sm8150_usb3_uniphy_rx_tbl),
4083        .pcs_tbl                = sm8150_usb3_uniphy_pcs_tbl,
4084        .pcs_tbl_num            = ARRAY_SIZE(sm8150_usb3_uniphy_pcs_tbl),
4085        .clk_list               = qmp_v4_phy_clk_l,
4086        .num_clks               = ARRAY_SIZE(qmp_v4_phy_clk_l),
4087        .reset_list             = msm8996_usb3phy_reset_l,
4088        .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
4089        .vreg_list              = qmp_phy_vreg_l,
4090        .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
4091        .regs                   = qmp_v4_usb3_uniphy_regs_layout,
4092
4093        .start_ctrl             = SERDES_START | PCS_START,
4094        .pwrdn_ctrl             = SW_PWRDN,
4095        .phy_status             = PHYSTATUS,
4096
4097        .has_pwrdn_delay        = true,
4098        .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
4099        .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
4100};
4101
4102static const struct qmp_phy_cfg sm8250_usb3phy_cfg = {
4103        .type                   = PHY_TYPE_USB3,
4104        .nlanes                 = 1,
4105
4106        .serdes_tbl             = sm8150_usb3_serdes_tbl,
4107        .serdes_tbl_num         = ARRAY_SIZE(sm8150_usb3_serdes_tbl),
4108        .tx_tbl                 = sm8250_usb3_tx_tbl,
4109        .tx_tbl_num             = ARRAY_SIZE(sm8250_usb3_tx_tbl),
4110        .rx_tbl                 = sm8250_usb3_rx_tbl,
4111        .rx_tbl_num             = ARRAY_SIZE(sm8250_usb3_rx_tbl),
4112        .pcs_tbl                = sm8250_usb3_pcs_tbl,
4113        .pcs_tbl_num            = ARRAY_SIZE(sm8250_usb3_pcs_tbl),
4114        .clk_list               = qmp_v4_sm8250_usbphy_clk_l,
4115        .num_clks               = ARRAY_SIZE(qmp_v4_sm8250_usbphy_clk_l),
4116        .reset_list             = msm8996_usb3phy_reset_l,
4117        .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
4118        .vreg_list              = qmp_phy_vreg_l,
4119        .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
4120        .regs                   = qmp_v4_usb3phy_regs_layout,
4121
4122        .start_ctrl             = SERDES_START | PCS_START,
4123        .pwrdn_ctrl             = SW_PWRDN,
4124        .phy_status             = PHYSTATUS,
4125
4126        .has_pwrdn_delay        = true,
4127        .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
4128        .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
4129
4130        .has_phy_dp_com_ctrl    = true,
4131        .is_dual_lane_phy       = true,
4132};
4133
4134static const struct qmp_phy_cfg sm8250_usb3_uniphy_cfg = {
4135        .type                   = PHY_TYPE_USB3,
4136        .nlanes                 = 1,
4137
4138        .serdes_tbl             = sm8150_usb3_uniphy_serdes_tbl,
4139        .serdes_tbl_num         = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
4140        .tx_tbl                 = sm8250_usb3_uniphy_tx_tbl,
4141        .tx_tbl_num             = ARRAY_SIZE(sm8250_usb3_uniphy_tx_tbl),
4142        .rx_tbl                 = sm8250_usb3_uniphy_rx_tbl,
4143        .rx_tbl_num             = ARRAY_SIZE(sm8250_usb3_uniphy_rx_tbl),
4144        .pcs_tbl                = sm8250_usb3_uniphy_pcs_tbl,
4145        .pcs_tbl_num            = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_tbl),
4146        .clk_list               = qmp_v4_phy_clk_l,
4147        .num_clks               = ARRAY_SIZE(qmp_v4_phy_clk_l),
4148        .reset_list             = msm8996_usb3phy_reset_l,
4149        .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
4150        .vreg_list              = qmp_phy_vreg_l,
4151        .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
4152        .regs                   = qmp_v4_usb3_uniphy_regs_layout,
4153
4154        .start_ctrl             = SERDES_START | PCS_START,
4155        .pwrdn_ctrl             = SW_PWRDN,
4156        .phy_status             = PHYSTATUS,
4157
4158        .has_pwrdn_delay        = true,
4159        .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
4160        .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
4161};
4162
4163static const struct qmp_phy_cfg sm8250_dpphy_cfg = {
4164        .type                   = PHY_TYPE_DP,
4165        .nlanes                 = 1,
4166
4167        .serdes_tbl             = qmp_v4_dp_serdes_tbl,
4168        .serdes_tbl_num         = ARRAY_SIZE(qmp_v4_dp_serdes_tbl),
4169        .tx_tbl                 = qmp_v4_dp_tx_tbl,
4170        .tx_tbl_num             = ARRAY_SIZE(qmp_v4_dp_tx_tbl),
4171
4172        .serdes_tbl_rbr         = qmp_v4_dp_serdes_tbl_rbr,
4173        .serdes_tbl_rbr_num     = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr),
4174        .serdes_tbl_hbr         = qmp_v4_dp_serdes_tbl_hbr,
4175        .serdes_tbl_hbr_num     = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr),
4176        .serdes_tbl_hbr2        = qmp_v4_dp_serdes_tbl_hbr2,
4177        .serdes_tbl_hbr2_num    = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2),
4178        .serdes_tbl_hbr3        = qmp_v4_dp_serdes_tbl_hbr3,
4179        .serdes_tbl_hbr3_num    = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3),
4180
4181        .clk_list               = qmp_v4_phy_clk_l,
4182        .num_clks               = ARRAY_SIZE(qmp_v4_phy_clk_l),
4183        .reset_list             = msm8996_usb3phy_reset_l,
4184        .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
4185        .vreg_list              = qmp_phy_vreg_l,
4186        .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
4187        .regs                   = qmp_v4_usb3phy_regs_layout,
4188
4189        .has_phy_dp_com_ctrl    = true,
4190        .is_dual_lane_phy       = true,
4191
4192        .dp_aux_init = qcom_qmp_v4_phy_dp_aux_init,
4193        .configure_dp_tx = qcom_qmp_v4_phy_configure_dp_tx,
4194        .configure_dp_phy = qcom_qmp_v4_phy_configure_dp_phy,
4195        .calibrate_dp_phy = qcom_qmp_v4_dp_phy_calibrate,
4196};
4197
4198static const struct qmp_phy_combo_cfg sm8250_usb3dpphy_cfg = {
4199        .usb_cfg                = &sm8250_usb3phy_cfg,
4200        .dp_cfg                 = &sm8250_dpphy_cfg,
4201};
4202
4203static const struct qmp_phy_cfg sdx55_usb3_uniphy_cfg = {
4204        .type                   = PHY_TYPE_USB3,
4205        .nlanes                 = 1,
4206
4207        .serdes_tbl             = sm8150_usb3_uniphy_serdes_tbl,
4208        .serdes_tbl_num         = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
4209        .tx_tbl                 = sdx55_usb3_uniphy_tx_tbl,
4210        .tx_tbl_num             = ARRAY_SIZE(sdx55_usb3_uniphy_tx_tbl),
4211        .rx_tbl                 = sdx55_usb3_uniphy_rx_tbl,
4212        .rx_tbl_num             = ARRAY_SIZE(sdx55_usb3_uniphy_rx_tbl),
4213        .pcs_tbl                = sm8250_usb3_uniphy_pcs_tbl,
4214        .pcs_tbl_num            = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_tbl),
4215        .clk_list               = qmp_v4_sdx55_usbphy_clk_l,
4216        .num_clks               = ARRAY_SIZE(qmp_v4_sdx55_usbphy_clk_l),
4217        .reset_list             = msm8996_usb3phy_reset_l,
4218        .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
4219        .vreg_list              = qmp_phy_vreg_l,
4220        .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
4221        .regs                   = qmp_v4_usb3_uniphy_regs_layout,
4222
4223        .start_ctrl             = SERDES_START | PCS_START,
4224        .pwrdn_ctrl             = SW_PWRDN,
4225        .phy_status             = PHYSTATUS,
4226
4227        .has_pwrdn_delay        = true,
4228        .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
4229        .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
4230};
4231
4232static const struct qmp_phy_cfg sdx55_qmp_pciephy_cfg = {
4233        .type = PHY_TYPE_PCIE,
4234        .nlanes = 2,
4235
4236        .serdes_tbl             = sdx55_qmp_pcie_serdes_tbl,
4237        .serdes_tbl_num         = ARRAY_SIZE(sdx55_qmp_pcie_serdes_tbl),
4238        .tx_tbl                 = sdx55_qmp_pcie_tx_tbl,
4239        .tx_tbl_num             = ARRAY_SIZE(sdx55_qmp_pcie_tx_tbl),
4240        .rx_tbl                 = sdx55_qmp_pcie_rx_tbl,
4241        .rx_tbl_num             = ARRAY_SIZE(sdx55_qmp_pcie_rx_tbl),
4242        .pcs_tbl                = sdx55_qmp_pcie_pcs_tbl,
4243        .pcs_tbl_num            = ARRAY_SIZE(sdx55_qmp_pcie_pcs_tbl),
4244        .pcs_misc_tbl           = sdx55_qmp_pcie_pcs_misc_tbl,
4245        .pcs_misc_tbl_num       = ARRAY_SIZE(sdx55_qmp_pcie_pcs_misc_tbl),
4246        .clk_list               = sdm845_pciephy_clk_l,
4247        .num_clks               = ARRAY_SIZE(sdm845_pciephy_clk_l),
4248        .reset_list             = sdm845_pciephy_reset_l,
4249        .num_resets             = ARRAY_SIZE(sdm845_pciephy_reset_l),
4250        .vreg_list              = qmp_phy_vreg_l,
4251        .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
4252        .regs                   = sm8250_pcie_regs_layout,
4253
4254        .start_ctrl             = PCS_START | SERDES_START,
4255        .pwrdn_ctrl             = SW_PWRDN,
4256        .phy_status             = PHYSTATUS_4_20,
4257
4258        .is_dual_lane_phy       = true,
4259        .has_pwrdn_delay        = true,
4260        .pwrdn_delay_min        = 995,          /* us */
4261        .pwrdn_delay_max        = 1005,         /* us */
4262};
4263
4264static const struct qmp_phy_cfg sdx65_usb3_uniphy_cfg = {
4265        .type                   = PHY_TYPE_USB3,
4266        .nlanes                 = 1,
4267
4268        .serdes_tbl             = sm8150_usb3_uniphy_serdes_tbl,
4269        .serdes_tbl_num         = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
4270        .tx_tbl                 = sdx65_usb3_uniphy_tx_tbl,
4271        .tx_tbl_num             = ARRAY_SIZE(sdx65_usb3_uniphy_tx_tbl),
4272        .rx_tbl                 = sdx65_usb3_uniphy_rx_tbl,
4273        .rx_tbl_num             = ARRAY_SIZE(sdx65_usb3_uniphy_rx_tbl),
4274        .pcs_tbl                = sm8350_usb3_uniphy_pcs_tbl,
4275        .pcs_tbl_num            = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_tbl),
4276        .clk_list               = qmp_v4_sdx55_usbphy_clk_l,
4277        .num_clks               = ARRAY_SIZE(qmp_v4_sdx55_usbphy_clk_l),
4278        .reset_list             = msm8996_usb3phy_reset_l,
4279        .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
4280        .vreg_list              = qmp_phy_vreg_l,
4281        .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
4282        .regs                   = sm8350_usb3_uniphy_regs_layout,
4283
4284        .start_ctrl             = SERDES_START | PCS_START,
4285        .pwrdn_ctrl             = SW_PWRDN,
4286        .phy_status             = PHYSTATUS,
4287
4288        .has_pwrdn_delay        = true,
4289        .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
4290        .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
4291};
4292
4293static const struct qmp_phy_cfg sm8350_ufsphy_cfg = {
4294        .type                   = PHY_TYPE_UFS,
4295        .nlanes                 = 2,
4296
4297        .serdes_tbl             = sm8350_ufsphy_serdes_tbl,
4298        .serdes_tbl_num         = ARRAY_SIZE(sm8350_ufsphy_serdes_tbl),
4299        .tx_tbl                 = sm8350_ufsphy_tx_tbl,
4300        .tx_tbl_num             = ARRAY_SIZE(sm8350_ufsphy_tx_tbl),
4301        .rx_tbl                 = sm8350_ufsphy_rx_tbl,
4302        .rx_tbl_num             = ARRAY_SIZE(sm8350_ufsphy_rx_tbl),
4303        .pcs_tbl                = sm8350_ufsphy_pcs_tbl,
4304        .pcs_tbl_num            = ARRAY_SIZE(sm8350_ufsphy_pcs_tbl),
4305        .clk_list               = sdm845_ufs_phy_clk_l,
4306        .num_clks               = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
4307        .vreg_list              = qmp_phy_vreg_l,
4308        .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
4309        .regs                   = sm8150_ufsphy_regs_layout,
4310
4311        .start_ctrl             = SERDES_START,
4312        .pwrdn_ctrl             = SW_PWRDN,
4313        .phy_status             = PHYSTATUS,
4314
4315        .is_dual_lane_phy       = true,
4316};
4317
4318static const struct qmp_phy_cfg sm8350_usb3phy_cfg = {
4319        .type                   = PHY_TYPE_USB3,
4320        .nlanes                 = 1,
4321
4322        .serdes_tbl             = sm8150_usb3_serdes_tbl,
4323        .serdes_tbl_num         = ARRAY_SIZE(sm8150_usb3_serdes_tbl),
4324        .tx_tbl                 = sm8350_usb3_tx_tbl,
4325        .tx_tbl_num             = ARRAY_SIZE(sm8350_usb3_tx_tbl),
4326        .rx_tbl                 = sm8350_usb3_rx_tbl,
4327        .rx_tbl_num             = ARRAY_SIZE(sm8350_usb3_rx_tbl),
4328        .pcs_tbl                = sm8350_usb3_pcs_tbl,
4329        .pcs_tbl_num            = ARRAY_SIZE(sm8350_usb3_pcs_tbl),
4330        .clk_list               = qmp_v4_sm8250_usbphy_clk_l,
4331        .num_clks               = ARRAY_SIZE(qmp_v4_sm8250_usbphy_clk_l),
4332        .reset_list             = msm8996_usb3phy_reset_l,
4333        .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
4334        .vreg_list              = qmp_phy_vreg_l,
4335        .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
4336        .regs                   = qmp_v4_usb3phy_regs_layout,
4337
4338        .start_ctrl             = SERDES_START | PCS_START,
4339        .pwrdn_ctrl             = SW_PWRDN,
4340        .phy_status             = PHYSTATUS,
4341
4342        .has_pwrdn_delay        = true,
4343        .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
4344        .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
4345
4346        .has_phy_dp_com_ctrl    = true,
4347        .is_dual_lane_phy       = true,
4348};
4349
4350static const struct qmp_phy_cfg sm8350_usb3_uniphy_cfg = {
4351        .type                   = PHY_TYPE_USB3,
4352        .nlanes                 = 1,
4353
4354        .serdes_tbl             = sm8150_usb3_uniphy_serdes_tbl,
4355        .serdes_tbl_num         = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
4356        .tx_tbl                 = sm8350_usb3_uniphy_tx_tbl,
4357        .tx_tbl_num             = ARRAY_SIZE(sm8350_usb3_uniphy_tx_tbl),
4358        .rx_tbl                 = sm8350_usb3_uniphy_rx_tbl,
4359        .rx_tbl_num             = ARRAY_SIZE(sm8350_usb3_uniphy_rx_tbl),
4360        .pcs_tbl                = sm8350_usb3_uniphy_pcs_tbl,
4361        .pcs_tbl_num            = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_tbl),
4362        .clk_list               = qmp_v4_phy_clk_l,
4363        .num_clks               = ARRAY_SIZE(qmp_v4_phy_clk_l),
4364        .reset_list             = msm8996_usb3phy_reset_l,
4365        .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
4366        .vreg_list              = qmp_phy_vreg_l,
4367        .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
4368        .regs                   = sm8350_usb3_uniphy_regs_layout,
4369
4370        .start_ctrl             = SERDES_START | PCS_START,
4371        .pwrdn_ctrl             = SW_PWRDN,
4372        .phy_status             = PHYSTATUS,
4373
4374        .has_pwrdn_delay        = true,
4375        .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
4376        .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
4377};
4378
4379static const struct qmp_phy_cfg sm8450_ufsphy_cfg = {
4380        .type                   = PHY_TYPE_UFS,
4381        .nlanes                 = 2,
4382
4383        .serdes_tbl             = sm8350_ufsphy_serdes_tbl,
4384        .serdes_tbl_num         = ARRAY_SIZE(sm8350_ufsphy_serdes_tbl),
4385        .tx_tbl                 = sm8350_ufsphy_tx_tbl,
4386        .tx_tbl_num             = ARRAY_SIZE(sm8350_ufsphy_tx_tbl),
4387        .rx_tbl                 = sm8350_ufsphy_rx_tbl,
4388        .rx_tbl_num             = ARRAY_SIZE(sm8350_ufsphy_rx_tbl),
4389        .pcs_tbl                = sm8350_ufsphy_pcs_tbl,
4390        .pcs_tbl_num            = ARRAY_SIZE(sm8350_ufsphy_pcs_tbl),
4391        .clk_list               = sm8450_ufs_phy_clk_l,
4392        .num_clks               = ARRAY_SIZE(sm8450_ufs_phy_clk_l),
4393        .vreg_list              = qmp_phy_vreg_l,
4394        .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
4395        .regs                   = sm8150_ufsphy_regs_layout,
4396
4397        .start_ctrl             = SERDES_START,
4398        .pwrdn_ctrl             = SW_PWRDN,
4399        .phy_status             = PHYSTATUS,
4400
4401        .is_dual_lane_phy       = true,
4402};
4403
4404static const struct qmp_phy_cfg sm8450_qmp_gen3x1_pciephy_cfg = {
4405        .type = PHY_TYPE_PCIE,
4406        .nlanes = 1,
4407
4408        .serdes_tbl             = sm8450_qmp_gen3x1_pcie_serdes_tbl,
4409        .serdes_tbl_num         = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_serdes_tbl),
4410        .tx_tbl                 = sm8450_qmp_gen3x1_pcie_tx_tbl,
4411        .tx_tbl_num             = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_tx_tbl),
4412        .rx_tbl                 = sm8450_qmp_gen3x1_pcie_rx_tbl,
4413        .rx_tbl_num             = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_rx_tbl),
4414        .pcs_tbl                = sm8450_qmp_gen3x1_pcie_pcs_tbl,
4415        .pcs_tbl_num            = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_tbl),
4416        .pcs_misc_tbl           = sm8450_qmp_gen3x1_pcie_pcs_misc_tbl,
4417        .pcs_misc_tbl_num       = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_misc_tbl),
4418        .clk_list               = sdm845_pciephy_clk_l,
4419        .num_clks               = ARRAY_SIZE(sdm845_pciephy_clk_l),
4420        .reset_list             = sdm845_pciephy_reset_l,
4421        .num_resets             = ARRAY_SIZE(sdm845_pciephy_reset_l),
4422        .vreg_list              = qmp_phy_vreg_l,
4423        .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
4424        .regs                   = sm8250_pcie_regs_layout,
4425
4426        .start_ctrl             = SERDES_START | PCS_START,
4427        .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
4428        .phy_status             = PHYSTATUS,
4429
4430        .has_pwrdn_delay        = true,
4431        .pwrdn_delay_min        = 995,          /* us */
4432        .pwrdn_delay_max        = 1005,         /* us */
4433};
4434
4435static const struct qmp_phy_cfg sm8450_qmp_gen4x2_pciephy_cfg = {
4436        .type = PHY_TYPE_PCIE,
4437        .nlanes = 2,
4438
4439        .serdes_tbl             = sm8450_qmp_gen4x2_pcie_serdes_tbl,
4440        .serdes_tbl_num         = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_serdes_tbl),
4441        .tx_tbl                 = sm8450_qmp_gen4x2_pcie_tx_tbl,
4442        .tx_tbl_num             = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_tx_tbl),
4443        .rx_tbl                 = sm8450_qmp_gen4x2_pcie_rx_tbl,
4444        .rx_tbl_num             = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_rx_tbl),
4445        .pcs_tbl                = sm8450_qmp_gen4x2_pcie_pcs_tbl,
4446        .pcs_tbl_num            = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_pcs_tbl),
4447        .pcs_misc_tbl           = sm8450_qmp_gen4x2_pcie_pcs_misc_tbl,
4448        .pcs_misc_tbl_num       = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_pcs_misc_tbl),
4449        .clk_list               = sdm845_pciephy_clk_l,
4450        .num_clks               = ARRAY_SIZE(sdm845_pciephy_clk_l),
4451        .reset_list             = sdm845_pciephy_reset_l,
4452        .num_resets             = ARRAY_SIZE(sdm845_pciephy_reset_l),
4453        .vreg_list              = qmp_phy_vreg_l,
4454        .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
4455        .regs                   = sm8250_pcie_regs_layout,
4456
4457        .start_ctrl             = SERDES_START | PCS_START,
4458        .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
4459        .phy_status             = PHYSTATUS_4_20,
4460
4461        .is_dual_lane_phy       = true,
4462        .has_pwrdn_delay        = true,
4463        .pwrdn_delay_min        = 995,          /* us */
4464        .pwrdn_delay_max        = 1005,         /* us */
4465};
4466
4467static const struct qmp_phy_cfg qcm2290_usb3phy_cfg = {
4468        .type                   = PHY_TYPE_USB3,
4469        .nlanes                 = 1,
4470
4471        .serdes_tbl             = qcm2290_usb3_serdes_tbl,
4472        .serdes_tbl_num         = ARRAY_SIZE(qcm2290_usb3_serdes_tbl),
4473        .tx_tbl                 = qcm2290_usb3_tx_tbl,
4474        .tx_tbl_num             = ARRAY_SIZE(qcm2290_usb3_tx_tbl),
4475        .rx_tbl                 = qcm2290_usb3_rx_tbl,
4476        .rx_tbl_num             = ARRAY_SIZE(qcm2290_usb3_rx_tbl),
4477        .pcs_tbl                = qcm2290_usb3_pcs_tbl,
4478        .pcs_tbl_num            = ARRAY_SIZE(qcm2290_usb3_pcs_tbl),
4479        .clk_list               = qcm2290_usb3phy_clk_l,
4480        .num_clks               = ARRAY_SIZE(qcm2290_usb3phy_clk_l),
4481        .reset_list             = qcm2290_usb3phy_reset_l,
4482        .num_resets             = ARRAY_SIZE(qcm2290_usb3phy_reset_l),
4483        .vreg_list              = qmp_phy_vreg_l,
4484        .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
4485        .regs                   = qcm2290_usb3phy_regs_layout,
4486
4487        .start_ctrl             = SERDES_START | PCS_START,
4488        .pwrdn_ctrl             = SW_PWRDN,
4489        .phy_status             = PHYSTATUS,
4490
4491        .is_dual_lane_phy       = true,
4492};
4493
4494static void qcom_qmp_phy_configure_lane(void __iomem *base,
4495                                        const unsigned int *regs,
4496                                        const struct qmp_phy_init_tbl tbl[],
4497                                        int num,
4498                                        u8 lane_mask)
4499{
4500        int i;
4501        const struct qmp_phy_init_tbl *t = tbl;
4502
4503        if (!t)
4504                return;
4505
4506        for (i = 0; i < num; i++, t++) {
4507                if (!(t->lane_mask & lane_mask))
4508                        continue;
4509
4510                if (t->in_layout)
4511                        writel(t->val, base + regs[t->offset]);
4512                else
4513                        writel(t->val, base + t->offset);
4514        }
4515}
4516
4517static void qcom_qmp_phy_configure(void __iomem *base,
4518                                   const unsigned int *regs,
4519                                   const struct qmp_phy_init_tbl tbl[],
4520                                   int num)
4521{
4522        qcom_qmp_phy_configure_lane(base, regs, tbl, num, 0xff);
4523}
4524
4525static int qcom_qmp_phy_serdes_init(struct qmp_phy *qphy)
4526{
4527        struct qcom_qmp *qmp = qphy->qmp;
4528        const struct qmp_phy_cfg *cfg = qphy->cfg;
4529        void __iomem *serdes = qphy->serdes;
4530        const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
4531        const struct qmp_phy_init_tbl *serdes_tbl = cfg->serdes_tbl;
4532        int serdes_tbl_num = cfg->serdes_tbl_num;
4533        int ret;
4534
4535        qcom_qmp_phy_configure(serdes, cfg->regs, serdes_tbl, serdes_tbl_num);
4536        if (cfg->serdes_tbl_sec)
4537                qcom_qmp_phy_configure(serdes, cfg->regs, cfg->serdes_tbl_sec,
4538                                       cfg->serdes_tbl_num_sec);
4539
4540        if (cfg->type == PHY_TYPE_DP) {
4541                switch (dp_opts->link_rate) {
4542                case 1620:
4543                        qcom_qmp_phy_configure(serdes, cfg->regs,
4544                                               cfg->serdes_tbl_rbr,
4545                                               cfg->serdes_tbl_rbr_num);
4546                        break;
4547                case 2700:
4548                        qcom_qmp_phy_configure(serdes, cfg->regs,
4549                                               cfg->serdes_tbl_hbr,
4550                                               cfg->serdes_tbl_hbr_num);
4551                        break;
4552                case 5400:
4553                        qcom_qmp_phy_configure(serdes, cfg->regs,
4554                                               cfg->serdes_tbl_hbr2,
4555                                               cfg->serdes_tbl_hbr2_num);
4556                        break;
4557                case 8100:
4558                        qcom_qmp_phy_configure(serdes, cfg->regs,
4559                                               cfg->serdes_tbl_hbr3,
4560                                               cfg->serdes_tbl_hbr3_num);
4561                        break;
4562                default:
4563                        /* Other link rates aren't supported */
4564                        return -EINVAL;
4565                }
4566        }
4567
4568
4569        if (cfg->has_phy_com_ctrl) {
4570                void __iomem *status;
4571                unsigned int mask, val;
4572
4573                qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET], SW_RESET);
4574                qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL],
4575                             SERDES_START | PCS_START);
4576
4577                status = serdes + cfg->regs[QPHY_COM_PCS_READY_STATUS];
4578                mask = cfg->mask_com_pcs_ready;
4579
4580                ret = readl_poll_timeout(status, val, (val & mask), 10,
4581                                         PHY_INIT_COMPLETE_TIMEOUT);
4582                if (ret) {
4583                        dev_err(qmp->dev,
4584                                "phy common block init timed-out\n");
4585                        return ret;
4586                }
4587        }
4588
4589        return 0;
4590}
4591
4592static void qcom_qmp_v3_phy_dp_aux_init(struct qmp_phy *qphy)
4593{
4594        writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
4595               DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN,
4596               qphy->pcs + QSERDES_DP_PHY_PD_CTL);
4597
4598        /* Turn on BIAS current for PHY/PLL */
4599        writel(QSERDES_V3_COM_BIAS_EN | QSERDES_V3_COM_BIAS_EN_MUX |
4600               QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL,
4601               qphy->serdes + QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN);
4602
4603        writel(DP_PHY_PD_CTL_PSR_PWRDN, qphy->pcs + QSERDES_DP_PHY_PD_CTL);
4604
4605        writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
4606               DP_PHY_PD_CTL_LANE_0_1_PWRDN |
4607               DP_PHY_PD_CTL_LANE_2_3_PWRDN | DP_PHY_PD_CTL_PLL_PWRDN |
4608               DP_PHY_PD_CTL_DP_CLAMP_EN,
4609               qphy->pcs + QSERDES_DP_PHY_PD_CTL);
4610
4611        writel(QSERDES_V3_COM_BIAS_EN |
4612               QSERDES_V3_COM_BIAS_EN_MUX | QSERDES_V3_COM_CLKBUF_R_EN |
4613               QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL |
4614               QSERDES_V3_COM_CLKBUF_RX_DRIVE_L,
4615               qphy->serdes + QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN);
4616
4617        writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG0);
4618        writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
4619        writel(0x24, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2);
4620        writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG3);
4621        writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG4);
4622        writel(0x26, qphy->pcs + QSERDES_DP_PHY_AUX_CFG5);
4623        writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG6);
4624        writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG7);
4625        writel(0xbb, qphy->pcs + QSERDES_DP_PHY_AUX_CFG8);
4626        writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG9);
4627        qphy->dp_aux_cfg = 0;
4628
4629        writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK |
4630               PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK |
4631               PHY_AUX_REQ_ERR_MASK,
4632               qphy->pcs + QSERDES_V3_DP_PHY_AUX_INTERRUPT_MASK);
4633}
4634
4635static const u8 qmp_dp_v3_pre_emphasis_hbr3_hbr2[4][4] = {
4636        { 0x00, 0x0c, 0x15, 0x1a },
4637        { 0x02, 0x0e, 0x16, 0xff },
4638        { 0x02, 0x11, 0xff, 0xff },
4639        { 0x04, 0xff, 0xff, 0xff }
4640};
4641
4642static const u8 qmp_dp_v3_voltage_swing_hbr3_hbr2[4][4] = {
4643        { 0x02, 0x12, 0x16, 0x1a },
4644        { 0x09, 0x19, 0x1f, 0xff },
4645        { 0x10, 0x1f, 0xff, 0xff },
4646        { 0x1f, 0xff, 0xff, 0xff }
4647};
4648
4649static const u8 qmp_dp_v3_pre_emphasis_hbr_rbr[4][4] = {
4650        { 0x00, 0x0c, 0x14, 0x19 },
4651        { 0x00, 0x0b, 0x12, 0xff },
4652        { 0x00, 0x0b, 0xff, 0xff },
4653        { 0x04, 0xff, 0xff, 0xff }
4654};
4655
4656static const u8 qmp_dp_v3_voltage_swing_hbr_rbr[4][4] = {
4657        { 0x08, 0x0f, 0x16, 0x1f },
4658        { 0x11, 0x1e, 0x1f, 0xff },
4659        { 0x19, 0x1f, 0xff, 0xff },
4660        { 0x1f, 0xff, 0xff, 0xff }
4661};
4662
4663static int qcom_qmp_phy_configure_dp_swing(struct qmp_phy *qphy,
4664                unsigned int drv_lvl_reg, unsigned int emp_post_reg)
4665{
4666        const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
4667        unsigned int v_level = 0, p_level = 0;
4668        u8 voltage_swing_cfg, pre_emphasis_cfg;
4669        int i;
4670
4671        for (i = 0; i < dp_opts->lanes; i++) {
4672                v_level = max(v_level, dp_opts->voltage[i]);
4673                p_level = max(p_level, dp_opts->pre[i]);
4674        }
4675
4676        if (dp_opts->link_rate <= 2700) {
4677                voltage_swing_cfg = qmp_dp_v3_voltage_swing_hbr_rbr[v_level][p_level];
4678                pre_emphasis_cfg = qmp_dp_v3_pre_emphasis_hbr_rbr[v_level][p_level];
4679        } else {
4680                voltage_swing_cfg = qmp_dp_v3_voltage_swing_hbr3_hbr2[v_level][p_level];
4681                pre_emphasis_cfg = qmp_dp_v3_pre_emphasis_hbr3_hbr2[v_level][p_level];
4682        }
4683
4684        /* TODO: Move check to config check */
4685        if (voltage_swing_cfg == 0xFF && pre_emphasis_cfg == 0xFF)
4686                return -EINVAL;
4687
4688        /* Enable MUX to use Cursor values from these registers */
4689        voltage_swing_cfg |= DP_PHY_TXn_TX_DRV_LVL_MUX_EN;
4690        pre_emphasis_cfg |= DP_PHY_TXn_TX_EMP_POST1_LVL_MUX_EN;
4691
4692        writel(voltage_swing_cfg, qphy->tx + drv_lvl_reg);
4693        writel(pre_emphasis_cfg, qphy->tx + emp_post_reg);
4694        writel(voltage_swing_cfg, qphy->tx2 + drv_lvl_reg);
4695        writel(pre_emphasis_cfg, qphy->tx2 + emp_post_reg);
4696
4697        return 0;
4698}
4699
4700static void qcom_qmp_v3_phy_configure_dp_tx(struct qmp_phy *qphy)
4701{
4702        const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
4703        u32 bias_en, drvr_en;
4704
4705        if (qcom_qmp_phy_configure_dp_swing(qphy,
4706                                QSERDES_V3_TX_TX_DRV_LVL,
4707                                QSERDES_V3_TX_TX_EMP_POST1_LVL) < 0)
4708                return;
4709
4710        if (dp_opts->lanes == 1) {
4711                bias_en = 0x3e;
4712                drvr_en = 0x13;
4713        } else {
4714                bias_en = 0x3f;
4715                drvr_en = 0x10;
4716        }
4717
4718        writel(drvr_en, qphy->tx + QSERDES_V3_TX_HIGHZ_DRVR_EN);
4719        writel(bias_en, qphy->tx + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN);
4720        writel(drvr_en, qphy->tx2 + QSERDES_V3_TX_HIGHZ_DRVR_EN);
4721        writel(bias_en, qphy->tx2 + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN);
4722}
4723
4724static bool qcom_qmp_phy_configure_dp_mode(struct qmp_phy *qphy)
4725{
4726        u32 val;
4727        bool reverse = false;
4728
4729        val = DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
4730              DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN;
4731
4732        /*
4733         * TODO: Assume orientation is CC1 for now and two lanes, need to
4734         * use type-c connector to understand orientation and lanes.
4735         *
4736         * Otherwise val changes to be like below if this code understood
4737         * the orientation of the type-c cable.
4738         *
4739         * if (lane_cnt == 4 || orientation == ORIENTATION_CC2)
4740         *      val |= DP_PHY_PD_CTL_LANE_0_1_PWRDN;
4741         * if (lane_cnt == 4 || orientation == ORIENTATION_CC1)
4742         *      val |= DP_PHY_PD_CTL_LANE_2_3_PWRDN;
4743         * if (orientation == ORIENTATION_CC2)
4744         *      writel(0x4c, qphy->pcs + QSERDES_V3_DP_PHY_MODE);
4745         */
4746        val |= DP_PHY_PD_CTL_LANE_2_3_PWRDN;
4747        writel(val, qphy->pcs + QSERDES_DP_PHY_PD_CTL);
4748
4749        writel(0x5c, qphy->pcs + QSERDES_DP_PHY_MODE);
4750
4751        return reverse;
4752}
4753
4754static int qcom_qmp_v3_phy_configure_dp_phy(struct qmp_phy *qphy)
4755{
4756        const struct qmp_phy_dp_clks *dp_clks = qphy->dp_clks;
4757        const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
4758        u32 phy_vco_div, status;
4759        unsigned long pixel_freq;
4760
4761        qcom_qmp_phy_configure_dp_mode(qphy);
4762
4763        writel(0x05, qphy->pcs + QSERDES_V3_DP_PHY_TX0_TX1_LANE_CTL);
4764        writel(0x05, qphy->pcs + QSERDES_V3_DP_PHY_TX2_TX3_LANE_CTL);
4765
4766        switch (dp_opts->link_rate) {
4767        case 1620:
4768                phy_vco_div = 0x1;
4769                pixel_freq = 1620000000UL / 2;
4770                break;
4771        case 2700:
4772                phy_vco_div = 0x1;
4773                pixel_freq = 2700000000UL / 2;
4774                break;
4775        case 5400:
4776                phy_vco_div = 0x2;
4777                pixel_freq = 5400000000UL / 4;
4778                break;
4779        case 8100:
4780                phy_vco_div = 0x0;
4781                pixel_freq = 8100000000UL / 6;
4782                break;
4783        default:
4784                /* Other link rates aren't supported */
4785                return -EINVAL;
4786        }
4787        writel(phy_vco_div, qphy->pcs + QSERDES_V3_DP_PHY_VCO_DIV);
4788
4789        clk_set_rate(dp_clks->dp_link_hw.clk, dp_opts->link_rate * 100000);
4790        clk_set_rate(dp_clks->dp_pixel_hw.clk, pixel_freq);
4791
4792        writel(0x04, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2);
4793        writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG);
4794        writel(0x05, qphy->pcs + QSERDES_DP_PHY_CFG);
4795        writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG);
4796        writel(0x09, qphy->pcs + QSERDES_DP_PHY_CFG);
4797
4798        writel(0x20, qphy->serdes + QSERDES_V3_COM_RESETSM_CNTRL);
4799
4800        if (readl_poll_timeout(qphy->serdes + QSERDES_V3_COM_C_READY_STATUS,
4801                        status,
4802                        ((status & BIT(0)) > 0),
4803                        500,
4804                        10000))
4805                return -ETIMEDOUT;
4806
4807        writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG);
4808
4809        if (readl_poll_timeout(qphy->pcs + QSERDES_V3_DP_PHY_STATUS,
4810                        status,
4811                        ((status & BIT(1)) > 0),
4812                        500,
4813                        10000))
4814                return -ETIMEDOUT;
4815
4816        writel(0x18, qphy->pcs + QSERDES_DP_PHY_CFG);
4817        udelay(2000);
4818        writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG);
4819
4820        return readl_poll_timeout(qphy->pcs + QSERDES_V3_DP_PHY_STATUS,
4821                        status,
4822                        ((status & BIT(1)) > 0),
4823                        500,
4824                        10000);
4825}
4826
4827/*
4828 * We need to calibrate the aux setting here as many times
4829 * as the caller tries
4830 */
4831static int qcom_qmp_v3_dp_phy_calibrate(struct qmp_phy *qphy)
4832{
4833        static const u8 cfg1_settings[] = { 0x13, 0x23, 0x1d };
4834        u8 val;
4835
4836        qphy->dp_aux_cfg++;
4837        qphy->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings);
4838        val = cfg1_settings[qphy->dp_aux_cfg];
4839
4840        writel(val, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
4841
4842        return 0;
4843}
4844
4845static void qcom_qmp_v4_phy_dp_aux_init(struct qmp_phy *qphy)
4846{
4847        writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_PSR_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
4848               DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN,
4849               qphy->pcs + QSERDES_DP_PHY_PD_CTL);
4850
4851        /* Turn on BIAS current for PHY/PLL */
4852        writel(0x17, qphy->serdes + QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN);
4853
4854        writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG0);
4855        writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
4856        writel(0xa4, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2);
4857        writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG3);
4858        writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG4);
4859        writel(0x26, qphy->pcs + QSERDES_DP_PHY_AUX_CFG5);
4860        writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG6);
4861        writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG7);
4862        writel(0xb7, qphy->pcs + QSERDES_DP_PHY_AUX_CFG8);
4863        writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG9);
4864        qphy->dp_aux_cfg = 0;
4865
4866        writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK |
4867               PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK |
4868               PHY_AUX_REQ_ERR_MASK,
4869               qphy->pcs + QSERDES_V4_DP_PHY_AUX_INTERRUPT_MASK);
4870}
4871
4872static void qcom_qmp_v4_phy_configure_dp_tx(struct qmp_phy *qphy)
4873{
4874        /* Program default values before writing proper values */
4875        writel(0x27, qphy->tx + QSERDES_V4_TX_TX_DRV_LVL);
4876        writel(0x27, qphy->tx2 + QSERDES_V4_TX_TX_DRV_LVL);
4877
4878        writel(0x20, qphy->tx + QSERDES_V4_TX_TX_EMP_POST1_LVL);
4879        writel(0x20, qphy->tx2 + QSERDES_V4_TX_TX_EMP_POST1_LVL);
4880
4881        qcom_qmp_phy_configure_dp_swing(qphy,
4882                        QSERDES_V4_TX_TX_DRV_LVL,
4883                        QSERDES_V4_TX_TX_EMP_POST1_LVL);
4884}
4885
4886static int qcom_qmp_v4_phy_configure_dp_phy(struct qmp_phy *qphy)
4887{
4888        const struct qmp_phy_dp_clks *dp_clks = qphy->dp_clks;
4889        const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
4890        u32 phy_vco_div, status;
4891        unsigned long pixel_freq;
4892        u32 bias0_en, drvr0_en, bias1_en, drvr1_en;
4893        bool reverse;
4894
4895        writel(0x0f, qphy->pcs + QSERDES_V4_DP_PHY_CFG_1);
4896
4897        reverse = qcom_qmp_phy_configure_dp_mode(qphy);
4898
4899        writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
4900        writel(0xa4, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2);
4901
4902        writel(0x05, qphy->pcs + QSERDES_V4_DP_PHY_TX0_TX1_LANE_CTL);
4903        writel(0x05, qphy->pcs + QSERDES_V4_DP_PHY_TX2_TX3_LANE_CTL);
4904
4905        switch (dp_opts->link_rate) {
4906        case 1620:
4907                phy_vco_div = 0x1;
4908                pixel_freq = 1620000000UL / 2;
4909                break;
4910        case 2700:
4911                phy_vco_div = 0x1;
4912                pixel_freq = 2700000000UL / 2;
4913                break;
4914        case 5400:
4915                phy_vco_div = 0x2;
4916                pixel_freq = 5400000000UL / 4;
4917                break;
4918        case 8100:
4919                phy_vco_div = 0x0;
4920                pixel_freq = 8100000000UL / 6;
4921                break;
4922        default:
4923                /* Other link rates aren't supported */
4924                return -EINVAL;
4925        }
4926        writel(phy_vco_div, qphy->pcs + QSERDES_V4_DP_PHY_VCO_DIV);
4927
4928        clk_set_rate(dp_clks->dp_link_hw.clk, dp_opts->link_rate * 100000);
4929        clk_set_rate(dp_clks->dp_pixel_hw.clk, pixel_freq);
4930
4931        writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG);
4932        writel(0x05, qphy->pcs + QSERDES_DP_PHY_CFG);
4933        writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG);
4934        writel(0x09, qphy->pcs + QSERDES_DP_PHY_CFG);
4935
4936        writel(0x20, qphy->serdes + QSERDES_V4_COM_RESETSM_CNTRL);
4937
4938        if (readl_poll_timeout(qphy->serdes + QSERDES_V4_COM_C_READY_STATUS,
4939                        status,
4940                        ((status & BIT(0)) > 0),
4941                        500,
4942                        10000))
4943                return -ETIMEDOUT;
4944
4945        if (readl_poll_timeout(qphy->serdes + QSERDES_V4_COM_CMN_STATUS,
4946                        status,
4947                        ((status & BIT(0)) > 0),
4948                        500,
4949                        10000))
4950                return -ETIMEDOUT;
4951
4952        if (readl_poll_timeout(qphy->serdes + QSERDES_V4_COM_CMN_STATUS,
4953                        status,
4954                        ((status & BIT(1)) > 0),
4955                        500,
4956                        10000))
4957                return -ETIMEDOUT;
4958
4959        writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG);
4960
4961        if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS,
4962                        status,
4963                        ((status & BIT(0)) > 0),
4964                        500,
4965                        10000))
4966                return -ETIMEDOUT;
4967
4968        if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS,
4969                        status,
4970                        ((status & BIT(1)) > 0),
4971                        500,
4972                        10000))
4973                return -ETIMEDOUT;
4974
4975        /*
4976         * At least for 7nm DP PHY this has to be done after enabling link
4977         * clock.
4978         */
4979
4980        if (dp_opts->lanes == 1) {
4981                bias0_en = reverse ? 0x3e : 0x15;
4982                bias1_en = reverse ? 0x15 : 0x3e;
4983                drvr0_en = reverse ? 0x13 : 0x10;
4984                drvr1_en = reverse ? 0x10 : 0x13;
4985        } else if (dp_opts->lanes == 2) {
4986                bias0_en = reverse ? 0x3f : 0x15;
4987                bias1_en = reverse ? 0x15 : 0x3f;
4988                drvr0_en = 0x10;
4989                drvr1_en = 0x10;
4990        } else {
4991                bias0_en = 0x3f;
4992                bias1_en = 0x3f;
4993                drvr0_en = 0x10;
4994                drvr1_en = 0x10;
4995        }
4996
4997        writel(drvr0_en, qphy->tx + QSERDES_V4_TX_HIGHZ_DRVR_EN);
4998        writel(bias0_en, qphy->tx + QSERDES_V4_TX_TRANSCEIVER_BIAS_EN);
4999        writel(drvr1_en, qphy->tx2 + QSERDES_V4_TX_HIGHZ_DRVR_EN);
5000        writel(bias1_en, qphy->tx2 + QSERDES_V4_TX_TRANSCEIVER_BIAS_EN);

5001
5002        writel(0x18, qphy->pcs + QSERDES_DP_PHY_CFG);
5003        udelay(2000);
5004        writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG);
5005
5006        if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS,
5007                        status,
5008                        ((status & BIT(1)) > 0),
5009                        500,
5010                        10000))
5011                return -ETIMEDOUT;
5012
5013        writel(0x0a, qphy->tx + QSERDES_V4_TX_TX_POL_INV);
5014        writel(0x0a, qphy->tx2 + QSERDES_V4_TX_TX_POL_INV);
5015
5016        writel(0x27, qphy->tx + QSERDES_V4_TX_TX_DRV_LVL);
5017        writel(0x27, qphy->tx2 + QSERDES_V4_TX_TX_DRV_LVL);
5018
5019        writel(0x20, qphy->tx + QSERDES_V4_TX_TX_EMP_POST1_LVL);
5020        writel(0x20, qphy->tx2 + QSERDES_V4_TX_TX_EMP_POST1_LVL);
5021
5022        return 0;
5023}
5024
5025/*
5026 * We need to calibrate the aux setting here as many times
5027 * as the caller tries
5028 */
5029static int qcom_qmp_v4_dp_phy_calibrate(struct qmp_phy *qphy)
5030{
5031        static const u8 cfg1_settings[] = { 0x20, 0x13, 0x23, 0x1d };
5032        u8 val;
5033
5034        qphy->dp_aux_cfg++;
5035        qphy->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings);
5036        val = cfg1_settings[qphy->dp_aux_cfg];
5037
5038        writel(val, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
5039
5040        return 0;
5041}
5042
5043static int qcom_qmp_dp_phy_configure(struct phy *phy, union phy_configure_opts *opts)
5044{
5045        const struct phy_configure_opts_dp *dp_opts = &opts->dp;
5046        struct qmp_phy *qphy = phy_get_drvdata(phy);
5047        const struct qmp_phy_cfg *cfg = qphy->cfg;
5048
5049        memcpy(&qphy->dp_opts, dp_opts, sizeof(*dp_opts));
5050        if (qphy->dp_opts.set_voltages) {
5051                cfg->configure_dp_tx(qphy);
5052                qphy->dp_opts.set_voltages = 0;
5053        }
5054
5055        return 0;
5056}
5057
5058static int qcom_qmp_dp_phy_calibrate(struct phy *phy)
5059{
5060        struct qmp_phy *qphy = phy_get_drvdata(phy);
5061        const struct qmp_phy_cfg *cfg = qphy->cfg;
5062
5063        if (cfg->calibrate_dp_phy)
5064                return cfg->calibrate_dp_phy(qphy);
5065
5066        return 0;
5067}
5068
5069static int qcom_qmp_phy_com_init(struct qmp_phy *qphy)
5070{
5071        struct qcom_qmp *qmp = qphy->qmp;
5072        const struct qmp_phy_cfg *cfg = qphy->cfg;
5073        void __iomem *serdes = qphy->serdes;
5074        void __iomem *pcs = qphy->pcs;
5075        void __iomem *dp_com = qmp->dp_com;
5076        int ret, i;
5077
5078        mutex_lock(&qmp->phy_mutex);
5079        if (qmp->init_count++) {
5080                mutex_unlock(&qmp->phy_mutex);
5081                return 0;
5082        }
5083
5084        /* turn on regulator supplies */
5085        ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs);
5086        if (ret) {
5087                dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret);
5088                goto err_unlock;
5089        }
5090
5091        for (i = 0; i < cfg->num_resets; i++) {
5092                ret = reset_control_assert(qmp->resets[i]);
5093                if (ret) {
5094                        dev_err(qmp->dev, "%s reset assert failed\n",
5095                                cfg->reset_list[i]);
5096                        goto err_disable_regulators;
5097                }
5098        }
5099
5100        for (i = cfg->num_resets - 1; i >= 0; i--) {
5101                ret = reset_control_deassert(qmp->resets[i]);
5102                if (ret) {
5103                        dev_err(qmp->dev, "%s reset deassert failed\n",
5104                                qphy->cfg->reset_list[i]);
5105                        goto err_assert_reset;
5106                }
5107        }
5108
5109        ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks);
5110        if (ret)
5111                goto err_assert_reset;
5112
5113        if (cfg->has_phy_dp_com_ctrl) {
5114                qphy_setbits(dp_com, QPHY_V3_DP_COM_POWER_DOWN_CTRL,
5115                             SW_PWRDN);
5116                /* override hardware control for reset of qmp phy */
5117                qphy_setbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL,
5118                             SW_DPPHY_RESET_MUX | SW_DPPHY_RESET |
5119                             SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET);
5120
5121                /* Default type-c orientation, i.e CC1 */
5122                qphy_setbits(dp_com, QPHY_V3_DP_COM_TYPEC_CTRL, 0x02);
5123
5124                qphy_setbits(dp_com, QPHY_V3_DP_COM_PHY_MODE_CTRL,
5125                             USB3_MODE | DP_MODE);
5126
5127                /* bring both QMP USB and QMP DP PHYs PCS block out of reset */
5128                qphy_clrbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL,
5129                             SW_DPPHY_RESET_MUX | SW_DPPHY_RESET |
5130                             SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET);
5131
5132                qphy_clrbits(dp_com, QPHY_V3_DP_COM_SWI_CTRL, 0x03);
5133                qphy_clrbits(dp_com, QPHY_V3_DP_COM_SW_RESET, SW_RESET);
5134        }
5135
5136        if (cfg->has_phy_com_ctrl) {
5137                qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL],
5138                             SW_PWRDN);
5139        } else {
5140                if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL])
5141                        qphy_setbits(pcs,
5142                                        cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
5143                                        cfg->pwrdn_ctrl);
5144                else
5145                        qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL,
5146                                        cfg->pwrdn_ctrl);
5147        }
5148
5149        mutex_unlock(&qmp->phy_mutex);
5150
5151        return 0;
5152
5153err_assert_reset:
5154        while (++i < cfg->num_resets)
5155                reset_control_assert(qmp->resets[i]);
5156err_disable_regulators:
5157        regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
5158err_unlock:
5159        mutex_unlock(&qmp->phy_mutex);
5160
5161        return ret;
5162}
5163
5164static int qcom_qmp_phy_com_exit(struct qmp_phy *qphy)
5165{
5166        struct qcom_qmp *qmp = qphy->qmp;
5167        const struct qmp_phy_cfg *cfg = qphy->cfg;
5168        void __iomem *serdes = qphy->serdes;
5169        int i = cfg->num_resets;
5170
5171        mutex_lock(&qmp->phy_mutex);
5172        if (--qmp->init_count) {
5173                mutex_unlock(&qmp->phy_mutex);
5174                return 0;
5175        }
5176
5177        reset_control_assert(qmp->ufs_reset);
5178        if (cfg->has_phy_com_ctrl) {
5179                qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL],
5180                             SERDES_START | PCS_START);
5181                qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET],
5182                             SW_RESET);
5183                qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL],
5184                             SW_PWRDN);
5185        }
5186
5187        while (--i >= 0)
5188                reset_control_assert(qmp->resets[i]);
5189
5190        clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
5191
5192        regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
5193
5194        mutex_unlock(&qmp->phy_mutex);
5195
5196        return 0;
5197}
5198
5199static int qcom_qmp_phy_init(struct phy *phy)
5200{
5201        struct qmp_phy *qphy = phy_get_drvdata(phy);
5202        struct qcom_qmp *qmp = qphy->qmp;
5203        const struct qmp_phy_cfg *cfg = qphy->cfg;
5204        int ret;
5205        dev_vdbg(qmp->dev, "Initializing QMP phy\n");
5206
5207        if (cfg->no_pcs_sw_reset) {
5208                /*
5209                 * Get UFS reset, which is delayed until now to avoid a
5210                 * circular dependency where UFS needs its PHY, but the PHY
5211                 * needs this UFS reset.
5212                 */
5213                if (!qmp->ufs_reset) {
5214                        qmp->ufs_reset =
5215                                devm_reset_control_get_exclusive(qmp->dev,
5216                                                                 "ufsphy");
5217
5218                        if (IS_ERR(qmp->ufs_reset)) {
5219                                ret = PTR_ERR(qmp->ufs_reset);
5220                                dev_err(qmp->dev,
5221                                        "failed to get UFS reset: %d\n",
5222                                        ret);
5223
5224                                qmp->ufs_reset = NULL;
5225                                return ret;
5226                        }
5227                }
5228
5229                ret = reset_control_assert(qmp->ufs_reset);
5230                if (ret)
5231                        return ret;
5232        }
5233
5234        ret = qcom_qmp_phy_com_init(qphy);
5235        if (ret)
5236                return ret;
5237
5238        if (cfg->type == PHY_TYPE_DP)
5239                cfg->dp_aux_init(qphy);
5240
5241        return 0;
5242}
5243
5244static int qcom_qmp_phy_power_on(struct phy *phy)
5245{
5246        struct qmp_phy *qphy = phy_get_drvdata(phy);
5247        struct qcom_qmp *qmp = qphy->qmp;
5248        const struct qmp_phy_cfg *cfg = qphy->cfg;
5249        void __iomem *tx = qphy->tx;
5250        void __iomem *rx = qphy->rx;
5251        void __iomem *pcs = qphy->pcs;
5252        void __iomem *pcs_misc = qphy->pcs_misc;
5253        void __iomem *status;
5254        unsigned int mask, val, ready;
5255        int ret;
5256
5257        qcom_qmp_phy_serdes_init(qphy);
5258
5259        if (cfg->has_lane_rst) {
5260                ret = reset_control_deassert(qphy->lane_rst);
5261                if (ret) {
5262                        dev_err(qmp->dev, "lane%d reset deassert failed\n",
5263                                qphy->index);
5264                        return ret;
5265                }
5266        }
5267
5268        ret = clk_prepare_enable(qphy->pipe_clk);
5269        if (ret) {
5270                dev_err(qmp->dev, "pipe_clk enable failed err=%d\n", ret);
5271                goto err_reset_lane;
5272        }
5273
5274        /* Tx, Rx, and PCS configurations */
5275        qcom_qmp_phy_configure_lane(tx, cfg->regs,
5276                                    cfg->tx_tbl, cfg->tx_tbl_num, 1);
5277        if (cfg->tx_tbl_sec)
5278                qcom_qmp_phy_configure_lane(tx, cfg->regs, cfg->tx_tbl_sec,
5279                                            cfg->tx_tbl_num_sec, 1);
5280
5281        /* Configuration for other LANE for USB-DP combo PHY */
5282        if (cfg->is_dual_lane_phy) {
5283                qcom_qmp_phy_configure_lane(qphy->tx2, cfg->regs,
5284                                            cfg->tx_tbl, cfg->tx_tbl_num, 2);
5285                if (cfg->tx_tbl_sec)
5286                        qcom_qmp_phy_configure_lane(qphy->tx2, cfg->regs,
5287                                                    cfg->tx_tbl_sec,
5288                                                    cfg->tx_tbl_num_sec, 2);
5289        }
5290
5291        /* Configure special DP tx tunings */
5292        if (cfg->type == PHY_TYPE_DP)
5293                cfg->configure_dp_tx(qphy);
5294
5295        qcom_qmp_phy_configure_lane(rx, cfg->regs,
5296                                    cfg->rx_tbl, cfg->rx_tbl_num, 1);
5297        if (cfg->rx_tbl_sec)
5298                qcom_qmp_phy_configure_lane(rx, cfg->regs,
5299                                            cfg->rx_tbl_sec, cfg->rx_tbl_num_sec, 1);
5300
5301        if (cfg->is_dual_lane_phy) {
5302                qcom_qmp_phy_configure_lane(qphy->rx2, cfg->regs,
5303                                            cfg->rx_tbl, cfg->rx_tbl_num, 2);
5304                if (cfg->rx_tbl_sec)
5305                        qcom_qmp_phy_configure_lane(qphy->rx2, cfg->regs,
5306                                                    cfg->rx_tbl_sec,
5307                                                    cfg->rx_tbl_num_sec, 2);
5308        }
5309
5310        /* Configure link rate, swing, etc. */
5311        if (cfg->type == PHY_TYPE_DP) {
5312                cfg->configure_dp_phy(qphy);
5313        } else {
5314                qcom_qmp_phy_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num);
5315                if (cfg->pcs_tbl_sec)
5316                        qcom_qmp_phy_configure(pcs, cfg->regs, cfg->pcs_tbl_sec,
5317                                               cfg->pcs_tbl_num_sec);
5318        }
5319
5320        ret = reset_control_deassert(qmp->ufs_reset);
5321        if (ret)
5322                goto err_disable_pipe_clk;
5323
5324        qcom_qmp_phy_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl,
5325                               cfg->pcs_misc_tbl_num);
5326        if (cfg->pcs_misc_tbl_sec)
5327                qcom_qmp_phy_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl_sec,
5328                                       cfg->pcs_misc_tbl_num_sec);
5329
5330        /*
5331         * Pull out PHY from POWER DOWN state.
5332         * This is active low enable signal to power-down PHY.
5333         */
5334        if(cfg->type == PHY_TYPE_PCIE)
5335                qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL, cfg->pwrdn_ctrl);
5336
5337        if (cfg->has_pwrdn_delay)
5338                usleep_range(cfg->pwrdn_delay_min, cfg->pwrdn_delay_max);
5339
5340        if (cfg->type != PHY_TYPE_DP) {
5341                /* Pull PHY out of reset state */
5342                if (!cfg->no_pcs_sw_reset)
5343                        qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
5344                /* start SerDes and Phy-Coding-Sublayer */
5345                qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
5346
5347                if (cfg->type == PHY_TYPE_UFS) {
5348                        status = pcs + cfg->regs[QPHY_PCS_READY_STATUS];
5349                        mask = PCS_READY;
5350                        ready = PCS_READY;
5351                } else {
5352                        status = pcs + cfg->regs[QPHY_PCS_STATUS];
5353                        mask = cfg->phy_status;
5354                        ready = 0;
5355                }
5356
5357                ret = readl_poll_timeout(status, val, (val & mask) == ready, 10,
5358                                         PHY_INIT_COMPLETE_TIMEOUT);
5359                if (ret) {
5360                        dev_err(qmp->dev, "phy initialization timed-out\n");
5361                        goto err_disable_pipe_clk;
5362                }
5363        }
5364        return 0;
5365
5366err_disable_pipe_clk:
5367        clk_disable_unprepare(qphy->pipe_clk);
5368err_reset_lane:
5369        if (cfg->has_lane_rst)
5370                reset_control_assert(qphy->lane_rst);
5371
5372        return ret;
5373}
5374
5375static int qcom_qmp_phy_power_off(struct phy *phy)
5376{
5377        struct qmp_phy *qphy = phy_get_drvdata(phy);
5378        const struct qmp_phy_cfg *cfg = qphy->cfg;
5379
5380        clk_disable_unprepare(qphy->pipe_clk);
5381
5382        if (cfg->type == PHY_TYPE_DP) {
5383                /* Assert DP PHY power down */
5384                writel(DP_PHY_PD_CTL_PSR_PWRDN, qphy->pcs + QSERDES_DP_PHY_PD_CTL);
5385        } else {
5386                /* PHY reset */
5387                if (!cfg->no_pcs_sw_reset)
5388                        qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
5389
5390                /* stop SerDes and Phy-Coding-Sublayer */
5391                qphy_clrbits(qphy->pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
5392
5393                /* Put PHY into POWER DOWN state: active low */
5394                if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL]) {
5395                        qphy_clrbits(qphy->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
5396                                     cfg->pwrdn_ctrl);
5397                } else {
5398                        qphy_clrbits(qphy->pcs, QPHY_POWER_DOWN_CONTROL,
5399                                        cfg->pwrdn_ctrl);
5400                }
5401        }
5402
5403        return 0;
5404}
5405
5406static int qcom_qmp_phy_exit(struct phy *phy)
5407{
5408        struct qmp_phy *qphy = phy_get_drvdata(phy);
5409        const struct qmp_phy_cfg *cfg = qphy->cfg;
5410
5411        if (cfg->has_lane_rst)
5412                reset_control_assert(qphy->lane_rst);
5413
5414        qcom_qmp_phy_com_exit(qphy);
5415
5416        return 0;
5417}
5418
5419static int qcom_qmp_phy_enable(struct phy *phy)
5420{
5421        int ret;
5422
5423        ret = qcom_qmp_phy_init(phy);
5424        if (ret)
5425                return ret;
5426
5427        ret = qcom_qmp_phy_power_on(phy);
5428        if (ret)
5429                qcom_qmp_phy_exit(phy);
5430
5431        return ret;
5432}
5433
5434static int qcom_qmp_phy_disable(struct phy *phy)
5435{
5436        int ret;
5437
5438        ret = qcom_qmp_phy_power_off(phy);
5439        if (ret)
5440                return ret;
5441        return qcom_qmp_phy_exit(phy);
5442}
5443
5444static int qcom_qmp_phy_set_mode(struct phy *phy,
5445                                 enum phy_mode mode, int submode)
5446{
5447        struct qmp_phy *qphy = phy_get_drvdata(phy);
5448
5449        qphy->mode = mode;
5450
5451        return 0;
5452}
5453
5454static void qcom_qmp_phy_enable_autonomous_mode(struct qmp_phy *qphy)
5455{
5456        const struct qmp_phy_cfg *cfg = qphy->cfg;
5457        void __iomem *pcs = qphy->pcs;
5458        void __iomem *pcs_misc = qphy->pcs_misc;
5459        u32 intr_mask;
5460
5461        if (qphy->mode == PHY_MODE_USB_HOST_SS ||
5462            qphy->mode == PHY_MODE_USB_DEVICE_SS)
5463                intr_mask = ARCVR_DTCT_EN | ALFPS_DTCT_EN;
5464        else
5465                intr_mask = ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL;
5466
5467        /* Clear any pending interrupts status */
5468        qphy_setbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
5469        /* Writing 1 followed by 0 clears the interrupt */
5470        qphy_clrbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
5471
5472        qphy_clrbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
5473                     ARCVR_DTCT_EN | ALFPS_DTCT_EN | ARCVR_DTCT_EVENT_SEL);
5474
5475        /* Enable required PHY autonomous mode interrupts */
5476        qphy_setbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], intr_mask);
5477
5478        /* Enable i/o clamp_n for autonomous mode */
5479        if (pcs_misc)
5480                qphy_clrbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN);
5481}
5482
5483static void qcom_qmp_phy_disable_autonomous_mode(struct qmp_phy *qphy)
5484{
5485        const struct qmp_phy_cfg *cfg = qphy->cfg;
5486        void __iomem *pcs = qphy->pcs;
5487        void __iomem *pcs_misc = qphy->pcs_misc;
5488
5489        /* Disable i/o clamp_n on resume for normal mode */
5490        if (pcs_misc)
5491                qphy_setbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN);
5492
5493        qphy_clrbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
5494                     ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL | ALFPS_DTCT_EN);
5495
5496        qphy_setbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
5497        /* Writing 1 followed by 0 clears the interrupt */
5498        qphy_clrbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
5499}
5500
5501static int __maybe_unused qcom_qmp_phy_runtime_suspend(struct device *dev)
5502{
5503        struct qcom_qmp *qmp = dev_get_drvdata(dev);
5504        struct qmp_phy *qphy = qmp->phys[0];
5505        const struct qmp_phy_cfg *cfg = qphy->cfg;
5506
5507        dev_vdbg(dev, "Suspending QMP phy, mode:%d\n", qphy->mode);
5508
5509        /* Supported only for USB3 PHY and luckily USB3 is the first phy */
5510        if (cfg->type != PHY_TYPE_USB3)
5511                return 0;
5512
5513        if (!qmp->init_count) {
5514                dev_vdbg(dev, "PHY not initialized, bailing out\n");
5515                return 0;
5516        }
5517
5518        qcom_qmp_phy_enable_autonomous_mode(qphy);
5519
5520        clk_disable_unprepare(qphy->pipe_clk);
5521        clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
5522
5523        return 0;
5524}
5525
5526static int __maybe_unused qcom_qmp_phy_runtime_resume(struct device *dev)
5527{
5528        struct qcom_qmp *qmp = dev_get_drvdata(dev);
5529        struct qmp_phy *qphy = qmp->phys[0];
5530        const struct qmp_phy_cfg *cfg = qphy->cfg;
5531        int ret = 0;
5532
5533        dev_vdbg(dev, "Resuming QMP phy, mode:%d\n", qphy->mode);
5534
5535        /* Supported only for USB3 PHY and luckily USB3 is the first phy */
5536        if (cfg->type != PHY_TYPE_USB3)
5537                return 0;
5538
5539        if (!qmp->init_count) {
5540                dev_vdbg(dev, "PHY not initialized, bailing out\n");
5541                return 0;
5542        }
5543
5544        ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks);
5545        if (ret)
5546                return ret;
5547
5548        ret = clk_prepare_enable(qphy->pipe_clk);
5549        if (ret) {
5550                dev_err(dev, "pipe_clk enable failed, err=%d\n", ret);
5551                clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
5552                return ret;
5553        }
5554
5555        qcom_qmp_phy_disable_autonomous_mode(qphy);
5556
5557        return 0;
5558}
5559
5560static int qcom_qmp_phy_vreg_init(struct device *dev, const struct qmp_phy_cfg *cfg)
5561{
5562        struct qcom_qmp *qmp = dev_get_drvdata(dev);
5563        int num = cfg->num_vregs;
5564        int i;
5565
5566        qmp->vregs = devm_kcalloc(dev, num, sizeof(*qmp->vregs), GFP_KERNEL);
5567        if (!qmp->vregs)
5568                return -ENOMEM;
5569
5570        for (i = 0; i < num; i++)
5571                qmp->vregs[i].supply = cfg->vreg_list[i];
5572
5573        return devm_regulator_bulk_get(dev, num, qmp->vregs);
5574}
5575
5576static int qcom_qmp_phy_reset_init(struct device *dev, const struct qmp_phy_cfg *cfg)
5577{
5578        struct qcom_qmp *qmp = dev_get_drvdata(dev);
5579        int i;
5580
5581        qmp->resets = devm_kcalloc(dev, cfg->num_resets,
5582                                   sizeof(*qmp->resets), GFP_KERNEL);
5583        if (!qmp->resets)
5584                return -ENOMEM;
5585
5586        for (i = 0; i < cfg->num_resets; i++) {
5587                struct reset_control *rst;
5588                const char *name = cfg->reset_list[i];
5589
5590                rst = devm_reset_control_get_exclusive(dev, name);
5591                if (IS_ERR(rst)) {
5592                        dev_err(dev, "failed to get %s reset\n", name);
5593                        return PTR_ERR(rst);
5594                }
5595                qmp->resets[i] = rst;
5596        }
5597
5598        return 0;
5599}
5600
5601static int qcom_qmp_phy_clk_init(struct device *dev, const struct qmp_phy_cfg *cfg)
5602{
5603        struct qcom_qmp *qmp = dev_get_drvdata(dev);
5604        int num = cfg->num_clks;
5605        int i;
5606
5607        qmp->clks = devm_kcalloc(dev, num, sizeof(*qmp->clks), GFP_KERNEL);
5608        if (!qmp->clks)
5609                return -ENOMEM;
5610
5611        for (i = 0; i < num; i++)
5612                qmp->clks[i].id = cfg->clk_list[i];
5613
5614        return devm_clk_bulk_get(dev, num, qmp->clks);
5615}
5616
5617static void phy_clk_release_provider(void *res)
5618{
5619        of_clk_del_provider(res);
5620}
5621
5622/*
5623 * Register a fixed rate pipe clock.
5624 *
5625 * The <s>_pipe_clksrc generated by PHY goes to the GCC that gate
5626 * controls it. The <s>_pipe_clk coming out of the GCC is requested
5627 * by the PHY driver for its operations.
5628 * We register the <s>_pipe_clksrc here. The gcc driver takes care
5629 * of assigning this <s>_pipe_clksrc as parent to <s>_pipe_clk.
5630 * Below picture shows this relationship.
5631 *
5632 *         +---------------+
5633 *         |   PHY block   |<<---------------------------------------+
5634 *         |               |                                         |
5635 *         |   +-------+   |                   +-----+               |
5636 *   I/P---^-->|  PLL  |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+
5637 *    clk  |   +-------+   |                   +-----+
5638 *         +---------------+
5639 */
5640static int phy_pipe_clk_register(struct qcom_qmp *qmp, struct device_node *np)
5641{
5642        struct clk_fixed_rate *fixed;
5643        struct clk_init_data init = { };
5644        int ret;
5645
5646        ret = of_property_read_string(np, "clock-output-names", &init.name);
5647        if (ret) {
5648                dev_err(qmp->dev, "%pOFn: No clock-output-names\n", np);
5649                return ret;
5650        }
5651
5652        fixed = devm_kzalloc(qmp->dev, sizeof(*fixed), GFP_KERNEL);
5653        if (!fixed)
5654                return -ENOMEM;
5655
5656        init.ops = &clk_fixed_rate_ops;
5657
5658        /* controllers using QMP phys use 125MHz pipe clock interface */
5659        fixed->fixed_rate = 125000000;
5660        fixed->hw.init = &init;
5661
5662        ret = devm_clk_hw_register(qmp->dev, &fixed->hw);
5663        if (ret)
5664                return ret;
5665
5666        ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, &fixed->hw);
5667        if (ret)
5668                return ret;
5669
5670        /*
5671         * Roll a devm action because the clock provider is the child node, but
5672         * the child node is not actually a device.
5673         */
5674        return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np);
5675}
5676
5677/*
5678 * Display Port PLL driver block diagram for branch clocks
5679 *
5680 *              +------------------------------+
5681 *              |         DP_VCO_CLK           |
5682 *              |                              |
5683 *              |    +-------------------+     |
5684 *              |    |   (DP PLL/VCO)    |     |
5685 *              |    +---------+---------+     |
5686 *              |              v               |
5687 *              |   +----------+-----------+   |
5688 *              |   | hsclk_divsel_clk_src |   |
5689 *              |   +----------+-----------+   |
5690 *              +------------------------------+
5691 *                              |
5692 *          +---------<---------v------------>----------+
5693 *          |                                           |
5694 * +--------v----------------+                          |
5695 * |    dp_phy_pll_link_clk  |                          |
5696 * |     link_clk            |                          |
5697 * +--------+----------------+                          |
5698 *          |                                           |
5699 *          |                                           |
5700 *          v                                           v
5701 * Input to DISPCC block                                |
5702 * for link clk, crypto clk                             |
5703 * and interface clock                                  |
5704 *                                                      |
5705 *                                                      |
5706 *      +--------<------------+-----------------+---<---+
5707 *      |                     |                 |
5708 * +----v---------+  +--------v-----+  +--------v------+
5709 * | vco_divided  |  | vco_divided  |  | vco_divided   |
5710 * |    _clk_src  |  |    _clk_src  |  |    _clk_src   |
5711 * |              |  |              |  |               |
5712 * |divsel_six    |  |  divsel_two  |  |  divsel_four  |
5713 * +-------+------+  +-----+--------+  +--------+------+
5714 *         |                 |                  |
5715 *         v---->----------v-------------<------v
5716 *                         |
5717 *              +----------+-----------------+
5718 *              |   dp_phy_pll_vco_div_clk   |
5719 *              +---------+------------------+
5720 *                        |
5721 *                        v
5722 *              Input to DISPCC block
5723 *              for DP pixel clock
5724 *
5725 */
5726static int qcom_qmp_dp_pixel_clk_determine_rate(struct clk_hw *hw,
5727                                                struct clk_rate_request *req)
5728{
5729        switch (req->rate) {
5730        case 1620000000UL / 2:
5731        case 2700000000UL / 2:
5732        /* 5.4 and 8.1 GHz are same link rate as 2.7GHz, i.e. div 4 and div 6 */
5733                return 0;
5734        default:
5735                return -EINVAL;
5736        }
5737}
5738
5739static unsigned long
5740qcom_qmp_dp_pixel_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
5741{
5742        const struct qmp_phy_dp_clks *dp_clks;
5743        const struct qmp_phy *qphy;
5744        const struct phy_configure_opts_dp *dp_opts;
5745
5746        dp_clks = container_of(hw, struct qmp_phy_dp_clks, dp_pixel_hw);
5747        qphy = dp_clks->qphy;
5748        dp_opts = &qphy->dp_opts;
5749
5750        switch (dp_opts->link_rate) {
5751        case 1620:
5752                return 1620000000UL / 2;
5753        case 2700:
5754                return 2700000000UL / 2;
5755        case 5400:
5756                return 5400000000UL / 4;
5757        case 8100:
5758                return 8100000000UL / 6;
5759        default:
5760                return 0;
5761        }
5762}
5763
5764static const struct clk_ops qcom_qmp_dp_pixel_clk_ops = {
5765        .determine_rate = qcom_qmp_dp_pixel_clk_determine_rate,
5766        .recalc_rate = qcom_qmp_dp_pixel_clk_recalc_rate,
5767};
5768
5769static int qcom_qmp_dp_link_clk_determine_rate(struct clk_hw *hw,
5770                                               struct clk_rate_request *req)
5771{
5772        switch (req->rate) {
5773        case 162000000:
5774        case 270000000:
5775        case 540000000:
5776        case 810000000:
5777                return 0;
5778        default:
5779                return -EINVAL;
5780        }
5781}
5782
5783static unsigned long
5784qcom_qmp_dp_link_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
5785{
5786        const struct qmp_phy_dp_clks *dp_clks;
5787        const struct qmp_phy *qphy;
5788        const struct phy_configure_opts_dp *dp_opts;
5789
5790        dp_clks = container_of(hw, struct qmp_phy_dp_clks, dp_link_hw);
5791        qphy = dp_clks->qphy;
5792        dp_opts = &qphy->dp_opts;
5793
5794        switch (dp_opts->link_rate) {
5795        case 1620:
5796        case 2700:
5797        case 5400:
5798        case 8100:
5799                return dp_opts->link_rate * 100000;
5800        default:
5801                return 0;
5802        }
5803}
5804
5805static const struct clk_ops qcom_qmp_dp_link_clk_ops = {
5806        .determine_rate = qcom_qmp_dp_link_clk_determine_rate,
5807        .recalc_rate = qcom_qmp_dp_link_clk_recalc_rate,
5808};
5809
5810static struct clk_hw *
5811qcom_qmp_dp_clks_hw_get(struct of_phandle_args *clkspec, void *data)
5812{
5813        struct qmp_phy_dp_clks *dp_clks = data;
5814        unsigned int idx = clkspec->args[0];
5815
5816        if (idx >= 2) {
5817                pr_err("%s: invalid index %u\n", __func__, idx);
5818                return ERR_PTR(-EINVAL);
5819        }
5820
5821        if (idx == 0)
5822                return &dp_clks->dp_link_hw;
5823
5824        return &dp_clks->dp_pixel_hw;
5825}
5826
5827static int phy_dp_clks_register(struct qcom_qmp *qmp, struct qmp_phy *qphy,
5828                                struct device_node *np)
5829{
5830        struct clk_init_data init = { };
5831        struct qmp_phy_dp_clks *dp_clks;
5832        char name[64];
5833        int ret;
5834
5835        dp_clks = devm_kzalloc(qmp->dev, sizeof(*dp_clks), GFP_KERNEL);
5836        if (!dp_clks)
5837                return -ENOMEM;
5838
5839        dp_clks->qphy = qphy;
5840        qphy->dp_clks = dp_clks;
5841
5842        snprintf(name, sizeof(name), "%s::link_clk", dev_name(qmp->dev));
5843        init.ops = &qcom_qmp_dp_link_clk_ops;
5844        init.name = name;
5845        dp_clks->dp_link_hw.init = &init;
5846        ret = devm_clk_hw_register(qmp->dev, &dp_clks->dp_link_hw);
5847        if (ret)
5848                return ret;
5849
5850        snprintf(name, sizeof(name), "%s::vco_div_clk", dev_name(qmp->dev));
5851        init.ops = &qcom_qmp_dp_pixel_clk_ops;
5852        init.name = name;
5853        dp_clks->dp_pixel_hw.init = &init;
5854        ret = devm_clk_hw_register(qmp->dev, &dp_clks->dp_pixel_hw);
5855        if (ret)
5856                return ret;
5857
5858        ret = of_clk_add_hw_provider(np, qcom_qmp_dp_clks_hw_get, dp_clks);
5859        if (ret)
5860                return ret;
5861
5862        /*
5863         * Roll a devm action because the clock provider is the child node, but
5864         * the child node is not actually a device.
5865         */
5866        return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np);
5867}
5868
5869static const struct phy_ops qcom_qmp_phy_gen_ops = {
5870        .init           = qcom_qmp_phy_enable,
5871        .exit           = qcom_qmp_phy_disable,
5872        .set_mode       = qcom_qmp_phy_set_mode,
5873        .owner          = THIS_MODULE,
5874};
5875
5876static const struct phy_ops qcom_qmp_phy_dp_ops = {
5877        .init           = qcom_qmp_phy_init,
5878        .configure      = qcom_qmp_dp_phy_configure,
5879        .power_on       = qcom_qmp_phy_power_on,
5880        .calibrate      = qcom_qmp_dp_phy_calibrate,
5881        .power_off      = qcom_qmp_phy_power_off,
5882        .exit           = qcom_qmp_phy_exit,
5883        .set_mode       = qcom_qmp_phy_set_mode,
5884        .owner          = THIS_MODULE,
5885};
5886
5887static const struct phy_ops qcom_qmp_pcie_ufs_ops = {
5888        .power_on       = qcom_qmp_phy_enable,
5889        .power_off      = qcom_qmp_phy_disable,
5890        .set_mode       = qcom_qmp_phy_set_mode,
5891        .owner          = THIS_MODULE,
5892};
5893
5894static void qcom_qmp_reset_control_put(void *data)
5895{
5896        reset_control_put(data);
5897}
5898
5899static
5900int qcom_qmp_phy_create(struct device *dev, struct device_node *np, int id,
5901                        void __iomem *serdes, const struct qmp_phy_cfg *cfg)
5902{
5903        struct qcom_qmp *qmp = dev_get_drvdata(dev);
5904        struct phy *generic_phy;
5905        struct qmp_phy *qphy;
5906        const struct phy_ops *ops;
5907        char prop_name[MAX_PROP_NAME];
5908        int ret;
5909
5910        qphy = devm_kzalloc(dev, sizeof(*qphy), GFP_KERNEL);
5911        if (!qphy)
5912                return -ENOMEM;
5913
5914        qphy->cfg = cfg;
5915        qphy->serdes = serdes;
5916        /*
5917         * Get memory resources for each phy lane:
5918         * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2.
5919         * For dual lane PHYs: tx2 -> 3, rx2 -> 4, pcs_misc (optional) -> 5
5920         * For single lane PHYs: pcs_misc (optional) -> 3.
5921         */
5922        qphy->tx = of_iomap(np, 0);
5923        if (!qphy->tx)
5924                return -ENOMEM;
5925
5926        qphy->rx = of_iomap(np, 1);
5927        if (!qphy->rx)
5928                return -ENOMEM;
5929
5930        qphy->pcs = of_iomap(np, 2);
5931        if (!qphy->pcs)
5932                return -ENOMEM;
5933
5934        /*
5935         * If this is a dual-lane PHY, then there should be registers for the
5936         * second lane. Some old device trees did not specify this, so fall
5937         * back to old legacy behavior of assuming they can be reached at an
5938         * offset from the first lane.
5939         */
5940        if (cfg->is_dual_lane_phy) {
5941                qphy->tx2 = of_iomap(np, 3);
5942                qphy->rx2 = of_iomap(np, 4);
5943                if (!qphy->tx2 || !qphy->rx2) {
5944                        dev_warn(dev,
5945                                 "Underspecified device tree, falling back to legacy register regions\n");
5946
5947                        /* In the old version, pcs_misc is at index 3. */
5948                        qphy->pcs_misc = qphy->tx2;
5949                        qphy->tx2 = qphy->tx + QMP_PHY_LEGACY_LANE_STRIDE;
5950                        qphy->rx2 = qphy->rx + QMP_PHY_LEGACY_LANE_STRIDE;
5951
5952                } else {
5953                        qphy->pcs_misc = of_iomap(np, 5);
5954                }
5955
5956        } else {
5957                qphy->pcs_misc = of_iomap(np, 3);
5958        }
5959
5960        if (!qphy->pcs_misc)
5961                dev_vdbg(dev, "PHY pcs_misc-reg not used\n");
5962
5963        /*
5964         * Get PHY's Pipe clock, if any. USB3 and PCIe are PIPE3
5965         * based phys, so they essentially have pipe clock. So,
5966         * we return error in case phy is USB3 or PIPE type.
5967         * Otherwise, we initialize pipe clock to NULL for
5968         * all phys that don't need this.
5969         */
5970        snprintf(prop_name, sizeof(prop_name), "pipe%d", id);
5971        qphy->pipe_clk = devm_get_clk_from_child(dev, np, prop_name);
5972        if (IS_ERR(qphy->pipe_clk)) {
5973                if (cfg->type == PHY_TYPE_PCIE ||
5974                    cfg->type == PHY_TYPE_USB3) {
5975                        ret = PTR_ERR(qphy->pipe_clk);
5976                        if (ret != -EPROBE_DEFER)
5977                                dev_err(dev,
5978                                        "failed to get lane%d pipe_clk, %d\n",
5979                                        id, ret);
5980                        return ret;
5981                }
5982                qphy->pipe_clk = NULL;
5983        }
5984
5985        /* Get lane reset, if any */
5986        if (cfg->has_lane_rst) {
5987                snprintf(prop_name, sizeof(prop_name), "lane%d", id);
5988                qphy->lane_rst = of_reset_control_get_exclusive(np, prop_name);
5989                if (IS_ERR(qphy->lane_rst)) {
5990                        dev_err(dev, "failed to get lane%d reset\n", id);
5991                        return PTR_ERR(qphy->lane_rst);
5992                }
5993                ret = devm_add_action_or_reset(dev, qcom_qmp_reset_control_put,
5994                                               qphy->lane_rst);
5995                if (ret)
5996                        return ret;
5997        }
5998
5999        if (cfg->type == PHY_TYPE_UFS || cfg->type == PHY_TYPE_PCIE)
6000                ops = &qcom_qmp_pcie_ufs_ops;

6001        else if (cfg->type == PHY_TYPE_DP)
6002                ops = &qcom_qmp_phy_dp_ops;
6003        else
6004                ops = &qcom_qmp_phy_gen_ops;
6005
6006        generic_phy = devm_phy_create(dev, np, ops);
6007        if (IS_ERR(generic_phy)) {
6008                ret = PTR_ERR(generic_phy);
6009                dev_err(dev, "failed to create qphy %d\n", ret);
6010                return ret;
6011        }
6012
6013        qphy->phy = generic_phy;
6014        qphy->index = id;
6015        qphy->qmp = qmp;
6016        qmp->phys[id] = qphy;
6017        phy_set_drvdata(generic_phy, qphy);
6018
6019        return 0;
6020}
6021
6022static const struct of_device_id qcom_qmp_phy_of_match_table[] = {
6023        {
6024                .compatible = "qcom,ipq8074-qmp-usb3-phy",
6025                .data = &ipq8074_usb3phy_cfg,
6026        }, {
6027                .compatible = "qcom,msm8996-qmp-pcie-phy",
6028                .data = &msm8996_pciephy_cfg,
6029        }, {
6030                .compatible = "qcom,msm8996-qmp-ufs-phy",
6031                .data = &msm8996_ufs_cfg,
6032        }, {
6033                .compatible = "qcom,msm8996-qmp-usb3-phy",
6034                .data = &msm8996_usb3phy_cfg,
6035        }, {
6036                .compatible = "qcom,msm8998-qmp-pcie-phy",
6037                .data = &msm8998_pciephy_cfg,
6038        }, {
6039                .compatible = "qcom,msm8998-qmp-ufs-phy",
6040                .data = &sdm845_ufsphy_cfg,
6041        }, {
6042                .compatible = "qcom,ipq8074-qmp-pcie-phy",
6043                .data = &ipq8074_pciephy_cfg,
6044        }, {
6045                .compatible = "qcom,ipq6018-qmp-pcie-phy",
6046                .data = &ipq6018_pciephy_cfg,
6047        }, {
6048                .compatible = "qcom,ipq6018-qmp-usb3-phy",
6049                .data = &ipq8074_usb3phy_cfg,
6050        }, {
6051                .compatible = "qcom,sc7180-qmp-usb3-phy",
6052                .data = &sc7180_usb3phy_cfg,
6053        }, {
6054                .compatible = "qcom,sc7180-qmp-usb3-dp-phy",
6055                /* It's a combo phy */
6056        }, {
6057                .compatible = "qcom,sc8180x-qmp-pcie-phy",
6058                .data = &sc8180x_pciephy_cfg,
6059        }, {
6060                .compatible = "qcom,sc8180x-qmp-ufs-phy",
6061                .data = &sm8150_ufsphy_cfg,
6062        }, {
6063                .compatible = "qcom,sc8280xp-qmp-ufs-phy",
6064                .data = &sm8350_ufsphy_cfg,
6065        }, {
6066                .compatible = "qcom,sc8180x-qmp-usb3-phy",
6067                .data = &sm8150_usb3phy_cfg,
6068        }, {
6069                .compatible = "qcom,sc8180x-qmp-usb3-dp-phy",
6070                /* It's a combo phy */
6071        }, {
6072                .compatible = "qcom,sdm845-qhp-pcie-phy",
6073                .data = &sdm845_qhp_pciephy_cfg,
6074        }, {
6075                .compatible = "qcom,sdm845-qmp-pcie-phy",
6076                .data = &sdm845_qmp_pciephy_cfg,
6077        }, {
6078                .compatible = "qcom,sdm845-qmp-usb3-phy",
6079                .data = &qmp_v3_usb3phy_cfg,
6080        }, {
6081                .compatible = "qcom,sdm845-qmp-usb3-uni-phy",
6082                .data = &qmp_v3_usb3_uniphy_cfg,
6083        }, {
6084                .compatible = "qcom,sdm845-qmp-ufs-phy",
6085                .data = &sdm845_ufsphy_cfg,
6086        }, {
6087                .compatible = "qcom,msm8998-qmp-usb3-phy",
6088                .data = &msm8998_usb3phy_cfg,
6089        }, {
6090                .compatible = "qcom,sm6115-qmp-ufs-phy",
6091                .data = &sm6115_ufsphy_cfg,
6092        }, {
6093                .compatible = "qcom,sm6350-qmp-ufs-phy",
6094                .data = &sdm845_ufsphy_cfg,
6095        }, {
6096                .compatible = "qcom,sm8150-qmp-ufs-phy",
6097                .data = &sm8150_ufsphy_cfg,
6098        }, {
6099                .compatible = "qcom,sm8250-qmp-ufs-phy",
6100                .data = &sm8150_ufsphy_cfg,
6101        }, {
6102                .compatible = "qcom,sm8150-qmp-usb3-phy",
6103                .data = &sm8150_usb3phy_cfg,
6104        }, {
6105                .compatible = "qcom,sm8150-qmp-usb3-uni-phy",
6106                .data = &sm8150_usb3_uniphy_cfg,
6107        }, {
6108                .compatible = "qcom,sm8250-qmp-usb3-phy",
6109                .data = &sm8250_usb3phy_cfg,
6110        }, {
6111                .compatible = "qcom,sm8250-qmp-usb3-dp-phy",
6112                /* It's a combo phy */
6113        }, {
6114                .compatible = "qcom,sm8250-qmp-usb3-uni-phy",
6115                .data = &sm8250_usb3_uniphy_cfg,
6116        }, {
6117                .compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy",
6118                .data = &sm8250_qmp_gen3x1_pciephy_cfg,
6119        }, {
6120                .compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy",
6121                .data = &sm8250_qmp_gen3x2_pciephy_cfg,
6122        }, {
6123                .compatible = "qcom,sm8350-qmp-ufs-phy",
6124                .data = &sm8350_ufsphy_cfg,
6125        }, {
6126                .compatible = "qcom,sm8250-qmp-modem-pcie-phy",
6127                .data = &sm8250_qmp_gen3x2_pciephy_cfg,
6128        }, {
6129                .compatible = "qcom,sdx55-qmp-pcie-phy",
6130                .data = &sdx55_qmp_pciephy_cfg,
6131        }, {
6132                .compatible = "qcom,sdx55-qmp-usb3-uni-phy",
6133                .data = &sdx55_usb3_uniphy_cfg,
6134        }, {
6135                .compatible = "qcom,sdx65-qmp-usb3-uni-phy",
6136                .data = &sdx65_usb3_uniphy_cfg,
6137        }, {
6138                .compatible = "qcom,sm8350-qmp-usb3-phy",
6139                .data = &sm8350_usb3phy_cfg,
6140        }, {
6141                .compatible = "qcom,sm8350-qmp-usb3-uni-phy",
6142                .data = &sm8350_usb3_uniphy_cfg,
6143        }, {
6144                .compatible = "qcom,sm8450-qmp-gen3x1-pcie-phy",
6145                .data = &sm8450_qmp_gen3x1_pciephy_cfg,
6146        }, {
6147                .compatible = "qcom,sm8450-qmp-gen4x2-pcie-phy",
6148                .data = &sm8450_qmp_gen4x2_pciephy_cfg,
6149        }, {
6150                .compatible = "qcom,sm8450-qmp-ufs-phy",
6151                .data = &sm8450_ufsphy_cfg,
6152        }, {
6153                .compatible = "qcom,sm8450-qmp-usb3-phy",
6154                .data = &sm8350_usb3phy_cfg,
6155        }, {
6156                .compatible = "qcom,qcm2290-qmp-usb3-phy",
6157                .data = &qcm2290_usb3phy_cfg,
6158        },
6159        { },
6160};
6161MODULE_DEVICE_TABLE(of, qcom_qmp_phy_of_match_table);
6162
6163static const struct of_device_id qcom_qmp_combo_phy_of_match_table[] = {
6164        {
6165                .compatible = "qcom,sc7180-qmp-usb3-dp-phy",
6166                .data = &sc7180_usb3dpphy_cfg,
6167        },
6168        {
6169                .compatible = "qcom,sm8250-qmp-usb3-dp-phy",
6170                .data = &sm8250_usb3dpphy_cfg,
6171        },
6172        {
6173                .compatible = "qcom,sc8180x-qmp-usb3-dp-phy",
6174                .data = &sc8180x_usb3dpphy_cfg,
6175        },
6176        { }
6177};
6178
6179static const struct dev_pm_ops qcom_qmp_phy_pm_ops = {
6180        SET_RUNTIME_PM_OPS(qcom_qmp_phy_runtime_suspend,
6181                           qcom_qmp_phy_runtime_resume, NULL)
6182};
6183
6184static int qcom_qmp_phy_probe(struct platform_device *pdev)
6185{
6186        struct qcom_qmp *qmp;
6187        struct device *dev = &pdev->dev;
6188        struct device_node *child;
6189        struct phy_provider *phy_provider;
6190        void __iomem *serdes;
6191        void __iomem *usb_serdes;
6192        void __iomem *dp_serdes = NULL;
6193        const struct qmp_phy_combo_cfg *combo_cfg = NULL;
6194        const struct qmp_phy_cfg *cfg = NULL;
6195        const struct qmp_phy_cfg *usb_cfg = NULL;
6196        const struct qmp_phy_cfg *dp_cfg = NULL;
6197        int num, id, expected_phys;
6198        int ret;
6199
6200        qmp = devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL);
6201        if (!qmp)
6202                return -ENOMEM;
6203
6204        qmp->dev = dev;
6205        dev_set_drvdata(dev, qmp);
6206
6207        /* Get the specific init parameters of QMP phy */
6208        cfg = of_device_get_match_data(dev);
6209        if (!cfg) {
6210                const struct of_device_id *match;
6211
6212                match = of_match_device(qcom_qmp_combo_phy_of_match_table, dev);
6213                if (!match)
6214                        return -EINVAL;
6215
6216                combo_cfg = match->data;
6217                if (!combo_cfg)
6218                        return -EINVAL;
6219
6220                usb_cfg = combo_cfg->usb_cfg;
6221                cfg = usb_cfg; /* Setup clks and regulators */
6222        }
6223
6224        /* per PHY serdes; usually located at base address */
6225        usb_serdes = serdes = devm_platform_ioremap_resource(pdev, 0);
6226        if (IS_ERR(serdes))
6227                return PTR_ERR(serdes);
6228
6229        /* per PHY dp_com; if PHY has dp_com control block */
6230        if (combo_cfg || cfg->has_phy_dp_com_ctrl) {
6231                qmp->dp_com = devm_platform_ioremap_resource(pdev, 1);
6232                if (IS_ERR(qmp->dp_com))
6233                        return PTR_ERR(qmp->dp_com);
6234        }
6235
6236        if (combo_cfg) {
6237                /* Only two serdes for combo PHY */
6238                dp_serdes = devm_platform_ioremap_resource(pdev, 2);
6239                if (IS_ERR(dp_serdes))
6240                        return PTR_ERR(dp_serdes);
6241
6242                dp_cfg = combo_cfg->dp_cfg;
6243                expected_phys = 2;
6244        } else {
6245                expected_phys = cfg->nlanes;
6246        }
6247
6248        mutex_init(&qmp->phy_mutex);
6249
6250        ret = qcom_qmp_phy_clk_init(dev, cfg);
6251        if (ret)
6252                return ret;
6253
6254        ret = qcom_qmp_phy_reset_init(dev, cfg);
6255        if (ret)
6256                return ret;
6257
6258        ret = qcom_qmp_phy_vreg_init(dev, cfg);
6259        if (ret) {
6260                if (ret != -EPROBE_DEFER)
6261                        dev_err(dev, "failed to get regulator supplies: %d\n",
6262                                ret);
6263                return ret;
6264        }
6265
6266        num = of_get_available_child_count(dev->of_node);
6267        /* do we have a rogue child node ? */
6268        if (num > expected_phys)
6269                return -EINVAL;
6270
6271        qmp->phys = devm_kcalloc(dev, num, sizeof(*qmp->phys), GFP_KERNEL);
6272        if (!qmp->phys)
6273                return -ENOMEM;
6274
6275        pm_runtime_set_active(dev);
6276        pm_runtime_enable(dev);
6277        /*
6278         * Prevent runtime pm from being ON by default. Users can enable
6279         * it using power/control in sysfs.
6280         */
6281        pm_runtime_forbid(dev);
6282
6283        id = 0;
6284        for_each_available_child_of_node(dev->of_node, child) {
6285                if (of_node_name_eq(child, "dp-phy")) {
6286                        cfg = dp_cfg;
6287                        serdes = dp_serdes;
6288                } else if (of_node_name_eq(child, "usb3-phy")) {
6289                        cfg = usb_cfg;
6290                        serdes = usb_serdes;
6291                }
6292
6293                /* Create per-lane phy */
6294                ret = qcom_qmp_phy_create(dev, child, id, serdes, cfg);
6295                if (ret) {
6296                        dev_err(dev, "failed to create lane%d phy, %d\n",
6297                                id, ret);
6298                        goto err_node_put;
6299                }
6300
6301                /*
6302                 * Register the pipe clock provided by phy.
6303                 * See function description to see details of this pipe clock.
6304                 */
6305                if (cfg->type == PHY_TYPE_USB3 || cfg->type == PHY_TYPE_PCIE) {
6306                        ret = phy_pipe_clk_register(qmp, child);
6307                        if (ret) {
6308                                dev_err(qmp->dev,
6309                                        "failed to register pipe clock source\n");
6310                                goto err_node_put;
6311                        }
6312                } else if (cfg->type == PHY_TYPE_DP) {
6313                        ret = phy_dp_clks_register(qmp, qmp->phys[id], child);
6314                        if (ret) {
6315                                dev_err(qmp->dev,
6316                                        "failed to register DP clock source\n");
6317                                goto err_node_put;
6318                        }
6319                }
6320                id++;
6321        }
6322
6323        phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
6324        if (!IS_ERR(phy_provider))
6325                dev_info(dev, "Registered Qcom-QMP phy\n");
6326        else
6327                pm_runtime_disable(dev);
6328
6329        return PTR_ERR_OR_ZERO(phy_provider);
6330
6331err_node_put:
6332        pm_runtime_disable(dev);
6333        of_node_put(child);
6334        return ret;
6335}
6336
6337static struct platform_driver qcom_qmp_phy_driver = {
6338        .probe          = qcom_qmp_phy_probe,
6339        .driver = {
6340                .name   = "qcom-qmp-phy",
6341                .pm     = &qcom_qmp_phy_pm_ops,
6342                .of_match_table = qcom_qmp_phy_of_match_table,
6343        },
6344};
6345
6346module_platform_driver(qcom_qmp_phy_driver);
6347
6348MODULE_AUTHOR("Vivek Gautam <vivek.gautam@codeaurora.org>");
6349MODULE_DESCRIPTION("Qualcomm QMP PHY driver");
6350MODULE_LICENSE("GPL v2");
6351