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13#include <linux/err.h>
14#include <linux/bug.h>
15#include <linux/kernel.h>
16#include <linux/module.h>
17#include <linux/spinlock.h>
18#include <linux/compiler.h>
19#include <linux/types.h>
20#include <linux/errno.h>
21#include <linux/log2.h>
22#include <linux/io.h>
23#include <linux/gpio/driver.h>
24#include <linux/slab.h>
25#include <linux/platform_device.h>
26#include <linux/mutex.h>
27#include <linux/acpi.h>
28#include <linux/seq_file.h>
29#include <linux/interrupt.h>
30#include <linux/list.h>
31#include <linux/bitops.h>
32#include <linux/pinctrl/pinconf.h>
33#include <linux/pinctrl/pinconf-generic.h>
34
35#include "core.h"
36#include "pinctrl-utils.h"
37#include "pinctrl-amd.h"
38
39static int amd_gpio_get_direction(struct gpio_chip *gc, unsigned offset)
40{
41 unsigned long flags;
42 u32 pin_reg;
43 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
44
45 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
46 pin_reg = readl(gpio_dev->base + offset * 4);
47 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
48
49 if (pin_reg & BIT(OUTPUT_ENABLE_OFF))
50 return GPIO_LINE_DIRECTION_OUT;
51
52 return GPIO_LINE_DIRECTION_IN;
53}
54
55static int amd_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
56{
57 unsigned long flags;
58 u32 pin_reg;
59 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
60
61 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
62 pin_reg = readl(gpio_dev->base + offset * 4);
63 pin_reg &= ~BIT(OUTPUT_ENABLE_OFF);
64 writel(pin_reg, gpio_dev->base + offset * 4);
65 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
66
67 return 0;
68}
69
70static int amd_gpio_direction_output(struct gpio_chip *gc, unsigned offset,
71 int value)
72{
73 u32 pin_reg;
74 unsigned long flags;
75 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
76
77 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
78 pin_reg = readl(gpio_dev->base + offset * 4);
79 pin_reg |= BIT(OUTPUT_ENABLE_OFF);
80 if (value)
81 pin_reg |= BIT(OUTPUT_VALUE_OFF);
82 else
83 pin_reg &= ~BIT(OUTPUT_VALUE_OFF);
84 writel(pin_reg, gpio_dev->base + offset * 4);
85 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
86
87 return 0;
88}
89
90static int amd_gpio_get_value(struct gpio_chip *gc, unsigned offset)
91{
92 u32 pin_reg;
93 unsigned long flags;
94 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
95
96 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
97 pin_reg = readl(gpio_dev->base + offset * 4);
98 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
99
100 return !!(pin_reg & BIT(PIN_STS_OFF));
101}
102
103static void amd_gpio_set_value(struct gpio_chip *gc, unsigned offset, int value)
104{
105 u32 pin_reg;
106 unsigned long flags;
107 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
108
109 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
110 pin_reg = readl(gpio_dev->base + offset * 4);
111 if (value)
112 pin_reg |= BIT(OUTPUT_VALUE_OFF);
113 else
114 pin_reg &= ~BIT(OUTPUT_VALUE_OFF);
115 writel(pin_reg, gpio_dev->base + offset * 4);
116 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
117}
118
119static int amd_gpio_set_debounce(struct gpio_chip *gc, unsigned offset,
120 unsigned debounce)
121{
122 u32 time;
123 u32 pin_reg;
124 int ret = 0;
125 unsigned long flags;
126 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
127
128 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
129 pin_reg = readl(gpio_dev->base + offset * 4);
130
131 if (debounce) {
132 pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF;
133 pin_reg &= ~DB_TMR_OUT_MASK;
134
135
136
137
138
139
140
141
142
143
144 if (debounce < 61) {
145 pin_reg |= 1;
146 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);
147 pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
148 } else if (debounce < 976) {
149 time = debounce / 61;
150 pin_reg |= time & DB_TMR_OUT_MASK;
151 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);
152 pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
153 } else if (debounce < 3900) {
154 time = debounce / 244;
155 pin_reg |= time & DB_TMR_OUT_MASK;
156 pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF);
157 pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
158 } else if (debounce < 250000) {
159 time = debounce / 15625;
160 pin_reg |= time & DB_TMR_OUT_MASK;
161 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);
162 pin_reg |= BIT(DB_TMR_LARGE_OFF);
163 } else if (debounce < 1000000) {
164 time = debounce / 62500;
165 pin_reg |= time & DB_TMR_OUT_MASK;
166 pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF);
167 pin_reg |= BIT(DB_TMR_LARGE_OFF);
168 } else {
169 pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF);
170 ret = -EINVAL;
171 }
172 } else {
173 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);
174 pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
175 pin_reg &= ~DB_TMR_OUT_MASK;
176 pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF);
177 }
178 writel(pin_reg, gpio_dev->base + offset * 4);
179 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
180
181 return ret;
182}
183
184static int amd_gpio_set_config(struct gpio_chip *gc, unsigned offset,
185 unsigned long config)
186{
187 u32 debounce;
188
189 if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE)
190 return -ENOTSUPP;
191
192 debounce = pinconf_to_config_argument(config);
193 return amd_gpio_set_debounce(gc, offset, debounce);
194}
195
196#ifdef CONFIG_DEBUG_FS
197static void amd_gpio_dbg_show(struct seq_file *s, struct gpio_chip *gc)
198{
199 u32 pin_reg;
200 u32 db_cntrl;
201 unsigned long flags;
202 unsigned int bank, i, pin_num;
203 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
204
205 bool tmr_out_unit;
206 unsigned int time;
207 unsigned int unit;
208 bool tmr_large;
209
210 char *level_trig;
211 char *active_level;
212 char *interrupt_enable;
213 char *interrupt_mask;
214 char *wake_cntrl0;
215 char *wake_cntrl1;
216 char *wake_cntrl2;
217 char *pin_sts;
218 char *pull_up_sel;
219 char *pull_up_enable;
220 char *pull_down_enable;
221 char *output_value;
222 char *output_enable;
223 char debounce_value[40];
224 char *debounce_enable;
225
226 for (bank = 0; bank < gpio_dev->hwbank_num; bank++) {
227 seq_printf(s, "GPIO bank%d\t", bank);
228
229 switch (bank) {
230 case 0:
231 i = 0;
232 pin_num = AMD_GPIO_PINS_BANK0;
233 break;
234 case 1:
235 i = 64;
236 pin_num = AMD_GPIO_PINS_BANK1 + i;
237 break;
238 case 2:
239 i = 128;
240 pin_num = AMD_GPIO_PINS_BANK2 + i;
241 break;
242 case 3:
243 i = 192;
244 pin_num = AMD_GPIO_PINS_BANK3 + i;
245 break;
246 default:
247
248 continue;
249 }
250 for (; i < pin_num; i++) {
251 seq_printf(s, "pin%d\t", i);
252 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
253 pin_reg = readl(gpio_dev->base + i * 4);
254 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
255
256 if (pin_reg & BIT(INTERRUPT_ENABLE_OFF)) {
257 u8 level = (pin_reg >> ACTIVE_LEVEL_OFF) &
258 ACTIVE_LEVEL_MASK;
259 interrupt_enable = "interrupt is enabled|";
260
261 if (level == ACTIVE_LEVEL_HIGH)
262 active_level = "Active high|";
263 else if (level == ACTIVE_LEVEL_LOW)
264 active_level = "Active low|";
265 else if (!(pin_reg & BIT(LEVEL_TRIG_OFF)) &&
266 level == ACTIVE_LEVEL_BOTH)
267 active_level = "Active on both|";
268 else
269 active_level = "Unknown Active level|";
270
271 if (pin_reg & BIT(LEVEL_TRIG_OFF))
272 level_trig = "Level trigger|";
273 else
274 level_trig = "Edge trigger|";
275
276 } else {
277 interrupt_enable =
278 "interrupt is disabled|";
279 active_level = " ";
280 level_trig = " ";
281 }
282
283 if (pin_reg & BIT(INTERRUPT_MASK_OFF))
284 interrupt_mask =
285 "interrupt is unmasked|";
286 else
287 interrupt_mask =
288 "interrupt is masked|";
289
290 if (pin_reg & BIT(WAKE_CNTRL_OFF_S0I3))
291 wake_cntrl0 = "enable wakeup in S0i3 state|";
292 else
293 wake_cntrl0 = "disable wakeup in S0i3 state|";
294
295 if (pin_reg & BIT(WAKE_CNTRL_OFF_S3))
296 wake_cntrl1 = "enable wakeup in S3 state|";
297 else
298 wake_cntrl1 = "disable wakeup in S3 state|";
299
300 if (pin_reg & BIT(WAKE_CNTRL_OFF_S4))
301 wake_cntrl2 = "enable wakeup in S4/S5 state|";
302 else
303 wake_cntrl2 = "disable wakeup in S4/S5 state|";
304
305 if (pin_reg & BIT(PULL_UP_ENABLE_OFF)) {
306 pull_up_enable = "pull-up is enabled|";
307 if (pin_reg & BIT(PULL_UP_SEL_OFF))
308 pull_up_sel = "8k pull-up|";
309 else
310 pull_up_sel = "4k pull-up|";
311 } else {
312 pull_up_enable = "pull-up is disabled|";
313 pull_up_sel = " ";
314 }
315
316 if (pin_reg & BIT(PULL_DOWN_ENABLE_OFF))
317 pull_down_enable = "pull-down is enabled|";
318 else
319 pull_down_enable = "Pull-down is disabled|";
320
321 if (pin_reg & BIT(OUTPUT_ENABLE_OFF)) {
322 pin_sts = " ";
323 output_enable = "output is enabled|";
324 if (pin_reg & BIT(OUTPUT_VALUE_OFF))
325 output_value = "output is high|";
326 else
327 output_value = "output is low|";
328 } else {
329 output_enable = "output is disabled|";
330 output_value = " ";
331
332 if (pin_reg & BIT(PIN_STS_OFF))
333 pin_sts = "input is high|";
334 else
335 pin_sts = "input is low|";
336 }
337
338 db_cntrl = (DB_CNTRl_MASK << DB_CNTRL_OFF) & pin_reg;
339 if (db_cntrl) {
340 tmr_out_unit = pin_reg & BIT(DB_TMR_OUT_UNIT_OFF);
341 tmr_large = pin_reg & BIT(DB_TMR_LARGE_OFF);
342 time = pin_reg & DB_TMR_OUT_MASK;
343 if (tmr_large) {
344 if (tmr_out_unit)
345 unit = 62500;
346 else
347 unit = 15625;
348 } else {
349 if (tmr_out_unit)
350 unit = 244;
351 else
352 unit = 61;
353 }
354 if ((DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF) == db_cntrl)
355 debounce_enable = "debouncing filter (high and low) enabled|";
356 else if ((DB_TYPE_PRESERVE_LOW_GLITCH << DB_CNTRL_OFF) == db_cntrl)
357 debounce_enable = "debouncing filter (low) enabled|";
358 else
359 debounce_enable = "debouncing filter (high) enabled|";
360
361 snprintf(debounce_value, sizeof(debounce_value),
362 "debouncing timeout is %u (us)|", time * unit);
363 } else {
364 debounce_enable = "debouncing filter disabled|";
365 snprintf(debounce_value, sizeof(debounce_value), " ");
366 }
367
368 seq_printf(s, "%s %s %s %s %s %s\n"
369 " %s %s %s %s %s %s %s %s %s 0x%x\n",
370 level_trig, active_level, interrupt_enable,
371 interrupt_mask, wake_cntrl0, wake_cntrl1,
372 wake_cntrl2, pin_sts, pull_up_sel,
373 pull_up_enable, pull_down_enable,
374 output_value, output_enable,
375 debounce_enable, debounce_value, pin_reg);
376 }
377 }
378}
379#else
380#define amd_gpio_dbg_show NULL
381#endif
382
383static void amd_gpio_irq_enable(struct irq_data *d)
384{
385 u32 pin_reg;
386 unsigned long flags;
387 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
388 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
389
390 gpiochip_enable_irq(gc, d->hwirq);
391
392 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
393 pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
394 pin_reg |= BIT(INTERRUPT_ENABLE_OFF);
395 pin_reg |= BIT(INTERRUPT_MASK_OFF);
396 writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
397 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
398}
399
400static void amd_gpio_irq_disable(struct irq_data *d)
401{
402 u32 pin_reg;
403 unsigned long flags;
404 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
405 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
406
407 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
408 pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
409 pin_reg &= ~BIT(INTERRUPT_ENABLE_OFF);
410 pin_reg &= ~BIT(INTERRUPT_MASK_OFF);
411 writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
412 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
413
414 gpiochip_disable_irq(gc, d->hwirq);
415}
416
417static void amd_gpio_irq_mask(struct irq_data *d)
418{
419 u32 pin_reg;
420 unsigned long flags;
421 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
422 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
423
424 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
425 pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
426 pin_reg &= ~BIT(INTERRUPT_MASK_OFF);
427 writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
428 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
429}
430
431static void amd_gpio_irq_unmask(struct irq_data *d)
432{
433 u32 pin_reg;
434 unsigned long flags;
435 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
436 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
437
438 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
439 pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
440 pin_reg |= BIT(INTERRUPT_MASK_OFF);
441 writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
442 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
443}
444
445static int amd_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
446{
447 u32 pin_reg;
448 unsigned long flags;
449 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
450 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
451 u32 wake_mask = BIT(WAKE_CNTRL_OFF_S0I3) | BIT(WAKE_CNTRL_OFF_S3);
452 int err;
453
454 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
455 pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
456
457 if (on)
458 pin_reg |= wake_mask;
459 else
460 pin_reg &= ~wake_mask;
461
462 writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
463 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
464
465 if (on)
466 err = enable_irq_wake(gpio_dev->irq);
467 else
468 err = disable_irq_wake(gpio_dev->irq);
469
470 if (err)
471 dev_err(&gpio_dev->pdev->dev, "failed to %s wake-up interrupt\n",
472 on ? "enable" : "disable");
473
474 return 0;
475}
476
477static void amd_gpio_irq_eoi(struct irq_data *d)
478{
479 u32 reg;
480 unsigned long flags;
481 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
482 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
483
484 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
485 reg = readl(gpio_dev->base + WAKE_INT_MASTER_REG);
486 reg |= EOI_MASK;
487 writel(reg, gpio_dev->base + WAKE_INT_MASTER_REG);
488 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
489}
490
491static int amd_gpio_irq_set_type(struct irq_data *d, unsigned int type)
492{
493 int ret = 0;
494 u32 pin_reg, pin_reg_irq_en, mask;
495 unsigned long flags;
496 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
497 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
498
499 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
500 pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
501
502 switch (type & IRQ_TYPE_SENSE_MASK) {
503 case IRQ_TYPE_EDGE_RISING:
504 pin_reg &= ~BIT(LEVEL_TRIG_OFF);
505 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
506 pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF;
507 irq_set_handler_locked(d, handle_edge_irq);
508 break;
509
510 case IRQ_TYPE_EDGE_FALLING:
511 pin_reg &= ~BIT(LEVEL_TRIG_OFF);
512 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
513 pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF;
514 irq_set_handler_locked(d, handle_edge_irq);
515 break;
516
517 case IRQ_TYPE_EDGE_BOTH:
518 pin_reg &= ~BIT(LEVEL_TRIG_OFF);
519 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
520 pin_reg |= BOTH_EADGE << ACTIVE_LEVEL_OFF;
521 irq_set_handler_locked(d, handle_edge_irq);
522 break;
523
524 case IRQ_TYPE_LEVEL_HIGH:
525 pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF;
526 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
527 pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF;
528 irq_set_handler_locked(d, handle_level_irq);
529 break;
530
531 case IRQ_TYPE_LEVEL_LOW:
532 pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF;
533 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
534 pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF;
535 irq_set_handler_locked(d, handle_level_irq);
536 break;
537
538 case IRQ_TYPE_NONE:
539 break;
540
541 default:
542 dev_err(&gpio_dev->pdev->dev, "Invalid type value\n");
543 ret = -EINVAL;
544 }
545
546 pin_reg |= CLR_INTR_STAT << INTERRUPT_STS_OFF;
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562 mask = BIT(INTERRUPT_ENABLE_OFF);
563 pin_reg_irq_en = pin_reg;
564 pin_reg_irq_en |= mask;
565 pin_reg_irq_en &= ~BIT(INTERRUPT_MASK_OFF);
566 writel(pin_reg_irq_en, gpio_dev->base + (d->hwirq)*4);
567 while ((readl(gpio_dev->base + (d->hwirq)*4) & mask) != mask)
568 continue;
569 writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
570 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
571
572 return ret;
573}
574
575static void amd_irq_ack(struct irq_data *d)
576{
577
578
579
580
581
582}
583
584static const struct irq_chip amd_gpio_irqchip = {
585 .name = "amd_gpio",
586 .irq_ack = amd_irq_ack,
587 .irq_enable = amd_gpio_irq_enable,
588 .irq_disable = amd_gpio_irq_disable,
589 .irq_mask = amd_gpio_irq_mask,
590 .irq_unmask = amd_gpio_irq_unmask,
591 .irq_set_wake = amd_gpio_irq_set_wake,
592 .irq_eoi = amd_gpio_irq_eoi,
593 .irq_set_type = amd_gpio_irq_set_type,
594
595
596
597
598
599
600 .flags = IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND | IRQCHIP_IMMUTABLE,
601 GPIOCHIP_IRQ_RESOURCE_HELPERS,
602};
603
604#define PIN_IRQ_PENDING (BIT(INTERRUPT_STS_OFF) | BIT(WAKE_STS_OFF))
605
606static bool do_amd_gpio_irq_handler(int irq, void *dev_id)
607{
608 struct amd_gpio *gpio_dev = dev_id;
609 struct gpio_chip *gc = &gpio_dev->gc;
610 unsigned int i, irqnr;
611 unsigned long flags;
612 u32 __iomem *regs;
613 bool ret = false;
614 u32 regval;
615 u64 status, mask;
616
617
618 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
619 status = readl(gpio_dev->base + WAKE_INT_STATUS_REG1);
620 status <<= 32;
621 status |= readl(gpio_dev->base + WAKE_INT_STATUS_REG0);
622 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
623
624
625 status &= (1ULL << 46) - 1;
626 regs = gpio_dev->base;
627 for (mask = 1, irqnr = 0; status; mask <<= 1, regs += 4, irqnr += 4) {
628 if (!(status & mask))
629 continue;
630 status &= ~mask;
631
632
633 for (i = 0; i < 4; i++) {
634 regval = readl(regs + i);
635
636 if (irq < 0 && (regval & BIT(WAKE_STS_OFF))) {
637 dev_dbg(&gpio_dev->pdev->dev,
638 "Waking due to GPIO %d: 0x%x",
639 irqnr + i, regval);
640 return true;
641 }
642
643 if (!(regval & PIN_IRQ_PENDING) ||
644 !(regval & BIT(INTERRUPT_MASK_OFF)))
645 continue;
646 generic_handle_domain_irq(gc->irq.domain, irqnr + i);
647
648
649
650
651
652
653
654
655
656 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
657 regval = readl(regs + i);
658 if (irq == 0) {
659 regval &= ~BIT(INTERRUPT_ENABLE_OFF);
660 dev_dbg(&gpio_dev->pdev->dev,
661 "Disabling spurious GPIO IRQ %d\n",
662 irqnr + i);
663 }
664 writel(regval, regs + i);
665 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
666 ret = true;
667 }
668 }
669
670 if (irq < 0)
671 return false;
672
673
674 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
675 regval = readl(gpio_dev->base + WAKE_INT_MASTER_REG);
676 regval |= EOI_MASK;
677 writel(regval, gpio_dev->base + WAKE_INT_MASTER_REG);
678 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
679
680 return ret;
681}
682
683static irqreturn_t amd_gpio_irq_handler(int irq, void *dev_id)
684{
685 return IRQ_RETVAL(do_amd_gpio_irq_handler(irq, dev_id));
686}
687
688static bool __maybe_unused amd_gpio_check_wake(void *dev_id)
689{
690 return do_amd_gpio_irq_handler(-1, dev_id);
691}
692
693static int amd_get_groups_count(struct pinctrl_dev *pctldev)
694{
695 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
696
697 return gpio_dev->ngroups;
698}
699
700static const char *amd_get_group_name(struct pinctrl_dev *pctldev,
701 unsigned group)
702{
703 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
704
705 return gpio_dev->groups[group].name;
706}
707
708static int amd_get_group_pins(struct pinctrl_dev *pctldev,
709 unsigned group,
710 const unsigned **pins,
711 unsigned *num_pins)
712{
713 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
714
715 *pins = gpio_dev->groups[group].pins;
716 *num_pins = gpio_dev->groups[group].npins;
717 return 0;
718}
719
720static const struct pinctrl_ops amd_pinctrl_ops = {
721 .get_groups_count = amd_get_groups_count,
722 .get_group_name = amd_get_group_name,
723 .get_group_pins = amd_get_group_pins,
724#ifdef CONFIG_OF
725 .dt_node_to_map = pinconf_generic_dt_node_to_map_group,
726 .dt_free_map = pinctrl_utils_free_map,
727#endif
728};
729
730static int amd_pinconf_get(struct pinctrl_dev *pctldev,
731 unsigned int pin,
732 unsigned long *config)
733{
734 u32 pin_reg;
735 unsigned arg;
736 unsigned long flags;
737 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
738 enum pin_config_param param = pinconf_to_config_param(*config);
739
740 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
741 pin_reg = readl(gpio_dev->base + pin*4);
742 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
743 switch (param) {
744 case PIN_CONFIG_INPUT_DEBOUNCE:
745 arg = pin_reg & DB_TMR_OUT_MASK;
746 break;
747
748 case PIN_CONFIG_BIAS_PULL_DOWN:
749 arg = (pin_reg >> PULL_DOWN_ENABLE_OFF) & BIT(0);
750 break;
751
752 case PIN_CONFIG_BIAS_PULL_UP:
753 arg = (pin_reg >> PULL_UP_SEL_OFF) & (BIT(0) | BIT(1));
754 break;
755
756 case PIN_CONFIG_DRIVE_STRENGTH:
757 arg = (pin_reg >> DRV_STRENGTH_SEL_OFF) & DRV_STRENGTH_SEL_MASK;
758 break;
759
760 default:
761 dev_err(&gpio_dev->pdev->dev, "Invalid config param %04x\n",
762 param);
763 return -ENOTSUPP;
764 }
765
766 *config = pinconf_to_config_packed(param, arg);
767
768 return 0;
769}
770
771static int amd_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
772 unsigned long *configs, unsigned num_configs)
773{
774 int i;
775 u32 arg;
776 int ret = 0;
777 u32 pin_reg;
778 unsigned long flags;
779 enum pin_config_param param;
780 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
781
782 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
783 for (i = 0; i < num_configs; i++) {
784 param = pinconf_to_config_param(configs[i]);
785 arg = pinconf_to_config_argument(configs[i]);
786 pin_reg = readl(gpio_dev->base + pin*4);
787
788 switch (param) {
789 case PIN_CONFIG_INPUT_DEBOUNCE:
790 pin_reg &= ~DB_TMR_OUT_MASK;
791 pin_reg |= arg & DB_TMR_OUT_MASK;
792 break;
793
794 case PIN_CONFIG_BIAS_PULL_DOWN:
795 pin_reg &= ~BIT(PULL_DOWN_ENABLE_OFF);
796 pin_reg |= (arg & BIT(0)) << PULL_DOWN_ENABLE_OFF;
797 break;
798
799 case PIN_CONFIG_BIAS_PULL_UP:
800 pin_reg &= ~BIT(PULL_UP_SEL_OFF);
801 pin_reg |= (arg & BIT(0)) << PULL_UP_SEL_OFF;
802 pin_reg &= ~BIT(PULL_UP_ENABLE_OFF);
803 pin_reg |= ((arg>>1) & BIT(0)) << PULL_UP_ENABLE_OFF;
804 break;
805
806 case PIN_CONFIG_DRIVE_STRENGTH:
807 pin_reg &= ~(DRV_STRENGTH_SEL_MASK
808 << DRV_STRENGTH_SEL_OFF);
809 pin_reg |= (arg & DRV_STRENGTH_SEL_MASK)
810 << DRV_STRENGTH_SEL_OFF;
811 break;
812
813 default:
814 dev_err(&gpio_dev->pdev->dev,
815 "Invalid config param %04x\n", param);
816 ret = -ENOTSUPP;
817 }
818
819 writel(pin_reg, gpio_dev->base + pin*4);
820 }
821 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
822
823 return ret;
824}
825
826static int amd_pinconf_group_get(struct pinctrl_dev *pctldev,
827 unsigned int group,
828 unsigned long *config)
829{
830 const unsigned *pins;
831 unsigned npins;
832 int ret;
833
834 ret = amd_get_group_pins(pctldev, group, &pins, &npins);
835 if (ret)
836 return ret;
837
838 if (amd_pinconf_get(pctldev, pins[0], config))
839 return -ENOTSUPP;
840
841 return 0;
842}
843
844static int amd_pinconf_group_set(struct pinctrl_dev *pctldev,
845 unsigned group, unsigned long *configs,
846 unsigned num_configs)
847{
848 const unsigned *pins;
849 unsigned npins;
850 int i, ret;
851
852 ret = amd_get_group_pins(pctldev, group, &pins, &npins);
853 if (ret)
854 return ret;
855 for (i = 0; i < npins; i++) {
856 if (amd_pinconf_set(pctldev, pins[i], configs, num_configs))
857 return -ENOTSUPP;
858 }
859 return 0;
860}
861
862static const struct pinconf_ops amd_pinconf_ops = {
863 .pin_config_get = amd_pinconf_get,
864 .pin_config_set = amd_pinconf_set,
865 .pin_config_group_get = amd_pinconf_group_get,
866 .pin_config_group_set = amd_pinconf_group_set,
867};
868
869static void amd_gpio_irq_init(struct amd_gpio *gpio_dev)
870{
871 struct pinctrl_desc *desc = gpio_dev->pctrl->desc;
872 unsigned long flags;
873 u32 pin_reg, mask;
874 int i;
875
876 mask = BIT(WAKE_CNTRL_OFF_S0I3) | BIT(WAKE_CNTRL_OFF_S3) |
877 BIT(INTERRUPT_MASK_OFF) | BIT(INTERRUPT_ENABLE_OFF) |
878 BIT(WAKE_CNTRL_OFF_S4);
879
880 for (i = 0; i < desc->npins; i++) {
881 int pin = desc->pins[i].number;
882 const struct pin_desc *pd = pin_desc_get(gpio_dev->pctrl, pin);
883
884 if (!pd)
885 continue;
886
887 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
888
889 pin_reg = readl(gpio_dev->base + i * 4);
890 pin_reg &= ~mask;
891 writel(pin_reg, gpio_dev->base + i * 4);
892
893 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
894 }
895}
896
897#ifdef CONFIG_PM_SLEEP
898static bool amd_gpio_should_save(struct amd_gpio *gpio_dev, unsigned int pin)
899{
900 const struct pin_desc *pd = pin_desc_get(gpio_dev->pctrl, pin);
901
902 if (!pd)
903 return false;
904
905
906
907
908
909 if (pd->mux_owner || pd->gpio_owner ||
910 gpiochip_line_is_irq(&gpio_dev->gc, pin))
911 return true;
912
913 return false;
914}
915
916static int amd_gpio_suspend(struct device *dev)
917{
918 struct amd_gpio *gpio_dev = dev_get_drvdata(dev);
919 struct pinctrl_desc *desc = gpio_dev->pctrl->desc;
920 int i;
921
922 for (i = 0; i < desc->npins; i++) {
923 int pin = desc->pins[i].number;
924
925 if (!amd_gpio_should_save(gpio_dev, pin))
926 continue;
927
928 gpio_dev->saved_regs[i] = readl(gpio_dev->base + pin*4);
929 }
930
931 return 0;
932}
933
934static int amd_gpio_resume(struct device *dev)
935{
936 struct amd_gpio *gpio_dev = dev_get_drvdata(dev);
937 struct pinctrl_desc *desc = gpio_dev->pctrl->desc;
938 int i;
939
940 for (i = 0; i < desc->npins; i++) {
941 int pin = desc->pins[i].number;
942
943 if (!amd_gpio_should_save(gpio_dev, pin))
944 continue;
945
946 writel(gpio_dev->saved_regs[i], gpio_dev->base + pin*4);
947 }
948
949 return 0;
950}
951
952static const struct dev_pm_ops amd_gpio_pm_ops = {
953 SET_LATE_SYSTEM_SLEEP_PM_OPS(amd_gpio_suspend,
954 amd_gpio_resume)
955};
956#endif
957
958static struct pinctrl_desc amd_pinctrl_desc = {
959 .pins = kerncz_pins,
960 .npins = ARRAY_SIZE(kerncz_pins),
961 .pctlops = &amd_pinctrl_ops,
962 .confops = &amd_pinconf_ops,
963 .owner = THIS_MODULE,
964};
965
966static int amd_gpio_probe(struct platform_device *pdev)
967{
968 int ret = 0;
969 struct resource *res;
970 struct amd_gpio *gpio_dev;
971 struct gpio_irq_chip *girq;
972
973 gpio_dev = devm_kzalloc(&pdev->dev,
974 sizeof(struct amd_gpio), GFP_KERNEL);
975 if (!gpio_dev)
976 return -ENOMEM;
977
978 raw_spin_lock_init(&gpio_dev->lock);
979
980 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
981 if (!res) {
982 dev_err(&pdev->dev, "Failed to get gpio io resource.\n");
983 return -EINVAL;
984 }
985
986 gpio_dev->base = devm_ioremap(&pdev->dev, res->start,
987 resource_size(res));
988 if (!gpio_dev->base)
989 return -ENOMEM;
990
991 gpio_dev->irq = platform_get_irq(pdev, 0);
992 if (gpio_dev->irq < 0)
993 return gpio_dev->irq;
994
995#ifdef CONFIG_PM_SLEEP
996 gpio_dev->saved_regs = devm_kcalloc(&pdev->dev, amd_pinctrl_desc.npins,
997 sizeof(*gpio_dev->saved_regs),
998 GFP_KERNEL);
999 if (!gpio_dev->saved_regs)
1000 return -ENOMEM;
1001#endif
1002
1003 gpio_dev->pdev = pdev;
1004 gpio_dev->gc.get_direction = amd_gpio_get_direction;
1005 gpio_dev->gc.direction_input = amd_gpio_direction_input;
1006 gpio_dev->gc.direction_output = amd_gpio_direction_output;
1007 gpio_dev->gc.get = amd_gpio_get_value;
1008 gpio_dev->gc.set = amd_gpio_set_value;
1009 gpio_dev->gc.set_config = amd_gpio_set_config;
1010 gpio_dev->gc.dbg_show = amd_gpio_dbg_show;
1011
1012 gpio_dev->gc.base = -1;
1013 gpio_dev->gc.label = pdev->name;
1014 gpio_dev->gc.owner = THIS_MODULE;
1015 gpio_dev->gc.parent = &pdev->dev;
1016 gpio_dev->gc.ngpio = resource_size(res) / 4;
1017
1018 gpio_dev->hwbank_num = gpio_dev->gc.ngpio / 64;
1019 gpio_dev->groups = kerncz_groups;
1020 gpio_dev->ngroups = ARRAY_SIZE(kerncz_groups);
1021
1022 amd_pinctrl_desc.name = dev_name(&pdev->dev);
1023 gpio_dev->pctrl = devm_pinctrl_register(&pdev->dev, &amd_pinctrl_desc,
1024 gpio_dev);
1025 if (IS_ERR(gpio_dev->pctrl)) {
1026 dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
1027 return PTR_ERR(gpio_dev->pctrl);
1028 }
1029
1030
1031 amd_gpio_irq_init(gpio_dev);
1032
1033 girq = &gpio_dev->gc.irq;
1034 gpio_irq_chip_set_chip(girq, &amd_gpio_irqchip);
1035
1036 girq->parent_handler = NULL;
1037 girq->num_parents = 0;
1038 girq->parents = NULL;
1039 girq->default_type = IRQ_TYPE_NONE;
1040 girq->handler = handle_simple_irq;
1041
1042 ret = gpiochip_add_data(&gpio_dev->gc, gpio_dev);
1043 if (ret)
1044 return ret;
1045
1046 ret = gpiochip_add_pin_range(&gpio_dev->gc, dev_name(&pdev->dev),
1047 0, 0, gpio_dev->gc.ngpio);
1048 if (ret) {
1049 dev_err(&pdev->dev, "Failed to add pin range\n");
1050 goto out2;
1051 }
1052
1053 ret = devm_request_irq(&pdev->dev, gpio_dev->irq, amd_gpio_irq_handler,
1054 IRQF_SHARED, KBUILD_MODNAME, gpio_dev);
1055 if (ret)
1056 goto out2;
1057
1058 platform_set_drvdata(pdev, gpio_dev);
1059 acpi_register_wakeup_handler(gpio_dev->irq, amd_gpio_check_wake, gpio_dev);
1060
1061 dev_dbg(&pdev->dev, "amd gpio driver loaded\n");
1062 return ret;
1063
1064out2:
1065 gpiochip_remove(&gpio_dev->gc);
1066
1067 return ret;
1068}
1069
1070static int amd_gpio_remove(struct platform_device *pdev)
1071{
1072 struct amd_gpio *gpio_dev;
1073
1074 gpio_dev = platform_get_drvdata(pdev);
1075
1076 gpiochip_remove(&gpio_dev->gc);
1077 acpi_unregister_wakeup_handler(amd_gpio_check_wake, gpio_dev);
1078
1079 return 0;
1080}
1081
1082#ifdef CONFIG_ACPI
1083static const struct acpi_device_id amd_gpio_acpi_match[] = {
1084 { "AMD0030", 0 },
1085 { "AMDI0030", 0},
1086 { "AMDI0031", 0},
1087 { },
1088};
1089MODULE_DEVICE_TABLE(acpi, amd_gpio_acpi_match);
1090#endif
1091
1092static struct platform_driver amd_gpio_driver = {
1093 .driver = {
1094 .name = "amd_gpio",
1095 .acpi_match_table = ACPI_PTR(amd_gpio_acpi_match),
1096#ifdef CONFIG_PM_SLEEP
1097 .pm = &amd_gpio_pm_ops,
1098#endif
1099 },
1100 .probe = amd_gpio_probe,
1101 .remove = amd_gpio_remove,
1102};
1103
1104module_platform_driver(amd_gpio_driver);
1105
1106MODULE_LICENSE("GPL v2");
1107MODULE_AUTHOR("Ken Xue <Ken.Xue@amd.com>, Jeff Wu <Jeff.Wu@amd.com>");
1108MODULE_DESCRIPTION("AMD GPIO pinctrl driver");
1109
