1/* SPDX-License-Identifier: GPL-2.0-only */ 2/* 3 * Copyright (c) 2013, Sony Mobile Communications AB. 4 */ 5#ifndef __PINCTRL_MSM_H__ 6#define __PINCTRL_MSM_H__ 7 8struct pinctrl_pin_desc; 9 10/** 11 * struct msm_function - a pinmux function 12 * @name: Name of the pinmux function. 13 * @groups: List of pingroups for this function. 14 * @ngroups: Number of entries in @groups. 15 */ 16struct msm_function { 17 const char *name; 18 const char * const *groups; 19 unsigned ngroups; 20}; 21 22/** 23 * struct msm_pingroup - Qualcomm pingroup definition 24 * @name: Name of the pingroup. 25 * @pins: A list of pins assigned to this pingroup. 26 * @npins: Number of entries in @pins. 27 * @funcs: A list of pinmux functions that can be selected for 28 * this group. The index of the selected function is used 29 * for programming the function selector. 30 * Entries should be indices into the groups list of the 31 * struct msm_pinctrl_soc_data. 32 * @ctl_reg: Offset of the register holding control bits for this group. 33 * @io_reg: Offset of the register holding input/output bits for this group. 34 * @intr_cfg_reg: Offset of the register holding interrupt configuration bits. 35 * @intr_status_reg: Offset of the register holding the status bits for this group. 36 * @intr_target_reg: Offset of the register specifying routing of the interrupts 37 * from this group. 38 * @mux_bit: Offset in @ctl_reg for the pinmux function selection. 39 * @pull_bit: Offset in @ctl_reg for the bias configuration. 40 * @drv_bit: Offset in @ctl_reg for the drive strength configuration. 41 * @od_bit: Offset in @ctl_reg for controlling open drain. 42 * @oe_bit: Offset in @ctl_reg for controlling output enable. 43 * @in_bit: Offset in @io_reg for the input bit value. 44 * @out_bit: Offset in @io_reg for the output bit value. 45 * @intr_enable_bit: Offset in @intr_cfg_reg for enabling the interrupt for this group. 46 * @intr_status_bit: Offset in @intr_status_reg for reading and acking the interrupt 47 * status. 48 * @intr_target_bit: Offset in @intr_target_reg for configuring the interrupt routing. 49 * @intr_target_kpss_val: Value in @intr_target_bit for specifying that the interrupt from 50 * this gpio should get routed to the KPSS processor. 51 * @intr_raw_status_bit: Offset in @intr_cfg_reg for the raw status bit. 52 * @intr_polarity_bit: Offset in @intr_cfg_reg for specifying polarity of the interrupt. 53 * @intr_detection_bit: Offset in @intr_cfg_reg for specifying interrupt type. 54 * @intr_detection_width: Number of bits used for specifying interrupt type, 55 * Should be 2 for SoCs that can detect both edges in hardware, 56 * otherwise 1. 57 */ 58struct msm_pingroup { 59 const char *name; 60 const unsigned *pins; 61 unsigned npins; 62 63 unsigned *funcs; 64 unsigned nfuncs; 65 66 u32 ctl_reg; 67 u32 io_reg; 68 u32 intr_cfg_reg; 69 u32 intr_status_reg; 70 u32 intr_target_reg; 71 72 unsigned int tile:2; 73 74 unsigned mux_bit:5; 75 76 unsigned pull_bit:5; 77 unsigned drv_bit:5; 78 79 unsigned od_bit:5; 80 unsigned egpio_enable:5; 81 unsigned egpio_present:5; 82 unsigned oe_bit:5; 83 unsigned in_bit:5; 84 unsigned out_bit:5; 85 86 unsigned intr_enable_bit:5; 87 unsigned intr_status_bit:5; 88 unsigned intr_ack_high:1; 89 90 unsigned intr_target_bit:5; 91 unsigned intr_target_kpss_val:5; 92 unsigned intr_raw_status_bit:5; 93 unsigned intr_polarity_bit:5; 94 unsigned intr_detection_bit:5; 95 unsigned intr_detection_width:5; 96}; 97 98/** 99 * struct msm_gpio_wakeirq_map - Map of GPIOs and their wakeup pins 100 * @gpio: The GPIOs that are wakeup capable 101 * @wakeirq: The interrupt at the always-on interrupt controller 102 */ 103struct msm_gpio_wakeirq_map { 104 unsigned int gpio; 105 unsigned int wakeirq; 106}; 107 108/** 109 * struct msm_pinctrl_soc_data - Qualcomm pin controller driver configuration 110 * @pins: An array describing all pins the pin controller affects. 111 * @npins: The number of entries in @pins. 112 * @functions: An array describing all mux functions the SoC supports. 113 * @nfunctions: The number of entries in @functions. 114 * @groups: An array describing all pin groups the pin SoC supports. 115 * @ngroups: The numbmer of entries in @groups. 116 * @ngpio: The number of pingroups the driver should expose as GPIOs. 117 * @pull_no_keeper: The SoC does not support keeper bias. 118 * @wakeirq_map: The map of wakeup capable GPIOs and the pin at PDC/MPM 119 * @nwakeirq_map: The number of entries in @wakeirq_map 120 * @wakeirq_dual_edge_errata: If true then GPIOs using the wakeirq_map need 121 * to be aware that their parent can't handle dual 122 * edge interrupts. 123 * @gpio_func: Which function number is GPIO (usually 0). 124 * @egpio_func: If non-zero then this SoC supports eGPIO. Even though in 125 * hardware this is a mux 1-level above the TLMM, we'll treat 126 * it as if this is just another mux state of the TLMM. Since 127 * it doesn't really map to hardware, we'll allocate a virtual 128 * function number for eGPIO and any time we see that function 129 * number used we'll treat it as a request to mux away from 130 * our TLMM towards another owner. 131 */ 132struct msm_pinctrl_soc_data { 133 const struct pinctrl_pin_desc *pins; 134 unsigned npins; 135 const struct msm_function *functions; 136 unsigned nfunctions; 137 const struct msm_pingroup *groups; 138 unsigned ngroups; 139 unsigned ngpios; 140 bool pull_no_keeper; 141 const char *const *tiles; 142 unsigned int ntiles; 143 const int *reserved_gpios; 144 const struct msm_gpio_wakeirq_map *wakeirq_map; 145 unsigned int nwakeirq_map; 146 bool wakeirq_dual_edge_errata; 147 unsigned int gpio_func; 148 unsigned int egpio_func; 149}; 150 151extern const struct dev_pm_ops msm_pinctrl_dev_pm_ops; 152 153int msm_pinctrl_probe(struct platform_device *pdev, 154 const struct msm_pinctrl_soc_data *soc_data); 155int msm_pinctrl_remove(struct platform_device *pdev); 156 157#endif 158