1
2
3
4
5#include <linux/completion.h>
6#include <linux/delay.h>
7#include <linux/err.h>
8#include <linux/errno.h>
9#include <linux/interrupt.h>
10#include <linux/io.h>
11#include <linux/iopoll.h>
12#include <linux/kernel.h>
13#include <linux/module.h>
14#include <linux/of_device.h>
15#include <linux/of.h>
16#include <linux/platform_device.h>
17#include <linux/pm_runtime.h>
18#include <linux/spi/spi.h>
19#include <linux/spi/spi-mem.h>
20#include <linux/bitfield.h>
21#include <linux/limits.h>
22#include <linux/log2.h>
23
24#define CDNS_XSPI_MAGIC_NUM_VALUE 0x6522
25#define CDNS_XSPI_MAX_BANKS 8
26#define CDNS_XSPI_NAME "cadence-xspi"
27
28
29
30
31
32
33
34#define CDNS_XSPI_CCP_PHY_DQ_TIMING 0x0000
35
36
37#define CDNS_XSPI_CCP_PHY_DQS_TIMING 0x0004
38
39
40#define CDNS_XSPI_CCP_PHY_GATE_LPBCK_CTRL 0x0008
41
42
43#define CDNS_XSPI_CCP_PHY_DLL_SLAVE_CTRL 0x0010
44
45
46#define CDNS_XSPI_DLL_PHY_CTRL 0x1034
47
48
49#define CDNS_XSPI_CMD_REG_0 0x0000
50#define CDNS_XSPI_CMD_REG_1 0x0004
51#define CDNS_XSPI_CMD_REG_2 0x0008
52#define CDNS_XSPI_CMD_REG_3 0x000C
53#define CDNS_XSPI_CMD_REG_4 0x0010
54#define CDNS_XSPI_CMD_REG_5 0x0014
55
56
57#define CDNS_XSPI_CMD_STATUS_REG 0x0044
58
59
60#define CDNS_XSPI_CTRL_STATUS_REG 0x0100
61#define CDNS_XSPI_INIT_COMPLETED BIT(16)
62#define CDNS_XSPI_INIT_LEGACY BIT(9)
63#define CDNS_XSPI_INIT_FAIL BIT(8)
64#define CDNS_XSPI_CTRL_BUSY BIT(7)
65
66
67#define CDNS_XSPI_INTR_STATUS_REG 0x0110
68#define CDNS_XSPI_STIG_DONE BIT(23)
69#define CDNS_XSPI_SDMA_ERROR BIT(22)
70#define CDNS_XSPI_SDMA_TRIGGER BIT(21)
71#define CDNS_XSPI_CMD_IGNRD_EN BIT(20)
72#define CDNS_XSPI_DDMA_TERR_EN BIT(18)
73#define CDNS_XSPI_CDMA_TREE_EN BIT(17)
74#define CDNS_XSPI_CTRL_IDLE_EN BIT(16)
75
76#define CDNS_XSPI_TRD_COMP_INTR_STATUS 0x0120
77#define CDNS_XSPI_TRD_ERR_INTR_STATUS 0x0130
78#define CDNS_XSPI_TRD_ERR_INTR_EN 0x0134
79
80
81#define CDNS_XSPI_INTR_ENABLE_REG 0x0114
82#define CDNS_XSPI_INTR_EN BIT(31)
83#define CDNS_XSPI_STIG_DONE_EN BIT(23)
84#define CDNS_XSPI_SDMA_ERROR_EN BIT(22)
85#define CDNS_XSPI_SDMA_TRIGGER_EN BIT(21)
86
87#define CDNS_XSPI_INTR_MASK (CDNS_XSPI_INTR_EN | \
88 CDNS_XSPI_STIG_DONE_EN | \
89 CDNS_XSPI_SDMA_ERROR_EN | \
90 CDNS_XSPI_SDMA_TRIGGER_EN)
91
92
93#define CDNS_XSPI_CTRL_CONFIG_REG 0x0230
94#define CDNS_XSPI_CTRL_WORK_MODE GENMASK(6, 5)
95
96#define CDNS_XSPI_WORK_MODE_DIRECT 0
97#define CDNS_XSPI_WORK_MODE_STIG 1
98#define CDNS_XSPI_WORK_MODE_ACMD 3
99
100
101#define CDNS_XSPI_SDMA_SIZE_REG 0x0240
102#define CDNS_XSPI_SDMA_TRD_INFO_REG 0x0244
103#define CDNS_XSPI_SDMA_DIR BIT(8)
104
105
106#define CDNS_XSPI_CTRL_FEATURES_REG 0x0F04
107#define CDNS_XSPI_NUM_BANKS GENMASK(25, 24)
108#define CDNS_XSPI_DMA_DATA_WIDTH BIT(21)
109#define CDNS_XSPI_NUM_THREADS GENMASK(3, 0)
110
111
112#define CDNS_XSPI_CTRL_VERSION_REG 0x0F00
113#define CDNS_XSPI_MAGIC_NUM GENMASK(31, 16)
114#define CDNS_XSPI_CTRL_REV GENMASK(7, 0)
115
116
117#define CDNS_XSPI_CMD_INSTR_TYPE GENMASK(6, 0)
118#define CDNS_XSPI_CMD_P1_R1_ADDR0 GENMASK(31, 24)
119#define CDNS_XSPI_CMD_P1_R2_ADDR1 GENMASK(7, 0)
120#define CDNS_XSPI_CMD_P1_R2_ADDR2 GENMASK(15, 8)
121#define CDNS_XSPI_CMD_P1_R2_ADDR3 GENMASK(23, 16)
122#define CDNS_XSPI_CMD_P1_R2_ADDR4 GENMASK(31, 24)
123#define CDNS_XSPI_CMD_P1_R3_ADDR5 GENMASK(7, 0)
124#define CDNS_XSPI_CMD_P1_R3_CMD GENMASK(23, 16)
125#define CDNS_XSPI_CMD_P1_R3_NUM_ADDR_BYTES GENMASK(30, 28)
126#define CDNS_XSPI_CMD_P1_R4_ADDR_IOS GENMASK(1, 0)
127#define CDNS_XSPI_CMD_P1_R4_CMD_IOS GENMASK(9, 8)
128#define CDNS_XSPI_CMD_P1_R4_BANK GENMASK(14, 12)
129
130
131#define CDNS_XSPI_CMD_DSEQ_R2_DCNT_L GENMASK(31, 16)
132#define CDNS_XSPI_CMD_DSEQ_R3_DCNT_H GENMASK(15, 0)
133#define CDNS_XSPI_CMD_DSEQ_R3_NUM_OF_DUMMY GENMASK(25, 20)
134#define CDNS_XSPI_CMD_DSEQ_R4_BANK GENMASK(14, 12)
135#define CDNS_XSPI_CMD_DSEQ_R4_DATA_IOS GENMASK(9, 8)
136#define CDNS_XSPI_CMD_DSEQ_R4_DIR BIT(4)
137
138
139#define CDNS_XSPI_CMD_STATUS_COMPLETED BIT(15)
140#define CDNS_XSPI_CMD_STATUS_FAILED BIT(14)
141#define CDNS_XSPI_CMD_STATUS_DQS_ERROR BIT(3)
142#define CDNS_XSPI_CMD_STATUS_CRC_ERROR BIT(2)
143#define CDNS_XSPI_CMD_STATUS_BUS_ERROR BIT(1)
144#define CDNS_XSPI_CMD_STATUS_INV_SEQ_ERROR BIT(0)
145
146#define CDNS_XSPI_STIG_DONE_FLAG BIT(0)
147#define CDNS_XSPI_TRD_STATUS 0x0104
148
149
150#define CDNS_XSPI_CMD_FLD_P1_INSTR_CMD_1(op, data_phase) ( \
151 FIELD_PREP(CDNS_XSPI_CMD_INSTR_TYPE, (data_phase) ? \
152 CDNS_XSPI_STIG_INSTR_TYPE_1 : CDNS_XSPI_STIG_INSTR_TYPE_0) | \
153 FIELD_PREP(CDNS_XSPI_CMD_P1_R1_ADDR0, (op)->addr.val & 0xff))
154
155#define CDNS_XSPI_CMD_FLD_P1_INSTR_CMD_2(op) ( \
156 FIELD_PREP(CDNS_XSPI_CMD_P1_R2_ADDR1, ((op)->addr.val >> 8) & 0xFF) | \
157 FIELD_PREP(CDNS_XSPI_CMD_P1_R2_ADDR2, ((op)->addr.val >> 16) & 0xFF) | \
158 FIELD_PREP(CDNS_XSPI_CMD_P1_R2_ADDR3, ((op)->addr.val >> 24) & 0xFF) | \
159 FIELD_PREP(CDNS_XSPI_CMD_P1_R2_ADDR4, ((op)->addr.val >> 32) & 0xFF))
160
161#define CDNS_XSPI_CMD_FLD_P1_INSTR_CMD_3(op) ( \
162 FIELD_PREP(CDNS_XSPI_CMD_P1_R3_ADDR5, ((op)->addr.val >> 40) & 0xFF) | \
163 FIELD_PREP(CDNS_XSPI_CMD_P1_R3_CMD, (op)->cmd.opcode) | \
164 FIELD_PREP(CDNS_XSPI_CMD_P1_R3_NUM_ADDR_BYTES, (op)->addr.nbytes))
165
166#define CDNS_XSPI_CMD_FLD_P1_INSTR_CMD_4(op, chipsel) ( \
167 FIELD_PREP(CDNS_XSPI_CMD_P1_R4_ADDR_IOS, ilog2((op)->addr.buswidth)) | \
168 FIELD_PREP(CDNS_XSPI_CMD_P1_R4_CMD_IOS, ilog2((op)->cmd.buswidth)) | \
169 FIELD_PREP(CDNS_XSPI_CMD_P1_R4_BANK, chipsel))
170
171#define CDNS_XSPI_CMD_FLD_DSEQ_CMD_1(op) \
172 FIELD_PREP(CDNS_XSPI_CMD_INSTR_TYPE, CDNS_XSPI_STIG_INSTR_TYPE_DATA_SEQ)
173
174#define CDNS_XSPI_CMD_FLD_DSEQ_CMD_2(op) \
175 FIELD_PREP(CDNS_XSPI_CMD_DSEQ_R2_DCNT_L, (op)->data.nbytes & 0xFFFF)
176
177#define CDNS_XSPI_CMD_FLD_DSEQ_CMD_3(op) ( \
178 FIELD_PREP(CDNS_XSPI_CMD_DSEQ_R3_DCNT_H, \
179 ((op)->data.nbytes >> 16) & 0xffff) | \
180 FIELD_PREP(CDNS_XSPI_CMD_DSEQ_R3_NUM_OF_DUMMY, (op)->dummy.nbytes * 8))
181
182#define CDNS_XSPI_CMD_FLD_DSEQ_CMD_4(op, chipsel) ( \
183 FIELD_PREP(CDNS_XSPI_CMD_DSEQ_R4_BANK, chipsel) | \
184 FIELD_PREP(CDNS_XSPI_CMD_DSEQ_R4_DATA_IOS, \
185 ilog2((op)->data.buswidth)) | \
186 FIELD_PREP(CDNS_XSPI_CMD_DSEQ_R4_DIR, \
187 ((op)->data.dir == SPI_MEM_DATA_IN) ? \
188 CDNS_XSPI_STIG_CMD_DIR_READ : CDNS_XSPI_STIG_CMD_DIR_WRITE))
189
190enum cdns_xspi_stig_instr_type {
191 CDNS_XSPI_STIG_INSTR_TYPE_0,
192 CDNS_XSPI_STIG_INSTR_TYPE_1,
193 CDNS_XSPI_STIG_INSTR_TYPE_DATA_SEQ = 127,
194};
195
196enum cdns_xspi_sdma_dir {
197 CDNS_XSPI_SDMA_DIR_READ,
198 CDNS_XSPI_SDMA_DIR_WRITE,
199};
200
201enum cdns_xspi_stig_cmd_dir {
202 CDNS_XSPI_STIG_CMD_DIR_READ,
203 CDNS_XSPI_STIG_CMD_DIR_WRITE,
204};
205
206struct cdns_xspi_dev {
207 struct platform_device *pdev;
208 struct device *dev;
209
210 void __iomem *iobase;
211 void __iomem *auxbase;
212 void __iomem *sdmabase;
213
214 int irq;
215 int cur_cs;
216 unsigned int sdmasize;
217
218 struct completion cmd_complete;
219 struct completion auto_cmd_complete;
220 struct completion sdma_complete;
221 bool sdma_error;
222
223 void *in_buffer;
224 const void *out_buffer;
225
226 u8 hw_num_banks;
227};
228
229static int cdns_xspi_wait_for_controller_idle(struct cdns_xspi_dev *cdns_xspi)
230{
231 u32 ctrl_stat;
232
233 return readl_relaxed_poll_timeout(cdns_xspi->iobase +
234 CDNS_XSPI_CTRL_STATUS_REG,
235 ctrl_stat,
236 ((ctrl_stat &
237 CDNS_XSPI_CTRL_BUSY) == 0),
238 100, 1000);
239}
240
241static void cdns_xspi_trigger_command(struct cdns_xspi_dev *cdns_xspi,
242 u32 cmd_regs[6])
243{
244 writel(cmd_regs[5], cdns_xspi->iobase + CDNS_XSPI_CMD_REG_5);
245 writel(cmd_regs[4], cdns_xspi->iobase + CDNS_XSPI_CMD_REG_4);
246 writel(cmd_regs[3], cdns_xspi->iobase + CDNS_XSPI_CMD_REG_3);
247 writel(cmd_regs[2], cdns_xspi->iobase + CDNS_XSPI_CMD_REG_2);
248 writel(cmd_regs[1], cdns_xspi->iobase + CDNS_XSPI_CMD_REG_1);
249 writel(cmd_regs[0], cdns_xspi->iobase + CDNS_XSPI_CMD_REG_0);
250}
251
252static int cdns_xspi_check_command_status(struct cdns_xspi_dev *cdns_xspi)
253{
254 int ret = 0;
255 u32 cmd_status = readl(cdns_xspi->iobase + CDNS_XSPI_CMD_STATUS_REG);
256
257 if (cmd_status & CDNS_XSPI_CMD_STATUS_COMPLETED) {
258 if ((cmd_status & CDNS_XSPI_CMD_STATUS_FAILED) != 0) {
259 if (cmd_status & CDNS_XSPI_CMD_STATUS_DQS_ERROR) {
260 dev_err(cdns_xspi->dev,
261 "Incorrect DQS pulses detected\n");
262 ret = -EPROTO;
263 }
264 if (cmd_status & CDNS_XSPI_CMD_STATUS_CRC_ERROR) {
265 dev_err(cdns_xspi->dev,
266 "CRC error received\n");
267 ret = -EPROTO;
268 }
269 if (cmd_status & CDNS_XSPI_CMD_STATUS_BUS_ERROR) {
270 dev_err(cdns_xspi->dev,
271 "Error resp on system DMA interface\n");
272 ret = -EPROTO;
273 }
274 if (cmd_status & CDNS_XSPI_CMD_STATUS_INV_SEQ_ERROR) {
275 dev_err(cdns_xspi->dev,
276 "Invalid command sequence detected\n");
277 ret = -EPROTO;
278 }
279 }
280 } else {
281 dev_err(cdns_xspi->dev, "Fatal err - command not completed\n");
282 ret = -EPROTO;
283 }
284
285 return ret;
286}
287
288static void cdns_xspi_set_interrupts(struct cdns_xspi_dev *cdns_xspi,
289 bool enabled)
290{
291 u32 intr_enable;
292
293 intr_enable = readl(cdns_xspi->iobase + CDNS_XSPI_INTR_ENABLE_REG);
294 if (enabled)
295 intr_enable |= CDNS_XSPI_INTR_MASK;
296 else
297 intr_enable &= ~CDNS_XSPI_INTR_MASK;
298 writel(intr_enable, cdns_xspi->iobase + CDNS_XSPI_INTR_ENABLE_REG);
299}
300
301static int cdns_xspi_controller_init(struct cdns_xspi_dev *cdns_xspi)
302{
303 u32 ctrl_ver;
304 u32 ctrl_features;
305 u16 hw_magic_num;
306
307 ctrl_ver = readl(cdns_xspi->iobase + CDNS_XSPI_CTRL_VERSION_REG);
308 hw_magic_num = FIELD_GET(CDNS_XSPI_MAGIC_NUM, ctrl_ver);
309 if (hw_magic_num != CDNS_XSPI_MAGIC_NUM_VALUE) {
310 dev_err(cdns_xspi->dev,
311 "Incorrect XSPI magic number: %x, expected: %x\n",
312 hw_magic_num, CDNS_XSPI_MAGIC_NUM_VALUE);
313 return -EIO;
314 }
315
316 ctrl_features = readl(cdns_xspi->iobase + CDNS_XSPI_CTRL_FEATURES_REG);
317 cdns_xspi->hw_num_banks = FIELD_GET(CDNS_XSPI_NUM_BANKS, ctrl_features);
318 cdns_xspi_set_interrupts(cdns_xspi, false);
319
320 return 0;
321}
322
323static void cdns_xspi_sdma_handle(struct cdns_xspi_dev *cdns_xspi)
324{
325 u32 sdma_size, sdma_trd_info;
326 u8 sdma_dir;
327
328 sdma_size = readl(cdns_xspi->iobase + CDNS_XSPI_SDMA_SIZE_REG);
329 sdma_trd_info = readl(cdns_xspi->iobase + CDNS_XSPI_SDMA_TRD_INFO_REG);
330 sdma_dir = FIELD_GET(CDNS_XSPI_SDMA_DIR, sdma_trd_info);
331
332 switch (sdma_dir) {
333 case CDNS_XSPI_SDMA_DIR_READ:
334 ioread8_rep(cdns_xspi->sdmabase,
335 cdns_xspi->in_buffer, sdma_size);
336 break;
337
338 case CDNS_XSPI_SDMA_DIR_WRITE:
339 iowrite8_rep(cdns_xspi->sdmabase,
340 cdns_xspi->out_buffer, sdma_size);
341 break;
342 }
343}
344
345static int cdns_xspi_send_stig_command(struct cdns_xspi_dev *cdns_xspi,
346 const struct spi_mem_op *op,
347 bool data_phase)
348{
349 u32 cmd_regs[6];
350 u32 cmd_status;
351 int ret;
352
353 ret = cdns_xspi_wait_for_controller_idle(cdns_xspi);
354 if (ret < 0)
355 return -EIO;
356
357 writel(FIELD_PREP(CDNS_XSPI_CTRL_WORK_MODE, CDNS_XSPI_WORK_MODE_STIG),
358 cdns_xspi->iobase + CDNS_XSPI_CTRL_CONFIG_REG);
359
360 cdns_xspi_set_interrupts(cdns_xspi, true);
361 cdns_xspi->sdma_error = false;
362
363 memset(cmd_regs, 0, sizeof(cmd_regs));
364 cmd_regs[1] = CDNS_XSPI_CMD_FLD_P1_INSTR_CMD_1(op, data_phase);
365 cmd_regs[2] = CDNS_XSPI_CMD_FLD_P1_INSTR_CMD_2(op);
366 cmd_regs[3] = CDNS_XSPI_CMD_FLD_P1_INSTR_CMD_3(op);
367 cmd_regs[4] = CDNS_XSPI_CMD_FLD_P1_INSTR_CMD_4(op,
368 cdns_xspi->cur_cs);
369
370 cdns_xspi_trigger_command(cdns_xspi, cmd_regs);
371
372 if (data_phase) {
373 cmd_regs[0] = CDNS_XSPI_STIG_DONE_FLAG;
374 cmd_regs[1] = CDNS_XSPI_CMD_FLD_DSEQ_CMD_1(op);
375 cmd_regs[2] = CDNS_XSPI_CMD_FLD_DSEQ_CMD_2(op);
376 cmd_regs[3] = CDNS_XSPI_CMD_FLD_DSEQ_CMD_3(op);
377 cmd_regs[4] = CDNS_XSPI_CMD_FLD_DSEQ_CMD_4(op,
378 cdns_xspi->cur_cs);
379
380 cdns_xspi->in_buffer = op->data.buf.in;
381 cdns_xspi->out_buffer = op->data.buf.out;
382
383 cdns_xspi_trigger_command(cdns_xspi, cmd_regs);
384
385 wait_for_completion(&cdns_xspi->sdma_complete);
386 if (cdns_xspi->sdma_error) {
387 cdns_xspi_set_interrupts(cdns_xspi, false);
388 return -EIO;
389 }
390 cdns_xspi_sdma_handle(cdns_xspi);
391 }
392
393 wait_for_completion(&cdns_xspi->cmd_complete);
394 cdns_xspi_set_interrupts(cdns_xspi, false);
395
396 cmd_status = cdns_xspi_check_command_status(cdns_xspi);
397 if (cmd_status)
398 return -EPROTO;
399
400 return 0;
401}
402
403static int cdns_xspi_mem_op(struct cdns_xspi_dev *cdns_xspi,
404 struct spi_mem *mem,
405 const struct spi_mem_op *op)
406{
407 enum spi_mem_data_dir dir = op->data.dir;
408
409 if (cdns_xspi->cur_cs != mem->spi->chip_select)
410 cdns_xspi->cur_cs = mem->spi->chip_select;
411
412 return cdns_xspi_send_stig_command(cdns_xspi, op,
413 (dir != SPI_MEM_NO_DATA));
414}
415
416static int cdns_xspi_mem_op_execute(struct spi_mem *mem,
417 const struct spi_mem_op *op)
418{
419 struct cdns_xspi_dev *cdns_xspi =
420 spi_master_get_devdata(mem->spi->master);
421 int ret = 0;
422
423 ret = cdns_xspi_mem_op(cdns_xspi, mem, op);
424
425 return ret;
426}
427
428static int cdns_xspi_adjust_mem_op_size(struct spi_mem *mem, struct spi_mem_op *op)
429{
430 struct cdns_xspi_dev *cdns_xspi =
431 spi_master_get_devdata(mem->spi->master);
432
433 op->data.nbytes = clamp_val(op->data.nbytes, 0, cdns_xspi->sdmasize);
434
435 return 0;
436}
437
438static const struct spi_controller_mem_ops cadence_xspi_mem_ops = {
439 .exec_op = cdns_xspi_mem_op_execute,
440 .adjust_op_size = cdns_xspi_adjust_mem_op_size,
441};
442
443static irqreturn_t cdns_xspi_irq_handler(int this_irq, void *dev)
444{
445 struct cdns_xspi_dev *cdns_xspi = dev;
446 u32 irq_status;
447 irqreturn_t result = IRQ_NONE;
448
449 irq_status = readl(cdns_xspi->iobase + CDNS_XSPI_INTR_STATUS_REG);
450 writel(irq_status, cdns_xspi->iobase + CDNS_XSPI_INTR_STATUS_REG);
451
452 if (irq_status &
453 (CDNS_XSPI_SDMA_ERROR | CDNS_XSPI_SDMA_TRIGGER |
454 CDNS_XSPI_STIG_DONE)) {
455 if (irq_status & CDNS_XSPI_SDMA_ERROR) {
456 dev_err(cdns_xspi->dev,
457 "Slave DMA transaction error\n");
458 cdns_xspi->sdma_error = true;
459 complete(&cdns_xspi->sdma_complete);
460 }
461
462 if (irq_status & CDNS_XSPI_SDMA_TRIGGER)
463 complete(&cdns_xspi->sdma_complete);
464
465 if (irq_status & CDNS_XSPI_STIG_DONE)
466 complete(&cdns_xspi->cmd_complete);
467
468 result = IRQ_HANDLED;
469 }
470
471 irq_status = readl(cdns_xspi->iobase + CDNS_XSPI_TRD_COMP_INTR_STATUS);
472 if (irq_status) {
473 writel(irq_status,
474 cdns_xspi->iobase + CDNS_XSPI_TRD_COMP_INTR_STATUS);
475
476 complete(&cdns_xspi->auto_cmd_complete);
477
478 result = IRQ_HANDLED;
479 }
480
481 return result;
482}
483
484static int cdns_xspi_of_get_plat_data(struct platform_device *pdev)
485{
486 struct device_node *node_prop = pdev->dev.of_node;
487 struct device_node *node_child;
488 unsigned int cs;
489
490 for_each_child_of_node(node_prop, node_child) {
491 if (!of_device_is_available(node_child))
492 continue;
493
494 if (of_property_read_u32(node_child, "reg", &cs)) {
495 dev_err(&pdev->dev, "Couldn't get memory chip select\n");
496 of_node_put(node_child);
497 return -ENXIO;
498 } else if (cs >= CDNS_XSPI_MAX_BANKS) {
499 dev_err(&pdev->dev, "reg (cs) parameter value too large\n");
500 of_node_put(node_child);
501 return -ENXIO;
502 }
503 }
504
505 return 0;
506}
507
508static void cdns_xspi_print_phy_config(struct cdns_xspi_dev *cdns_xspi)
509{
510 struct device *dev = cdns_xspi->dev;
511
512 dev_info(dev, "PHY configuration\n");
513 dev_info(dev, " * xspi_dll_phy_ctrl: %08x\n",
514 readl(cdns_xspi->iobase + CDNS_XSPI_DLL_PHY_CTRL));
515 dev_info(dev, " * phy_dq_timing: %08x\n",
516 readl(cdns_xspi->auxbase + CDNS_XSPI_CCP_PHY_DQ_TIMING));
517 dev_info(dev, " * phy_dqs_timing: %08x\n",
518 readl(cdns_xspi->auxbase + CDNS_XSPI_CCP_PHY_DQS_TIMING));
519 dev_info(dev, " * phy_gate_loopback_ctrl: %08x\n",
520 readl(cdns_xspi->auxbase + CDNS_XSPI_CCP_PHY_GATE_LPBCK_CTRL));
521 dev_info(dev, " * phy_dll_slave_ctrl: %08x\n",
522 readl(cdns_xspi->auxbase + CDNS_XSPI_CCP_PHY_DLL_SLAVE_CTRL));
523}
524
525static int cdns_xspi_probe(struct platform_device *pdev)
526{
527 struct device *dev = &pdev->dev;
528 struct spi_master *master = NULL;
529 struct cdns_xspi_dev *cdns_xspi = NULL;
530 struct resource *res;
531 int ret;
532
533 master = devm_spi_alloc_master(dev, sizeof(*cdns_xspi));
534 if (!master)
535 return -ENOMEM;
536
537 master->mode_bits = SPI_3WIRE | SPI_TX_DUAL | SPI_TX_QUAD |
538 SPI_RX_DUAL | SPI_RX_QUAD | SPI_TX_OCTAL | SPI_RX_OCTAL |
539 SPI_MODE_0 | SPI_MODE_3;
540
541 master->mem_ops = &cadence_xspi_mem_ops;
542 master->dev.of_node = pdev->dev.of_node;
543 master->bus_num = -1;
544
545 platform_set_drvdata(pdev, master);
546
547 cdns_xspi = spi_master_get_devdata(master);
548 cdns_xspi->pdev = pdev;
549 cdns_xspi->dev = &pdev->dev;
550 cdns_xspi->cur_cs = 0;
551
552 init_completion(&cdns_xspi->cmd_complete);
553 init_completion(&cdns_xspi->auto_cmd_complete);
554 init_completion(&cdns_xspi->sdma_complete);
555
556 ret = cdns_xspi_of_get_plat_data(pdev);
557 if (ret)
558 return -ENODEV;
559
560 cdns_xspi->iobase = devm_platform_ioremap_resource_byname(pdev, "io");
561 if (IS_ERR(cdns_xspi->iobase)) {
562 dev_err(dev, "Failed to remap controller base address\n");
563 return PTR_ERR(cdns_xspi->iobase);
564 }
565
566 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sdma");
567 cdns_xspi->sdmabase = devm_ioremap_resource(dev, res);
568 if (IS_ERR(cdns_xspi->sdmabase)) {
569 dev_err(dev, "Failed to remap SDMA address\n");
570 return PTR_ERR(cdns_xspi->sdmabase);
571 }
572 cdns_xspi->sdmasize = resource_size(res);
573
574 cdns_xspi->auxbase = devm_platform_ioremap_resource_byname(pdev, "aux");
575 if (IS_ERR(cdns_xspi->auxbase)) {
576 dev_err(dev, "Failed to remap AUX address\n");
577 return PTR_ERR(cdns_xspi->auxbase);
578 }
579
580 cdns_xspi->irq = platform_get_irq(pdev, 0);
581 if (cdns_xspi->irq < 0)
582 return -ENXIO;
583
584 ret = devm_request_irq(dev, cdns_xspi->irq, cdns_xspi_irq_handler,
585 IRQF_SHARED, pdev->name, cdns_xspi);
586 if (ret) {
587 dev_err(dev, "Failed to request IRQ: %d\n", cdns_xspi->irq);
588 return ret;
589 }
590
591 cdns_xspi_print_phy_config(cdns_xspi);
592
593 ret = cdns_xspi_controller_init(cdns_xspi);
594 if (ret) {
595 dev_err(dev, "Failed to initialize controller\n");
596 return ret;
597 }
598
599 master->num_chipselect = 1 << cdns_xspi->hw_num_banks;
600
601 ret = devm_spi_register_master(dev, master);
602 if (ret) {
603 dev_err(dev, "Failed to register SPI master\n");
604 return ret;
605 }
606
607 dev_info(dev, "Successfully registered SPI master\n");
608
609 return 0;
610}
611
612#ifdef CONFIG_OF
613static const struct of_device_id cdns_xspi_of_match[] = {
614 {
615 .compatible = "cdns,xspi-nor",
616 },
617 { }
618};
619MODULE_DEVICE_TABLE(of, cdns_xspi_of_match);
620#else
621#define cdns_xspi_of_match NULL
622#endif
623
624static struct platform_driver cdns_xspi_platform_driver = {
625 .probe = cdns_xspi_probe,
626 .remove = NULL,
627 .driver = {
628 .name = CDNS_XSPI_NAME,
629 .of_match_table = cdns_xspi_of_match,
630 },
631};
632
633module_platform_driver(cdns_xspi_platform_driver);
634
635MODULE_DESCRIPTION("Cadence XSPI Controller Driver");
636MODULE_LICENSE("GPL v2");
637MODULE_ALIAS("platform:" CDNS_XSPI_NAME);
638MODULE_AUTHOR("Konrad Kociolek <konrad@cadence.com>");
639MODULE_AUTHOR("Jayshri Pawar <jpawar@cadence.com>");
640MODULE_AUTHOR("Parshuram Thombare <pthombar@cadence.com>");
641
