LXR linux/drivers/tty/serial/pmac

   1/* SPDX-License-Identifier: GPL-2.0 */
   2#ifndef __PMAC_ZILOG_H__
   3#define __PMAC_ZILOG_H__
   4
   5/*
   6 * At most 2 ESCCs with 2 ports each
   7 */
   8#define MAX_ZS_PORTS    4
   9
  10/* 
  11 * We wrap our port structure around the generic uart_port.
  12 */
  13#define NUM_ZSREGS    17
  14
  15struct uart_pmac_port {
  16        struct uart_port                port;
  17        struct uart_pmac_port           *mate;
  18
  19#ifdef CONFIG_PPC_PMAC
  20        /* macio_dev for the escc holding this port (maybe be null on
  21         * early inited port)
  22         */
  23        struct macio_dev                *dev;
  24        /* device node to this port, this points to one of 2 childs
  25         * of "escc" node (ie. ch-a or ch-b)
  26         */
  27        struct device_node              *node;
  28#else
  29        struct platform_device          *pdev;
  30#endif
  31
  32        /* Port type as obtained from device tree (IRDA, modem, ...) */
  33        int                             port_type;
  34        u8                              curregs[NUM_ZSREGS];
  35
  36        unsigned int                    flags;
  37#define PMACZILOG_FLAG_IS_CONS          0x00000001
  38#define PMACZILOG_FLAG_IS_KGDB          0x00000002
  39#define PMACZILOG_FLAG_MODEM_STATUS     0x00000004
  40#define PMACZILOG_FLAG_IS_CHANNEL_A     0x00000008
  41#define PMACZILOG_FLAG_REGS_HELD        0x00000010
  42#define PMACZILOG_FLAG_TX_STOPPED       0x00000020
  43#define PMACZILOG_FLAG_TX_ACTIVE        0x00000040
  44#define PMACZILOG_FLAG_IS_IRDA          0x00000100
  45#define PMACZILOG_FLAG_IS_INTMODEM      0x00000200
  46#define PMACZILOG_FLAG_RSRC_REQUESTED   0x00000800
  47#define PMACZILOG_FLAG_IS_OPEN          0x00002000
  48#define PMACZILOG_FLAG_IS_EXTCLK        0x00008000
  49#define PMACZILOG_FLAG_BREAK            0x00010000
  50
  51        unsigned char                   parity_mask;
  52        unsigned char                   prev_status;
  53
  54        volatile u8                     __iomem *control_reg;
  55        volatile u8                     __iomem *data_reg;
  56
  57        unsigned char                   irq_name[8];
  58};
  59
  60#define to_pmz(p) ((struct uart_pmac_port *)(p))
  61
  62static inline struct uart_pmac_port *pmz_get_port_A(struct uart_pmac_port *uap)
  63{
  64        if (uap->flags & PMACZILOG_FLAG_IS_CHANNEL_A)
  65                return uap;
  66        return uap->mate;
  67}
  68
  69/*
  70 * Register accessors. Note that we don't need to enforce a recovery
  71 * delay on PCI PowerMac hardware, it's dealt in HW by the MacIO chip,
  72 * though if we try to use this driver on older machines, we might have
  73 * to add it back
  74 */
  75static inline u8 read_zsreg(struct uart_pmac_port *port, u8 reg)
  76{
  77        if (reg != 0)
  78                writeb(reg, port->control_reg);
  79        return readb(port->control_reg);
  80}
  81
  82static inline void write_zsreg(struct uart_pmac_port *port, u8 reg, u8 value)
  83{
  84        if (reg != 0)
  85                writeb(reg, port->control_reg);
  86        writeb(value, port->control_reg);
  87}
  88
  89static inline u8 read_zsdata(struct uart_pmac_port *port)
  90{
  91        return readb(port->data_reg);
  92}
  93
  94static inline void write_zsdata(struct uart_pmac_port *port, u8 data)
  95{
  96        writeb(data, port->data_reg);
  97}
  98
  99static inline void zssync(struct uart_pmac_port *port)
 100{
 101        (void)readb(port->control_reg);
 102}
 103
 104/* Conversion routines to/from brg time constants from/to bits
 105 * per second.
 106 */
 107#define BRG_TO_BPS(brg, freq) ((freq) / 2 / ((brg) + 2))
 108#define BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2)
 109
 110#define ZS_CLOCK         3686400        /* Z8530 RTxC input clock rate */
 111
 112/* The Zilog register set */
 113
 114#define FLAG    0x7e
 115
 116/* Write Register 0 */
 117#define R0      0               /* Register selects */
 118#define R1      1
 119#define R2      2
 120#define R3      3
 121#define R4      4
 122#define R5      5
 123#define R6      6
 124#define R7      7
 125#define R8      8
 126#define R9      9
 127#define R10     10
 128#define R11     11
 129#define R12     12
 130#define R13     13
 131#define R14     14
 132#define R15     15
 133#define R7P     16
 134
 135#define NULLCODE        0       /* Null Code */
 136#define POINT_HIGH      0x8     /* Select upper half of registers */
 137#define RES_EXT_INT     0x10    /* Reset Ext. Status Interrupts */
 138#define SEND_ABORT      0x18    /* HDLC Abort */
 139#define RES_RxINT_FC    0x20    /* Reset RxINT on First Character */
 140#define RES_Tx_P        0x28    /* Reset TxINT Pending */
 141#define ERR_RES         0x30    /* Error Reset */
 142#define RES_H_IUS       0x38    /* Reset highest IUS */
 143
 144#define RES_Rx_CRC      0x40    /* Reset Rx CRC Checker */
 145#define RES_Tx_CRC      0x80    /* Reset Tx CRC Checker */
 146#define RES_EOM_L       0xC0    /* Reset EOM latch */
 147
 148/* Write Register 1 */
 149
 150#define EXT_INT_ENAB    0x1     /* Ext Int Enable */
 151#define TxINT_ENAB      0x2     /* Tx Int Enable */
 152#define PAR_SPEC        0x4     /* Parity is special condition */
 153
 154#define RxINT_DISAB     0       /* Rx Int Disable */
 155#define RxINT_FCERR     0x8     /* Rx Int on First Character Only or Error */
 156#define INT_ALL_Rx      0x10    /* Int on all Rx Characters or error */
 157#define INT_ERR_Rx      0x18    /* Int on error only */
 158#define RxINT_MASK      0x18
 159
 160#define WT_RDY_RT       0x20    /* W/Req reflects recv if 1, xmit if 0 */
 161#define WT_FN_RDYFN     0x40    /* W/Req pin is DMA request if 1, wait if 0 */
 162#define WT_RDY_ENAB     0x80    /* Enable W/Req pin */
 163
 164/* Write Register #2 (Interrupt Vector) */
 165
 166/* Write Register 3 */
 167
 168#define RxENABLE        0x1     /* Rx Enable */
 169#define SYNC_L_INH      0x2     /* Sync Character Load Inhibit */
 170#define ADD_SM          0x4     /* Address Search Mode (SDLC) */
 171#define RxCRC_ENAB      0x8     /* Rx CRC Enable */
 172#define ENT_HM          0x10    /* Enter Hunt Mode */
 173#define AUTO_ENAB       0x20    /* Auto Enables */
 174#define Rx5             0x0     /* Rx 5 Bits/Character */
 175#define Rx7             0x40    /* Rx 7 Bits/Character */
 176#define Rx6             0x80    /* Rx 6 Bits/Character */
 177#define Rx8             0xc0    /* Rx 8 Bits/Character */
 178#define RxN_MASK        0xc0
 179
 180/* Write Register 4 */
 181
 182#define PAR_ENAB        0x1     /* Parity Enable */
 183#define PAR_EVEN        0x2     /* Parity Even/Odd* */
 184
 185#define SYNC_ENAB       0       /* Sync Modes Enable */
 186#define SB1             0x4     /* 1 stop bit/char */
 187#define SB15            0x8     /* 1.5 stop bits/char */
 188#define SB2             0xc     /* 2 stop bits/char */
 189#define SB_MASK         0xc
 190
 191#define MONSYNC         0       /* 8 Bit Sync character */
 192#define BISYNC          0x10    /* 16 bit sync character */
 193#define SDLC            0x20    /* SDLC Mode (01111110 Sync Flag) */
 194#define EXTSYNC         0x30    /* External Sync Mode */
 195
 196#define X1CLK           0x0     /* x1 clock mode */
 197#define X16CLK          0x40    /* x16 clock mode */
 198#define X32CLK          0x80    /* x32 clock mode */
 199#define X64CLK          0xC0    /* x64 clock mode */
 200#define XCLK_MASK       0xC0
 201
 202/* Write Register 5 */
 203
 204#define TxCRC_ENAB      0x1     /* Tx CRC Enable */
 205#define RTS             0x2     /* RTS */
 206#define SDLC_CRC        0x4     /* SDLC/CRC-16 */
 207#define TxENABLE        0x8     /* Tx Enable */
 208#define SND_BRK         0x10    /* Send Break */
 209#define Tx5             0x0     /* Tx 5 bits (or less)/character */
 210#define Tx7             0x20    /* Tx 7 bits/character */
 211#define Tx6             0x40    /* Tx 6 bits/character */
 212#define Tx8             0x60    /* Tx 8 bits/character */
 213#define TxN_MASK        0x60
 214#define DTR             0x80    /* DTR */
 215
 216/* Write Register 6 (Sync bits 0-7/SDLC Address Field) */
 217
 218/* Write Register 7 (Sync bits 8-15/SDLC 01111110) */
 219
 220/* Write Register 7' (Some enhanced feature control) */
 221#define ENEXREAD        0x40    /* Enable read of some write registers */
 222
 223/* Write Register 8 (transmit buffer) */
 224
 225/* Write Register 9 (Master interrupt control) */
 226#define VIS     1       /* Vector Includes Status */
 227#define NV      2       /* No Vector */
 228#define DLC     4       /* Disable Lower Chain */
 229#define MIE     8       /* Master Interrupt Enable */
 230#define STATHI  0x10    /* Status high */
 231#define NORESET 0       /* No reset on write to R9 */
 232#define CHRB    0x40    /* Reset channel B */
 233#define CHRA    0x80    /* Reset channel A */
 234#define FHWRES  0xc0    /* Force hardware reset */
 235
 236/* Write Register 10 (misc control bits) */
 237#define BIT6    1       /* 6 bit/8bit sync */
 238#define LOOPMODE 2      /* SDLC Loop mode */
 239#define ABUNDER 4       /* Abort/flag on SDLC xmit underrun */
 240#define MARKIDLE 8      /* Mark/flag on idle */
 241#define GAOP    0x10    /* Go active on poll */
 242#define NRZ     0       /* NRZ mode */
 243#define NRZI    0x20    /* NRZI mode */
 244#define FM1     0x40    /* FM1 (transition = 1) */
 245#define FM0     0x60    /* FM0 (transition = 0) */
 246#define CRCPS   0x80    /* CRC Preset I/O */
 247
 248/* Write Register 11 (Clock Mode control) */
 249#define TRxCXT  0       /* TRxC = Xtal output */
 250#define TRxCTC  1       /* TRxC = Transmit clock */
 251#define TRxCBR  2       /* TRxC = BR Generator Output */
 252#define TRxCDP  3       /* TRxC = DPLL output */
 253#define TRxCOI  4       /* TRxC O/I */
 254#define TCRTxCP 0       /* Transmit clock = RTxC pin */
 255#define TCTRxCP 8       /* Transmit clock = TRxC pin */
 256#define TCBR    0x10    /* Transmit clock = BR Generator output */
 257#define TCDPLL  0x18    /* Transmit clock = DPLL output */
 258#define RCRTxCP 0       /* Receive clock = RTxC pin */
 259#define RCTRxCP 0x20    /* Receive clock = TRxC pin */
 260#define RCBR    0x40    /* Receive clock = BR Generator output */
 261#define RCDPLL  0x60    /* Receive clock = DPLL output */
 262#define RTxCX   0x80    /* RTxC Xtal/No Xtal */
 263
 264/* Write Register 12 (lower byte of baud rate generator time constant) */
 265
 266/* Write Register 13 (upper byte of baud rate generator time constant) */
 267
 268/* Write Register 14 (Misc control bits) */
 269#define BRENAB  1       /* Baud rate generator enable */
 270#define BRSRC   2       /* Baud rate generator source */
 271#define DTRREQ  4       /* DTR/Request function */
 272#define AUTOECHO 8      /* Auto Echo */
 273#define LOOPBAK 0x10    /* Local loopback */
 274#define SEARCH  0x20    /* Enter search mode */
 275#define RMC     0x40    /* Reset missing clock */
 276#define DISDPLL 0x60    /* Disable DPLL */
 277#define SSBR    0x80    /* Set DPLL source = BR generator */
 278#define SSRTxC  0xa0    /* Set DPLL source = RTxC */
 279#define SFMM    0xc0    /* Set FM mode */
 280#define SNRZI   0xe0    /* Set NRZI mode */
 281
 282/* Write Register 15 (external/status interrupt control) */
 283#define EN85C30 1       /* Enable some 85c30-enhanced registers */
 284#define ZCIE    2       /* Zero count IE */
 285#define ENSTFIFO 4      /* Enable status FIFO (SDLC) */
 286#define DCDIE   8       /* DCD IE */
 287#define SYNCIE  0x10    /* Sync/hunt IE */
 288#define CTSIE   0x20    /* CTS IE */
 289#define TxUIE   0x40    /* Tx Underrun/EOM IE */
 290#define BRKIE   0x80    /* Break/Abort IE */
 291
 292
 293/* Read Register 0 */
 294#define Rx_CH_AV        0x1     /* Rx Character Available */
 295#define ZCOUNT          0x2     /* Zero count */
 296#define Tx_BUF_EMP      0x4     /* Tx Buffer empty */
 297#define DCD             0x8     /* DCD */
 298#define SYNC_HUNT       0x10    /* Sync/hunt */
 299#define CTS             0x20    /* CTS */
 300#define TxEOM           0x40    /* Tx underrun */
 301#define BRK_ABRT        0x80    /* Break/Abort */
 302
 303/* Read Register 1 */
 304#define ALL_SNT         0x1     /* All sent */
 305/* Residue Data for 8 Rx bits/char programmed */
 306#define RES3            0x8     /* 0/3 */
 307#define RES4            0x4     /* 0/4 */
 308#define RES5            0xc     /* 0/5 */
 309#define RES6            0x2     /* 0/6 */
 310#define RES7            0xa     /* 0/7 */
 311#define RES8            0x6     /* 0/8 */
 312#define RES18           0xe     /* 1/8 */
 313#define RES28           0x0     /* 2/8 */
 314/* Special Rx Condition Interrupts */
 315#define PAR_ERR         0x10    /* Parity error */
 316#define Rx_OVR          0x20    /* Rx Overrun Error */
 317#define CRC_ERR         0x40    /* CRC/Framing Error */
 318#define END_FR          0x80    /* End of Frame (SDLC) */
 319
 320/* Read Register 2 (channel b only) - Interrupt vector */
 321#define CHB_Tx_EMPTY    0x00
 322#define CHB_EXT_STAT    0x02
 323#define CHB_Rx_AVAIL    0x04
 324#define CHB_SPECIAL     0x06
 325#define CHA_Tx_EMPTY    0x08
 326#define CHA_EXT_STAT    0x0a
 327#define CHA_Rx_AVAIL    0x0c
 328#define CHA_SPECIAL     0x0e
 329#define STATUS_MASK     0x06
 330
 331/* Read Register 3 (interrupt pending register) ch a only */
 332#define CHBEXT  0x1             /* Channel B Ext/Stat IP */
 333#define CHBTxIP 0x2             /* Channel B Tx IP */
 334#define CHBRxIP 0x4             /* Channel B Rx IP */
 335#define CHAEXT  0x8             /* Channel A Ext/Stat IP */
 336#define CHATxIP 0x10            /* Channel A Tx IP */
 337#define CHARxIP 0x20            /* Channel A Rx IP */
 338
 339/* Read Register 8 (receive data register) */
 340
 341/* Read Register 10  (misc status bits) */
 342#define ONLOOP  2               /* On loop */
 343#define LOOPSEND 0x10           /* Loop sending */
 344#define CLK2MIS 0x40            /* Two clocks missing */
 345#define CLK1MIS 0x80            /* One clock missing */
 346
 347/* Read Register 12 (lower byte of baud rate generator constant) */
 348
 349/* Read Register 13 (upper byte of baud rate generator constant) */
 350
 351/* Read Register 15 (value of WR 15) */
 352
 353/* Misc macros */
 354#define ZS_CLEARERR(port)    (write_zsreg(port, 0, ERR_RES))
 355#define ZS_CLEARFIFO(port)   do {                       \
 356                                     read_zsdata(port); \
 357                                     read_zsdata(port); \
 358                                     read_zsdata(port); \
 359                                } while(0)
 360
 361#define ZS_IS_CONS(UP)                  ((UP)->flags & PMACZILOG_FLAG_IS_CONS)
 362#define ZS_IS_KGDB(UP)                  ((UP)->flags & PMACZILOG_FLAG_IS_KGDB)
 363#define ZS_IS_CHANNEL_A(UP)             ((UP)->flags & PMACZILOG_FLAG_IS_CHANNEL_A)
 364#define ZS_REGS_HELD(UP)                ((UP)->flags & PMACZILOG_FLAG_REGS_HELD)
 365#define ZS_TX_STOPPED(UP)               ((UP)->flags & PMACZILOG_FLAG_TX_STOPPED)
 366#define ZS_TX_ACTIVE(UP)                ((UP)->flags & PMACZILOG_FLAG_TX_ACTIVE)
 367#define ZS_WANTS_MODEM_STATUS(UP)       ((UP)->flags & PMACZILOG_FLAG_MODEM_STATUS)
 368#define ZS_IS_IRDA(UP)                  ((UP)->flags & PMACZILOG_FLAG_IS_IRDA)
 369#define ZS_IS_INTMODEM(UP)              ((UP)->flags & PMACZILOG_FLAG_IS_INTMODEM)
 370#define ZS_IS_OPEN(UP)                  ((UP)->flags & PMACZILOG_FLAG_IS_OPEN)
 371#define ZS_IS_EXTCLK(UP)                ((UP)->flags & PMACZILOG_FLAG_IS_EXTCLK)
 372
 373#endif /* __PMAC_ZILOG_H__ */
 374