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13#ifndef __CROS_EC_COMMANDS_H
14#define __CROS_EC_COMMANDS_H
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18
19#define BUILD_ASSERT(_cond)
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27
28#define EC_PROTO_VERSION 0x00000002
29
30
31#define EC_VER_MASK(version) BIT(version)
32
33
34#define EC_LPC_ADDR_ACPI_DATA 0x62
35#define EC_LPC_ADDR_ACPI_CMD 0x66
36
37
38#define EC_LPC_ADDR_HOST_DATA 0x200
39#define EC_LPC_ADDR_HOST_CMD 0x204
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41
42
43#define EC_LPC_ADDR_HOST_ARGS 0x800
44#define EC_LPC_ADDR_HOST_PARAM 0x804
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46
47
48#define EC_LPC_ADDR_HOST_PACKET 0x800
49#define EC_LPC_HOST_PACKET_SIZE 0x100
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57
58#define EC_HOST_CMD_REGION0 0x800
59#define EC_HOST_CMD_REGION1 0x880
60#define EC_HOST_CMD_REGION_SIZE 0x80
61#define EC_HOST_CMD_MEC_REGION_SIZE 0x8
62
63
64#define EC_LPC_CMDR_DATA BIT(0)
65#define EC_LPC_CMDR_PENDING BIT(1)
66#define EC_LPC_CMDR_BUSY BIT(2)
67#define EC_LPC_CMDR_CMD BIT(3)
68#define EC_LPC_CMDR_ACPI_BRST BIT(4)
69#define EC_LPC_CMDR_SCI BIT(5)
70#define EC_LPC_CMDR_SMI BIT(6)
71
72#define EC_LPC_ADDR_MEMMAP 0x900
73#define EC_MEMMAP_SIZE 255
74#define EC_MEMMAP_TEXT_MAX 8
75
76
77#define EC_MEMMAP_TEMP_SENSOR 0x00
78#define EC_MEMMAP_FAN 0x10
79#define EC_MEMMAP_TEMP_SENSOR_B 0x18
80#define EC_MEMMAP_ID 0x20
81#define EC_MEMMAP_ID_VERSION 0x22
82#define EC_MEMMAP_THERMAL_VERSION 0x23
83#define EC_MEMMAP_BATTERY_VERSION 0x24
84#define EC_MEMMAP_SWITCHES_VERSION 0x25
85#define EC_MEMMAP_EVENTS_VERSION 0x26
86#define EC_MEMMAP_HOST_CMD_FLAGS 0x27
87
88#define EC_MEMMAP_SWITCHES 0x30
89
90#define EC_MEMMAP_HOST_EVENTS 0x34
91
92#define EC_MEMMAP_BATT_VOLT 0x40
93#define EC_MEMMAP_BATT_RATE 0x44
94#define EC_MEMMAP_BATT_CAP 0x48
95#define EC_MEMMAP_BATT_FLAG 0x4c
96#define EC_MEMMAP_BATT_COUNT 0x4d
97#define EC_MEMMAP_BATT_INDEX 0x4e
98
99#define EC_MEMMAP_BATT_DCAP 0x50
100#define EC_MEMMAP_BATT_DVLT 0x54
101#define EC_MEMMAP_BATT_LFCC 0x58
102#define EC_MEMMAP_BATT_CCNT 0x5c
103
104#define EC_MEMMAP_BATT_MFGR 0x60
105#define EC_MEMMAP_BATT_MODEL 0x68
106#define EC_MEMMAP_BATT_SERIAL 0x70
107#define EC_MEMMAP_BATT_TYPE 0x78
108#define EC_MEMMAP_ALS 0x80
109
110#define EC_MEMMAP_ACC_STATUS 0x90
111
112#define EC_MEMMAP_ACC_DATA 0x92
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114
115
116#define EC_MEMMAP_GYRO_DATA 0xa0
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123
124#define EC_MEMMAP_NO_ACPI 0xe0
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126
127#define EC_MEMMAP_ACC_STATUS_SAMPLE_ID_MASK 0x0f
128#define EC_MEMMAP_ACC_STATUS_BUSY_BIT BIT(4)
129#define EC_MEMMAP_ACC_STATUS_PRESENCE_BIT BIT(7)
130
131
132#define EC_TEMP_SENSOR_ENTRIES 16
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137
138#define EC_TEMP_SENSOR_B_ENTRIES 8
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140
141#define EC_TEMP_SENSOR_NOT_PRESENT 0xff
142#define EC_TEMP_SENSOR_ERROR 0xfe
143#define EC_TEMP_SENSOR_NOT_POWERED 0xfd
144#define EC_TEMP_SENSOR_NOT_CALIBRATED 0xfc
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149#define EC_TEMP_SENSOR_OFFSET 200
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154#define EC_ALS_ENTRIES 2
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161#define EC_TEMP_SENSOR_DEFAULT (296 - EC_TEMP_SENSOR_OFFSET)
162
163#define EC_FAN_SPEED_ENTRIES 4
164#define EC_FAN_SPEED_NOT_PRESENT 0xffff
165#define EC_FAN_SPEED_STALLED 0xfffe
166
167
168#define EC_BATT_FLAG_AC_PRESENT 0x01
169#define EC_BATT_FLAG_BATT_PRESENT 0x02
170#define EC_BATT_FLAG_DISCHARGING 0x04
171#define EC_BATT_FLAG_CHARGING 0x08
172#define EC_BATT_FLAG_LEVEL_CRITICAL 0x10
173
174#define EC_BATT_FLAG_INVALID_DATA 0x20
175
176
177#define EC_SWITCH_LID_OPEN 0x01
178#define EC_SWITCH_POWER_BUTTON_PRESSED 0x02
179#define EC_SWITCH_WRITE_PROTECT_DISABLED 0x04
180
181#define EC_SWITCH_IGNORE1 0x08
182
183#define EC_SWITCH_DEDICATED_RECOVERY 0x10
184
185#define EC_SWITCH_IGNORE0 0x20
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188
189#define EC_HOST_CMD_FLAG_LPC_ARGS_SUPPORTED 0x01
190
191#define EC_HOST_CMD_FLAG_VERSION_3 0x02
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193
194#define EC_WIRELESS_SWITCH_ALL ~0x00
195#define EC_WIRELESS_SWITCH_WLAN 0x01
196#define EC_WIRELESS_SWITCH_BLUETOOTH 0x02
197#define EC_WIRELESS_SWITCH_WWAN 0x04
198#define EC_WIRELESS_SWITCH_WLAN_POWER 0x08
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220#define EC_CMD_ACPI_READ 0x0080
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235#define EC_CMD_ACPI_WRITE 0x0081
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244#define EC_CMD_ACPI_BURST_ENABLE 0x0082
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252#define EC_CMD_ACPI_BURST_DISABLE 0x0083
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261#define EC_CMD_ACPI_QUERY_EVENT 0x0084
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266#define EC_ACPI_MEM_VERSION 0x00
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271#define EC_ACPI_MEM_TEST 0x01
272
273#define EC_ACPI_MEM_TEST_COMPLIMENT 0x02
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276#define EC_ACPI_MEM_KEYBOARD_BACKLIGHT 0x03
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278#define EC_ACPI_MEM_FAN_DUTY 0x04
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295#define EC_ACPI_MEM_TEMP_ID 0x05
296#define EC_ACPI_MEM_TEMP_THRESHOLD 0x06
297#define EC_ACPI_MEM_TEMP_COMMIT 0x07
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304#define EC_ACPI_MEM_TEMP_COMMIT_SELECT_MASK BIT(0)
305#define EC_ACPI_MEM_TEMP_COMMIT_ENABLE_MASK BIT(1)
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322#define EC_ACPI_MEM_CHARGING_LIMIT 0x08
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325#define EC_ACPI_MEM_CHARGING_LIMIT_STEP_MA 64
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327#define EC_ACPI_MEM_CHARGING_LIMIT_DISABLED 0xff
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339#define EC_ACPI_MEM_DEVICE_ORIENTATION 0x09
340#define EC_ACPI_MEM_TBMD_SHIFT 0
341#define EC_ACPI_MEM_TBMD_MASK 0x1
342#define EC_ACPI_MEM_DDPN_SHIFT 1
343#define EC_ACPI_MEM_DDPN_MASK 0x7
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357#define EC_ACPI_MEM_DEVICE_FEATURES0 0x0a
358#define EC_ACPI_MEM_DEVICE_FEATURES1 0x0b
359#define EC_ACPI_MEM_DEVICE_FEATURES2 0x0c
360#define EC_ACPI_MEM_DEVICE_FEATURES3 0x0d
361#define EC_ACPI_MEM_DEVICE_FEATURES4 0x0e
362#define EC_ACPI_MEM_DEVICE_FEATURES5 0x0f
363#define EC_ACPI_MEM_DEVICE_FEATURES6 0x10
364#define EC_ACPI_MEM_DEVICE_FEATURES7 0x11
365
366#define EC_ACPI_MEM_BATTERY_INDEX 0x12
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375#define EC_ACPI_MEM_USB_PORT_POWER 0x13
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381#define EC_ACPI_MEM_MAPPED_BEGIN 0x20
382#define EC_ACPI_MEM_MAPPED_SIZE 0xe0
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384
385#define EC_ACPI_MEM_VERSION_CURRENT 2
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427#define __ec_align1 __packed
428#define __ec_align2 __packed
429#define __ec_align4 __packed
430#define __ec_align_size1 __packed
431#define __ec_align_offset1 __packed
432#define __ec_align_offset2 __packed
433#define __ec_todo_packed __packed
434#define __ec_todo_unpacked
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438
439#define EC_LPC_STATUS_TO_HOST 0x01
440
441#define EC_LPC_STATUS_FROM_HOST 0x02
442
443#define EC_LPC_STATUS_PROCESSING 0x04
444
445#define EC_LPC_STATUS_LAST_CMD 0x08
446
447#define EC_LPC_STATUS_BURST_MODE 0x10
448
449#define EC_LPC_STATUS_SCI_PENDING 0x20
450
451#define EC_LPC_STATUS_SMI_PENDING 0x40
452
453#define EC_LPC_STATUS_RESERVED 0x80
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459#define EC_LPC_STATUS_BUSY_MASK \
460 (EC_LPC_STATUS_FROM_HOST | EC_LPC_STATUS_PROCESSING)
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465
466enum ec_status {
467 EC_RES_SUCCESS = 0,
468 EC_RES_INVALID_COMMAND = 1,
469 EC_RES_ERROR = 2,
470 EC_RES_INVALID_PARAM = 3,
471 EC_RES_ACCESS_DENIED = 4,
472 EC_RES_INVALID_RESPONSE = 5,
473 EC_RES_INVALID_VERSION = 6,
474 EC_RES_INVALID_CHECKSUM = 7,
475 EC_RES_IN_PROGRESS = 8,
476 EC_RES_UNAVAILABLE = 9,
477 EC_RES_TIMEOUT = 10,
478 EC_RES_OVERFLOW = 11,
479 EC_RES_INVALID_HEADER = 12,
480 EC_RES_REQUEST_TRUNCATED = 13,
481 EC_RES_RESPONSE_TOO_BIG = 14,
482 EC_RES_BUS_ERROR = 15,
483 EC_RES_BUSY = 16,
484 EC_RES_INVALID_HEADER_VERSION = 17,
485 EC_RES_INVALID_HEADER_CRC = 18,
486 EC_RES_INVALID_DATA_CRC = 19,
487 EC_RES_DUP_UNAVAILABLE = 20,
488};
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497enum host_event_code {
498 EC_HOST_EVENT_LID_CLOSED = 1,
499 EC_HOST_EVENT_LID_OPEN = 2,
500 EC_HOST_EVENT_POWER_BUTTON = 3,
501 EC_HOST_EVENT_AC_CONNECTED = 4,
502 EC_HOST_EVENT_AC_DISCONNECTED = 5,
503 EC_HOST_EVENT_BATTERY_LOW = 6,
504 EC_HOST_EVENT_BATTERY_CRITICAL = 7,
505 EC_HOST_EVENT_BATTERY = 8,
506 EC_HOST_EVENT_THERMAL_THRESHOLD = 9,
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508 EC_HOST_EVENT_DEVICE = 10,
509 EC_HOST_EVENT_THERMAL = 11,
510 EC_HOST_EVENT_USB_CHARGER = 12,
511 EC_HOST_EVENT_KEY_PRESSED = 13,
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517 EC_HOST_EVENT_INTERFACE_READY = 14,
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519 EC_HOST_EVENT_KEYBOARD_RECOVERY = 15,
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522 EC_HOST_EVENT_THERMAL_SHUTDOWN = 16,
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524 EC_HOST_EVENT_BATTERY_SHUTDOWN = 17,
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527 EC_HOST_EVENT_THROTTLE_START = 18,
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529 EC_HOST_EVENT_THROTTLE_STOP = 19,
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532 EC_HOST_EVENT_HANG_DETECT = 20,
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534 EC_HOST_EVENT_HANG_REBOOT = 21,
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537 EC_HOST_EVENT_PD_MCU = 22,
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540 EC_HOST_EVENT_BATTERY_STATUS = 23,
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543 EC_HOST_EVENT_PANIC = 24,
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546 EC_HOST_EVENT_KEYBOARD_FASTBOOT = 25,
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549 EC_HOST_EVENT_RTC = 26,
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552 EC_HOST_EVENT_MKBP = 27,
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555 EC_HOST_EVENT_USB_MUX = 28,
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558 EC_HOST_EVENT_MODE_CHANGE = 29,
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561 EC_HOST_EVENT_KEYBOARD_RECOVERY_HW_REINIT = 30,
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564 EC_HOST_EVENT_WOV = 31,
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573 EC_HOST_EVENT_INVALID = 32
574};
575
576#define EC_HOST_EVENT_MASK(event_code) BIT_ULL((event_code) - 1)
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586struct ec_lpc_host_args {
587 uint8_t flags;
588 uint8_t command_version;
589 uint8_t data_size;
590 uint8_t checksum;
591} __ec_align4;
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603#define EC_HOST_ARGS_FLAG_FROM_HOST 0x01
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611#define EC_HOST_ARGS_FLAG_TO_HOST 0x02
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653#define EC_SPI_FRAME_START 0xec
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658#define EC_SPI_PAST_END 0xed
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665#define EC_SPI_RX_READY 0xf8
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671#define EC_SPI_RECEIVING 0xf9
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674#define EC_SPI_PROCESSING 0xfa
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680#define EC_SPI_RX_BAD_DATA 0xfb
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687#define EC_SPI_NOT_READY 0xfc
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694#define EC_SPI_OLD_READY 0xfd
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714#define EC_PROTO2_REQUEST_HEADER_BYTES 3
715#define EC_PROTO2_REQUEST_TRAILER_BYTES 1
716#define EC_PROTO2_REQUEST_OVERHEAD (EC_PROTO2_REQUEST_HEADER_BYTES + \
717 EC_PROTO2_REQUEST_TRAILER_BYTES)
718
719#define EC_PROTO2_RESPONSE_HEADER_BYTES 2
720#define EC_PROTO2_RESPONSE_TRAILER_BYTES 1
721#define EC_PROTO2_RESPONSE_OVERHEAD (EC_PROTO2_RESPONSE_HEADER_BYTES + \
722 EC_PROTO2_RESPONSE_TRAILER_BYTES)
723
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725#define EC_PROTO2_MAX_PARAM_SIZE 0xfc
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728#define EC_PROTO2_MAX_REQUEST_SIZE (EC_PROTO2_REQUEST_OVERHEAD + \
729 EC_PROTO2_MAX_PARAM_SIZE)
730#define EC_PROTO2_MAX_RESPONSE_SIZE (EC_PROTO2_RESPONSE_OVERHEAD + \
731 EC_PROTO2_MAX_PARAM_SIZE)
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739#define EC_COMMAND_PROTOCOL_3 0xda
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741#define EC_HOST_REQUEST_VERSION 3
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755struct ec_host_request {
756 uint8_t struct_version;
757 uint8_t checksum;
758 uint16_t command;
759 uint8_t command_version;
760 uint8_t reserved;
761 uint16_t data_len;
762} __ec_align4;
763
764#define EC_HOST_RESPONSE_VERSION 3
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775struct ec_host_response {
776 uint8_t struct_version;
777 uint8_t checksum;
778 uint16_t result;
779 uint16_t data_len;
780 uint16_t reserved;
781} __ec_align4;
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844struct ec_host_request4 {
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851 uint8_t fields0;
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858 uint8_t fields1;
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861 uint16_t command;
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864 uint16_t data_len;
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867 uint8_t reserved;
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870 uint8_t header_crc;
871} __ec_align4;
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874struct ec_host_response4 {
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881 uint8_t fields0;
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887 uint8_t fields1;
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890 uint16_t result;
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893 uint16_t data_len;
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896 uint8_t reserved;
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899 uint8_t header_crc;
900} __ec_align4;
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903#define EC_PACKET4_0_STRUCT_VERSION_MASK 0x0f
904#define EC_PACKET4_0_IS_RESPONSE_MASK 0x10
905#define EC_PACKET4_0_SEQ_NUM_SHIFT 5
906#define EC_PACKET4_0_SEQ_NUM_MASK 0x60
907#define EC_PACKET4_0_SEQ_DUP_MASK 0x80
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910#define EC_PACKET4_1_COMMAND_VERSION_MASK 0x1f
911#define EC_PACKET4_1_DATA_CRC_PRESENT_MASK 0x80
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935#define EC_CMD_PROTO_VERSION 0x0000
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941struct ec_response_proto_version {
942 uint32_t version;
943} __ec_align4;
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949#define EC_CMD_HELLO 0x0001
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955struct ec_params_hello {
956 uint32_t in_data;
957} __ec_align4;
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963struct ec_response_hello {
964 uint32_t out_data;
965} __ec_align4;
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968#define EC_CMD_GET_VERSION 0x0002
969
970enum ec_current_image {
971 EC_IMAGE_UNKNOWN = 0,
972 EC_IMAGE_RO,
973 EC_IMAGE_RW
974};
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983struct ec_response_get_version {
984 char version_string_ro[32];
985 char version_string_rw[32];
986 char reserved[32];
987 uint32_t current_image;
988} __ec_align4;
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991#define EC_CMD_READ_TEST 0x0003
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998struct ec_params_read_test {
999 uint32_t offset;
1000 uint32_t size;
1001} __ec_align4;
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1007struct ec_response_read_test {
1008 uint32_t data[32];
1009} __ec_align4;
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1016#define EC_CMD_GET_BUILD_INFO 0x0004
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1019#define EC_CMD_GET_CHIP_INFO 0x0005
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1027struct ec_response_get_chip_info {
1028 char vendor[32];
1029 char name[32];
1030 char revision[32];
1031} __ec_align4;
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1034#define EC_CMD_GET_BOARD_VERSION 0x0006
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1040struct ec_response_board_version {
1041 uint16_t board_version;
1042} __ec_align2;
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1052#define EC_CMD_READ_MEMMAP 0x0007
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1059struct ec_params_read_memmap {
1060 uint8_t offset;
1061 uint8_t size;
1062} __ec_align1;
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1065#define EC_CMD_GET_CMD_VERSIONS 0x0008
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1071struct ec_params_get_cmd_versions {
1072 uint8_t cmd;
1073} __ec_align1;
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1080struct ec_params_get_cmd_versions_v1 {
1081 uint16_t cmd;
1082} __ec_align2;
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1089struct ec_response_get_cmd_versions {
1090 uint32_t version_mask;
1091} __ec_align4;
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1100#define EC_CMD_GET_COMMS_STATUS 0x0009
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1103enum ec_comms_status {
1104 EC_COMMS_STATUS_PROCESSING = BIT(0),
1105};
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1112struct ec_response_get_comms_status {
1113 uint32_t flags;
1114} __ec_align4;
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1117#define EC_CMD_TEST_PROTOCOL 0x000A
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1120struct ec_params_test_protocol {
1121 uint32_t ec_result;
1122 uint32_t ret_len;
1123 uint8_t buf[32];
1124} __ec_align4;
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1127struct ec_response_test_protocol {
1128 uint8_t buf[32];
1129} __ec_align4;
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1132#define EC_CMD_GET_PROTOCOL_INFO 0x000B
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1136#define EC_PROTOCOL_INFO_IN_PROGRESS_SUPPORTED BIT(0)
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1146struct ec_response_get_protocol_info {
1147
1148 uint32_t protocol_versions;
1149 uint16_t max_request_packet_size;
1150 uint16_t max_response_packet_size;
1151 uint32_t flags;
1152} __ec_align4;
1153
1154
1155
1156
1157
1158
1159#define EC_GSV_SET 0x80000000
1160
1161
1162
1163
1164
1165#define EC_GSV_PARAM_MASK 0x00ffffff
1166
1167struct ec_params_get_set_value {
1168 uint32_t flags;
1169 uint32_t value;
1170} __ec_align4;
1171
1172struct ec_response_get_set_value {
1173 uint32_t flags;
1174 uint32_t value;
1175} __ec_align4;
1176
1177
1178#define EC_CMD_GSV_PAUSE_IN_S5 0x000C
1179
1180
1181
1182#define EC_CMD_GET_FEATURES 0x000D
1183
1184
1185enum ec_feature_code {
1186
1187
1188
1189
1190 EC_FEATURE_LIMITED = 0,
1191
1192
1193
1194
1195 EC_FEATURE_FLASH = 1,
1196
1197
1198
1199 EC_FEATURE_PWM_FAN = 2,
1200
1201
1202
1203 EC_FEATURE_PWM_KEYB = 3,
1204
1205
1206
1207 EC_FEATURE_LIGHTBAR = 4,
1208
1209 EC_FEATURE_LED = 5,
1210
1211
1212
1213
1214 EC_FEATURE_MOTION_SENSE = 6,
1215
1216 EC_FEATURE_KEYB = 7,
1217
1218 EC_FEATURE_PSTORE = 8,
1219
1220 EC_FEATURE_PORT80 = 9,
1221
1222
1223
1224
1225 EC_FEATURE_THERMAL = 10,
1226
1227 EC_FEATURE_BKLIGHT_SWITCH = 11,
1228
1229 EC_FEATURE_WIFI_SWITCH = 12,
1230
1231 EC_FEATURE_HOST_EVENTS = 13,
1232
1233 EC_FEATURE_GPIO = 14,
1234
1235 EC_FEATURE_I2C = 15,
1236
1237 EC_FEATURE_CHARGER = 16,
1238
1239 EC_FEATURE_BATTERY = 17,
1240
1241
1242
1243
1244 EC_FEATURE_SMART_BATTERY = 18,
1245
1246 EC_FEATURE_HANG_DETECT = 19,
1247
1248 EC_FEATURE_PMU = 20,
1249
1250 EC_FEATURE_SUB_MCU = 21,
1251
1252 EC_FEATURE_USB_PD = 22,
1253
1254 EC_FEATURE_USB_MUX = 23,
1255
1256 EC_FEATURE_MOTION_SENSE_FIFO = 24,
1257
1258 EC_FEATURE_VSTORE = 25,
1259
1260 EC_FEATURE_USBC_SS_MUX_VIRTUAL = 26,
1261
1262 EC_FEATURE_RTC = 27,
1263
1264 EC_FEATURE_FINGERPRINT = 28,
1265
1266 EC_FEATURE_TOUCHPAD = 29,
1267
1268 EC_FEATURE_RWSIG = 30,
1269
1270 EC_FEATURE_DEVICE_EVENT = 31,
1271
1272 EC_FEATURE_UNIFIED_WAKE_MASKS = 32,
1273
1274 EC_FEATURE_HOST_EVENT64 = 33,
1275
1276 EC_FEATURE_EXEC_IN_RAM = 34,
1277
1278 EC_FEATURE_CEC = 35,
1279
1280 EC_FEATURE_MOTION_SENSE_TIGHT_TIMESTAMPS = 36,
1281
1282
1283
1284
1285
1286 EC_FEATURE_REFINED_TABLET_MODE_HYSTERESIS = 37,
1287
1288 EC_FEATURE_SCP = 39,
1289
1290 EC_FEATURE_ISH = 40,
1291
1292 EC_FEATURE_TYPEC_CMD = 41,
1293
1294
1295
1296
1297 EC_FEATURE_TYPEC_REQUIRE_AP_MODE_ENTRY = 42,
1298
1299
1300
1301
1302 EC_FEATURE_TYPEC_MUX_REQUIRE_AP_ACK = 43,
1303};
1304
1305#define EC_FEATURE_MASK_0(event_code) BIT(event_code % 32)
1306#define EC_FEATURE_MASK_1(event_code) BIT(event_code - 32)
1307
1308struct ec_response_get_features {
1309 uint32_t flags[2];
1310} __ec_align4;
1311
1312
1313
1314#define EC_CMD_GET_SKU_ID 0x000E
1315
1316
1317#define EC_CMD_SET_SKU_ID 0x000F
1318
1319struct ec_sku_id_info {
1320 uint32_t sku_id;
1321} __ec_align4;
1322
1323
1324
1325
1326
1327#define EC_CMD_FLASH_INFO 0x0010
1328#define EC_VER_FLASH_INFO 2
1329
1330
1331
1332
1333
1334
1335
1336
1337
1338
1339
1340
1341
1342struct ec_response_flash_info {
1343 uint32_t flash_size;
1344 uint32_t write_block_size;
1345 uint32_t erase_block_size;
1346 uint32_t protect_block_size;
1347} __ec_align4;
1348
1349
1350
1351
1352
1353#define EC_FLASH_INFO_ERASE_TO_0 BIT(0)
1354
1355
1356
1357
1358
1359
1360
1361
1362#define EC_FLASH_INFO_SELECT_REQUIRED BIT(1)
1363
1364
1365
1366
1367
1368
1369
1370
1371
1372
1373
1374
1375
1376
1377
1378
1379
1380
1381
1382
1383
1384
1385
1386
1387
1388
1389
1390
1391
1392
1393struct ec_response_flash_info_1 {
1394
1395 uint32_t flash_size;
1396 uint32_t write_block_size;
1397 uint32_t erase_block_size;
1398 uint32_t protect_block_size;
1399
1400
1401 uint32_t write_ideal_size;
1402 uint32_t flags;
1403} __ec_align4;
1404
1405struct ec_params_flash_info_2 {
1406
1407 uint16_t num_banks_desc;
1408
1409 uint8_t reserved[2];
1410} __ec_align4;
1411
1412struct ec_flash_bank {
1413
1414 uint16_t count;
1415
1416 uint8_t size_exp;
1417
1418 uint8_t write_size_exp;
1419
1420 uint8_t erase_size_exp;
1421
1422 uint8_t protect_size_exp;
1423
1424 uint8_t reserved[2];
1425};
1426
1427struct ec_response_flash_info_2 {
1428
1429 uint32_t flash_size;
1430
1431 uint32_t flags;
1432
1433 uint32_t write_ideal_size;
1434
1435 uint16_t num_banks_total;
1436
1437 uint16_t num_banks_desc;
1438 struct ec_flash_bank banks[];
1439} __ec_align4;
1440
1441
1442
1443
1444
1445
1446#define EC_CMD_FLASH_READ 0x0011
1447
1448
1449
1450
1451
1452
1453struct ec_params_flash_read {
1454 uint32_t offset;
1455 uint32_t size;
1456} __ec_align4;
1457
1458
1459#define EC_CMD_FLASH_WRITE 0x0012
1460#define EC_VER_FLASH_WRITE 1
1461
1462
1463#define EC_FLASH_WRITE_VER0_SIZE 64
1464
1465
1466
1467
1468
1469
1470struct ec_params_flash_write {
1471 uint32_t offset;
1472 uint32_t size;
1473
1474} __ec_align4;
1475
1476
1477#define EC_CMD_FLASH_ERASE 0x0013
1478
1479
1480
1481
1482
1483
1484struct ec_params_flash_erase {
1485 uint32_t offset;
1486 uint32_t size;
1487} __ec_align4;
1488
1489
1490
1491
1492
1493
1494
1495
1496
1497
1498
1499
1500
1501
1502
1503
1504
1505
1506enum ec_flash_erase_cmd {
1507 FLASH_ERASE_SECTOR,
1508 FLASH_ERASE_SECTOR_ASYNC,
1509 FLASH_ERASE_GET_RESULT,
1510};
1511
1512
1513
1514
1515
1516
1517
1518
1519struct ec_params_flash_erase_v1 {
1520 uint8_t cmd;
1521 uint8_t reserved;
1522 uint16_t flag;
1523 struct ec_params_flash_erase params;
1524} __ec_align4;
1525
1526
1527
1528
1529
1530
1531
1532
1533
1534
1535
1536#define EC_CMD_FLASH_PROTECT 0x0015
1537#define EC_VER_FLASH_PROTECT 1
1538
1539
1540
1541#define EC_FLASH_PROTECT_RO_AT_BOOT BIT(0)
1542
1543
1544
1545
1546#define EC_FLASH_PROTECT_RO_NOW BIT(1)
1547
1548#define EC_FLASH_PROTECT_ALL_NOW BIT(2)
1549
1550#define EC_FLASH_PROTECT_GPIO_ASSERTED BIT(3)
1551
1552#define EC_FLASH_PROTECT_ERROR_STUCK BIT(4)
1553
1554
1555
1556
1557
1558#define EC_FLASH_PROTECT_ERROR_INCONSISTENT BIT(5)
1559
1560#define EC_FLASH_PROTECT_ALL_AT_BOOT BIT(6)
1561
1562#define EC_FLASH_PROTECT_RW_AT_BOOT BIT(7)
1563
1564#define EC_FLASH_PROTECT_RW_NOW BIT(8)
1565
1566#define EC_FLASH_PROTECT_ROLLBACK_AT_BOOT BIT(9)
1567
1568#define EC_FLASH_PROTECT_ROLLBACK_NOW BIT(10)
1569
1570
1571
1572
1573
1574
1575
1576struct ec_params_flash_protect {
1577 uint32_t mask;
1578 uint32_t flags;
1579} __ec_align4;
1580
1581
1582
1583
1584
1585
1586
1587
1588
1589
1590struct ec_response_flash_protect {
1591 uint32_t flags;
1592 uint32_t valid_flags;
1593 uint32_t writable_flags;
1594} __ec_align4;
1595
1596
1597
1598
1599
1600
1601
1602#define EC_CMD_FLASH_REGION_INFO 0x0016
1603#define EC_VER_FLASH_REGION_INFO 1
1604
1605enum ec_flash_region {
1606
1607 EC_FLASH_REGION_RO = 0,
1608
1609
1610
1611
1612
1613
1614
1615
1616
1617 EC_FLASH_REGION_ACTIVE,
1618
1619
1620
1621
1622 EC_FLASH_REGION_WP_RO,
1623
1624 EC_FLASH_REGION_UPDATE,
1625
1626 EC_FLASH_REGION_COUNT,
1627};
1628
1629
1630
1631
1632#define EC_FLASH_REGION_RW EC_FLASH_REGION_ACTIVE
1633
1634
1635
1636
1637
1638
1639struct ec_params_flash_region_info {
1640 uint32_t region;
1641} __ec_align4;
1642
1643struct ec_response_flash_region_info {
1644 uint32_t offset;
1645 uint32_t size;
1646} __ec_align4;
1647
1648
1649#define EC_CMD_VBNV_CONTEXT 0x0017
1650#define EC_VER_VBNV_CONTEXT 1
1651#define EC_VBNV_BLOCK_SIZE 16
1652
1653enum ec_vbnvcontext_op {
1654 EC_VBNV_CONTEXT_OP_READ,
1655 EC_VBNV_CONTEXT_OP_WRITE,
1656};
1657
1658struct ec_params_vbnvcontext {
1659 uint32_t op;
1660 uint8_t block[EC_VBNV_BLOCK_SIZE];
1661} __ec_align4;
1662
1663struct ec_response_vbnvcontext {
1664 uint8_t block[EC_VBNV_BLOCK_SIZE];
1665} __ec_align4;
1666
1667
1668
1669#define EC_CMD_FLASH_SPI_INFO 0x0018
1670
1671struct ec_response_flash_spi_info {
1672
1673 uint8_t jedec[3];
1674
1675
1676 uint8_t reserved0;
1677
1678
1679 uint8_t mfr_dev_id[2];
1680
1681
1682 uint8_t sr1, sr2;
1683} __ec_align1;
1684
1685
1686
1687#define EC_CMD_FLASH_SELECT 0x0019
1688
1689
1690
1691
1692
1693struct ec_params_flash_select {
1694 uint8_t select;
1695} __ec_align4;
1696
1697
1698
1699
1700
1701
1702#define EC_CMD_PWM_GET_FAN_TARGET_RPM 0x0020
1703
1704struct ec_response_pwm_get_fan_rpm {
1705 uint32_t rpm;
1706} __ec_align4;
1707
1708
1709#define EC_CMD_PWM_SET_FAN_TARGET_RPM 0x0021
1710
1711
1712struct ec_params_pwm_set_fan_target_rpm_v0 {
1713 uint32_t rpm;
1714} __ec_align4;
1715
1716
1717struct ec_params_pwm_set_fan_target_rpm_v1 {
1718 uint32_t rpm;
1719 uint8_t fan_idx;
1720} __ec_align_size1;
1721
1722
1723
1724#define EC_CMD_PWM_GET_KEYBOARD_BACKLIGHT 0x0022
1725
1726struct ec_response_pwm_get_keyboard_backlight {
1727 uint8_t percent;
1728 uint8_t enabled;
1729} __ec_align1;
1730
1731
1732
1733#define EC_CMD_PWM_SET_KEYBOARD_BACKLIGHT 0x0023
1734
1735struct ec_params_pwm_set_keyboard_backlight {
1736 uint8_t percent;
1737} __ec_align1;
1738
1739
1740#define EC_CMD_PWM_SET_FAN_DUTY 0x0024
1741
1742
1743struct ec_params_pwm_set_fan_duty_v0 {
1744 uint32_t percent;
1745} __ec_align4;
1746
1747
1748struct ec_params_pwm_set_fan_duty_v1 {
1749 uint32_t percent;
1750 uint8_t fan_idx;
1751} __ec_align_size1;
1752
1753#define EC_CMD_PWM_SET_DUTY 0x0025
1754
1755#define EC_PWM_MAX_DUTY 0xffff
1756
1757enum ec_pwm_type {
1758
1759 EC_PWM_TYPE_GENERIC = 0,
1760
1761 EC_PWM_TYPE_KB_LIGHT,
1762
1763 EC_PWM_TYPE_DISPLAY_LIGHT,
1764 EC_PWM_TYPE_COUNT,
1765};
1766
1767struct ec_params_pwm_set_duty {
1768 uint16_t duty;
1769 uint8_t pwm_type;
1770 uint8_t index;
1771} __ec_align4;
1772
1773#define EC_CMD_PWM_GET_DUTY 0x0026
1774
1775struct ec_params_pwm_get_duty {
1776 uint8_t pwm_type;
1777 uint8_t index;
1778} __ec_align1;
1779
1780struct ec_response_pwm_get_duty {
1781 uint16_t duty;
1782} __ec_align2;
1783
1784
1785
1786
1787
1788
1789
1790
1791#define EC_CMD_LIGHTBAR_CMD 0x0028
1792
1793struct rgb_s {
1794 uint8_t r, g, b;
1795} __ec_todo_unpacked;
1796
1797#define LB_BATTERY_LEVELS 4
1798
1799
1800
1801
1802
1803struct lightbar_params_v0 {
1804
1805 int32_t google_ramp_up;
1806 int32_t google_ramp_down;
1807 int32_t s3s0_ramp_up;
1808 int32_t s0_tick_delay[2];
1809 int32_t s0a_tick_delay[2];
1810 int32_t s0s3_ramp_down;
1811 int32_t s3_sleep_for;
1812 int32_t s3_ramp_up;
1813 int32_t s3_ramp_down;
1814
1815
1816 uint8_t new_s0;
1817 uint8_t osc_min[2];
1818 uint8_t osc_max[2];
1819 uint8_t w_ofs[2];
1820
1821
1822 uint8_t bright_bl_off_fixed[2];
1823 uint8_t bright_bl_on_min[2];
1824 uint8_t bright_bl_on_max[2];
1825
1826
1827 uint8_t battery_threshold[LB_BATTERY_LEVELS - 1];
1828
1829
1830 uint8_t s0_idx[2][LB_BATTERY_LEVELS];
1831 uint8_t s3_idx[2][LB_BATTERY_LEVELS];
1832
1833
1834 struct rgb_s color[8];
1835} __ec_todo_packed;
1836
1837struct lightbar_params_v1 {
1838
1839 int32_t google_ramp_up;
1840 int32_t google_ramp_down;
1841 int32_t s3s0_ramp_up;
1842 int32_t s0_tick_delay[2];
1843 int32_t s0a_tick_delay[2];
1844 int32_t s0s3_ramp_down;
1845 int32_t s3_sleep_for;
1846 int32_t s3_ramp_up;
1847 int32_t s3_ramp_down;
1848 int32_t s5_ramp_up;
1849 int32_t s5_ramp_down;
1850 int32_t tap_tick_delay;
1851 int32_t tap_gate_delay;
1852 int32_t tap_display_time;
1853
1854
1855 uint8_t tap_pct_red;
1856 uint8_t tap_pct_green;
1857 uint8_t tap_seg_min_on;
1858 uint8_t tap_seg_max_on;
1859 uint8_t tap_seg_osc;
1860 uint8_t tap_idx[3];
1861
1862
1863 uint8_t osc_min[2];
1864 uint8_t osc_max[2];
1865 uint8_t w_ofs[2];
1866
1867
1868 uint8_t bright_bl_off_fixed[2];
1869 uint8_t bright_bl_on_min[2];
1870 uint8_t bright_bl_on_max[2];
1871
1872
1873 uint8_t battery_threshold[LB_BATTERY_LEVELS - 1];
1874
1875
1876 uint8_t s0_idx[2][LB_BATTERY_LEVELS];
1877 uint8_t s3_idx[2][LB_BATTERY_LEVELS];
1878
1879
1880 uint8_t s5_idx;
1881
1882
1883 struct rgb_s color[8];
1884} __ec_todo_packed;
1885
1886
1887
1888
1889
1890
1891
1892
1893
1894
1895struct lightbar_params_v2_timing {
1896
1897 int32_t google_ramp_up;
1898 int32_t google_ramp_down;
1899 int32_t s3s0_ramp_up;
1900 int32_t s0_tick_delay[2];
1901 int32_t s0a_tick_delay[2];
1902 int32_t s0s3_ramp_down;
1903 int32_t s3_sleep_for;
1904 int32_t s3_ramp_up;
1905 int32_t s3_ramp_down;
1906 int32_t s5_ramp_up;
1907 int32_t s5_ramp_down;
1908 int32_t tap_tick_delay;
1909 int32_t tap_gate_delay;
1910 int32_t tap_display_time;
1911} __ec_todo_packed;
1912
1913struct lightbar_params_v2_tap {
1914
1915 uint8_t tap_pct_red;
1916 uint8_t tap_pct_green;
1917 uint8_t tap_seg_min_on;
1918 uint8_t tap_seg_max_on;
1919 uint8_t tap_seg_osc;
1920 uint8_t tap_idx[3];
1921} __ec_todo_packed;
1922
1923struct lightbar_params_v2_oscillation {
1924
1925 uint8_t osc_min[2];
1926 uint8_t osc_max[2];
1927 uint8_t w_ofs[2];
1928} __ec_todo_packed;
1929
1930struct lightbar_params_v2_brightness {
1931
1932 uint8_t bright_bl_off_fixed[2];
1933 uint8_t bright_bl_on_min[2];
1934 uint8_t bright_bl_on_max[2];
1935} __ec_todo_packed;
1936
1937struct lightbar_params_v2_thresholds {
1938
1939 uint8_t battery_threshold[LB_BATTERY_LEVELS - 1];
1940} __ec_todo_packed;
1941
1942struct lightbar_params_v2_colors {
1943
1944 uint8_t s0_idx[2][LB_BATTERY_LEVELS];
1945 uint8_t s3_idx[2][LB_BATTERY_LEVELS];
1946
1947
1948 uint8_t s5_idx;
1949
1950
1951 struct rgb_s color[8];
1952} __ec_todo_packed;
1953
1954
1955#define EC_LB_PROG_LEN 192
1956struct lightbar_program {
1957 uint8_t size;
1958 uint8_t data[EC_LB_PROG_LEN];
1959} __ec_todo_unpacked;
1960
1961struct ec_params_lightbar {
1962 uint8_t cmd;
1963 union {
1964
1965
1966
1967
1968
1969
1970
1971
1972
1973
1974
1975
1976 struct __ec_todo_unpacked {
1977 uint8_t num;
1978 } set_brightness, seq, demo;
1979
1980 struct __ec_todo_unpacked {
1981 uint8_t ctrl, reg, value;
1982 } reg;
1983
1984 struct __ec_todo_unpacked {
1985 uint8_t led, red, green, blue;
1986 } set_rgb;
1987
1988 struct __ec_todo_unpacked {
1989 uint8_t led;
1990 } get_rgb;
1991
1992 struct __ec_todo_unpacked {
1993 uint8_t enable;
1994 } manual_suspend_ctrl;
1995
1996 struct lightbar_params_v0 set_params_v0;
1997 struct lightbar_params_v1 set_params_v1;
1998
1999 struct lightbar_params_v2_timing set_v2par_timing;
2000 struct lightbar_params_v2_tap set_v2par_tap;
2001 struct lightbar_params_v2_oscillation set_v2par_osc;
2002 struct lightbar_params_v2_brightness set_v2par_bright;
2003 struct lightbar_params_v2_thresholds set_v2par_thlds;
2004 struct lightbar_params_v2_colors set_v2par_colors;
2005
2006 struct lightbar_program set_program;
2007 };
2008} __ec_todo_packed;
2009
2010struct ec_response_lightbar {
2011 union {
2012 struct __ec_todo_unpacked {
2013 struct __ec_todo_unpacked {
2014 uint8_t reg;
2015 uint8_t ic0;
2016 uint8_t ic1;
2017 } vals[23];
2018 } dump;
2019
2020 struct __ec_todo_unpacked {
2021 uint8_t num;
2022 } get_seq, get_brightness, get_demo;
2023
2024 struct lightbar_params_v0 get_params_v0;
2025 struct lightbar_params_v1 get_params_v1;
2026
2027
2028 struct lightbar_params_v2_timing get_params_v2_timing;
2029 struct lightbar_params_v2_tap get_params_v2_tap;
2030 struct lightbar_params_v2_oscillation get_params_v2_osc;
2031 struct lightbar_params_v2_brightness get_params_v2_bright;
2032 struct lightbar_params_v2_thresholds get_params_v2_thlds;
2033 struct lightbar_params_v2_colors get_params_v2_colors;
2034
2035 struct __ec_todo_unpacked {
2036 uint32_t num;
2037 uint32_t flags;
2038 } version;
2039
2040 struct __ec_todo_unpacked {
2041 uint8_t red, green, blue;
2042 } get_rgb;
2043
2044
2045
2046
2047
2048
2049
2050
2051
2052
2053 };
2054} __ec_todo_packed;
2055
2056
2057enum lightbar_command {
2058 LIGHTBAR_CMD_DUMP = 0,
2059 LIGHTBAR_CMD_OFF = 1,
2060 LIGHTBAR_CMD_ON = 2,
2061 LIGHTBAR_CMD_INIT = 3,
2062 LIGHTBAR_CMD_SET_BRIGHTNESS = 4,
2063 LIGHTBAR_CMD_SEQ = 5,
2064 LIGHTBAR_CMD_REG = 6,
2065 LIGHTBAR_CMD_SET_RGB = 7,
2066 LIGHTBAR_CMD_GET_SEQ = 8,
2067 LIGHTBAR_CMD_DEMO = 9,
2068 LIGHTBAR_CMD_GET_PARAMS_V0 = 10,
2069 LIGHTBAR_CMD_SET_PARAMS_V0 = 11,
2070 LIGHTBAR_CMD_VERSION = 12,
2071 LIGHTBAR_CMD_GET_BRIGHTNESS = 13,
2072 LIGHTBAR_CMD_GET_RGB = 14,
2073 LIGHTBAR_CMD_GET_DEMO = 15,
2074 LIGHTBAR_CMD_GET_PARAMS_V1 = 16,
2075 LIGHTBAR_CMD_SET_PARAMS_V1 = 17,
2076 LIGHTBAR_CMD_SET_PROGRAM = 18,
2077 LIGHTBAR_CMD_MANUAL_SUSPEND_CTRL = 19,
2078 LIGHTBAR_CMD_SUSPEND = 20,
2079 LIGHTBAR_CMD_RESUME = 21,
2080 LIGHTBAR_CMD_GET_PARAMS_V2_TIMING = 22,
2081 LIGHTBAR_CMD_SET_PARAMS_V2_TIMING = 23,
2082 LIGHTBAR_CMD_GET_PARAMS_V2_TAP = 24,
2083 LIGHTBAR_CMD_SET_PARAMS_V2_TAP = 25,
2084 LIGHTBAR_CMD_GET_PARAMS_V2_OSCILLATION = 26,
2085 LIGHTBAR_CMD_SET_PARAMS_V2_OSCILLATION = 27,
2086 LIGHTBAR_CMD_GET_PARAMS_V2_BRIGHTNESS = 28,
2087 LIGHTBAR_CMD_SET_PARAMS_V2_BRIGHTNESS = 29,
2088 LIGHTBAR_CMD_GET_PARAMS_V2_THRESHOLDS = 30,
2089 LIGHTBAR_CMD_SET_PARAMS_V2_THRESHOLDS = 31,
2090 LIGHTBAR_CMD_GET_PARAMS_V2_COLORS = 32,
2091 LIGHTBAR_CMD_SET_PARAMS_V2_COLORS = 33,
2092 LIGHTBAR_NUM_CMDS
2093};
2094
2095
2096
2097
2098#define EC_CMD_LED_CONTROL 0x0029
2099
2100enum ec_led_id {
2101
2102 EC_LED_ID_BATTERY_LED = 0,
2103
2104
2105
2106
2107 EC_LED_ID_POWER_LED,
2108
2109 EC_LED_ID_ADAPTER_LED,
2110
2111 EC_LED_ID_LEFT_LED,
2112
2113 EC_LED_ID_RIGHT_LED,
2114
2115 EC_LED_ID_RECOVERY_HW_REINIT_LED,
2116
2117 EC_LED_ID_SYSRQ_DEBUG_LED,
2118
2119 EC_LED_ID_COUNT
2120};
2121
2122
2123#define EC_LED_FLAGS_QUERY BIT(0)
2124#define EC_LED_FLAGS_AUTO BIT(1)
2125
2126enum ec_led_colors {
2127 EC_LED_COLOR_RED = 0,
2128 EC_LED_COLOR_GREEN,
2129 EC_LED_COLOR_BLUE,
2130 EC_LED_COLOR_YELLOW,
2131 EC_LED_COLOR_WHITE,
2132 EC_LED_COLOR_AMBER,
2133
2134 EC_LED_COLOR_COUNT
2135};
2136
2137struct ec_params_led_control {
2138 uint8_t led_id;
2139 uint8_t flags;
2140
2141 uint8_t brightness[EC_LED_COLOR_COUNT];
2142} __ec_align1;
2143
2144struct ec_response_led_control {
2145
2146
2147
2148
2149
2150
2151
2152 uint8_t brightness_range[EC_LED_COLOR_COUNT];
2153} __ec_align1;
2154
2155
2156
2157
2158
2159
2160
2161
2162
2163
2164#define EC_CMD_VBOOT_HASH 0x002A
2165
2166struct ec_params_vboot_hash {
2167 uint8_t cmd;
2168 uint8_t hash_type;
2169 uint8_t nonce_size;
2170 uint8_t reserved0;
2171 uint32_t offset;
2172 uint32_t size;
2173 uint8_t nonce_data[64];
2174} __ec_align4;
2175
2176struct ec_response_vboot_hash {
2177 uint8_t status;
2178 uint8_t hash_type;
2179 uint8_t digest_size;
2180 uint8_t reserved0;
2181 uint32_t offset;
2182 uint32_t size;
2183 uint8_t hash_digest[64];
2184} __ec_align4;
2185
2186enum ec_vboot_hash_cmd {
2187 EC_VBOOT_HASH_GET = 0,
2188 EC_VBOOT_HASH_ABORT = 1,
2189 EC_VBOOT_HASH_START = 2,
2190 EC_VBOOT_HASH_RECALC = 3,
2191};
2192
2193enum ec_vboot_hash_type {
2194 EC_VBOOT_HASH_TYPE_SHA256 = 0,
2195};
2196
2197enum ec_vboot_hash_status {
2198 EC_VBOOT_HASH_STATUS_NONE = 0,
2199 EC_VBOOT_HASH_STATUS_DONE = 1,
2200 EC_VBOOT_HASH_STATUS_BUSY = 2,
2201};
2202
2203
2204
2205
2206
2207
2208#define EC_VBOOT_HASH_OFFSET_RO 0xfffffffe
2209#define EC_VBOOT_HASH_OFFSET_ACTIVE 0xfffffffd
2210#define EC_VBOOT_HASH_OFFSET_UPDATE 0xfffffffc
2211
2212
2213
2214
2215
2216#define EC_VBOOT_HASH_OFFSET_RW EC_VBOOT_HASH_OFFSET_ACTIVE
2217
2218
2219
2220
2221
2222
2223#define EC_CMD_MOTION_SENSE_CMD 0x002B
2224
2225
2226enum motionsense_command {
2227
2228
2229
2230
2231 MOTIONSENSE_CMD_DUMP = 0,
2232
2233
2234
2235
2236
2237
2238 MOTIONSENSE_CMD_INFO = 1,
2239
2240
2241
2242
2243
2244
2245
2246
2247
2248
2249
2250 MOTIONSENSE_CMD_EC_RATE = 2,
2251
2252
2253
2254
2255
2256 MOTIONSENSE_CMD_SENSOR_ODR = 3,
2257
2258
2259
2260
2261
2262 MOTIONSENSE_CMD_SENSOR_RANGE = 4,
2263
2264
2265
2266
2267
2268
2269
2270
2271 MOTIONSENSE_CMD_KB_WAKE_ANGLE = 5,
2272
2273
2274
2275
2276 MOTIONSENSE_CMD_DATA = 6,
2277
2278
2279
2280
2281 MOTIONSENSE_CMD_FIFO_INFO = 7,
2282
2283
2284
2285
2286
2287 MOTIONSENSE_CMD_FIFO_FLUSH = 8,
2288
2289
2290
2291
2292 MOTIONSENSE_CMD_FIFO_READ = 9,
2293
2294
2295
2296
2297
2298 MOTIONSENSE_CMD_PERFORM_CALIB = 10,
2299
2300
2301
2302
2303
2304
2305
2306 MOTIONSENSE_CMD_SENSOR_OFFSET = 11,
2307
2308
2309
2310
2311
2312 MOTIONSENSE_CMD_LIST_ACTIVITIES = 12,
2313
2314
2315
2316
2317
2318 MOTIONSENSE_CMD_SET_ACTIVITY = 13,
2319
2320
2321
2322
2323 MOTIONSENSE_CMD_LID_ANGLE = 14,
2324
2325
2326
2327
2328
2329
2330 MOTIONSENSE_CMD_FIFO_INT_ENABLE = 15,
2331
2332
2333
2334
2335
2336 MOTIONSENSE_CMD_SPOOF = 16,
2337
2338
2339 MOTIONSENSE_CMD_TABLET_MODE_LID_ANGLE = 17,
2340
2341
2342
2343
2344
2345 MOTIONSENSE_CMD_SENSOR_SCALE = 18,
2346
2347
2348 MOTIONSENSE_NUM_CMDS
2349};
2350
2351
2352enum motionsensor_type {
2353 MOTIONSENSE_TYPE_ACCEL = 0,
2354 MOTIONSENSE_TYPE_GYRO = 1,
2355 MOTIONSENSE_TYPE_MAG = 2,
2356 MOTIONSENSE_TYPE_PROX = 3,
2357 MOTIONSENSE_TYPE_LIGHT = 4,
2358 MOTIONSENSE_TYPE_ACTIVITY = 5,
2359 MOTIONSENSE_TYPE_BARO = 6,
2360 MOTIONSENSE_TYPE_SYNC = 7,
2361 MOTIONSENSE_TYPE_MAX,
2362};
2363
2364
2365enum motionsensor_location {
2366 MOTIONSENSE_LOC_BASE = 0,
2367 MOTIONSENSE_LOC_LID = 1,
2368 MOTIONSENSE_LOC_CAMERA = 2,
2369 MOTIONSENSE_LOC_MAX,
2370};
2371
2372
2373enum motionsensor_chip {
2374 MOTIONSENSE_CHIP_KXCJ9 = 0,
2375 MOTIONSENSE_CHIP_LSM6DS0 = 1,
2376 MOTIONSENSE_CHIP_BMI160 = 2,
2377 MOTIONSENSE_CHIP_SI1141 = 3,
2378 MOTIONSENSE_CHIP_SI1142 = 4,
2379 MOTIONSENSE_CHIP_SI1143 = 5,
2380 MOTIONSENSE_CHIP_KX022 = 6,
2381 MOTIONSENSE_CHIP_L3GD20H = 7,
2382 MOTIONSENSE_CHIP_BMA255 = 8,
2383 MOTIONSENSE_CHIP_BMP280 = 9,
2384 MOTIONSENSE_CHIP_OPT3001 = 10,
2385 MOTIONSENSE_CHIP_BH1730 = 11,
2386 MOTIONSENSE_CHIP_GPIO = 12,
2387 MOTIONSENSE_CHIP_LIS2DH = 13,
2388 MOTIONSENSE_CHIP_LSM6DSM = 14,
2389 MOTIONSENSE_CHIP_LIS2DE = 15,
2390 MOTIONSENSE_CHIP_LIS2MDL = 16,
2391 MOTIONSENSE_CHIP_LSM6DS3 = 17,
2392 MOTIONSENSE_CHIP_LSM6DSO = 18,
2393 MOTIONSENSE_CHIP_LNG2DM = 19,
2394 MOTIONSENSE_CHIP_MAX,
2395};
2396
2397
2398enum motionsensor_orientation {
2399 MOTIONSENSE_ORIENTATION_LANDSCAPE = 0,
2400 MOTIONSENSE_ORIENTATION_PORTRAIT = 1,
2401 MOTIONSENSE_ORIENTATION_UPSIDE_DOWN_PORTRAIT = 2,
2402 MOTIONSENSE_ORIENTATION_UPSIDE_DOWN_LANDSCAPE = 3,
2403 MOTIONSENSE_ORIENTATION_UNKNOWN = 4,
2404};
2405
2406struct ec_response_motion_sensor_data {
2407
2408 uint8_t flags;
2409
2410 uint8_t sensor_num;
2411
2412 union {
2413 int16_t data[3];
2414 struct __ec_todo_packed {
2415 uint16_t reserved;
2416 uint32_t timestamp;
2417 };
2418 struct __ec_todo_unpacked {
2419 uint8_t activity;
2420 uint8_t state;
2421 int16_t add_info[2];
2422 };
2423 };
2424} __ec_todo_packed;
2425
2426
2427struct ec_response_motion_sense_fifo_info {
2428
2429 uint16_t size;
2430
2431 uint16_t count;
2432
2433
2434
2435 uint32_t timestamp;
2436
2437 uint16_t total_lost;
2438
2439 uint16_t lost[];
2440} __ec_todo_packed;
2441
2442struct ec_response_motion_sense_fifo_data {
2443 uint32_t number_data;
2444 struct ec_response_motion_sensor_data data[];
2445} __ec_todo_packed;
2446
2447
2448enum motionsensor_activity {
2449 MOTIONSENSE_ACTIVITY_RESERVED = 0,
2450 MOTIONSENSE_ACTIVITY_SIG_MOTION = 1,
2451 MOTIONSENSE_ACTIVITY_DOUBLE_TAP = 2,
2452 MOTIONSENSE_ACTIVITY_ORIENTATION = 3,
2453};
2454
2455struct ec_motion_sense_activity {
2456 uint8_t sensor_num;
2457 uint8_t activity;
2458 uint8_t enable;
2459 uint8_t reserved;
2460 uint16_t parameters[3];
2461} __ec_todo_unpacked;
2462
2463
2464#define MOTIONSENSE_MODULE_FLAG_ACTIVE BIT(0)
2465
2466
2467#define MOTIONSENSE_SENSOR_FLAG_PRESENT BIT(0)
2468
2469
2470
2471
2472
2473#define MOTIONSENSE_SENSOR_FLAG_FLUSH BIT(0)
2474#define MOTIONSENSE_SENSOR_FLAG_TIMESTAMP BIT(1)
2475#define MOTIONSENSE_SENSOR_FLAG_WAKEUP BIT(2)
2476#define MOTIONSENSE_SENSOR_FLAG_TABLET_MODE BIT(3)
2477#define MOTIONSENSE_SENSOR_FLAG_ODR BIT(4)
2478
2479
2480
2481
2482
2483
2484#define EC_MOTION_SENSE_NO_VALUE -1
2485
2486#define EC_MOTION_SENSE_INVALID_CALIB_TEMP 0x8000
2487
2488
2489
2490#define MOTION_SENSE_SET_OFFSET BIT(0)
2491
2492
2493#define MOTION_SENSE_DEFAULT_SCALE BIT(15)
2494
2495#define LID_ANGLE_UNRELIABLE 500
2496
2497enum motionsense_spoof_mode {
2498
2499 MOTIONSENSE_SPOOF_MODE_DISABLE = 0,
2500
2501
2502 MOTIONSENSE_SPOOF_MODE_CUSTOM,
2503
2504
2505 MOTIONSENSE_SPOOF_MODE_LOCK_CURRENT,
2506
2507
2508 MOTIONSENSE_SPOOF_MODE_QUERY,
2509};
2510
2511struct ec_params_motion_sense {
2512 uint8_t cmd;
2513 union {
2514
2515 struct __ec_todo_unpacked {
2516
2517
2518
2519
2520
2521 uint8_t max_sensor_count;
2522 } dump;
2523
2524
2525
2526
2527 struct __ec_todo_unpacked {
2528
2529
2530
2531 int16_t data;
2532 } kb_wake_angle;
2533
2534
2535
2536
2537
2538 struct __ec_todo_unpacked {
2539 uint8_t sensor_num;
2540 } info, info_3, data, fifo_flush, perform_calib,
2541 list_activities;
2542
2543
2544
2545
2546
2547 struct __ec_todo_unpacked {
2548 uint8_t sensor_num;
2549
2550
2551 uint8_t roundup;
2552
2553 uint16_t reserved;
2554
2555
2556 int32_t data;
2557 } ec_rate, sensor_odr, sensor_range;
2558
2559
2560 struct __ec_todo_packed {
2561 uint8_t sensor_num;
2562
2563
2564
2565
2566
2567
2568 uint16_t flags;
2569
2570
2571
2572
2573
2574
2575
2576 int16_t temp;
2577
2578
2579
2580
2581
2582
2583
2584
2585 int16_t offset[3];
2586 } sensor_offset;
2587
2588
2589 struct __ec_todo_packed {
2590 uint8_t sensor_num;
2591
2592
2593
2594
2595
2596
2597 uint16_t flags;
2598
2599
2600
2601
2602
2603
2604
2605 int16_t temp;
2606
2607
2608
2609
2610
2611
2612
2613
2614 uint16_t scale[3];
2615 } sensor_scale;
2616
2617
2618
2619
2620
2621
2622 struct __ec_todo_unpacked {
2623
2624
2625
2626
2627 uint32_t max_data_vector;
2628 } fifo_read;
2629
2630 struct ec_motion_sense_activity set_activity;
2631
2632
2633
2634
2635
2636 struct __ec_todo_unpacked {
2637
2638
2639
2640
2641 int8_t enable;
2642 } fifo_int_enable;
2643
2644
2645 struct __ec_todo_packed {
2646 uint8_t sensor_id;
2647
2648
2649 uint8_t spoof_enable;
2650
2651
2652 uint8_t reserved;
2653
2654
2655 int16_t components[3];
2656 } spoof;
2657
2658
2659 struct __ec_todo_unpacked {
2660
2661
2662
2663
2664 int16_t lid_angle;
2665
2666
2667
2668
2669
2670
2671
2672
2673 int16_t hys_degree;
2674 } tablet_mode_threshold;
2675 };
2676} __ec_todo_packed;
2677
2678struct ec_response_motion_sense {
2679 union {
2680
2681 struct __ec_todo_unpacked {
2682
2683 uint8_t module_flags;
2684
2685
2686 uint8_t sensor_count;
2687
2688
2689
2690
2691
2692 struct ec_response_motion_sensor_data sensor[0];
2693 } dump;
2694
2695
2696 struct __ec_todo_unpacked {
2697
2698 uint8_t type;
2699
2700
2701 uint8_t location;
2702
2703
2704 uint8_t chip;
2705 } info;
2706
2707
2708 struct __ec_todo_unpacked {
2709
2710 uint8_t type;
2711
2712
2713 uint8_t location;
2714
2715
2716 uint8_t chip;
2717
2718
2719 uint32_t min_frequency;
2720
2721
2722 uint32_t max_frequency;
2723
2724
2725 uint32_t fifo_max_event_count;
2726 } info_3;
2727
2728
2729 struct ec_response_motion_sensor_data data;
2730
2731
2732
2733
2734
2735
2736
2737
2738 struct __ec_todo_unpacked {
2739
2740 int32_t ret;
2741 } ec_rate, sensor_odr, sensor_range, kb_wake_angle,
2742 fifo_int_enable, spoof;
2743
2744
2745
2746
2747
2748 struct __ec_todo_unpacked {
2749 int16_t temp;
2750 int16_t offset[3];
2751 } sensor_offset, perform_calib;
2752
2753
2754 struct __ec_todo_unpacked {
2755 int16_t temp;
2756 uint16_t scale[3];
2757 } sensor_scale;
2758
2759 struct ec_response_motion_sense_fifo_info fifo_info, fifo_flush;
2760
2761 struct ec_response_motion_sense_fifo_data fifo_read;
2762
2763 struct __ec_todo_packed {
2764 uint16_t reserved;
2765 uint32_t enabled;
2766 uint32_t disabled;
2767 } list_activities;
2768
2769
2770
2771
2772 struct __ec_todo_unpacked {
2773
2774
2775
2776
2777 uint16_t value;
2778 } lid_angle;
2779
2780
2781 struct __ec_todo_unpacked {
2782
2783
2784
2785
2786 uint16_t lid_angle;
2787
2788
2789 uint16_t hys_degree;
2790 } tablet_mode_threshold;
2791
2792 };
2793} __ec_todo_packed;
2794
2795
2796
2797
2798
2799#define EC_CMD_FORCE_LID_OPEN 0x002C
2800
2801struct ec_params_force_lid_open {
2802 uint8_t enabled;
2803} __ec_align1;
2804
2805
2806
2807#define EC_CMD_CONFIG_POWER_BUTTON 0x002D
2808
2809enum ec_config_power_button_flags {
2810
2811 EC_POWER_BUTTON_ENABLE_PULSE = BIT(0),
2812};
2813
2814struct ec_params_config_power_button {
2815
2816 uint8_t flags;
2817} __ec_align1;
2818
2819
2820
2821
2822
2823#define EC_CMD_USB_CHARGE_SET_MODE 0x0030
2824
2825struct ec_params_usb_charge_set_mode {
2826 uint8_t usb_port_id;
2827 uint8_t mode:7;
2828 uint8_t inhibit_charge:1;
2829} __ec_align1;
2830
2831
2832
2833
2834
2835#define EC_PSTORE_SIZE_MAX 64
2836
2837
2838#define EC_CMD_PSTORE_INFO 0x0040
2839
2840struct ec_response_pstore_info {
2841
2842 uint32_t pstore_size;
2843
2844 uint32_t access_size;
2845} __ec_align4;
2846
2847
2848
2849
2850
2851
2852#define EC_CMD_PSTORE_READ 0x0041
2853
2854struct ec_params_pstore_read {
2855 uint32_t offset;
2856 uint32_t size;
2857} __ec_align4;
2858
2859
2860#define EC_CMD_PSTORE_WRITE 0x0042
2861
2862struct ec_params_pstore_write {
2863 uint32_t offset;
2864 uint32_t size;
2865 uint8_t data[EC_PSTORE_SIZE_MAX];
2866} __ec_align4;
2867
2868
2869
2870
2871
2872struct ec_params_rtc {
2873 uint32_t time;
2874} __ec_align4;
2875
2876struct ec_response_rtc {
2877 uint32_t time;
2878} __ec_align4;
2879
2880
2881#define EC_CMD_RTC_GET_VALUE 0x0044
2882#define EC_CMD_RTC_GET_ALARM 0x0045
2883
2884
2885#define EC_CMD_RTC_SET_VALUE 0x0046
2886#define EC_CMD_RTC_SET_ALARM 0x0047
2887
2888
2889#define EC_RTC_ALARM_CLEAR 0
2890
2891
2892
2893
2894
2895#define EC_PORT80_SIZE_MAX 32
2896
2897
2898#define EC_CMD_PORT80_LAST_BOOT 0x0048
2899#define EC_CMD_PORT80_READ 0x0048
2900
2901enum ec_port80_subcmd {
2902 EC_PORT80_GET_INFO = 0,
2903 EC_PORT80_READ_BUFFER,
2904};
2905
2906struct ec_params_port80_read {
2907 uint16_t subcmd;
2908 union {
2909 struct __ec_todo_unpacked {
2910 uint32_t offset;
2911 uint32_t num_entries;
2912 } read_buffer;
2913 };
2914} __ec_todo_packed;
2915
2916struct ec_response_port80_read {
2917 union {
2918 struct __ec_todo_unpacked {
2919 uint32_t writes;
2920 uint32_t history_size;
2921 uint32_t last_boot;
2922 } get_info;
2923 struct __ec_todo_unpacked {
2924 uint16_t codes[EC_PORT80_SIZE_MAX];
2925 } data;
2926 };
2927} __ec_todo_packed;
2928
2929struct ec_response_port80_last_boot {
2930 uint16_t code;
2931} __ec_align2;
2932
2933
2934
2935
2936
2937#define EC_VSTORE_SLOT_SIZE 64
2938
2939
2940#define EC_VSTORE_SLOT_MAX 32
2941
2942
2943#define EC_CMD_VSTORE_INFO 0x0049
2944struct ec_response_vstore_info {
2945
2946 uint32_t slot_locked;
2947
2948 uint8_t slot_count;
2949} __ec_align_size1;
2950
2951
2952
2953
2954
2955
2956#define EC_CMD_VSTORE_READ 0x004A
2957
2958struct ec_params_vstore_read {
2959 uint8_t slot;
2960} __ec_align1;
2961
2962struct ec_response_vstore_read {
2963 uint8_t data[EC_VSTORE_SLOT_SIZE];
2964} __ec_align1;
2965
2966
2967
2968
2969#define EC_CMD_VSTORE_WRITE 0x004B
2970
2971struct ec_params_vstore_write {
2972 uint8_t slot;
2973 uint8_t data[EC_VSTORE_SLOT_SIZE];
2974} __ec_align1;
2975
2976
2977
2978
2979
2980
2981
2982
2983#define EC_CMD_THERMAL_SET_THRESHOLD 0x0050
2984#define EC_CMD_THERMAL_GET_THRESHOLD 0x0051
2985
2986
2987
2988
2989
2990
2991struct ec_params_thermal_set_threshold {
2992 uint8_t sensor_type;
2993 uint8_t threshold_id;
2994 uint16_t value;
2995} __ec_align2;
2996
2997
2998struct ec_params_thermal_get_threshold {
2999 uint8_t sensor_type;
3000 uint8_t threshold_id;
3001} __ec_align1;
3002
3003struct ec_response_thermal_get_threshold {
3004 uint16_t value;
3005} __ec_align2;
3006
3007
3008
3009enum ec_temp_thresholds {
3010 EC_TEMP_THRESH_WARN = 0,
3011 EC_TEMP_THRESH_HIGH,
3012 EC_TEMP_THRESH_HALT,
3013
3014 EC_TEMP_THRESH_COUNT
3015};
3016
3017
3018
3019
3020
3021
3022
3023
3024
3025
3026
3027
3028
3029
3030
3031
3032
3033
3034
3035
3036
3037
3038
3039struct ec_thermal_config {
3040 uint32_t temp_host[EC_TEMP_THRESH_COUNT];
3041 uint32_t temp_host_release[EC_TEMP_THRESH_COUNT];
3042 uint32_t temp_fan_off;
3043 uint32_t temp_fan_max;
3044} __ec_align4;
3045
3046
3047struct ec_params_thermal_get_threshold_v1 {
3048 uint32_t sensor_num;
3049} __ec_align4;
3050
3051
3052
3053
3054
3055
3056struct ec_params_thermal_set_threshold_v1 {
3057 uint32_t sensor_num;
3058 struct ec_thermal_config cfg;
3059} __ec_align4;
3060
3061
3062
3063
3064
3065#define EC_CMD_THERMAL_AUTO_FAN_CTRL 0x0052
3066
3067
3068struct ec_params_auto_fan_ctrl_v1 {
3069 uint8_t fan_idx;
3070} __ec_align1;
3071
3072
3073#define EC_CMD_TMP006_GET_CALIBRATION 0x0053
3074#define EC_CMD_TMP006_SET_CALIBRATION 0x0054
3075
3076
3077
3078
3079
3080
3081
3082
3083
3084
3085
3086struct ec_params_tmp006_get_calibration {
3087 uint8_t index;
3088} __ec_align1;
3089
3090
3091struct ec_response_tmp006_get_calibration_v0 {
3092 float s0;
3093 float b0;
3094 float b1;
3095 float b2;
3096} __ec_align4;
3097
3098struct ec_params_tmp006_set_calibration_v0 {
3099 uint8_t index;
3100 uint8_t reserved[3];
3101 float s0;
3102 float b0;
3103 float b1;
3104 float b2;
3105} __ec_align4;
3106
3107
3108struct ec_response_tmp006_get_calibration_v1 {
3109 uint8_t algorithm;
3110 uint8_t num_params;
3111 uint8_t reserved[2];
3112 float val[];
3113} __ec_align4;
3114
3115struct ec_params_tmp006_set_calibration_v1 {
3116 uint8_t index;
3117 uint8_t algorithm;
3118 uint8_t num_params;
3119 uint8_t reserved;
3120 float val[];
3121} __ec_align4;
3122
3123
3124
3125#define EC_CMD_TMP006_GET_RAW 0x0055
3126
3127struct ec_params_tmp006_get_raw {
3128 uint8_t index;
3129} __ec_align1;
3130
3131struct ec_response_tmp006_get_raw {
3132 int32_t t;
3133 int32_t v;
3134} __ec_align4;
3135
3136
3137
3138
3139
3140
3141
3142
3143
3144
3145
3146
3147
3148
3149#define EC_CMD_MKBP_STATE 0x0060
3150
3151
3152
3153
3154#define EC_CMD_MKBP_INFO 0x0061
3155
3156struct ec_response_mkbp_info {
3157 uint32_t rows;
3158 uint32_t cols;
3159
3160 uint8_t reserved;
3161} __ec_align_size1;
3162
3163struct ec_params_mkbp_info {
3164 uint8_t info_type;
3165 uint8_t event_type;
3166} __ec_align1;
3167
3168enum ec_mkbp_info_type {
3169
3170
3171
3172
3173
3174 EC_MKBP_INFO_KBD = 0,
3175
3176
3177
3178
3179
3180
3181
3182
3183
3184
3185 EC_MKBP_INFO_SUPPORTED = 1,
3186
3187
3188
3189
3190
3191
3192
3193
3194
3195
3196
3197
3198
3199
3200
3201
3202
3203
3204 EC_MKBP_INFO_CURRENT = 2,
3205};
3206
3207
3208#define EC_CMD_MKBP_SIMULATE_KEY 0x0062
3209
3210struct ec_params_mkbp_simulate_key {
3211 uint8_t col;
3212 uint8_t row;
3213 uint8_t pressed;
3214} __ec_align1;
3215
3216#define EC_CMD_GET_KEYBOARD_ID 0x0063
3217
3218struct ec_response_keyboard_id {
3219 uint32_t keyboard_id;
3220} __ec_align4;
3221
3222enum keyboard_id {
3223 KEYBOARD_ID_UNSUPPORTED = 0,
3224 KEYBOARD_ID_UNREADABLE = 0xffffffff,
3225};
3226
3227
3228#define EC_CMD_MKBP_SET_CONFIG 0x0064
3229#define EC_CMD_MKBP_GET_CONFIG 0x0065
3230
3231
3232enum mkbp_config_flags {
3233 EC_MKBP_FLAGS_ENABLE = 1,
3234};
3235
3236enum mkbp_config_valid {
3237 EC_MKBP_VALID_SCAN_PERIOD = BIT(0),
3238 EC_MKBP_VALID_POLL_TIMEOUT = BIT(1),
3239 EC_MKBP_VALID_MIN_POST_SCAN_DELAY = BIT(3),
3240 EC_MKBP_VALID_OUTPUT_SETTLE = BIT(4),
3241 EC_MKBP_VALID_DEBOUNCE_DOWN = BIT(5),
3242 EC_MKBP_VALID_DEBOUNCE_UP = BIT(6),
3243 EC_MKBP_VALID_FIFO_MAX_DEPTH = BIT(7),
3244};
3245
3246
3247
3248
3249
3250
3251
3252struct ec_mkbp_config {
3253 uint32_t valid_mask;
3254 uint8_t flags;
3255 uint8_t valid_flags;
3256 uint16_t scan_period_us;
3257
3258 uint32_t poll_timeout_us;
3259
3260
3261
3262
3263
3264 uint16_t min_post_scan_delay_us;
3265
3266 uint16_t output_settle_us;
3267 uint16_t debounce_down_us;
3268 uint16_t debounce_up_us;
3269
3270 uint8_t fifo_max_depth;
3271} __ec_align_size1;
3272
3273struct ec_params_mkbp_set_config {
3274 struct ec_mkbp_config config;
3275} __ec_align_size1;
3276
3277struct ec_response_mkbp_get_config {
3278 struct ec_mkbp_config config;
3279} __ec_align_size1;
3280
3281
3282#define EC_CMD_KEYSCAN_SEQ_CTRL 0x0066
3283
3284enum ec_keyscan_seq_cmd {
3285 EC_KEYSCAN_SEQ_STATUS = 0,
3286 EC_KEYSCAN_SEQ_CLEAR = 1,
3287 EC_KEYSCAN_SEQ_ADD = 2,
3288 EC_KEYSCAN_SEQ_START = 3,
3289 EC_KEYSCAN_SEQ_COLLECT = 4,
3290};
3291
3292enum ec_collect_flags {
3293
3294
3295
3296
3297 EC_KEYSCAN_SEQ_FLAG_DONE = BIT(0),
3298};
3299
3300struct ec_collect_item {
3301 uint8_t flags;
3302} __ec_align1;
3303
3304struct ec_params_keyscan_seq_ctrl {
3305 uint8_t cmd;
3306 union {
3307 struct __ec_align1 {
3308 uint8_t active;
3309 uint8_t num_items;
3310
3311 uint8_t cur_item;
3312 } status;
3313 struct __ec_todo_unpacked {
3314
3315
3316
3317
3318 uint32_t time_us;
3319 uint8_t scan[0];
3320 } add;
3321 struct __ec_align1 {
3322 uint8_t start_item;
3323 uint8_t num_items;
3324 } collect;
3325 };
3326} __ec_todo_packed;
3327
3328struct ec_result_keyscan_seq_ctrl {
3329 union {
3330 struct __ec_todo_unpacked {
3331 uint8_t num_items;
3332
3333 struct ec_collect_item item[0];
3334 } collect;
3335 };
3336} __ec_todo_packed;
3337
3338
3339
3340
3341
3342
3343#define EC_CMD_GET_NEXT_EVENT 0x0067
3344
3345#define EC_MKBP_HAS_MORE_EVENTS_SHIFT 7
3346
3347
3348
3349
3350
3351#define EC_MKBP_HAS_MORE_EVENTS BIT(EC_MKBP_HAS_MORE_EVENTS_SHIFT)
3352
3353
3354#define EC_MKBP_EVENT_TYPE_MASK (BIT(EC_MKBP_HAS_MORE_EVENTS_SHIFT) - 1)
3355
3356enum ec_mkbp_event {
3357
3358 EC_MKBP_EVENT_KEY_MATRIX = 0,
3359
3360
3361 EC_MKBP_EVENT_HOST_EVENT = 1,
3362
3363
3364 EC_MKBP_EVENT_SENSOR_FIFO = 2,
3365
3366
3367 EC_MKBP_EVENT_BUTTON = 3,
3368
3369
3370 EC_MKBP_EVENT_SWITCH = 4,
3371
3372
3373 EC_MKBP_EVENT_FINGERPRINT = 5,
3374
3375
3376
3377
3378
3379 EC_MKBP_EVENT_SYSRQ = 6,
3380
3381
3382
3383
3384
3385 EC_MKBP_EVENT_HOST_EVENT64 = 7,
3386
3387
3388 EC_MKBP_EVENT_CEC_EVENT = 8,
3389
3390
3391 EC_MKBP_EVENT_CEC_MESSAGE = 9,
3392
3393
3394 EC_MKBP_EVENT_PCHG = 12,
3395
3396
3397 EC_MKBP_EVENT_COUNT,
3398};
3399BUILD_ASSERT(EC_MKBP_EVENT_COUNT <= EC_MKBP_EVENT_TYPE_MASK);
3400
3401union __ec_align_offset1 ec_response_get_next_data {
3402 uint8_t key_matrix[13];
3403
3404
3405 uint32_t host_event;
3406 uint64_t host_event64;
3407
3408 struct __ec_todo_unpacked {
3409
3410 uint8_t reserved[3];
3411 struct ec_response_motion_sense_fifo_info info;
3412 } sensor_fifo;
3413
3414 uint32_t buttons;
3415
3416 uint32_t switches;
3417
3418 uint32_t fp_events;
3419
3420 uint32_t sysrq;
3421
3422
3423 uint32_t cec_events;
3424};
3425
3426union __ec_align_offset1 ec_response_get_next_data_v1 {
3427 uint8_t key_matrix[16];
3428
3429
3430 uint32_t host_event;
3431 uint64_t host_event64;
3432
3433 struct __ec_todo_unpacked {
3434
3435 uint8_t reserved[3];
3436 struct ec_response_motion_sense_fifo_info info;
3437 } sensor_fifo;
3438
3439 uint32_t buttons;
3440
3441 uint32_t switches;
3442
3443 uint32_t fp_events;
3444
3445 uint32_t sysrq;
3446
3447
3448 uint32_t cec_events;
3449
3450 uint8_t cec_message[16];
3451};
3452BUILD_ASSERT(sizeof(union ec_response_get_next_data_v1) == 16);
3453
3454struct ec_response_get_next_event {
3455 uint8_t event_type;
3456
3457 union ec_response_get_next_data data;
3458} __ec_align1;
3459
3460struct ec_response_get_next_event_v1 {
3461 uint8_t event_type;
3462
3463 union ec_response_get_next_data_v1 data;
3464} __ec_align1;
3465
3466
3467
3468#define EC_MKBP_POWER_BUTTON 0
3469#define EC_MKBP_VOL_UP 1
3470#define EC_MKBP_VOL_DOWN 2
3471#define EC_MKBP_RECOVERY 3
3472
3473
3474#define EC_MKBP_LID_OPEN 0
3475#define EC_MKBP_TABLET_MODE 1
3476#define EC_MKBP_BASE_ATTACHED 2
3477#define EC_MKBP_FRONT_PROXIMITY 3
3478
3479
3480#define EC_CMD_KEYBOARD_FACTORY_TEST 0x0068
3481
3482struct ec_response_keyboard_factory_test {
3483 uint16_t shorted;
3484} __ec_align2;
3485
3486
3487#define EC_MKBP_FP_RAW_EVENT(fp_events) ((fp_events) & 0x00FFFFFF)
3488#define EC_MKBP_FP_ERRCODE(fp_events) ((fp_events) & 0x0000000F)
3489#define EC_MKBP_FP_ENROLL_PROGRESS_OFFSET 4
3490#define EC_MKBP_FP_ENROLL_PROGRESS(fpe) (((fpe) & 0x00000FF0) \
3491 >> EC_MKBP_FP_ENROLL_PROGRESS_OFFSET)
3492#define EC_MKBP_FP_MATCH_IDX_OFFSET 12
3493#define EC_MKBP_FP_MATCH_IDX_MASK 0x0000F000
3494#define EC_MKBP_FP_MATCH_IDX(fpe) (((fpe) & EC_MKBP_FP_MATCH_IDX_MASK) \
3495 >> EC_MKBP_FP_MATCH_IDX_OFFSET)
3496#define EC_MKBP_FP_ENROLL BIT(27)
3497#define EC_MKBP_FP_MATCH BIT(28)
3498#define EC_MKBP_FP_FINGER_DOWN BIT(29)
3499#define EC_MKBP_FP_FINGER_UP BIT(30)
3500#define EC_MKBP_FP_IMAGE_READY BIT(31)
3501
3502#define EC_MKBP_FP_ERR_ENROLL_OK 0
3503#define EC_MKBP_FP_ERR_ENROLL_LOW_QUALITY 1
3504#define EC_MKBP_FP_ERR_ENROLL_IMMOBILE 2
3505#define EC_MKBP_FP_ERR_ENROLL_LOW_COVERAGE 3
3506#define EC_MKBP_FP_ERR_ENROLL_INTERNAL 5
3507
3508#define EC_MKBP_FP_ERR_ENROLL_PROBLEM_MASK 1
3509
3510#define EC_MKBP_FP_ERR_MATCH_NO 0
3511#define EC_MKBP_FP_ERR_MATCH_NO_INTERNAL 6
3512#define EC_MKBP_FP_ERR_MATCH_NO_TEMPLATES 7
3513#define EC_MKBP_FP_ERR_MATCH_NO_LOW_QUALITY 2
3514#define EC_MKBP_FP_ERR_MATCH_NO_LOW_COVERAGE 4
3515#define EC_MKBP_FP_ERR_MATCH_YES 1
3516#define EC_MKBP_FP_ERR_MATCH_YES_UPDATED 3
3517#define EC_MKBP_FP_ERR_MATCH_YES_UPDATE_FAILED 5
3518
3519
3520
3521
3522
3523
3524#define EC_CMD_TEMP_SENSOR_GET_INFO 0x0070
3525
3526struct ec_params_temp_sensor_get_info {
3527 uint8_t id;
3528} __ec_align1;
3529
3530struct ec_response_temp_sensor_get_info {
3531 char sensor_name[32];
3532 uint8_t sensor_type;
3533} __ec_align1;
3534
3535
3536
3537
3538
3539
3540
3541
3542
3543
3544
3545
3546
3547
3548
3549
3550
3551
3552struct ec_params_host_event_mask {
3553 uint32_t mask;
3554} __ec_align4;
3555
3556struct ec_response_host_event_mask {
3557 uint32_t mask;
3558} __ec_align4;
3559
3560
3561#define EC_CMD_HOST_EVENT_GET_B 0x0087
3562#define EC_CMD_HOST_EVENT_GET_SMI_MASK 0x0088
3563#define EC_CMD_HOST_EVENT_GET_SCI_MASK 0x0089
3564#define EC_CMD_HOST_EVENT_GET_WAKE_MASK 0x008D
3565
3566
3567#define EC_CMD_HOST_EVENT_SET_SMI_MASK 0x008A
3568#define EC_CMD_HOST_EVENT_SET_SCI_MASK 0x008B
3569#define EC_CMD_HOST_EVENT_CLEAR 0x008C
3570#define EC_CMD_HOST_EVENT_SET_WAKE_MASK 0x008E
3571#define EC_CMD_HOST_EVENT_CLEAR_B 0x008F
3572
3573
3574
3575
3576
3577
3578struct ec_params_host_event {
3579
3580
3581 uint8_t action;
3582
3583
3584
3585
3586
3587 uint8_t mask_type;
3588
3589
3590 uint16_t reserved;
3591
3592
3593 uint64_t value;
3594} __ec_align4;
3595
3596
3597
3598
3599
3600
3601struct ec_response_host_event {
3602
3603
3604 uint64_t value;
3605} __ec_align4;
3606
3607enum ec_host_event_action {
3608
3609
3610
3611
3612 EC_HOST_EVENT_GET,
3613
3614
3615 EC_HOST_EVENT_SET,
3616
3617
3618 EC_HOST_EVENT_CLEAR,
3619};
3620
3621enum ec_host_event_mask_type {
3622
3623
3624 EC_HOST_EVENT_MAIN,
3625
3626
3627 EC_HOST_EVENT_B,
3628
3629
3630 EC_HOST_EVENT_SCI_MASK,
3631
3632
3633 EC_HOST_EVENT_SMI_MASK,
3634
3635
3636 EC_HOST_EVENT_ALWAYS_REPORT_MASK,
3637
3638
3639 EC_HOST_EVENT_ACTIVE_WAKE_MASK,
3640
3641
3642 EC_HOST_EVENT_LAZY_WAKE_MASK_S0IX,
3643
3644
3645 EC_HOST_EVENT_LAZY_WAKE_MASK_S3,
3646
3647
3648 EC_HOST_EVENT_LAZY_WAKE_MASK_S5,
3649};
3650
3651#define EC_CMD_HOST_EVENT 0x00A4
3652
3653
3654
3655
3656
3657#define EC_CMD_SWITCH_ENABLE_BKLIGHT 0x0090
3658
3659struct ec_params_switch_enable_backlight {
3660 uint8_t enabled;
3661} __ec_align1;
3662
3663
3664#define EC_CMD_SWITCH_ENABLE_WIRELESS 0x0091
3665#define EC_VER_SWITCH_ENABLE_WIRELESS 1
3666
3667
3668struct ec_params_switch_enable_wireless_v0 {
3669 uint8_t enabled;
3670} __ec_align1;
3671
3672
3673struct ec_params_switch_enable_wireless_v1 {
3674
3675 uint8_t now_flags;
3676
3677
3678 uint8_t now_mask;
3679
3680
3681
3682
3683
3684
3685 uint8_t suspend_flags;
3686
3687
3688 uint8_t suspend_mask;
3689} __ec_align1;
3690
3691
3692struct ec_response_switch_enable_wireless_v1 {
3693
3694 uint8_t now_flags;
3695
3696
3697 uint8_t suspend_flags;
3698} __ec_align1;
3699
3700
3701
3702
3703
3704#define EC_CMD_GPIO_SET 0x0092
3705
3706struct ec_params_gpio_set {
3707 char name[32];
3708 uint8_t val;
3709} __ec_align1;
3710
3711
3712#define EC_CMD_GPIO_GET 0x0093
3713
3714
3715struct ec_params_gpio_get {
3716 char name[32];
3717} __ec_align1;
3718
3719struct ec_response_gpio_get {
3720 uint8_t val;
3721} __ec_align1;
3722
3723
3724struct ec_params_gpio_get_v1 {
3725 uint8_t subcmd;
3726 union {
3727 struct __ec_align1 {
3728 char name[32];
3729 } get_value_by_name;
3730 struct __ec_align1 {
3731 uint8_t index;
3732 } get_info;
3733 };
3734} __ec_align1;
3735
3736struct ec_response_gpio_get_v1 {
3737 union {
3738 struct __ec_align1 {
3739 uint8_t val;
3740 } get_value_by_name, get_count;
3741 struct __ec_todo_unpacked {
3742 uint8_t val;
3743 char name[32];
3744 uint32_t flags;
3745 } get_info;
3746 };
3747} __ec_todo_packed;
3748
3749enum gpio_get_subcmd {
3750 EC_GPIO_GET_BY_NAME = 0,
3751 EC_GPIO_GET_COUNT = 1,
3752 EC_GPIO_GET_INFO = 2,
3753};
3754
3755
3756
3757
3758
3759
3760
3761
3762
3763
3764
3765
3766#define EC_CMD_I2C_READ 0x0094
3767
3768struct ec_params_i2c_read {
3769 uint16_t addr;
3770 uint8_t read_size;
3771 uint8_t port;
3772 uint8_t offset;
3773} __ec_align_size1;
3774
3775struct ec_response_i2c_read {
3776 uint16_t data;
3777} __ec_align2;
3778
3779
3780#define EC_CMD_I2C_WRITE 0x0095
3781
3782struct ec_params_i2c_write {
3783 uint16_t data;
3784 uint16_t addr;
3785 uint8_t write_size;
3786 uint8_t port;
3787 uint8_t offset;
3788} __ec_align_size1;
3789
3790
3791
3792
3793
3794
3795
3796#define EC_CMD_CHARGE_CONTROL 0x0096
3797#define EC_VER_CHARGE_CONTROL 1
3798
3799enum ec_charge_control_mode {
3800 CHARGE_CONTROL_NORMAL = 0,
3801 CHARGE_CONTROL_IDLE,
3802 CHARGE_CONTROL_DISCHARGE,
3803};
3804
3805struct ec_params_charge_control {
3806 uint32_t mode;
3807} __ec_align4;
3808
3809
3810
3811
3812#define EC_CMD_CONSOLE_SNAPSHOT 0x0097
3813
3814
3815
3816
3817
3818
3819
3820
3821
3822
3823
3824
3825
3826#define EC_CMD_CONSOLE_READ 0x0098
3827
3828enum ec_console_read_subcmd {
3829 CONSOLE_READ_NEXT = 0,
3830 CONSOLE_READ_RECENT
3831};
3832
3833struct ec_params_console_read_v1 {
3834 uint8_t subcmd;
3835} __ec_align1;
3836
3837
3838
3839
3840
3841
3842
3843
3844
3845
3846#define EC_CMD_BATTERY_CUT_OFF 0x0099
3847
3848#define EC_BATTERY_CUTOFF_FLAG_AT_SHUTDOWN BIT(0)
3849
3850struct ec_params_battery_cutoff {
3851 uint8_t flags;
3852} __ec_align1;
3853
3854
3855
3856
3857
3858
3859
3860#define EC_CMD_USB_MUX 0x009A
3861
3862struct ec_params_usb_mux {
3863 uint8_t mux;
3864} __ec_align1;
3865
3866
3867
3868
3869enum ec_ldo_state {
3870 EC_LDO_STATE_OFF = 0,
3871 EC_LDO_STATE_ON = 1,
3872};
3873
3874
3875
3876
3877#define EC_CMD_LDO_SET 0x009B
3878
3879struct ec_params_ldo_set {
3880 uint8_t index;
3881 uint8_t state;
3882} __ec_align1;
3883
3884
3885
3886
3887#define EC_CMD_LDO_GET 0x009C
3888
3889struct ec_params_ldo_get {
3890 uint8_t index;
3891} __ec_align1;
3892
3893struct ec_response_ldo_get {
3894 uint8_t state;
3895} __ec_align1;
3896
3897
3898
3899
3900
3901
3902
3903#define EC_CMD_POWER_INFO 0x009D
3904
3905struct ec_response_power_info {
3906 uint32_t usb_dev_type;
3907 uint16_t voltage_ac;
3908 uint16_t voltage_system;
3909 uint16_t current_system;
3910 uint16_t usb_current_limit;
3911} __ec_align4;
3912
3913
3914
3915
3916#define EC_CMD_I2C_PASSTHRU 0x009E
3917
3918
3919#define EC_I2C_FLAG_READ BIT(15)
3920
3921
3922#define EC_I2C_ADDR_MASK 0x3ff
3923
3924#define EC_I2C_STATUS_NAK BIT(0)
3925#define EC_I2C_STATUS_TIMEOUT BIT(1)
3926
3927
3928#define EC_I2C_STATUS_ERROR (EC_I2C_STATUS_NAK | EC_I2C_STATUS_TIMEOUT)
3929
3930struct ec_params_i2c_passthru_msg {
3931 uint16_t addr_flags;
3932 uint16_t len;
3933} __ec_align2;
3934
3935struct ec_params_i2c_passthru {
3936 uint8_t port;
3937 uint8_t num_msgs;
3938 struct ec_params_i2c_passthru_msg msg[];
3939
3940} __ec_align2;
3941
3942struct ec_response_i2c_passthru {
3943 uint8_t i2c_status;
3944 uint8_t num_msgs;
3945 uint8_t data[];
3946} __ec_align1;
3947
3948
3949
3950
3951#define EC_CMD_HANG_DETECT 0x009F
3952
3953
3954
3955#define EC_HANG_START_ON_POWER_PRESS BIT(0)
3956
3957
3958#define EC_HANG_START_ON_LID_CLOSE BIT(1)
3959
3960
3961#define EC_HANG_START_ON_LID_OPEN BIT(2)
3962
3963
3964#define EC_HANG_START_ON_RESUME BIT(3)
3965
3966
3967
3968
3969#define EC_HANG_STOP_ON_POWER_RELEASE BIT(8)
3970
3971
3972#define EC_HANG_STOP_ON_HOST_COMMAND BIT(9)
3973
3974
3975#define EC_HANG_STOP_ON_SUSPEND BIT(10)
3976
3977
3978
3979
3980
3981
3982
3983#define EC_HANG_START_NOW BIT(30)
3984
3985
3986
3987
3988
3989
3990#define EC_HANG_STOP_NOW BIT(31)
3991
3992struct ec_params_hang_detect {
3993
3994 uint32_t flags;
3995
3996
3997 uint16_t host_event_timeout_msec;
3998
3999
4000 uint16_t warm_reboot_timeout_msec;
4001} __ec_align4;
4002
4003
4004
4005
4006
4007
4008
4009
4010#define EC_CMD_CHARGE_STATE 0x00A0
4011
4012
4013enum charge_state_command {
4014 CHARGE_STATE_CMD_GET_STATE,
4015 CHARGE_STATE_CMD_GET_PARAM,
4016 CHARGE_STATE_CMD_SET_PARAM,
4017 CHARGE_STATE_NUM_CMDS
4018};
4019
4020
4021
4022
4023
4024enum charge_state_params {
4025 CS_PARAM_CHG_VOLTAGE,
4026 CS_PARAM_CHG_CURRENT,
4027 CS_PARAM_CHG_INPUT_CURRENT,
4028 CS_PARAM_CHG_STATUS,
4029 CS_PARAM_CHG_OPTION,
4030 CS_PARAM_LIMIT_POWER,
4031
4032
4033
4034
4035
4036 CS_NUM_BASE_PARAMS,
4037
4038
4039 CS_PARAM_CUSTOM_PROFILE_MIN = 0x10000,
4040 CS_PARAM_CUSTOM_PROFILE_MAX = 0x1ffff,
4041
4042
4043 CS_PARAM_DEBUG_MIN = 0x20000,
4044 CS_PARAM_DEBUG_CTL_MODE = 0x20000,
4045 CS_PARAM_DEBUG_MANUAL_MODE,
4046 CS_PARAM_DEBUG_SEEMS_DEAD,
4047 CS_PARAM_DEBUG_SEEMS_DISCONNECTED,
4048 CS_PARAM_DEBUG_BATT_REMOVED,
4049 CS_PARAM_DEBUG_MANUAL_CURRENT,
4050 CS_PARAM_DEBUG_MANUAL_VOLTAGE,
4051 CS_PARAM_DEBUG_MAX = 0x2ffff,
4052
4053
4054};
4055
4056struct ec_params_charge_state {
4057 uint8_t cmd;
4058 union {
4059
4060
4061 struct __ec_todo_unpacked {
4062 uint32_t param;
4063 } get_param;
4064
4065 struct __ec_todo_unpacked {
4066 uint32_t param;
4067 uint32_t value;
4068 } set_param;
4069 };
4070} __ec_todo_packed;
4071
4072struct ec_response_charge_state {
4073 union {
4074 struct __ec_align4 {
4075 int ac;
4076 int chg_voltage;
4077 int chg_current;
4078 int chg_input_current;
4079 int batt_state_of_charge;
4080 } get_state;
4081
4082 struct __ec_align4 {
4083 uint32_t value;
4084 } get_param;
4085
4086
4087 };
4088} __ec_align4;
4089
4090
4091
4092
4093
4094#define EC_CMD_CHARGE_CURRENT_LIMIT 0x00A1
4095
4096struct ec_params_current_limit {
4097 uint32_t limit;
4098} __ec_align4;
4099
4100
4101
4102
4103#define EC_CMD_EXTERNAL_POWER_LIMIT 0x00A2
4104
4105
4106struct ec_params_external_power_limit_v1 {
4107 uint16_t current_lim;
4108 uint16_t voltage_lim;
4109} __ec_align2;
4110
4111#define EC_POWER_LIMIT_NONE 0xffff
4112
4113
4114
4115
4116#define EC_CMD_OVERRIDE_DEDICATED_CHARGER_LIMIT 0x00A3
4117
4118struct ec_params_dedicated_charger_limit {
4119 uint16_t current_lim;
4120 uint16_t voltage_lim;
4121} __ec_align2;
4122
4123
4124
4125
4126
4127#define EC_CMD_HIBERNATION_DELAY 0x00A8
4128
4129struct ec_params_hibernation_delay {
4130
4131
4132
4133
4134 uint32_t seconds;
4135} __ec_align4;
4136
4137struct ec_response_hibernation_delay {
4138
4139
4140
4141
4142 uint32_t time_g3;
4143
4144
4145
4146
4147
4148 uint32_t time_remaining;
4149
4150
4151
4152
4153
4154 uint32_t hibernate_delay;
4155} __ec_align4;
4156
4157
4158#define EC_CMD_HOST_SLEEP_EVENT 0x00A9
4159
4160enum host_sleep_event {
4161 HOST_SLEEP_EVENT_S3_SUSPEND = 1,
4162 HOST_SLEEP_EVENT_S3_RESUME = 2,
4163 HOST_SLEEP_EVENT_S0IX_SUSPEND = 3,
4164 HOST_SLEEP_EVENT_S0IX_RESUME = 4,
4165
4166 HOST_SLEEP_EVENT_S3_WAKEABLE_SUSPEND = 5,
4167};
4168
4169struct ec_params_host_sleep_event {
4170 uint8_t sleep_event;
4171} __ec_align1;
4172
4173
4174
4175
4176
4177#define EC_HOST_SLEEP_TIMEOUT_DEFAULT 0
4178
4179
4180#define EC_HOST_SLEEP_TIMEOUT_INFINITE 0xFFFF
4181
4182struct ec_params_host_sleep_event_v1 {
4183
4184 uint8_t sleep_event;
4185
4186
4187 uint8_t reserved;
4188 union {
4189
4190 struct {
4191
4192
4193
4194
4195
4196
4197 uint16_t sleep_timeout_ms;
4198 } suspend_params;
4199
4200
4201 };
4202} __ec_align2;
4203
4204
4205#define EC_HOST_RESUME_SLEEP_TIMEOUT 0x80000000
4206
4207
4208
4209
4210
4211
4212#define EC_HOST_RESUME_SLEEP_TRANSITIONS_MASK 0x7FFFFFFF
4213
4214struct ec_response_host_sleep_event_v1 {
4215 union {
4216
4217 struct {
4218
4219
4220
4221
4222
4223 uint32_t sleep_transitions;
4224 } resume_response;
4225
4226
4227 };
4228} __ec_align4;
4229
4230
4231
4232#define EC_CMD_DEVICE_EVENT 0x00AA
4233
4234enum ec_device_event {
4235 EC_DEVICE_EVENT_TRACKPAD,
4236 EC_DEVICE_EVENT_DSP,
4237 EC_DEVICE_EVENT_WIFI,
4238 EC_DEVICE_EVENT_WLC,
4239};
4240
4241enum ec_device_event_param {
4242
4243 EC_DEVICE_EVENT_PARAM_GET_CURRENT_EVENTS,
4244
4245 EC_DEVICE_EVENT_PARAM_GET_ENABLED_EVENTS,
4246
4247 EC_DEVICE_EVENT_PARAM_SET_ENABLED_EVENTS,
4248};
4249
4250#define EC_DEVICE_EVENT_MASK(event_code) BIT(event_code % 32)
4251
4252struct ec_params_device_event {
4253 uint32_t event_mask;
4254 uint8_t param;
4255} __ec_align_size1;
4256
4257struct ec_response_device_event {
4258 uint32_t event_mask;
4259} __ec_align4;
4260
4261
4262
4263
4264
4265#define EC_CMD_SB_READ_WORD 0x00B0
4266#define EC_CMD_SB_WRITE_WORD 0x00B1
4267
4268
4269
4270
4271#define EC_CMD_SB_READ_BLOCK 0x00B2
4272#define EC_CMD_SB_WRITE_BLOCK 0x00B3
4273
4274struct ec_params_sb_rd {
4275 uint8_t reg;
4276} __ec_align1;
4277
4278struct ec_response_sb_rd_word {
4279 uint16_t value;
4280} __ec_align2;
4281
4282struct ec_params_sb_wr_word {
4283 uint8_t reg;
4284 uint16_t value;
4285} __ec_align1;
4286
4287struct ec_response_sb_rd_block {
4288 uint8_t data[32];
4289} __ec_align1;
4290
4291struct ec_params_sb_wr_block {
4292 uint8_t reg;
4293 uint16_t data[32];
4294} __ec_align1;
4295
4296
4297
4298
4299
4300
4301
4302
4303
4304
4305#define EC_CMD_BATTERY_VENDOR_PARAM 0x00B4
4306
4307enum ec_battery_vendor_param_mode {
4308 BATTERY_VENDOR_PARAM_MODE_GET = 0,
4309 BATTERY_VENDOR_PARAM_MODE_SET,
4310};
4311
4312struct ec_params_battery_vendor_param {
4313 uint32_t param;
4314 uint32_t value;
4315 uint8_t mode;
4316} __ec_align_size1;
4317
4318struct ec_response_battery_vendor_param {
4319 uint32_t value;
4320} __ec_align4;
4321
4322
4323
4324
4325
4326#define EC_CMD_SB_FW_UPDATE 0x00B5
4327
4328enum ec_sb_fw_update_subcmd {
4329 EC_SB_FW_UPDATE_PREPARE = 0x0,
4330 EC_SB_FW_UPDATE_INFO = 0x1,
4331 EC_SB_FW_UPDATE_BEGIN = 0x2,
4332 EC_SB_FW_UPDATE_WRITE = 0x3,
4333 EC_SB_FW_UPDATE_END = 0x4,
4334 EC_SB_FW_UPDATE_STATUS = 0x5,
4335 EC_SB_FW_UPDATE_PROTECT = 0x6,
4336 EC_SB_FW_UPDATE_MAX = 0x7,
4337};
4338
4339#define SB_FW_UPDATE_CMD_WRITE_BLOCK_SIZE 32
4340#define SB_FW_UPDATE_CMD_STATUS_SIZE 2
4341#define SB_FW_UPDATE_CMD_INFO_SIZE 8
4342
4343struct ec_sb_fw_update_header {
4344 uint16_t subcmd;
4345 uint16_t fw_id;
4346} __ec_align4;
4347
4348struct ec_params_sb_fw_update {
4349 struct ec_sb_fw_update_header hdr;
4350 union {
4351
4352
4353
4354
4355
4356
4357
4358
4359
4360 struct __ec_align4 {
4361 uint8_t data[SB_FW_UPDATE_CMD_WRITE_BLOCK_SIZE];
4362 } write;
4363 };
4364} __ec_align4;
4365
4366struct ec_response_sb_fw_update {
4367 union {
4368
4369 struct __ec_align1 {
4370 uint8_t data[SB_FW_UPDATE_CMD_INFO_SIZE];
4371 } info;
4372
4373
4374 struct __ec_align1 {
4375 uint8_t data[SB_FW_UPDATE_CMD_STATUS_SIZE];
4376 } status;
4377 };
4378} __ec_align1;
4379
4380
4381
4382
4383
4384
4385#define EC_CMD_ENTERING_MODE 0x00B6
4386
4387struct ec_params_entering_mode {
4388 int vboot_mode;
4389} __ec_align4;
4390
4391#define VBOOT_MODE_NORMAL 0
4392#define VBOOT_MODE_DEVELOPER 1
4393#define VBOOT_MODE_RECOVERY 2
4394
4395
4396
4397
4398
4399
4400#define EC_CMD_I2C_PASSTHRU_PROTECT 0x00B7
4401
4402enum ec_i2c_passthru_protect_subcmd {
4403 EC_CMD_I2C_PASSTHRU_PROTECT_STATUS = 0x0,
4404 EC_CMD_I2C_PASSTHRU_PROTECT_ENABLE = 0x1,
4405};
4406
4407struct ec_params_i2c_passthru_protect {
4408 uint8_t subcmd;
4409 uint8_t port;
4410} __ec_align1;
4411
4412struct ec_response_i2c_passthru_protect {
4413 uint8_t status;
4414} __ec_align1;
4415
4416
4417
4418
4419
4420
4421
4422
4423
4424#define MAX_CEC_MSG_LEN 16
4425
4426
4427#define EC_CMD_CEC_WRITE_MSG 0x00B8
4428
4429
4430
4431
4432
4433struct ec_params_cec_write {
4434 uint8_t msg[MAX_CEC_MSG_LEN];
4435} __ec_align1;
4436
4437
4438#define EC_CMD_CEC_SET 0x00BA
4439
4440
4441
4442
4443
4444
4445
4446
4447
4448struct ec_params_cec_set {
4449 uint8_t cmd;
4450 uint8_t val;
4451} __ec_align1;
4452
4453
4454#define EC_CMD_CEC_GET 0x00BB
4455
4456
4457
4458
4459
4460struct ec_params_cec_get {
4461 uint8_t cmd;
4462} __ec_align1;
4463
4464
4465
4466
4467
4468
4469
4470
4471struct ec_response_cec_get {
4472 uint8_t val;
4473} __ec_align1;
4474
4475
4476enum cec_command {
4477
4478 CEC_CMD_ENABLE,
4479
4480 CEC_CMD_LOGICAL_ADDRESS,
4481};
4482
4483
4484enum mkbp_cec_event {
4485
4486 EC_MKBP_CEC_SEND_OK = BIT(0),
4487
4488 EC_MKBP_CEC_SEND_FAILED = BIT(1),
4489};
4490
4491
4492
4493
4494#define EC_CMD_EC_CODEC 0x00BC
4495
4496enum ec_codec_subcmd {
4497 EC_CODEC_GET_CAPABILITIES = 0x0,
4498 EC_CODEC_GET_SHM_ADDR = 0x1,
4499 EC_CODEC_SET_SHM_ADDR = 0x2,
4500 EC_CODEC_SUBCMD_COUNT,
4501};
4502
4503enum ec_codec_cap {
4504 EC_CODEC_CAP_WOV_AUDIO_SHM = 0,
4505 EC_CODEC_CAP_WOV_LANG_SHM = 1,
4506 EC_CODEC_CAP_LAST = 32,
4507};
4508
4509enum ec_codec_shm_id {
4510 EC_CODEC_SHM_ID_WOV_AUDIO = 0x0,
4511 EC_CODEC_SHM_ID_WOV_LANG = 0x1,
4512 EC_CODEC_SHM_ID_LAST,
4513};
4514
4515enum ec_codec_shm_type {
4516 EC_CODEC_SHM_TYPE_EC_RAM = 0x0,
4517 EC_CODEC_SHM_TYPE_SYSTEM_RAM = 0x1,
4518};
4519
4520struct __ec_align1 ec_param_ec_codec_get_shm_addr {
4521 uint8_t shm_id;
4522 uint8_t reserved[3];
4523};
4524
4525struct __ec_align4 ec_param_ec_codec_set_shm_addr {
4526 uint64_t phys_addr;
4527 uint32_t len;
4528 uint8_t shm_id;
4529 uint8_t reserved[3];
4530};
4531
4532struct __ec_align4 ec_param_ec_codec {
4533 uint8_t cmd;
4534 uint8_t reserved[3];
4535
4536 union {
4537 struct ec_param_ec_codec_get_shm_addr
4538 get_shm_addr_param;
4539 struct ec_param_ec_codec_set_shm_addr
4540 set_shm_addr_param;
4541 };
4542};
4543
4544struct __ec_align4 ec_response_ec_codec_get_capabilities {
4545 uint32_t capabilities;
4546};
4547
4548struct __ec_align4 ec_response_ec_codec_get_shm_addr {
4549 uint64_t phys_addr;
4550 uint32_t len;
4551 uint8_t type;
4552 uint8_t reserved[3];
4553};
4554
4555
4556
4557
4558#define EC_CMD_EC_CODEC_DMIC 0x00BD
4559
4560enum ec_codec_dmic_subcmd {
4561 EC_CODEC_DMIC_GET_MAX_GAIN = 0x0,
4562 EC_CODEC_DMIC_SET_GAIN_IDX = 0x1,
4563 EC_CODEC_DMIC_GET_GAIN_IDX = 0x2,
4564 EC_CODEC_DMIC_SUBCMD_COUNT,
4565};
4566
4567enum ec_codec_dmic_channel {
4568 EC_CODEC_DMIC_CHANNEL_0 = 0x0,
4569 EC_CODEC_DMIC_CHANNEL_1 = 0x1,
4570 EC_CODEC_DMIC_CHANNEL_2 = 0x2,
4571 EC_CODEC_DMIC_CHANNEL_3 = 0x3,
4572 EC_CODEC_DMIC_CHANNEL_4 = 0x4,
4573 EC_CODEC_DMIC_CHANNEL_5 = 0x5,
4574 EC_CODEC_DMIC_CHANNEL_6 = 0x6,
4575 EC_CODEC_DMIC_CHANNEL_7 = 0x7,
4576 EC_CODEC_DMIC_CHANNEL_COUNT,
4577};
4578
4579struct __ec_align1 ec_param_ec_codec_dmic_set_gain_idx {
4580 uint8_t channel;
4581 uint8_t gain;
4582 uint8_t reserved[2];
4583};
4584
4585struct __ec_align1 ec_param_ec_codec_dmic_get_gain_idx {
4586 uint8_t channel;
4587 uint8_t reserved[3];
4588};
4589
4590struct __ec_align4 ec_param_ec_codec_dmic {
4591 uint8_t cmd;
4592 uint8_t reserved[3];
4593
4594 union {
4595 struct ec_param_ec_codec_dmic_set_gain_idx
4596 set_gain_idx_param;
4597 struct ec_param_ec_codec_dmic_get_gain_idx
4598 get_gain_idx_param;
4599 };
4600};
4601
4602struct __ec_align1 ec_response_ec_codec_dmic_get_max_gain {
4603 uint8_t max_gain;
4604};
4605
4606struct __ec_align1 ec_response_ec_codec_dmic_get_gain_idx {
4607 uint8_t gain;
4608};
4609
4610
4611
4612
4613
4614#define EC_CMD_EC_CODEC_I2S_RX 0x00BE
4615
4616enum ec_codec_i2s_rx_subcmd {
4617 EC_CODEC_I2S_RX_ENABLE = 0x0,
4618 EC_CODEC_I2S_RX_DISABLE = 0x1,
4619 EC_CODEC_I2S_RX_SET_SAMPLE_DEPTH = 0x2,
4620 EC_CODEC_I2S_RX_SET_DAIFMT = 0x3,
4621 EC_CODEC_I2S_RX_SET_BCLK = 0x4,
4622 EC_CODEC_I2S_RX_RESET = 0x5,
4623 EC_CODEC_I2S_RX_SUBCMD_COUNT,
4624};
4625
4626enum ec_codec_i2s_rx_sample_depth {
4627 EC_CODEC_I2S_RX_SAMPLE_DEPTH_16 = 0x0,
4628 EC_CODEC_I2S_RX_SAMPLE_DEPTH_24 = 0x1,
4629 EC_CODEC_I2S_RX_SAMPLE_DEPTH_COUNT,
4630};
4631
4632enum ec_codec_i2s_rx_daifmt {
4633 EC_CODEC_I2S_RX_DAIFMT_I2S = 0x0,
4634 EC_CODEC_I2S_RX_DAIFMT_RIGHT_J = 0x1,
4635 EC_CODEC_I2S_RX_DAIFMT_LEFT_J = 0x2,
4636 EC_CODEC_I2S_RX_DAIFMT_COUNT,
4637};
4638
4639struct __ec_align1 ec_param_ec_codec_i2s_rx_set_sample_depth {
4640 uint8_t depth;
4641 uint8_t reserved[3];
4642};
4643
4644struct __ec_align1 ec_param_ec_codec_i2s_rx_set_gain {
4645 uint8_t left;
4646 uint8_t right;
4647 uint8_t reserved[2];
4648};
4649
4650struct __ec_align1 ec_param_ec_codec_i2s_rx_set_daifmt {
4651 uint8_t daifmt;
4652 uint8_t reserved[3];
4653};
4654
4655struct __ec_align4 ec_param_ec_codec_i2s_rx_set_bclk {
4656 uint32_t bclk;
4657};
4658
4659struct __ec_align4 ec_param_ec_codec_i2s_rx {
4660 uint8_t cmd;
4661 uint8_t reserved[3];
4662
4663 union {
4664 struct ec_param_ec_codec_i2s_rx_set_sample_depth
4665 set_sample_depth_param;
4666 struct ec_param_ec_codec_i2s_rx_set_daifmt
4667 set_daifmt_param;
4668 struct ec_param_ec_codec_i2s_rx_set_bclk
4669 set_bclk_param;
4670 };
4671};
4672
4673
4674
4675
4676#define EC_CMD_EC_CODEC_WOV 0x00BF
4677
4678enum ec_codec_wov_subcmd {
4679 EC_CODEC_WOV_SET_LANG = 0x0,
4680 EC_CODEC_WOV_SET_LANG_SHM = 0x1,
4681 EC_CODEC_WOV_GET_LANG = 0x2,
4682 EC_CODEC_WOV_ENABLE = 0x3,
4683 EC_CODEC_WOV_DISABLE = 0x4,
4684 EC_CODEC_WOV_READ_AUDIO = 0x5,
4685 EC_CODEC_WOV_READ_AUDIO_SHM = 0x6,
4686 EC_CODEC_WOV_SUBCMD_COUNT,
4687};
4688
4689
4690
4691
4692
4693
4694
4695
4696struct __ec_align4 ec_param_ec_codec_wov_set_lang {
4697 uint8_t hash[32];
4698 uint32_t total_len;
4699 uint32_t offset;
4700 uint8_t buf[128];
4701 uint32_t len;
4702};
4703
4704struct __ec_align4 ec_param_ec_codec_wov_set_lang_shm {
4705 uint8_t hash[32];
4706 uint32_t total_len;
4707};
4708
4709struct __ec_align4 ec_param_ec_codec_wov {
4710 uint8_t cmd;
4711 uint8_t reserved[3];
4712
4713 union {
4714 struct ec_param_ec_codec_wov_set_lang
4715 set_lang_param;
4716 struct ec_param_ec_codec_wov_set_lang_shm
4717 set_lang_shm_param;
4718 };
4719};
4720
4721struct __ec_align4 ec_response_ec_codec_wov_get_lang {
4722 uint8_t hash[32];
4723};
4724
4725struct __ec_align4 ec_response_ec_codec_wov_read_audio {
4726 uint8_t buf[128];
4727 uint32_t len;
4728};
4729
4730struct __ec_align4 ec_response_ec_codec_wov_read_audio_shm {
4731 uint32_t offset;
4732 uint32_t len;
4733};
4734
4735
4736
4737
4738
4739
4740
4741
4742#define EC_CMD_REBOOT_EC 0x00D2
4743
4744
4745enum ec_reboot_cmd {
4746 EC_REBOOT_CANCEL = 0,
4747 EC_REBOOT_JUMP_RO = 1,
4748 EC_REBOOT_JUMP_RW = 2,
4749
4750 EC_REBOOT_COLD = 4,
4751 EC_REBOOT_DISABLE_JUMP = 5,
4752 EC_REBOOT_HIBERNATE = 6,
4753 EC_REBOOT_HIBERNATE_CLEAR_AP_OFF = 7,
4754 EC_REBOOT_COLD_AP_OFF = 8,
4755};
4756
4757
4758#define EC_REBOOT_FLAG_RESERVED0 BIT(0)
4759#define EC_REBOOT_FLAG_ON_AP_SHUTDOWN BIT(1)
4760#define EC_REBOOT_FLAG_SWITCH_RW_SLOT BIT(2)
4761
4762struct ec_params_reboot_ec {
4763 uint8_t cmd;
4764 uint8_t flags;
4765} __ec_align1;
4766
4767
4768
4769
4770
4771
4772
4773#define EC_CMD_GET_PANIC_INFO 0x00D3
4774
4775
4776
4777
4778
4779
4780
4781
4782
4783
4784
4785
4786
4787
4788
4789
4790
4791
4792#define EC_CMD_REBOOT 0x00D1
4793
4794
4795
4796
4797
4798
4799
4800
4801#define EC_CMD_RESEND_RESPONSE 0x00DB
4802
4803
4804
4805
4806
4807
4808
4809
4810
4811
4812
4813#define EC_CMD_VERSION0 0x00DC
4814
4815
4816
4817
4818
4819
4820
4821
4822
4823#define EC_CMD_PD_EXCHANGE_STATUS 0x0100
4824#define EC_VER_PD_EXCHANGE_STATUS 2
4825
4826enum pd_charge_state {
4827 PD_CHARGE_NO_CHANGE = 0,
4828 PD_CHARGE_NONE,
4829 PD_CHARGE_5V,
4830 PD_CHARGE_MAX
4831};
4832
4833
4834#define EC_STATUS_HIBERNATING BIT(0)
4835
4836struct ec_params_pd_status {
4837 uint8_t status;
4838 int8_t batt_soc;
4839 uint8_t charge_state;
4840} __ec_align1;
4841
4842
4843#define PD_STATUS_HOST_EVENT BIT(0)
4844#define PD_STATUS_IN_RW BIT(1)
4845#define PD_STATUS_JUMPED_TO_IMAGE BIT(2)
4846#define PD_STATUS_TCPC_ALERT_0 BIT(3)
4847#define PD_STATUS_TCPC_ALERT_1 BIT(4)
4848#define PD_STATUS_TCPC_ALERT_2 BIT(5)
4849#define PD_STATUS_TCPC_ALERT_3 BIT(6)
4850#define PD_STATUS_EC_INT_ACTIVE (PD_STATUS_TCPC_ALERT_0 | \
4851 PD_STATUS_TCPC_ALERT_1 | \
4852 PD_STATUS_HOST_EVENT)
4853struct ec_response_pd_status {
4854 uint32_t curr_lim_ma;
4855 uint16_t status;
4856 int8_t active_charge_port;
4857} __ec_align_size1;
4858
4859
4860#define EC_CMD_PD_HOST_EVENT_STATUS 0x0104
4861
4862
4863#define PD_EVENT_UPDATE_DEVICE BIT(0)
4864#define PD_EVENT_POWER_CHANGE BIT(1)
4865#define PD_EVENT_IDENTITY_RECEIVED BIT(2)
4866#define PD_EVENT_DATA_SWAP BIT(3)
4867struct ec_response_host_event_status {
4868 uint32_t status;
4869} __ec_align4;
4870
4871
4872#define EC_CMD_USB_PD_CONTROL 0x0101
4873
4874enum usb_pd_control_role {
4875 USB_PD_CTRL_ROLE_NO_CHANGE = 0,
4876 USB_PD_CTRL_ROLE_TOGGLE_ON = 1,
4877 USB_PD_CTRL_ROLE_TOGGLE_OFF = 2,
4878 USB_PD_CTRL_ROLE_FORCE_SINK = 3,
4879 USB_PD_CTRL_ROLE_FORCE_SOURCE = 4,
4880 USB_PD_CTRL_ROLE_FREEZE = 5,
4881 USB_PD_CTRL_ROLE_COUNT
4882};
4883
4884enum usb_pd_control_mux {
4885 USB_PD_CTRL_MUX_NO_CHANGE = 0,
4886 USB_PD_CTRL_MUX_NONE = 1,
4887 USB_PD_CTRL_MUX_USB = 2,
4888 USB_PD_CTRL_MUX_DP = 3,
4889 USB_PD_CTRL_MUX_DOCK = 4,
4890 USB_PD_CTRL_MUX_AUTO = 5,
4891 USB_PD_CTRL_MUX_COUNT
4892};
4893
4894enum usb_pd_control_swap {
4895 USB_PD_CTRL_SWAP_NONE = 0,
4896 USB_PD_CTRL_SWAP_DATA = 1,
4897 USB_PD_CTRL_SWAP_POWER = 2,
4898 USB_PD_CTRL_SWAP_VCONN = 3,
4899 USB_PD_CTRL_SWAP_COUNT
4900};
4901
4902struct ec_params_usb_pd_control {
4903 uint8_t port;
4904 uint8_t role;
4905 uint8_t mux;
4906 uint8_t swap;
4907} __ec_align1;
4908
4909#define PD_CTRL_RESP_ENABLED_COMMS BIT(0)
4910#define PD_CTRL_RESP_ENABLED_CONNECTED BIT(1)
4911#define PD_CTRL_RESP_ENABLED_PD_CAPABLE BIT(2)
4912
4913#define PD_CTRL_RESP_ROLE_POWER BIT(0)
4914#define PD_CTRL_RESP_ROLE_DATA BIT(1)
4915#define PD_CTRL_RESP_ROLE_VCONN BIT(2)
4916#define PD_CTRL_RESP_ROLE_DR_POWER BIT(3)
4917#define PD_CTRL_RESP_ROLE_DR_DATA BIT(4)
4918#define PD_CTRL_RESP_ROLE_USB_COMM BIT(5)
4919#define PD_CTRL_RESP_ROLE_EXT_POWERED BIT(6)
4920
4921struct ec_response_usb_pd_control {
4922 uint8_t enabled;
4923 uint8_t role;
4924 uint8_t polarity;
4925 uint8_t state;
4926} __ec_align1;
4927
4928struct ec_response_usb_pd_control_v1 {
4929 uint8_t enabled;
4930 uint8_t role;
4931 uint8_t polarity;
4932 char state[32];
4933} __ec_align1;
4934
4935
4936#define USBC_PD_CC_NONE 0
4937#define USBC_PD_CC_NO_UFP 1
4938#define USBC_PD_CC_AUDIO_ACC 2
4939#define USBC_PD_CC_DEBUG_ACC 3
4940#define USBC_PD_CC_UFP_ATTACHED 4
4941#define USBC_PD_CC_DFP_ATTACHED 5
4942
4943
4944#define USB_PD_CTRL_ACTIVE_CABLE BIT(0)
4945
4946#define USB_PD_CTRL_OPTICAL_CABLE BIT(1)
4947
4948#define USB_PD_CTRL_TBT_LEGACY_ADAPTER BIT(2)
4949
4950#define USB_PD_CTRL_ACTIVE_LINK_UNIDIR BIT(3)
4951
4952struct ec_response_usb_pd_control_v2 {
4953 uint8_t enabled;
4954 uint8_t role;
4955 uint8_t polarity;
4956 char state[32];
4957 uint8_t cc_state;
4958 uint8_t dp_mode;
4959 uint8_t reserved;
4960 uint8_t control_flags;
4961 uint8_t cable_speed;
4962 uint8_t cable_gen;
4963} __ec_align1;
4964
4965#define EC_CMD_USB_PD_PORTS 0x0102
4966
4967
4968#define EC_USB_PD_MAX_PORTS 8
4969
4970struct ec_response_usb_pd_ports {
4971 uint8_t num_ports;
4972} __ec_align1;
4973
4974#define EC_CMD_USB_PD_POWER_INFO 0x0103
4975
4976#define PD_POWER_CHARGING_PORT 0xff
4977struct ec_params_usb_pd_power_info {
4978 uint8_t port;
4979} __ec_align1;
4980
4981enum usb_chg_type {
4982 USB_CHG_TYPE_NONE,
4983 USB_CHG_TYPE_PD,
4984 USB_CHG_TYPE_C,
4985 USB_CHG_TYPE_PROPRIETARY,
4986 USB_CHG_TYPE_BC12_DCP,
4987 USB_CHG_TYPE_BC12_CDP,
4988 USB_CHG_TYPE_BC12_SDP,
4989 USB_CHG_TYPE_OTHER,
4990 USB_CHG_TYPE_VBUS,
4991 USB_CHG_TYPE_UNKNOWN,
4992 USB_CHG_TYPE_DEDICATED,
4993};
4994enum usb_power_roles {
4995 USB_PD_PORT_POWER_DISCONNECTED,
4996 USB_PD_PORT_POWER_SOURCE,
4997 USB_PD_PORT_POWER_SINK,
4998 USB_PD_PORT_POWER_SINK_NOT_CHARGING,
4999};
5000
5001struct usb_chg_measures {
5002 uint16_t voltage_max;
5003 uint16_t voltage_now;
5004 uint16_t current_max;
5005 uint16_t current_lim;
5006} __ec_align2;
5007
5008struct ec_response_usb_pd_power_info {
5009 uint8_t role;
5010 uint8_t type;
5011 uint8_t dualrole;
5012 uint8_t reserved1;
5013 struct usb_chg_measures meas;
5014 uint32_t max_power;
5015} __ec_align4;
5016
5017
5018
5019
5020
5021
5022
5023#define EC_CMD_CHARGE_PORT_COUNT 0x0105
5024struct ec_response_charge_port_count {
5025 uint8_t port_count;
5026} __ec_align1;
5027
5028
5029#define EC_CMD_USB_PD_FW_UPDATE 0x0110
5030
5031enum usb_pd_fw_update_cmds {
5032 USB_PD_FW_REBOOT,
5033 USB_PD_FW_FLASH_ERASE,
5034 USB_PD_FW_FLASH_WRITE,
5035 USB_PD_FW_ERASE_SIG,
5036};
5037
5038struct ec_params_usb_pd_fw_update {
5039 uint16_t dev_id;
5040 uint8_t cmd;
5041 uint8_t port;
5042 uint32_t size;
5043
5044} __ec_align4;
5045
5046
5047#define EC_CMD_USB_PD_RW_HASH_ENTRY 0x0111
5048
5049#define PD_RW_HASH_SIZE 20
5050struct ec_params_usb_pd_rw_hash_entry {
5051 uint16_t dev_id;
5052 uint8_t dev_rw_hash[PD_RW_HASH_SIZE];
5053 uint8_t reserved;
5054
5055
5056
5057
5058 uint32_t current_image;
5059} __ec_align1;
5060
5061
5062#define EC_CMD_USB_PD_DEV_INFO 0x0112
5063
5064struct ec_params_usb_pd_info_request {
5065 uint8_t port;
5066} __ec_align1;
5067
5068
5069#define EC_CMD_USB_PD_DISCOVERY 0x0113
5070struct ec_params_usb_pd_discovery_entry {
5071 uint16_t vid;
5072 uint16_t pid;
5073 uint8_t ptype;
5074} __ec_align_size1;
5075
5076
5077#define EC_CMD_PD_CHARGE_PORT_OVERRIDE 0x0114
5078
5079
5080enum usb_pd_override_ports {
5081 OVERRIDE_DONT_CHARGE = -2,
5082 OVERRIDE_OFF = -1,
5083
5084};
5085
5086struct ec_params_charge_port_override {
5087 int16_t override_port;
5088} __ec_align2;
5089
5090
5091
5092
5093
5094
5095#define EC_CMD_PD_GET_LOG_ENTRY 0x0115
5096
5097struct ec_response_pd_log {
5098 uint32_t timestamp;
5099 uint8_t type;
5100 uint8_t size_port;
5101 uint16_t data;
5102 uint8_t payload[];
5103} __ec_align4;
5104
5105
5106#define PD_LOG_TIMESTAMP_SHIFT 10
5107
5108#define PD_LOG_SIZE_MASK 0x1f
5109#define PD_LOG_PORT_MASK 0xe0
5110#define PD_LOG_PORT_SHIFT 5
5111#define PD_LOG_PORT_SIZE(port, size) (((port) << PD_LOG_PORT_SHIFT) | \
5112 ((size) & PD_LOG_SIZE_MASK))
5113#define PD_LOG_PORT(size_port) ((size_port) >> PD_LOG_PORT_SHIFT)
5114#define PD_LOG_SIZE(size_port) ((size_port) & PD_LOG_SIZE_MASK)
5115
5116
5117
5118#define PD_EVENT_MCU_BASE 0x00
5119#define PD_EVENT_MCU_CHARGE (PD_EVENT_MCU_BASE+0)
5120#define PD_EVENT_MCU_CONNECT (PD_EVENT_MCU_BASE+1)
5121
5122#define PD_EVENT_MCU_BOARD_CUSTOM (PD_EVENT_MCU_BASE+2)
5123
5124#define PD_EVENT_ACC_BASE 0x20
5125#define PD_EVENT_ACC_RW_FAIL (PD_EVENT_ACC_BASE+0)
5126#define PD_EVENT_ACC_RW_ERASE (PD_EVENT_ACC_BASE+1)
5127
5128#define PD_EVENT_PS_BASE 0x40
5129#define PD_EVENT_PS_FAULT (PD_EVENT_PS_BASE+0)
5130
5131#define PD_EVENT_VIDEO_BASE 0x60
5132#define PD_EVENT_VIDEO_DP_MODE (PD_EVENT_VIDEO_BASE+0)
5133#define PD_EVENT_VIDEO_CODEC (PD_EVENT_VIDEO_BASE+1)
5134
5135#define PD_EVENT_NO_ENTRY 0xff
5136
5137
5138
5139
5140
5141
5142
5143#define CHARGE_FLAGS_DUAL_ROLE BIT(15)
5144
5145#define CHARGE_FLAGS_DELAYED_OVERRIDE BIT(14)
5146
5147#define CHARGE_FLAGS_OVERRIDE BIT(13)
5148
5149#define CHARGE_FLAGS_TYPE_SHIFT 3
5150#define CHARGE_FLAGS_TYPE_MASK (0xf << CHARGE_FLAGS_TYPE_SHIFT)
5151
5152#define CHARGE_FLAGS_ROLE_MASK (7 << 0)
5153
5154
5155
5156
5157#define PS_FAULT_OCP 1
5158#define PS_FAULT_FAST_OCP 2
5159#define PS_FAULT_OVP 3
5160#define PS_FAULT_DISCH 4
5161
5162
5163
5164
5165struct mcdp_version {
5166 uint8_t major;
5167 uint8_t minor;
5168 uint16_t build;
5169} __ec_align4;
5170
5171struct mcdp_info {
5172 uint8_t family[2];
5173 uint8_t chipid[2];
5174 struct mcdp_version irom;
5175 struct mcdp_version fw;
5176} __ec_align4;
5177
5178
5179#define MCDP_CHIPID(chipid) ((chipid[0] << 8) | chipid[1])
5180#define MCDP_FAMILY(family) ((family[0] << 8) | family[1])
5181
5182
5183#define EC_CMD_USB_PD_GET_AMODE 0x0116
5184struct ec_params_usb_pd_get_mode_request {
5185 uint16_t svid_idx;
5186 uint8_t port;
5187} __ec_align_size1;
5188
5189struct ec_params_usb_pd_get_mode_response {
5190 uint16_t svid;
5191 uint16_t opos;
5192 uint32_t vdo[6];
5193} __ec_align4;
5194
5195#define EC_CMD_USB_PD_SET_AMODE 0x0117
5196
5197enum pd_mode_cmd {
5198 PD_EXIT_MODE = 0,
5199 PD_ENTER_MODE = 1,
5200
5201 PD_MODE_CMD_COUNT,
5202};
5203
5204struct ec_params_usb_pd_set_mode_request {
5205 uint32_t cmd;
5206 uint16_t svid;
5207 uint8_t opos;
5208 uint8_t port;
5209} __ec_align4;
5210
5211
5212#define EC_CMD_PD_WRITE_LOG_ENTRY 0x0118
5213
5214struct ec_params_pd_write_log_entry {
5215 uint8_t type;
5216 uint8_t port;
5217} __ec_align1;
5218
5219
5220
5221#define EC_CMD_PD_CONTROL 0x0119
5222
5223enum ec_pd_control_cmd {
5224 PD_SUSPEND = 0,
5225 PD_RESUME,
5226 PD_RESET,
5227 PD_CONTROL_DISABLE,
5228 PD_CHIP_ON,
5229};
5230
5231struct ec_params_pd_control {
5232 uint8_t chip;
5233 uint8_t subcmd;
5234} __ec_align1;
5235
5236
5237#define EC_CMD_USB_PD_MUX_INFO 0x011A
5238
5239struct ec_params_usb_pd_mux_info {
5240 uint8_t port;
5241} __ec_align1;
5242
5243
5244#define USB_PD_MUX_NONE 0
5245#define USB_PD_MUX_USB_ENABLED BIT(0)
5246#define USB_PD_MUX_DP_ENABLED BIT(1)
5247#define USB_PD_MUX_POLARITY_INVERTED BIT(2)
5248#define USB_PD_MUX_HPD_IRQ BIT(3)
5249#define USB_PD_MUX_HPD_LVL BIT(4)
5250#define USB_PD_MUX_SAFE_MODE BIT(5)
5251#define USB_PD_MUX_TBT_COMPAT_ENABLED BIT(6)
5252#define USB_PD_MUX_USB4_ENABLED BIT(7)
5253
5254struct ec_response_usb_pd_mux_info {
5255 uint8_t flags;
5256} __ec_align1;
5257
5258#define EC_CMD_PD_CHIP_INFO 0x011B
5259
5260struct ec_params_pd_chip_info {
5261 uint8_t port;
5262 uint8_t renew;
5263} __ec_align1;
5264
5265struct ec_response_pd_chip_info {
5266 uint16_t vendor_id;
5267 uint16_t product_id;
5268 uint16_t device_id;
5269 union {
5270 uint8_t fw_version_string[8];
5271 uint64_t fw_version_number;
5272 };
5273} __ec_align2;
5274
5275struct ec_response_pd_chip_info_v1 {
5276 uint16_t vendor_id;
5277 uint16_t product_id;
5278 uint16_t device_id;
5279 union {
5280 uint8_t fw_version_string[8];
5281 uint64_t fw_version_number;
5282 };
5283 union {
5284 uint8_t min_req_fw_version_string[8];
5285 uint64_t min_req_fw_version_number;
5286 };
5287} __ec_align2;
5288
5289
5290#define EC_CMD_RWSIG_CHECK_STATUS 0x011C
5291
5292struct ec_response_rwsig_check_status {
5293 uint32_t status;
5294} __ec_align4;
5295
5296
5297#define EC_CMD_RWSIG_ACTION 0x011D
5298
5299enum rwsig_action {
5300 RWSIG_ACTION_ABORT = 0,
5301 RWSIG_ACTION_CONTINUE = 1,
5302};
5303
5304struct ec_params_rwsig_action {
5305 uint32_t action;
5306} __ec_align4;
5307
5308
5309#define EC_CMD_EFS_VERIFY 0x011E
5310
5311struct ec_params_efs_verify {
5312 uint8_t region;
5313} __ec_align1;
5314
5315
5316
5317
5318
5319
5320#define EC_CMD_GET_CROS_BOARD_INFO 0x011F
5321
5322
5323
5324
5325#define EC_CMD_SET_CROS_BOARD_INFO 0x0120
5326
5327enum cbi_data_tag {
5328 CBI_TAG_BOARD_VERSION = 0,
5329 CBI_TAG_OEM_ID = 1,
5330 CBI_TAG_SKU_ID = 2,
5331 CBI_TAG_DRAM_PART_NUM = 3,
5332 CBI_TAG_OEM_NAME = 4,
5333 CBI_TAG_MODEL_ID = 5,
5334 CBI_TAG_COUNT,
5335};
5336
5337
5338
5339
5340
5341
5342
5343#define CBI_GET_RELOAD BIT(0)
5344
5345struct ec_params_get_cbi {
5346 uint32_t tag;
5347 uint32_t flag;
5348} __ec_align4;
5349
5350
5351
5352
5353
5354
5355
5356
5357
5358#define CBI_SET_NO_SYNC BIT(0)
5359#define CBI_SET_INIT BIT(1)
5360
5361struct ec_params_set_cbi {
5362 uint32_t tag;
5363 uint32_t flag;
5364 uint32_t size;
5365 uint8_t data[];
5366} __ec_align1;
5367
5368
5369
5370
5371#define EC_CMD_GET_UPTIME_INFO 0x0121
5372
5373struct ec_response_uptime_info {
5374
5375
5376
5377
5378
5379
5380
5381
5382 uint32_t time_since_ec_boot_ms;
5383
5384
5385
5386
5387
5388
5389
5390 uint32_t ap_resets_since_ec_boot;
5391
5392
5393
5394
5395
5396 uint32_t ec_reset_flags;
5397
5398
5399 struct ap_reset_log_entry {
5400
5401
5402
5403
5404 uint16_t reset_cause;
5405
5406
5407 uint16_t reserved;
5408
5409
5410
5411
5412
5413
5414 uint32_t reset_time_ms;
5415 } recent_ap_reset[4];
5416} __ec_align4;
5417
5418
5419
5420
5421
5422
5423
5424#define EC_CMD_ADD_ENTROPY 0x0122
5425
5426enum add_entropy_action {
5427
5428 ADD_ENTROPY_ASYNC = 0,
5429
5430
5431
5432
5433
5434 ADD_ENTROPY_RESET_ASYNC = 1,
5435
5436 ADD_ENTROPY_GET_RESULT = 2,
5437};
5438
5439struct ec_params_rollback_add_entropy {
5440 uint8_t action;
5441} __ec_align1;
5442
5443
5444
5445
5446#define EC_CMD_ADC_READ 0x0123
5447
5448struct ec_params_adc_read {
5449 uint8_t adc_channel;
5450} __ec_align1;
5451
5452struct ec_response_adc_read {
5453 int32_t adc_value;
5454} __ec_align4;
5455
5456
5457
5458
5459#define EC_CMD_ROLLBACK_INFO 0x0124
5460
5461struct ec_response_rollback_info {
5462 int32_t id;
5463 int32_t rollback_min_version;
5464 int32_t rw_rollback_version;
5465} __ec_align4;
5466
5467
5468
5469#define EC_CMD_AP_RESET 0x0125
5470
5471
5472
5473
5474#define EC_CMD_PCHG_COUNT 0x0134
5475
5476#define EC_PCHG_MAX_PORTS 8
5477
5478struct ec_response_pchg_count {
5479 uint8_t port_count;
5480} __ec_align1;
5481
5482
5483
5484
5485#define EC_CMD_PCHG 0x0135
5486
5487struct ec_params_pchg {
5488 uint8_t port;
5489} __ec_align1;
5490
5491struct ec_response_pchg {
5492 uint32_t error;
5493 uint8_t state;
5494 uint8_t battery_percentage;
5495 uint8_t unused0;
5496 uint8_t unused1;
5497
5498 uint32_t fw_version;
5499 uint32_t dropped_event_count;
5500} __ec_align2;
5501
5502enum pchg_state {
5503
5504 PCHG_STATE_RESET = 0,
5505
5506 PCHG_STATE_INITIALIZED,
5507
5508 PCHG_STATE_ENABLED,
5509
5510 PCHG_STATE_DETECTED,
5511
5512 PCHG_STATE_CHARGING,
5513
5514 PCHG_STATE_FULL,
5515
5516 PCHG_STATE_DOWNLOAD,
5517
5518 PCHG_STATE_DOWNLOADING,
5519
5520 PCHG_STATE_CONNECTED,
5521
5522 PCHG_STATE_COUNT,
5523};
5524
5525#define EC_PCHG_STATE_TEXT { \
5526 [PCHG_STATE_RESET] = "RESET", \
5527 [PCHG_STATE_INITIALIZED] = "INITIALIZED", \
5528 [PCHG_STATE_ENABLED] = "ENABLED", \
5529 [PCHG_STATE_DETECTED] = "DETECTED", \
5530 [PCHG_STATE_CHARGING] = "CHARGING", \
5531 [PCHG_STATE_FULL] = "FULL", \
5532 [PCHG_STATE_DOWNLOAD] = "DOWNLOAD", \
5533 [PCHG_STATE_DOWNLOADING] = "DOWNLOADING", \
5534 [PCHG_STATE_CONNECTED] = "CONNECTED", \
5535 }
5536
5537
5538
5539
5540#define EC_CMD_PCHG_UPDATE 0x0136
5541
5542
5543#define EC_MKBP_PCHG_PORT_SHIFT 28
5544
5545#define EC_MKBP_PCHG_EVENT_TO_PORT(e) (((e) >> EC_MKBP_PCHG_PORT_SHIFT) & 0xf)
5546
5547#define EC_MKBP_PCHG_EVENT_MASK(e) ((e) \
5548 & GENMASK(EC_MKBP_PCHG_PORT_SHIFT-1, 0))
5549
5550#define EC_MKBP_PCHG_UPDATE_OPENED BIT(0)
5551#define EC_MKBP_PCHG_WRITE_COMPLETE BIT(1)
5552#define EC_MKBP_PCHG_UPDATE_CLOSED BIT(2)
5553#define EC_MKBP_PCHG_UPDATE_ERROR BIT(3)
5554#define EC_MKBP_PCHG_DEVICE_EVENT BIT(4)
5555
5556enum ec_pchg_update_cmd {
5557
5558 EC_PCHG_UPDATE_CMD_RESET_TO_NORMAL = 0,
5559
5560 EC_PCHG_UPDATE_CMD_OPEN,
5561
5562 EC_PCHG_UPDATE_CMD_WRITE,
5563
5564 EC_PCHG_UPDATE_CMD_CLOSE,
5565
5566 EC_PCHG_UPDATE_CMD_COUNT,
5567};
5568
5569struct ec_params_pchg_update {
5570
5571 uint8_t port;
5572
5573 uint8_t cmd;
5574
5575 uint8_t reserved0;
5576 uint8_t reserved1;
5577
5578 uint32_t version;
5579
5580 uint32_t crc32;
5581
5582 uint32_t addr;
5583
5584 uint32_t size;
5585
5586 uint8_t data[];
5587} __ec_align4;
5588
5589BUILD_ASSERT(EC_PCHG_UPDATE_CMD_COUNT
5590 < BIT(sizeof(((struct ec_params_pchg_update *)0)->cmd)*8));
5591
5592struct ec_response_pchg_update {
5593
5594 uint32_t block_size;
5595} __ec_align4;
5596
5597
5598
5599
5600
5601
5602
5603
5604
5605
5606#define EC_CMD_REGULATOR_GET_INFO 0x012C
5607
5608
5609#define EC_REGULATOR_NAME_MAX_LEN 16
5610
5611
5612#define EC_REGULATOR_VOLTAGE_MAX_COUNT 16
5613
5614struct ec_params_regulator_get_info {
5615 uint32_t index;
5616} __ec_align4;
5617
5618struct ec_response_regulator_get_info {
5619 char name[EC_REGULATOR_NAME_MAX_LEN];
5620 uint16_t num_voltages;
5621 uint16_t voltages_mv[EC_REGULATOR_VOLTAGE_MAX_COUNT];
5622} __ec_align2;
5623
5624
5625
5626
5627#define EC_CMD_REGULATOR_ENABLE 0x012D
5628
5629struct ec_params_regulator_enable {
5630 uint32_t index;
5631 uint8_t enable;
5632} __ec_align4;
5633
5634
5635
5636
5637
5638
5639#define EC_CMD_REGULATOR_IS_ENABLED 0x012E
5640
5641struct ec_params_regulator_is_enabled {
5642 uint32_t index;
5643} __ec_align4;
5644
5645struct ec_response_regulator_is_enabled {
5646 uint8_t enabled;
5647} __ec_align1;
5648
5649
5650
5651
5652
5653
5654
5655
5656
5657#define EC_CMD_REGULATOR_SET_VOLTAGE 0x012F
5658
5659struct ec_params_regulator_set_voltage {
5660 uint32_t index;
5661 uint32_t min_mv;
5662 uint32_t max_mv;
5663} __ec_align4;
5664
5665
5666
5667
5668
5669
5670
5671#define EC_CMD_REGULATOR_GET_VOLTAGE 0x0130
5672
5673struct ec_params_regulator_get_voltage {
5674 uint32_t index;
5675} __ec_align4;
5676
5677struct ec_response_regulator_get_voltage {
5678 uint32_t voltage_mv;
5679} __ec_align4;
5680
5681
5682
5683
5684
5685
5686
5687
5688
5689
5690
5691
5692#define EC_CMD_TYPEC_DISCOVERY 0x0131
5693
5694enum typec_partner_type {
5695 TYPEC_PARTNER_SOP = 0,
5696 TYPEC_PARTNER_SOP_PRIME = 1,
5697};
5698
5699struct ec_params_typec_discovery {
5700 uint8_t port;
5701 uint8_t partner_type;
5702} __ec_align1;
5703
5704struct svid_mode_info {
5705 uint16_t svid;
5706 uint16_t mode_count;
5707 uint32_t mode_vdo[6];
5708};
5709
5710struct ec_response_typec_discovery {
5711 uint8_t identity_count;
5712 uint8_t svid_count;
5713 uint16_t reserved;
5714 uint32_t discovery_vdo[6];
5715 struct svid_mode_info svids[];
5716} __ec_align1;
5717
5718
5719#define EC_CMD_TYPEC_CONTROL 0x0132
5720
5721enum typec_control_command {
5722 TYPEC_CONTROL_COMMAND_EXIT_MODES,
5723 TYPEC_CONTROL_COMMAND_CLEAR_EVENTS,
5724 TYPEC_CONTROL_COMMAND_ENTER_MODE,
5725};
5726
5727struct ec_params_typec_control {
5728 uint8_t port;
5729 uint8_t command;
5730 uint16_t reserved;
5731
5732
5733
5734
5735
5736
5737 union {
5738 uint32_t clear_events_mask;
5739 uint8_t mode_to_enter;
5740 uint8_t placeholder[128];
5741 };
5742} __ec_align1;
5743
5744
5745
5746
5747
5748
5749
5750
5751
5752
5753
5754#define EC_CMD_TYPEC_STATUS 0x0133
5755
5756
5757
5758
5759
5760
5761
5762
5763enum pd_power_role {
5764 PD_ROLE_SINK = 0,
5765 PD_ROLE_SOURCE = 1
5766};
5767
5768
5769
5770
5771
5772
5773
5774
5775enum pd_data_role {
5776 PD_ROLE_UFP = 0,
5777 PD_ROLE_DFP = 1,
5778 PD_ROLE_DISCONNECTED = 2,
5779};
5780
5781enum pd_vconn_role {
5782 PD_ROLE_VCONN_OFF = 0,
5783 PD_ROLE_VCONN_SRC = 1,
5784};
5785
5786
5787
5788
5789
5790enum tcpc_cc_polarity {
5791
5792
5793
5794
5795
5796 POLARITY_CC1 = 0,
5797 POLARITY_CC2 = 1,
5798
5799
5800
5801
5802
5803 POLARITY_CC1_DTS = 2,
5804 POLARITY_CC2_DTS = 3,
5805
5806
5807
5808
5809
5810
5811
5812 POLARITY_COUNT
5813};
5814
5815#define PD_STATUS_EVENT_SOP_DISC_DONE BIT(0)
5816#define PD_STATUS_EVENT_SOP_PRIME_DISC_DONE BIT(1)
5817#define PD_STATUS_EVENT_HARD_RESET BIT(2)
5818
5819struct ec_params_typec_status {
5820 uint8_t port;
5821} __ec_align1;
5822
5823struct ec_response_typec_status {
5824 uint8_t pd_enabled;
5825 uint8_t dev_connected;
5826 uint8_t sop_connected;
5827 uint8_t source_cap_count;
5828
5829 uint8_t power_role;
5830 uint8_t data_role;
5831 uint8_t vconn_role;
5832 uint8_t sink_cap_count;
5833
5834 uint8_t polarity;
5835 uint8_t cc_state;
5836 uint8_t dp_pin;
5837 uint8_t mux_state;
5838
5839 char tc_state[32];
5840
5841 uint32_t events;
5842
5843
5844
5845
5846
5847
5848
5849
5850
5851
5852
5853 uint16_t sop_revision;
5854 uint16_t sop_prime_revision;
5855
5856 uint32_t source_cap_pdos[7];
5857
5858 uint32_t sink_cap_pdos[7];
5859} __ec_align1;
5860
5861
5862
5863
5864
5865
5866
5867
5868#define EC_CMD_CR51_BASE 0x0300
5869#define EC_CMD_CR51_LAST 0x03FF
5870
5871
5872
5873
5874
5875#define EC_CMD_FP_PASSTHRU 0x0400
5876
5877#define EC_FP_FLAG_NOT_COMPLETE 0x1
5878
5879struct ec_params_fp_passthru {
5880 uint16_t len;
5881 uint16_t flags;
5882 uint8_t data[];
5883} __ec_align2;
5884
5885
5886#define EC_CMD_FP_MODE 0x0402
5887
5888
5889#define FP_MODE_DEEPSLEEP BIT(0)
5890
5891#define FP_MODE_FINGER_DOWN BIT(1)
5892
5893#define FP_MODE_FINGER_UP BIT(2)
5894
5895#define FP_MODE_CAPTURE BIT(3)
5896
5897#define FP_MODE_ENROLL_SESSION BIT(4)
5898
5899#define FP_MODE_ENROLL_IMAGE BIT(5)
5900
5901#define FP_MODE_MATCH BIT(6)
5902
5903#define FP_MODE_RESET_SENSOR BIT(7)
5904
5905#define FP_MODE_DONT_CHANGE BIT(31)
5906
5907#define FP_VALID_MODES (FP_MODE_DEEPSLEEP | \
5908 FP_MODE_FINGER_DOWN | \
5909 FP_MODE_FINGER_UP | \
5910 FP_MODE_CAPTURE | \
5911 FP_MODE_ENROLL_SESSION | \
5912 FP_MODE_ENROLL_IMAGE | \
5913 FP_MODE_MATCH | \
5914 FP_MODE_RESET_SENSOR | \
5915 FP_MODE_DONT_CHANGE)
5916
5917
5918#define FP_MODE_CAPTURE_TYPE_SHIFT 28
5919#define FP_MODE_CAPTURE_TYPE_MASK (0x7 << FP_MODE_CAPTURE_TYPE_SHIFT)
5920
5921
5922
5923
5924enum fp_capture_type {
5925
5926 FP_CAPTURE_VENDOR_FORMAT = 0,
5927
5928 FP_CAPTURE_SIMPLE_IMAGE = 1,
5929
5930 FP_CAPTURE_PATTERN0 = 2,
5931
5932 FP_CAPTURE_PATTERN1 = 3,
5933
5934 FP_CAPTURE_QUALITY_TEST = 4,
5935
5936 FP_CAPTURE_RESET_TEST = 5,
5937 FP_CAPTURE_TYPE_MAX,
5938};
5939
5940#define FP_CAPTURE_TYPE(mode) (((mode) & FP_MODE_CAPTURE_TYPE_MASK) \
5941 >> FP_MODE_CAPTURE_TYPE_SHIFT)
5942
5943struct ec_params_fp_mode {
5944 uint32_t mode;
5945} __ec_align4;
5946
5947struct ec_response_fp_mode {
5948 uint32_t mode;
5949} __ec_align4;
5950
5951
5952#define EC_CMD_FP_INFO 0x0403
5953
5954
5955#define FP_ERROR_DEAD_PIXELS(errors) ((errors) & 0x3FF)
5956
5957#define FP_ERROR_DEAD_PIXELS_UNKNOWN (0x3FF)
5958
5959#define FP_ERROR_NO_IRQ BIT(12)
5960
5961#define FP_ERROR_SPI_COMM BIT(13)
5962
5963#define FP_ERROR_BAD_HWID BIT(14)
5964
5965#define FP_ERROR_INIT_FAIL BIT(15)
5966
5967struct ec_response_fp_info_v0 {
5968
5969 uint32_t vendor_id;
5970 uint32_t product_id;
5971 uint32_t model_id;
5972 uint32_t version;
5973
5974 uint32_t frame_size;
5975 uint32_t pixel_format;
5976 uint16_t width;
5977 uint16_t height;
5978 uint16_t bpp;
5979 uint16_t errors;
5980} __ec_align4;
5981
5982struct ec_response_fp_info {
5983
5984 uint32_t vendor_id;
5985 uint32_t product_id;
5986 uint32_t model_id;
5987 uint32_t version;
5988
5989 uint32_t frame_size;
5990 uint32_t pixel_format;
5991 uint16_t width;
5992 uint16_t height;
5993 uint16_t bpp;
5994 uint16_t errors;
5995
5996 uint32_t template_size;
5997 uint16_t template_max;
5998 uint16_t template_valid;
5999 uint32_t template_dirty;
6000 uint32_t template_version;
6001} __ec_align4;
6002
6003
6004#define EC_CMD_FP_FRAME 0x0404
6005
6006
6007#define FP_FRAME_INDEX_SHIFT 28
6008
6009#define FP_FRAME_INDEX_RAW_IMAGE 0
6010
6011#define FP_FRAME_INDEX_TEMPLATE 1
6012#define FP_FRAME_GET_BUFFER_INDEX(offset) ((offset) >> FP_FRAME_INDEX_SHIFT)
6013#define FP_FRAME_OFFSET_MASK 0x0FFFFFFF
6014
6015
6016#define FP_TEMPLATE_FORMAT_VERSION 3
6017
6018
6019#define FP_CONTEXT_NONCE_BYTES 12
6020#define FP_CONTEXT_USERID_WORDS (32 / sizeof(uint32_t))
6021#define FP_CONTEXT_TAG_BYTES 16
6022#define FP_CONTEXT_SALT_BYTES 16
6023#define FP_CONTEXT_TPM_BYTES 32
6024
6025struct ec_fp_template_encryption_metadata {
6026
6027
6028
6029 uint16_t struct_version;
6030
6031 uint16_t reserved;
6032
6033
6034
6035
6036 uint8_t nonce[FP_CONTEXT_NONCE_BYTES];
6037 uint8_t salt[FP_CONTEXT_SALT_BYTES];
6038 uint8_t tag[FP_CONTEXT_TAG_BYTES];
6039};
6040
6041struct ec_params_fp_frame {
6042
6043
6044
6045
6046
6047 uint32_t offset;
6048 uint32_t size;
6049} __ec_align4;
6050
6051
6052#define EC_CMD_FP_TEMPLATE 0x0405
6053
6054
6055#define FP_TEMPLATE_COMMIT 0x80000000
6056
6057struct ec_params_fp_template {
6058 uint32_t offset;
6059 uint32_t size;
6060 uint8_t data[];
6061} __ec_align4;
6062
6063
6064#define EC_CMD_FP_CONTEXT 0x0406
6065
6066struct ec_params_fp_context {
6067 uint32_t userid[FP_CONTEXT_USERID_WORDS];
6068} __ec_align4;
6069
6070#define EC_CMD_FP_STATS 0x0407
6071
6072#define FPSTATS_CAPTURE_INV BIT(0)
6073#define FPSTATS_MATCHING_INV BIT(1)
6074
6075struct ec_response_fp_stats {
6076 uint32_t capture_time_us;
6077 uint32_t matching_time_us;
6078 uint32_t overall_time_us;
6079 struct {
6080 uint32_t lo;
6081 uint32_t hi;
6082 } overall_t0;
6083 uint8_t timestamps_invalid;
6084 int8_t template_matched;
6085} __ec_align2;
6086
6087#define EC_CMD_FP_SEED 0x0408
6088struct ec_params_fp_seed {
6089
6090
6091
6092 uint16_t struct_version;
6093
6094 uint16_t reserved;
6095
6096 uint8_t seed[FP_CONTEXT_TPM_BYTES];
6097} __ec_align4;
6098
6099#define EC_CMD_FP_ENC_STATUS 0x0409
6100
6101
6102#define FP_ENC_STATUS_SEED_SET BIT(0)
6103
6104struct ec_response_fp_encryption_status {
6105
6106 uint32_t valid_flags;
6107
6108 uint32_t status;
6109} __ec_align4;
6110
6111
6112
6113
6114
6115#define EC_CMD_TP_SELF_TEST 0x0500
6116
6117
6118#define EC_CMD_TP_FRAME_INFO 0x0501
6119
6120struct ec_response_tp_frame_info {
6121 uint32_t n_frames;
6122 uint32_t frame_sizes[];
6123} __ec_align4;
6124
6125
6126#define EC_CMD_TP_FRAME_SNAPSHOT 0x0502
6127
6128
6129#define EC_CMD_TP_FRAME_GET 0x0503
6130
6131struct ec_params_tp_frame_get {
6132 uint32_t frame_index;
6133 uint32_t offset;
6134 uint32_t size;
6135} __ec_align4;
6136
6137
6138
6139
6140#define EC_COMM_TEXT_MAX 8
6141
6142
6143
6144
6145
6146#define EC_CMD_BATTERY_GET_STATIC 0x0600
6147
6148
6149
6150
6151
6152struct ec_params_battery_static_info {
6153 uint8_t index;
6154} __ec_align_size1;
6155
6156
6157
6158
6159
6160
6161
6162
6163
6164
6165
6166struct ec_response_battery_static_info {
6167 uint16_t design_capacity;
6168 uint16_t design_voltage;
6169 char manufacturer[EC_COMM_TEXT_MAX];
6170 char model[EC_COMM_TEXT_MAX];
6171 char serial[EC_COMM_TEXT_MAX];
6172 char type[EC_COMM_TEXT_MAX];
6173
6174 uint32_t cycle_count;
6175} __ec_align4;
6176
6177
6178
6179
6180
6181#define EC_CMD_BATTERY_GET_DYNAMIC 0x0601
6182
6183
6184
6185
6186
6187struct ec_params_battery_dynamic_info {
6188 uint8_t index;
6189} __ec_align_size1;
6190
6191
6192
6193
6194
6195
6196
6197
6198
6199
6200
6201struct ec_response_battery_dynamic_info {
6202 int16_t actual_voltage;
6203 int16_t actual_current;
6204 int16_t remaining_capacity;
6205 int16_t full_capacity;
6206 int16_t flags;
6207 int16_t desired_voltage;
6208 int16_t desired_current;
6209} __ec_align2;
6210
6211
6212
6213
6214#define EC_CMD_CHARGER_CONTROL 0x0602
6215
6216
6217
6218
6219
6220
6221
6222
6223
6224
6225
6226struct ec_params_charger_control {
6227 int16_t max_current;
6228 uint16_t otg_voltage;
6229 uint8_t allow_charging;
6230} __ec_align_size1;
6231
6232
6233#define EC_CMD_USB_PD_MUX_ACK 0x0603
6234
6235struct ec_params_usb_pd_mux_ack {
6236 uint8_t port;
6237} __ec_align1;
6238
6239
6240
6241
6242
6243
6244
6245
6246
6247
6248
6249
6250
6251
6252
6253
6254
6255
6256
6257
6258
6259
6260
6261
6262
6263
6264
6265#define EC_CMD_BOARD_SPECIFIC_BASE 0x3E00
6266#define EC_CMD_BOARD_SPECIFIC_LAST 0x3FFF
6267
6268
6269
6270
6271
6272#define EC_PRIVATE_HOST_COMMAND_VALUE(command) \
6273 (EC_CMD_BOARD_SPECIFIC_BASE + (command))
6274
6275
6276
6277
6278
6279
6280
6281
6282
6283
6284
6285
6286
6287
6288
6289
6290
6291
6292
6293
6294
6295
6296
6297
6298
6299#define EC_CMD_PASSTHRU_OFFSET(n) (0x4000 * (n))
6300#define EC_CMD_PASSTHRU_MAX(n) (EC_CMD_PASSTHRU_OFFSET(n) + 0x3fff)
6301
6302
6303
6304
6305
6306
6307
6308
6309#define EC_HOST_PARAM_SIZE EC_PROTO2_MAX_PARAM_SIZE
6310#define EC_LPC_ADDR_OLD_PARAM EC_HOST_CMD_REGION1
6311#define EC_OLD_PARAM_SIZE EC_HOST_CMD_REGION_SIZE
6312
6313
6314
6315#endif
6316