1
2
3
4#include <linux/module.h>
5#include <linux/err.h>
6#include <linux/kernel.h>
7#include <linux/delay.h>
8#include <linux/regulator/consumer.h>
9#include <linux/types.h>
10#include <linux/clk.h>
11#include <linux/of.h>
12#include <linux/platform_device.h>
13#include <linux/regmap.h>
14#include <sound/soc.h>
15#include <sound/pcm.h>
16#include <sound/pcm_params.h>
17#include <sound/tlv.h>
18#include <sound/jack.h>
19
20#define CDC_D_REVISION1 (0xf000)
21#define CDC_D_PERPH_SUBTYPE (0xf005)
22#define CDC_D_INT_EN_SET (0xf015)
23#define CDC_D_INT_EN_CLR (0xf016)
24#define MBHC_SWITCH_INT BIT(7)
25#define MBHC_MIC_ELECTRICAL_INS_REM_DET BIT(6)
26#define MBHC_BUTTON_PRESS_DET BIT(5)
27#define MBHC_BUTTON_RELEASE_DET BIT(4)
28#define CDC_D_CDC_RST_CTL (0xf046)
29#define RST_CTL_DIG_SW_RST_N_MASK BIT(7)
30#define RST_CTL_DIG_SW_RST_N_RESET 0
31#define RST_CTL_DIG_SW_RST_N_REMOVE_RESET BIT(7)
32
33#define CDC_D_CDC_TOP_CLK_CTL (0xf048)
34#define TOP_CLK_CTL_A_MCLK_MCLK2_EN_MASK (BIT(2) | BIT(3))
35#define TOP_CLK_CTL_A_MCLK_EN_ENABLE BIT(2)
36#define TOP_CLK_CTL_A_MCLK2_EN_ENABLE BIT(3)
37
38#define CDC_D_CDC_ANA_CLK_CTL (0xf049)
39#define ANA_CLK_CTL_EAR_HPHR_CLK_EN_MASK BIT(0)
40#define ANA_CLK_CTL_EAR_HPHR_CLK_EN BIT(0)
41#define ANA_CLK_CTL_EAR_HPHL_CLK_EN BIT(1)
42#define ANA_CLK_CTL_SPKR_CLK_EN_MASK BIT(4)
43#define ANA_CLK_CTL_SPKR_CLK_EN BIT(4)
44#define ANA_CLK_CTL_TXA_CLK25_EN BIT(5)
45
46#define CDC_D_CDC_DIG_CLK_CTL (0xf04A)
47#define DIG_CLK_CTL_RXD1_CLK_EN BIT(0)
48#define DIG_CLK_CTL_RXD2_CLK_EN BIT(1)
49#define DIG_CLK_CTL_RXD3_CLK_EN BIT(2)
50#define DIG_CLK_CTL_D_MBHC_CLK_EN_MASK BIT(3)
51#define DIG_CLK_CTL_D_MBHC_CLK_EN BIT(3)
52#define DIG_CLK_CTL_TXD_CLK_EN BIT(4)
53#define DIG_CLK_CTL_NCP_CLK_EN_MASK BIT(6)
54#define DIG_CLK_CTL_NCP_CLK_EN BIT(6)
55#define DIG_CLK_CTL_RXD_PDM_CLK_EN_MASK BIT(7)
56#define DIG_CLK_CTL_RXD_PDM_CLK_EN BIT(7)
57
58#define CDC_D_CDC_CONN_TX1_CTL (0xf050)
59#define CONN_TX1_SERIAL_TX1_MUX GENMASK(1, 0)
60#define CONN_TX1_SERIAL_TX1_ADC_1 0x0
61#define CONN_TX1_SERIAL_TX1_RX_PDM_LB 0x1
62#define CONN_TX1_SERIAL_TX1_ZERO 0x2
63
64#define CDC_D_CDC_CONN_TX2_CTL (0xf051)
65#define CONN_TX2_SERIAL_TX2_MUX GENMASK(1, 0)
66#define CONN_TX2_SERIAL_TX2_ADC_2 0x0
67#define CONN_TX2_SERIAL_TX2_RX_PDM_LB 0x1
68#define CONN_TX2_SERIAL_TX2_ZERO 0x2
69#define CDC_D_CDC_CONN_HPHR_DAC_CTL (0xf052)
70#define CDC_D_CDC_CONN_RX1_CTL (0xf053)
71#define CDC_D_CDC_CONN_RX2_CTL (0xf054)
72#define CDC_D_CDC_CONN_RX3_CTL (0xf055)
73#define CDC_D_CDC_CONN_RX_LB_CTL (0xf056)
74#define CDC_D_SEC_ACCESS (0xf0D0)
75#define CDC_D_PERPH_RESET_CTL3 (0xf0DA)
76#define CDC_D_PERPH_RESET_CTL4 (0xf0DB)
77#define CDC_A_REVISION1 (0xf100)
78#define CDC_A_REVISION2 (0xf101)
79#define CDC_A_REVISION3 (0xf102)
80#define CDC_A_REVISION4 (0xf103)
81#define CDC_A_PERPH_TYPE (0xf104)
82#define CDC_A_PERPH_SUBTYPE (0xf105)
83#define CDC_A_INT_RT_STS (0xf110)
84#define CDC_A_INT_SET_TYPE (0xf111)
85#define CDC_A_INT_POLARITY_HIGH (0xf112)
86#define CDC_A_INT_POLARITY_LOW (0xf113)
87#define CDC_A_INT_LATCHED_CLR (0xf114)
88#define CDC_A_INT_EN_SET (0xf115)
89#define CDC_A_INT_EN_CLR (0xf116)
90#define CDC_A_INT_LATCHED_STS (0xf118)
91#define CDC_A_INT_PENDING_STS (0xf119)
92#define CDC_A_INT_MID_SEL (0xf11A)
93#define CDC_A_INT_PRIORITY (0xf11B)
94#define CDC_A_MICB_1_EN (0xf140)
95#define MICB_1_EN_MICB_ENABLE BIT(7)
96#define MICB_1_EN_BYP_CAP_MASK BIT(6)
97#define MICB_1_EN_NO_EXT_BYP_CAP BIT(6)
98#define MICB_1_EN_EXT_BYP_CAP 0
99#define MICB_1_EN_PULL_DOWN_EN_MASK BIT(5)
100#define MICB_1_EN_PULL_DOWN_EN_ENABLE BIT(5)
101#define MICB_1_EN_OPA_STG2_TAIL_CURR_MASK GENMASK(3, 1)
102#define MICB_1_EN_OPA_STG2_TAIL_CURR_1_60UA (0x4)
103#define MICB_1_EN_PULL_UP_EN_MASK BIT(4)
104#define MICB_1_EN_TX3_GND_SEL_MASK BIT(0)
105#define MICB_1_EN_TX3_GND_SEL_TX_GND 0
106
107#define CDC_A_MICB_1_VAL (0xf141)
108#define MICB_MIN_VAL 1600
109#define MICB_STEP_SIZE 50
110#define MICB_VOLTAGE_REGVAL(v) (((v - MICB_MIN_VAL)/MICB_STEP_SIZE) << 3)
111#define MICB_1_VAL_MICB_OUT_VAL_MASK GENMASK(7, 3)
112#define MICB_1_VAL_MICB_OUT_VAL_V2P70V ((0x16) << 3)
113#define MICB_1_VAL_MICB_OUT_VAL_V1P80V ((0x4) << 3)
114#define CDC_A_MICB_1_CTL (0xf142)
115
116#define MICB_1_CTL_CFILT_REF_SEL_MASK BIT(1)
117#define MICB_1_CTL_CFILT_REF_SEL_HPF_REF BIT(1)
118#define MICB_1_CTL_EXT_PRECHARG_EN_MASK BIT(5)
119#define MICB_1_CTL_EXT_PRECHARG_EN_ENABLE BIT(5)
120#define MICB_1_CTL_INT_PRECHARG_BYP_MASK BIT(6)
121#define MICB_1_CTL_INT_PRECHARG_BYP_EXT_PRECHRG_SEL BIT(6)
122
123#define CDC_A_MICB_1_INT_RBIAS (0xf143)
124#define MICB_1_INT_TX1_INT_RBIAS_EN_MASK BIT(7)
125#define MICB_1_INT_TX1_INT_RBIAS_EN_ENABLE BIT(7)
126#define MICB_1_INT_TX1_INT_RBIAS_EN_DISABLE 0
127
128#define MICB_1_INT_TX1_INT_PULLUP_EN_MASK BIT(6)
129#define MICB_1_INT_TX1_INT_PULLUP_EN_TX1N_TO_MICBIAS BIT(6)
130#define MICB_1_INT_TX1_INT_PULLUP_EN_TX1N_TO_GND 0
131
132#define MICB_1_INT_TX2_INT_RBIAS_EN_MASK BIT(4)
133#define MICB_1_INT_TX2_INT_RBIAS_EN_ENABLE BIT(4)
134#define MICB_1_INT_TX2_INT_RBIAS_EN_DISABLE 0
135#define MICB_1_INT_TX2_INT_PULLUP_EN_MASK BIT(3)
136#define MICB_1_INT_TX2_INT_PULLUP_EN_TX1N_TO_MICBIAS BIT(3)
137#define MICB_1_INT_TX2_INT_PULLUP_EN_TX1N_TO_GND 0
138
139#define MICB_1_INT_TX3_INT_RBIAS_EN_MASK BIT(1)
140#define MICB_1_INT_TX3_INT_RBIAS_EN_ENABLE BIT(1)
141#define MICB_1_INT_TX3_INT_RBIAS_EN_DISABLE 0
142#define MICB_1_INT_TX3_INT_PULLUP_EN_MASK BIT(0)
143#define MICB_1_INT_TX3_INT_PULLUP_EN_TX1N_TO_MICBIAS BIT(0)
144#define MICB_1_INT_TX3_INT_PULLUP_EN_TX1N_TO_GND 0
145
146#define CDC_A_MICB_2_EN (0xf144)
147#define CDC_A_MICB_2_EN_ENABLE BIT(7)
148#define CDC_A_MICB_2_PULL_DOWN_EN_MASK BIT(5)
149#define CDC_A_MICB_2_PULL_DOWN_EN BIT(5)
150#define CDC_A_TX_1_2_ATEST_CTL_2 (0xf145)
151#define CDC_A_MASTER_BIAS_CTL (0xf146)
152#define CDC_A_MBHC_DET_CTL_1 (0xf147)
153#define CDC_A_MBHC_DET_CTL_L_DET_EN BIT(7)
154#define CDC_A_MBHC_DET_CTL_GND_DET_EN BIT(6)
155#define CDC_A_MBHC_DET_CTL_MECH_DET_TYPE_INSERTION BIT(5)
156#define CDC_A_MBHC_DET_CTL_MECH_DET_TYPE_REMOVAL (0)
157#define CDC_A_MBHC_DET_CTL_MECH_DET_TYPE_MASK BIT(5)
158#define CDC_A_MBHC_DET_CTL_MECH_DET_TYPE_SHIFT (5)
159#define CDC_A_MBHC_DET_CTL_MIC_CLAMP_CTL_AUTO BIT(4)
160#define CDC_A_MBHC_DET_CTL_MIC_CLAMP_CTL_MANUAL BIT(3)
161#define CDC_A_MBHC_DET_CTL_MIC_CLAMP_CTL_MASK GENMASK(4, 3)
162#define CDC_A_MBHC_DET_CTL_MBHC_BIAS_EN BIT(2)
163#define CDC_A_MBHC_DET_CTL_2 (0xf150)
164#define CDC_A_MBHC_DET_CTL_HS_L_DET_PULL_UP_CTRL_I_3P0 (BIT(7) | BIT(6))
165#define CDC_A_MBHC_DET_CTL_HS_L_DET_COMPA_CTRL_V0P9_VDD BIT(5)
166#define CDC_A_PLUG_TYPE_MASK GENMASK(4, 3)
167#define CDC_A_HPHL_PLUG_TYPE_NO BIT(4)
168#define CDC_A_GND_PLUG_TYPE_NO BIT(3)
169#define CDC_A_MBHC_DET_CTL_HPHL_100K_TO_GND_EN_MASK BIT(0)
170#define CDC_A_MBHC_DET_CTL_HPHL_100K_TO_GND_EN BIT(0)
171#define CDC_A_MBHC_FSM_CTL (0xf151)
172#define CDC_A_MBHC_FSM_CTL_MBHC_FSM_EN BIT(7)
173#define CDC_A_MBHC_FSM_CTL_MBHC_FSM_EN_MASK BIT(7)
174#define CDC_A_MBHC_FSM_CTL_BTN_ISRC_CTRL_I_100UA (0x3 << 4)
175#define CDC_A_MBHC_FSM_CTL_BTN_ISRC_CTRL_MASK GENMASK(6, 4)
176#define CDC_A_MBHC_DBNC_TIMER (0xf152)
177#define CDC_A_MBHC_DBNC_TIMER_BTN_DBNC_T_16MS BIT(3)
178#define CDC_A_MBHC_DBNC_TIMER_INSREM_DBNC_T_256_MS (0x9 << 4)
179#define CDC_A_MBHC_BTN0_ZDET_CTL_0 (0xf153)
180#define CDC_A_MBHC_BTN1_ZDET_CTL_1 (0xf154)
181#define CDC_A_MBHC_BTN2_ZDET_CTL_2 (0xf155)
182#define CDC_A_MBHC_BTN3_CTL (0xf156)
183#define CDC_A_MBHC_BTN4_CTL (0xf157)
184#define CDC_A_MBHC_BTN_VREF_FINE_SHIFT (2)
185#define CDC_A_MBHC_BTN_VREF_FINE_MASK GENMASK(4, 2)
186#define CDC_A_MBHC_BTN_VREF_COARSE_MASK GENMASK(7, 5)
187#define CDC_A_MBHC_BTN_VREF_COARSE_SHIFT (5)
188#define CDC_A_MBHC_BTN_VREF_MASK (CDC_A_MBHC_BTN_VREF_COARSE_MASK | \
189 CDC_A_MBHC_BTN_VREF_FINE_MASK)
190#define CDC_A_MBHC_RESULT_1 (0xf158)
191#define CDC_A_MBHC_RESULT_1_BTN_RESULT_MASK GENMASK(4, 0)
192#define CDC_A_TX_1_EN (0xf160)
193#define CDC_A_TX_2_EN (0xf161)
194#define CDC_A_TX_1_2_TEST_CTL_1 (0xf162)
195#define CDC_A_TX_1_2_TEST_CTL_2 (0xf163)
196#define CDC_A_TX_1_2_ATEST_CTL (0xf164)
197#define CDC_A_TX_1_2_OPAMP_BIAS (0xf165)
198#define CDC_A_TX_3_EN (0xf167)
199#define CDC_A_NCP_EN (0xf180)
200#define CDC_A_NCP_CLK (0xf181)
201#define CDC_A_NCP_FBCTRL (0xf183)
202#define CDC_A_NCP_FBCTRL_FB_CLK_INV_MASK BIT(5)
203#define CDC_A_NCP_FBCTRL_FB_CLK_INV BIT(5)
204#define CDC_A_NCP_BIAS (0xf184)
205#define CDC_A_NCP_VCTRL (0xf185)
206#define CDC_A_NCP_TEST (0xf186)
207#define CDC_A_NCP_CLIM_ADDR (0xf187)
208#define CDC_A_RX_CLOCK_DIVIDER (0xf190)
209#define CDC_A_RX_COM_OCP_CTL (0xf191)
210#define CDC_A_RX_COM_OCP_COUNT (0xf192)
211#define CDC_A_RX_COM_BIAS_DAC (0xf193)
212#define RX_COM_BIAS_DAC_RX_BIAS_EN_MASK BIT(7)
213#define RX_COM_BIAS_DAC_RX_BIAS_EN_ENABLE BIT(7)
214#define RX_COM_BIAS_DAC_DAC_REF_EN_MASK BIT(0)
215#define RX_COM_BIAS_DAC_DAC_REF_EN_ENABLE BIT(0)
216
217#define CDC_A_RX_HPH_BIAS_PA (0xf194)
218#define CDC_A_RX_HPH_BIAS_LDO_OCP (0xf195)
219#define CDC_A_RX_HPH_BIAS_CNP (0xf196)
220#define CDC_A_RX_HPH_CNP_EN (0xf197)
221#define CDC_A_RX_HPH_L_PA_DAC_CTL (0xf19B)
222#define RX_HPA_L_PA_DAC_CTL_DATA_RESET_MASK BIT(1)
223#define RX_HPA_L_PA_DAC_CTL_DATA_RESET_RESET BIT(1)
224#define CDC_A_RX_HPH_R_PA_DAC_CTL (0xf19D)
225#define RX_HPH_R_PA_DAC_CTL_DATA_RESET BIT(1)
226#define RX_HPH_R_PA_DAC_CTL_DATA_RESET_MASK BIT(1)
227
228#define CDC_A_RX_EAR_CTL (0xf19E)
229#define RX_EAR_CTL_SPK_VBAT_LDO_EN_MASK BIT(0)
230#define RX_EAR_CTL_SPK_VBAT_LDO_EN_ENABLE BIT(0)
231#define RX_EAR_CTL_PA_EAR_PA_EN_MASK BIT(6)
232#define RX_EAR_CTL_PA_EAR_PA_EN_ENABLE BIT(6)
233#define RX_EAR_CTL_PA_SEL_MASK BIT(7)
234#define RX_EAR_CTL_PA_SEL BIT(7)
235
236#define CDC_A_SPKR_DAC_CTL (0xf1B0)
237#define SPKR_DAC_CTL_DAC_RESET_MASK BIT(4)
238#define SPKR_DAC_CTL_DAC_RESET_NORMAL 0
239
240#define CDC_A_SPKR_DRV_CTL (0xf1B2)
241#define SPKR_DRV_CTL_DEF_MASK 0xEF
242#define SPKR_DRV_CLASSD_PA_EN_MASK BIT(7)
243#define SPKR_DRV_CLASSD_PA_EN_ENABLE BIT(7)
244#define SPKR_DRV_CAL_EN BIT(6)
245#define SPKR_DRV_SETTLE_EN BIT(5)
246#define SPKR_DRV_FW_EN BIT(3)
247#define SPKR_DRV_BOOST_SET BIT(2)
248#define SPKR_DRV_CMFB_SET BIT(1)
249#define SPKR_DRV_GAIN_SET BIT(0)
250#define SPKR_DRV_CTL_DEF_VAL (SPKR_DRV_CLASSD_PA_EN_ENABLE | \
251 SPKR_DRV_CAL_EN | SPKR_DRV_SETTLE_EN | \
252 SPKR_DRV_FW_EN | SPKR_DRV_BOOST_SET | \
253 SPKR_DRV_CMFB_SET | SPKR_DRV_GAIN_SET)
254#define CDC_A_SPKR_OCP_CTL (0xf1B4)
255#define CDC_A_SPKR_PWRSTG_CTL (0xf1B5)
256#define SPKR_PWRSTG_CTL_DAC_EN_MASK BIT(0)
257#define SPKR_PWRSTG_CTL_DAC_EN BIT(0)
258#define SPKR_PWRSTG_CTL_MASK 0xE0
259#define SPKR_PWRSTG_CTL_BBM_MASK BIT(7)
260#define SPKR_PWRSTG_CTL_BBM_EN BIT(7)
261#define SPKR_PWRSTG_CTL_HBRDGE_EN_MASK BIT(6)
262#define SPKR_PWRSTG_CTL_HBRDGE_EN BIT(6)
263#define SPKR_PWRSTG_CTL_CLAMP_EN_MASK BIT(5)
264#define SPKR_PWRSTG_CTL_CLAMP_EN BIT(5)
265
266#define CDC_A_SPKR_DRV_DBG (0xf1B7)
267#define CDC_A_CURRENT_LIMIT (0xf1C0)
268#define CDC_A_BOOST_EN_CTL (0xf1C3)
269#define CDC_A_SLOPE_COMP_IP_ZERO (0xf1C4)
270#define CDC_A_SEC_ACCESS (0xf1D0)
271#define CDC_A_PERPH_RESET_CTL3 (0xf1DA)
272#define CDC_A_PERPH_RESET_CTL4 (0xf1DB)
273
274#define MSM8916_WCD_ANALOG_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
275 SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000)
276#define MSM8916_WCD_ANALOG_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
277 SNDRV_PCM_FMTBIT_S32_LE)
278
279static int btn_mask = SND_JACK_BTN_0 | SND_JACK_BTN_1 |
280 SND_JACK_BTN_2 | SND_JACK_BTN_3 | SND_JACK_BTN_4;
281static int hs_jack_mask = SND_JACK_HEADPHONE | SND_JACK_HEADSET;
282
283static const char * const supply_names[] = {
284 "vdd-cdc-io",
285 "vdd-cdc-tx-rx-cx",
286};
287
288#define MBHC_MAX_BUTTONS (5)
289
290struct pm8916_wcd_analog_priv {
291 u16 pmic_rev;
292 u16 codec_version;
293 bool mbhc_btn_enabled;
294
295 int mbhc_btn0_released;
296 bool detect_accessory_type;
297 struct clk *mclk;
298 struct snd_soc_component *component;
299 struct regulator_bulk_data supplies[ARRAY_SIZE(supply_names)];
300 struct snd_soc_jack *jack;
301 bool hphl_jack_type_normally_open;
302 bool gnd_jack_type_normally_open;
303
304 u32 vref_btn_cs[MBHC_MAX_BUTTONS];
305
306 u32 vref_btn_micb[MBHC_MAX_BUTTONS];
307 unsigned int micbias1_cap_mode;
308 unsigned int micbias2_cap_mode;
309 unsigned int micbias_mv;
310};
311
312static const char *const adc2_mux_text[] = { "ZERO", "INP2", "INP3" };
313static const char *const rdac2_mux_text[] = { "RX1", "RX2" };
314static const char *const hph_text[] = { "ZERO", "Switch", };
315
316static const struct soc_enum hph_enum = SOC_ENUM_SINGLE_VIRT(
317 ARRAY_SIZE(hph_text), hph_text);
318
319static const struct snd_kcontrol_new ear_mux = SOC_DAPM_ENUM("EAR_S", hph_enum);
320static const struct snd_kcontrol_new hphl_mux = SOC_DAPM_ENUM("HPHL", hph_enum);
321static const struct snd_kcontrol_new hphr_mux = SOC_DAPM_ENUM("HPHR", hph_enum);
322
323
324static const struct soc_enum adc2_enum = SOC_ENUM_SINGLE_VIRT(
325 ARRAY_SIZE(adc2_mux_text), adc2_mux_text);
326
327
328static const struct soc_enum rdac2_mux_enum = SOC_ENUM_SINGLE(
329 CDC_D_CDC_CONN_HPHR_DAC_CTL, 0, 2, rdac2_mux_text);
330
331static const struct snd_kcontrol_new spkr_switch[] = {
332 SOC_DAPM_SINGLE("Switch", CDC_A_SPKR_DAC_CTL, 7, 1, 0)
333};
334
335static const struct snd_kcontrol_new rdac2_mux = SOC_DAPM_ENUM(
336 "RDAC2 MUX Mux", rdac2_mux_enum);
337static const struct snd_kcontrol_new tx_adc2_mux = SOC_DAPM_ENUM(
338 "ADC2 MUX Mux", adc2_enum);
339
340
341static const DECLARE_TLV_DB_SCALE(analog_gain, 0, 600, 0);
342
343static const struct snd_kcontrol_new pm8916_wcd_analog_snd_controls[] = {
344 SOC_SINGLE_TLV("ADC1 Volume", CDC_A_TX_1_EN, 3, 8, 0, analog_gain),
345 SOC_SINGLE_TLV("ADC2 Volume", CDC_A_TX_2_EN, 3, 8, 0, analog_gain),
346 SOC_SINGLE_TLV("ADC3 Volume", CDC_A_TX_3_EN, 3, 8, 0, analog_gain),
347};
348
349static void pm8916_wcd_analog_micbias_enable(struct snd_soc_component *component)
350{
351 struct pm8916_wcd_analog_priv *wcd = snd_soc_component_get_drvdata(component);
352
353 snd_soc_component_update_bits(component, CDC_A_MICB_1_CTL,
354 MICB_1_CTL_EXT_PRECHARG_EN_MASK |
355 MICB_1_CTL_INT_PRECHARG_BYP_MASK,
356 MICB_1_CTL_INT_PRECHARG_BYP_EXT_PRECHRG_SEL
357 | MICB_1_CTL_EXT_PRECHARG_EN_ENABLE);
358
359 if (wcd->micbias_mv) {
360 snd_soc_component_update_bits(component, CDC_A_MICB_1_VAL,
361 MICB_1_VAL_MICB_OUT_VAL_MASK,
362 MICB_VOLTAGE_REGVAL(wcd->micbias_mv));
363
364
365
366
367 if (wcd->micbias_mv >= 2700)
368 msleep(50);
369 }
370
371 snd_soc_component_update_bits(component, CDC_A_MICB_1_CTL,
372 MICB_1_CTL_EXT_PRECHARG_EN_MASK |
373 MICB_1_CTL_INT_PRECHARG_BYP_MASK, 0);
374
375}
376
377static int pm8916_wcd_analog_enable_micbias(struct snd_soc_component *component,
378 int event, unsigned int cap_mode)
379{
380 switch (event) {
381 case SND_SOC_DAPM_POST_PMU:
382 pm8916_wcd_analog_micbias_enable(component);
383 snd_soc_component_update_bits(component, CDC_A_MICB_1_EN,
384 MICB_1_EN_BYP_CAP_MASK, cap_mode);
385 break;
386 }
387
388 return 0;
389}
390
391static int pm8916_wcd_analog_enable_micbias_int(struct snd_soc_dapm_widget *w,
392 struct snd_kcontrol *kcontrol,
393 int event)
394{
395 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
396
397 switch (event) {
398 case SND_SOC_DAPM_PRE_PMU:
399 snd_soc_component_update_bits(component, CDC_A_MICB_1_EN,
400 MICB_1_EN_OPA_STG2_TAIL_CURR_MASK,
401 MICB_1_EN_OPA_STG2_TAIL_CURR_1_60UA);
402 break;
403 }
404
405 return 0;
406}
407
408static int pm8916_wcd_analog_enable_micbias1(struct snd_soc_dapm_widget *w,
409 struct snd_kcontrol *kcontrol,
410 int event)
411{
412 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
413 struct pm8916_wcd_analog_priv *wcd = snd_soc_component_get_drvdata(component);
414
415 return pm8916_wcd_analog_enable_micbias(component, event,
416 wcd->micbias1_cap_mode);
417}
418
419static int pm8916_wcd_analog_enable_micbias2(struct snd_soc_dapm_widget *w,
420 struct snd_kcontrol *kcontrol,
421 int event)
422{
423 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
424 struct pm8916_wcd_analog_priv *wcd = snd_soc_component_get_drvdata(component);
425
426 return pm8916_wcd_analog_enable_micbias(component, event,
427 wcd->micbias2_cap_mode);
428
429}
430
431static int pm8916_mbhc_configure_bias(struct pm8916_wcd_analog_priv *priv,
432 bool micbias2_enabled)
433{
434 struct snd_soc_component *component = priv->component;
435 u32 coarse, fine, reg_val, reg_addr;
436 int *vrefs, i;
437
438 if (!micbias2_enabled) {
439
440 snd_soc_component_update_bits(component, CDC_A_MICB_1_INT_RBIAS,
441 MICB_1_INT_TX2_INT_RBIAS_EN_MASK,
442 MICB_1_INT_TX2_INT_RBIAS_EN_ENABLE);
443
444 snd_soc_component_update_bits(component, CDC_A_MICB_2_EN,
445 CDC_A_MICB_2_PULL_DOWN_EN_MASK,
446 0);
447
448 snd_soc_component_update_bits(component, CDC_A_MBHC_FSM_CTL,
449 CDC_A_MBHC_FSM_CTL_BTN_ISRC_CTRL_MASK,
450 CDC_A_MBHC_FSM_CTL_BTN_ISRC_CTRL_I_100UA);
451 }
452 snd_soc_component_update_bits(component, CDC_A_MBHC_FSM_CTL,
453 CDC_A_MBHC_FSM_CTL_MBHC_FSM_EN_MASK,
454 CDC_A_MBHC_FSM_CTL_MBHC_FSM_EN);
455
456 if (micbias2_enabled)
457 vrefs = &priv->vref_btn_micb[0];
458 else
459 vrefs = &priv->vref_btn_cs[0];
460
461
462 reg_addr = CDC_A_MBHC_BTN0_ZDET_CTL_0;
463 for (i = 0; i < MBHC_MAX_BUTTONS; i++) {
464
465 coarse = (vrefs[i] / 100);
466 fine = ((vrefs[i] % 100) / 12);
467 reg_val = (coarse << CDC_A_MBHC_BTN_VREF_COARSE_SHIFT) |
468 (fine << CDC_A_MBHC_BTN_VREF_FINE_SHIFT);
469 snd_soc_component_update_bits(component, reg_addr,
470 CDC_A_MBHC_BTN_VREF_MASK,
471 reg_val);
472 reg_addr++;
473 }
474
475 return 0;
476}
477
478static void pm8916_wcd_setup_mbhc(struct pm8916_wcd_analog_priv *wcd)
479{
480 struct snd_soc_component *component = wcd->component;
481 bool micbias_enabled = false;
482 u32 plug_type = 0;
483 u32 int_en_mask;
484
485 snd_soc_component_write(component, CDC_A_MBHC_DET_CTL_1,
486 CDC_A_MBHC_DET_CTL_L_DET_EN |
487 CDC_A_MBHC_DET_CTL_MECH_DET_TYPE_INSERTION |
488 CDC_A_MBHC_DET_CTL_MIC_CLAMP_CTL_AUTO |
489 CDC_A_MBHC_DET_CTL_MBHC_BIAS_EN);
490
491 if (wcd->hphl_jack_type_normally_open)
492 plug_type |= CDC_A_HPHL_PLUG_TYPE_NO;
493
494 if (wcd->gnd_jack_type_normally_open)
495 plug_type |= CDC_A_GND_PLUG_TYPE_NO;
496
497 snd_soc_component_write(component, CDC_A_MBHC_DET_CTL_2,
498 CDC_A_MBHC_DET_CTL_HS_L_DET_PULL_UP_CTRL_I_3P0 |
499 CDC_A_MBHC_DET_CTL_HS_L_DET_COMPA_CTRL_V0P9_VDD |
500 plug_type |
501 CDC_A_MBHC_DET_CTL_HPHL_100K_TO_GND_EN);
502
503
504 snd_soc_component_write(component, CDC_A_MBHC_DBNC_TIMER,
505 CDC_A_MBHC_DBNC_TIMER_INSREM_DBNC_T_256_MS |
506 CDC_A_MBHC_DBNC_TIMER_BTN_DBNC_T_16MS);
507
508
509 snd_soc_component_update_bits(component, CDC_D_CDC_DIG_CLK_CTL,
510 DIG_CLK_CTL_D_MBHC_CLK_EN_MASK,
511 DIG_CLK_CTL_D_MBHC_CLK_EN);
512
513 if (snd_soc_component_read(component, CDC_A_MICB_2_EN) & CDC_A_MICB_2_EN_ENABLE)
514 micbias_enabled = true;
515
516 pm8916_mbhc_configure_bias(wcd, micbias_enabled);
517
518 int_en_mask = MBHC_SWITCH_INT;
519 if (wcd->mbhc_btn_enabled)
520 int_en_mask |= MBHC_BUTTON_PRESS_DET | MBHC_BUTTON_RELEASE_DET;
521
522 snd_soc_component_update_bits(component, CDC_D_INT_EN_CLR, int_en_mask, 0);
523 snd_soc_component_update_bits(component, CDC_D_INT_EN_SET, int_en_mask, int_en_mask);
524 wcd->mbhc_btn0_released = false;
525 wcd->detect_accessory_type = true;
526}
527
528static int pm8916_wcd_analog_enable_micbias_int2(struct
529 snd_soc_dapm_widget
530 *w, struct snd_kcontrol
531 *kcontrol, int event)
532{
533 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
534 struct pm8916_wcd_analog_priv *wcd = snd_soc_component_get_drvdata(component);
535
536 switch (event) {
537 case SND_SOC_DAPM_PRE_PMU:
538 snd_soc_component_update_bits(component, CDC_A_MICB_2_EN,
539 CDC_A_MICB_2_PULL_DOWN_EN_MASK, 0);
540 break;
541 case SND_SOC_DAPM_POST_PMU:
542 pm8916_mbhc_configure_bias(wcd, true);
543 break;
544 case SND_SOC_DAPM_POST_PMD:
545 pm8916_mbhc_configure_bias(wcd, false);
546 break;
547 }
548
549 return pm8916_wcd_analog_enable_micbias_int(w, kcontrol, event);
550}
551
552static int pm8916_wcd_analog_enable_adc(struct snd_soc_dapm_widget *w,
553 struct snd_kcontrol *kcontrol,
554 int event)
555{
556 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
557 u16 adc_reg = CDC_A_TX_1_2_TEST_CTL_2;
558 u8 init_bit_shift;
559
560 if (w->reg == CDC_A_TX_1_EN)
561 init_bit_shift = 5;
562 else
563 init_bit_shift = 4;
564
565 switch (event) {
566 case SND_SOC_DAPM_PRE_PMU:
567 if (w->reg == CDC_A_TX_2_EN)
568 snd_soc_component_update_bits(component, CDC_A_MICB_1_CTL,
569 MICB_1_CTL_CFILT_REF_SEL_MASK,
570 MICB_1_CTL_CFILT_REF_SEL_HPF_REF);
571
572
573
574
575
576 usleep_range(10000, 10010);
577 snd_soc_component_update_bits(component, adc_reg, 1 << init_bit_shift,
578 1 << init_bit_shift);
579 switch (w->reg) {
580 case CDC_A_TX_1_EN:
581 snd_soc_component_update_bits(component, CDC_D_CDC_CONN_TX1_CTL,
582 CONN_TX1_SERIAL_TX1_MUX,
583 CONN_TX1_SERIAL_TX1_ADC_1);
584 break;
585 case CDC_A_TX_2_EN:
586 case CDC_A_TX_3_EN:
587 snd_soc_component_update_bits(component, CDC_D_CDC_CONN_TX2_CTL,
588 CONN_TX2_SERIAL_TX2_MUX,
589 CONN_TX2_SERIAL_TX2_ADC_2);
590 break;
591 }
592 break;
593 case SND_SOC_DAPM_POST_PMU:
594
595
596
597
598 usleep_range(12000, 12010);
599 snd_soc_component_update_bits(component, adc_reg, 1 << init_bit_shift, 0x00);
600 break;
601 case SND_SOC_DAPM_POST_PMD:
602 switch (w->reg) {
603 case CDC_A_TX_1_EN:
604 snd_soc_component_update_bits(component, CDC_D_CDC_CONN_TX1_CTL,
605 CONN_TX1_SERIAL_TX1_MUX,
606 CONN_TX1_SERIAL_TX1_ZERO);
607 break;
608 case CDC_A_TX_2_EN:
609 snd_soc_component_update_bits(component, CDC_A_MICB_1_CTL,
610 MICB_1_CTL_CFILT_REF_SEL_MASK, 0);
611 fallthrough;
612 case CDC_A_TX_3_EN:
613 snd_soc_component_update_bits(component, CDC_D_CDC_CONN_TX2_CTL,
614 CONN_TX2_SERIAL_TX2_MUX,
615 CONN_TX2_SERIAL_TX2_ZERO);
616 break;
617 }
618
619
620 break;
621 }
622 return 0;
623}
624
625static int pm8916_wcd_analog_enable_spk_pa(struct snd_soc_dapm_widget *w,
626 struct snd_kcontrol *kcontrol,
627 int event)
628{
629 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
630
631 switch (event) {
632 case SND_SOC_DAPM_PRE_PMU:
633 snd_soc_component_update_bits(component, CDC_A_SPKR_PWRSTG_CTL,
634 SPKR_PWRSTG_CTL_DAC_EN_MASK |
635 SPKR_PWRSTG_CTL_BBM_MASK |
636 SPKR_PWRSTG_CTL_HBRDGE_EN_MASK |
637 SPKR_PWRSTG_CTL_CLAMP_EN_MASK,
638 SPKR_PWRSTG_CTL_DAC_EN|
639 SPKR_PWRSTG_CTL_BBM_EN |
640 SPKR_PWRSTG_CTL_HBRDGE_EN |
641 SPKR_PWRSTG_CTL_CLAMP_EN);
642
643 snd_soc_component_update_bits(component, CDC_A_RX_EAR_CTL,
644 RX_EAR_CTL_SPK_VBAT_LDO_EN_MASK,
645 RX_EAR_CTL_SPK_VBAT_LDO_EN_ENABLE);
646 break;
647 case SND_SOC_DAPM_POST_PMU:
648 snd_soc_component_update_bits(component, CDC_A_SPKR_DRV_CTL,
649 SPKR_DRV_CTL_DEF_MASK,
650 SPKR_DRV_CTL_DEF_VAL);
651 snd_soc_component_update_bits(component, w->reg,
652 SPKR_DRV_CLASSD_PA_EN_MASK,
653 SPKR_DRV_CLASSD_PA_EN_ENABLE);
654 break;
655 case SND_SOC_DAPM_POST_PMD:
656 snd_soc_component_update_bits(component, CDC_A_SPKR_PWRSTG_CTL,
657 SPKR_PWRSTG_CTL_DAC_EN_MASK|
658 SPKR_PWRSTG_CTL_BBM_MASK |
659 SPKR_PWRSTG_CTL_HBRDGE_EN_MASK |
660 SPKR_PWRSTG_CTL_CLAMP_EN_MASK, 0);
661
662 snd_soc_component_update_bits(component, CDC_A_SPKR_DAC_CTL,
663 SPKR_DAC_CTL_DAC_RESET_MASK,
664 SPKR_DAC_CTL_DAC_RESET_NORMAL);
665 snd_soc_component_update_bits(component, CDC_A_RX_EAR_CTL,
666 RX_EAR_CTL_SPK_VBAT_LDO_EN_MASK, 0);
667 break;
668 }
669 return 0;
670}
671
672static int pm8916_wcd_analog_enable_ear_pa(struct snd_soc_dapm_widget *w,
673 struct snd_kcontrol *kcontrol,
674 int event)
675{
676 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
677
678 switch (event) {
679 case SND_SOC_DAPM_PRE_PMU:
680 snd_soc_component_update_bits(component, CDC_A_RX_EAR_CTL,
681 RX_EAR_CTL_PA_SEL_MASK, RX_EAR_CTL_PA_SEL);
682 break;
683 case SND_SOC_DAPM_POST_PMU:
684 snd_soc_component_update_bits(component, CDC_A_RX_EAR_CTL,
685 RX_EAR_CTL_PA_EAR_PA_EN_MASK,
686 RX_EAR_CTL_PA_EAR_PA_EN_ENABLE);
687 break;
688 case SND_SOC_DAPM_POST_PMD:
689 snd_soc_component_update_bits(component, CDC_A_RX_EAR_CTL,
690 RX_EAR_CTL_PA_EAR_PA_EN_MASK, 0);
691
692 usleep_range(7000, 7100);
693 snd_soc_component_update_bits(component, CDC_A_RX_EAR_CTL,
694 RX_EAR_CTL_PA_SEL_MASK, 0);
695 break;
696 }
697 return 0;
698}
699
700static const struct reg_default wcd_reg_defaults_2_0[] = {
701 {CDC_A_RX_COM_OCP_CTL, 0xD1},
702 {CDC_A_RX_COM_OCP_COUNT, 0xFF},
703 {CDC_D_SEC_ACCESS, 0xA5},
704 {CDC_D_PERPH_RESET_CTL3, 0x0F},
705 {CDC_A_TX_1_2_OPAMP_BIAS, 0x4F},
706 {CDC_A_NCP_FBCTRL, 0x28},
707 {CDC_A_SPKR_DRV_CTL, 0x69},
708 {CDC_A_SPKR_DRV_DBG, 0x01},
709 {CDC_A_BOOST_EN_CTL, 0x5F},
710 {CDC_A_SLOPE_COMP_IP_ZERO, 0x88},
711 {CDC_A_SEC_ACCESS, 0xA5},
712 {CDC_A_PERPH_RESET_CTL3, 0x0F},
713 {CDC_A_CURRENT_LIMIT, 0x82},
714 {CDC_A_SPKR_DAC_CTL, 0x03},
715 {CDC_A_SPKR_OCP_CTL, 0xE1},
716 {CDC_A_MASTER_BIAS_CTL, 0x30},
717};
718
719static int pm8916_wcd_analog_probe(struct snd_soc_component *component)
720{
721 struct pm8916_wcd_analog_priv *priv = dev_get_drvdata(component->dev);
722 int err, reg;
723
724 err = regulator_bulk_enable(ARRAY_SIZE(priv->supplies), priv->supplies);
725 if (err != 0) {
726 dev_err(component->dev, "failed to enable regulators (%d)\n", err);
727 return err;
728 }
729
730 snd_soc_component_init_regmap(component,
731 dev_get_regmap(component->dev->parent, NULL));
732 snd_soc_component_set_drvdata(component, priv);
733 priv->pmic_rev = snd_soc_component_read(component, CDC_D_REVISION1);
734 priv->codec_version = snd_soc_component_read(component, CDC_D_PERPH_SUBTYPE);
735
736 dev_info(component->dev, "PMIC REV: %d\t CODEC Version: %d\n",
737 priv->pmic_rev, priv->codec_version);
738
739 snd_soc_component_write(component, CDC_D_PERPH_RESET_CTL4, 0x01);
740 snd_soc_component_write(component, CDC_A_PERPH_RESET_CTL4, 0x01);
741
742 for (reg = 0; reg < ARRAY_SIZE(wcd_reg_defaults_2_0); reg++)
743 snd_soc_component_write(component, wcd_reg_defaults_2_0[reg].reg,
744 wcd_reg_defaults_2_0[reg].def);
745
746 priv->component = component;
747
748 snd_soc_component_update_bits(component, CDC_D_CDC_RST_CTL,
749 RST_CTL_DIG_SW_RST_N_MASK,
750 RST_CTL_DIG_SW_RST_N_REMOVE_RESET);
751
752 pm8916_wcd_setup_mbhc(priv);
753
754 return 0;
755}
756
757static void pm8916_wcd_analog_remove(struct snd_soc_component *component)
758{
759 struct pm8916_wcd_analog_priv *priv = dev_get_drvdata(component->dev);
760
761 snd_soc_component_update_bits(component, CDC_D_CDC_RST_CTL,
762 RST_CTL_DIG_SW_RST_N_MASK, 0);
763
764 regulator_bulk_disable(ARRAY_SIZE(priv->supplies),
765 priv->supplies);
766}
767
768static const struct snd_soc_dapm_route pm8916_wcd_analog_audio_map[] = {
769
770 {"PDM_RX1", NULL, "PDM Playback"},
771 {"PDM_RX2", NULL, "PDM Playback"},
772 {"PDM_RX3", NULL, "PDM Playback"},
773 {"PDM Capture", NULL, "PDM_TX"},
774
775
776 {"PDM_TX", NULL, "ADC2"},
777 {"PDM_TX", NULL, "ADC3"},
778 {"ADC2", NULL, "ADC2 MUX"},
779 {"ADC3", NULL, "ADC2 MUX"},
780 {"ADC2 MUX", "INP2", "ADC2_INP2"},
781 {"ADC2 MUX", "INP3", "ADC2_INP3"},
782
783 {"PDM_TX", NULL, "ADC1"},
784 {"ADC1", NULL, "AMIC1"},
785 {"ADC2_INP2", NULL, "AMIC2"},
786 {"ADC2_INP3", NULL, "AMIC3"},
787
788
789 {"HPHR DAC", NULL, "RDAC2 MUX"},
790 {"RDAC2 MUX", "RX1", "PDM_RX1"},
791 {"RDAC2 MUX", "RX2", "PDM_RX2"},
792 {"HPHL DAC", NULL, "PDM_RX1"},
793 {"PDM_RX1", NULL, "RXD1_CLK"},
794 {"PDM_RX2", NULL, "RXD2_CLK"},
795 {"PDM_RX3", NULL, "RXD3_CLK"},
796
797 {"PDM_RX1", NULL, "RXD_PDM_CLK"},
798 {"PDM_RX2", NULL, "RXD_PDM_CLK"},
799 {"PDM_RX3", NULL, "RXD_PDM_CLK"},
800
801 {"ADC1", NULL, "TXD_CLK"},
802 {"ADC2", NULL, "TXD_CLK"},
803 {"ADC3", NULL, "TXD_CLK"},
804
805 {"ADC1", NULL, "TXA_CLK25"},
806 {"ADC2", NULL, "TXA_CLK25"},
807 {"ADC3", NULL, "TXA_CLK25"},
808
809 {"PDM_RX1", NULL, "A_MCLK2"},
810 {"PDM_RX2", NULL, "A_MCLK2"},
811 {"PDM_RX3", NULL, "A_MCLK2"},
812
813 {"PDM_TX", NULL, "A_MCLK2"},
814 {"A_MCLK2", NULL, "A_MCLK"},
815
816
817 {"EAR", NULL, "EAR_S"},
818 {"EAR_S", "Switch", "EAR PA"},
819 {"EAR PA", NULL, "RX_BIAS"},
820 {"EAR PA", NULL, "HPHL DAC"},
821 {"EAR PA", NULL, "HPHR DAC"},
822 {"EAR PA", NULL, "EAR CP"},
823
824
825 {"HPH_L", NULL, "HPHL PA"},
826 {"HPH_R", NULL, "HPHR PA"},
827
828 {"HPHL DAC", NULL, "EAR_HPHL_CLK"},
829 {"HPHR DAC", NULL, "EAR_HPHR_CLK"},
830
831 {"CP", NULL, "NCP_CLK"},
832
833 {"HPHL PA", NULL, "HPHL"},
834 {"HPHR PA", NULL, "HPHR"},
835 {"HPHL PA", NULL, "CP"},
836 {"HPHL PA", NULL, "RX_BIAS"},
837 {"HPHR PA", NULL, "CP"},
838 {"HPHR PA", NULL, "RX_BIAS"},
839 {"HPHL", "Switch", "HPHL DAC"},
840 {"HPHR", "Switch", "HPHR DAC"},
841
842 {"RX_BIAS", NULL, "DAC_REF"},
843
844 {"SPK_OUT", NULL, "SPK PA"},
845 {"SPK PA", NULL, "RX_BIAS"},
846 {"SPK PA", NULL, "SPKR_CLK"},
847 {"SPK PA", NULL, "SPK DAC"},
848 {"SPK DAC", "Switch", "PDM_RX3"},
849
850 {"MIC_BIAS1", NULL, "INT_LDO_H"},
851 {"MIC_BIAS2", NULL, "INT_LDO_H"},
852 {"MIC_BIAS1", NULL, "vdd-micbias"},
853 {"MIC_BIAS2", NULL, "vdd-micbias"},
854
855 {"MIC BIAS External1", NULL, "MIC_BIAS1"},
856 {"MIC BIAS Internal1", NULL, "MIC_BIAS1"},
857 {"MIC BIAS External2", NULL, "MIC_BIAS2"},
858 {"MIC BIAS Internal2", NULL, "MIC_BIAS2"},
859 {"MIC BIAS Internal3", NULL, "MIC_BIAS1"},
860};
861
862static const struct snd_soc_dapm_widget pm8916_wcd_analog_dapm_widgets[] = {
863
864 SND_SOC_DAPM_AIF_IN("PDM_RX1", NULL, 0, SND_SOC_NOPM, 0, 0),
865 SND_SOC_DAPM_AIF_IN("PDM_RX2", NULL, 0, SND_SOC_NOPM, 0, 0),
866 SND_SOC_DAPM_AIF_IN("PDM_RX3", NULL, 0, SND_SOC_NOPM, 0, 0),
867 SND_SOC_DAPM_AIF_OUT("PDM_TX", NULL, 0, SND_SOC_NOPM, 0, 0),
868
869 SND_SOC_DAPM_INPUT("AMIC1"),
870 SND_SOC_DAPM_INPUT("AMIC3"),
871 SND_SOC_DAPM_INPUT("AMIC2"),
872 SND_SOC_DAPM_OUTPUT("EAR"),
873 SND_SOC_DAPM_OUTPUT("HPH_L"),
874 SND_SOC_DAPM_OUTPUT("HPH_R"),
875
876
877 SND_SOC_DAPM_SUPPLY("INT_LDO_H", SND_SOC_NOPM, 1, 0, NULL, 0),
878
879 SND_SOC_DAPM_PGA_E("EAR PA", SND_SOC_NOPM,
880 0, 0, NULL, 0,
881 pm8916_wcd_analog_enable_ear_pa,
882 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
883 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
884 SND_SOC_DAPM_MUX("EAR_S", SND_SOC_NOPM, 0, 0, &ear_mux),
885 SND_SOC_DAPM_SUPPLY("EAR CP", CDC_A_NCP_EN, 4, 0, NULL, 0),
886
887 SND_SOC_DAPM_PGA("HPHL PA", CDC_A_RX_HPH_CNP_EN, 5, 0, NULL, 0),
888 SND_SOC_DAPM_MUX("HPHL", SND_SOC_NOPM, 0, 0, &hphl_mux),
889 SND_SOC_DAPM_MIXER("HPHL DAC", CDC_A_RX_HPH_L_PA_DAC_CTL, 3, 0, NULL,
890 0),
891 SND_SOC_DAPM_PGA("HPHR PA", CDC_A_RX_HPH_CNP_EN, 4, 0, NULL, 0),
892 SND_SOC_DAPM_MUX("HPHR", SND_SOC_NOPM, 0, 0, &hphr_mux),
893 SND_SOC_DAPM_MIXER("HPHR DAC", CDC_A_RX_HPH_R_PA_DAC_CTL, 3, 0, NULL,
894 0),
895 SND_SOC_DAPM_MIXER("SPK DAC", SND_SOC_NOPM, 0, 0,
896 spkr_switch, ARRAY_SIZE(spkr_switch)),
897
898
899 SND_SOC_DAPM_OUTPUT("SPK_OUT"),
900 SND_SOC_DAPM_PGA_E("SPK PA", CDC_A_SPKR_DRV_CTL,
901 6, 0, NULL, 0,
902 pm8916_wcd_analog_enable_spk_pa,
903 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
904 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
905 SND_SOC_DAPM_REGULATOR_SUPPLY("vdd-micbias", 0, 0),
906 SND_SOC_DAPM_SUPPLY("CP", CDC_A_NCP_EN, 0, 0, NULL, 0),
907
908 SND_SOC_DAPM_SUPPLY("DAC_REF", CDC_A_RX_COM_BIAS_DAC, 0, 0, NULL, 0),
909 SND_SOC_DAPM_SUPPLY("RX_BIAS", CDC_A_RX_COM_BIAS_DAC, 7, 0, NULL, 0),
910
911
912 SND_SOC_DAPM_SUPPLY("MIC_BIAS1", CDC_A_MICB_1_EN, 7, 0,
913 pm8916_wcd_analog_enable_micbias1,
914 SND_SOC_DAPM_POST_PMU),
915 SND_SOC_DAPM_SUPPLY("MIC_BIAS2", CDC_A_MICB_2_EN, 7, 0,
916 pm8916_wcd_analog_enable_micbias2,
917 SND_SOC_DAPM_POST_PMU),
918
919 SND_SOC_DAPM_SUPPLY("MIC BIAS External1", SND_SOC_NOPM, 0, 0, NULL, 0),
920 SND_SOC_DAPM_SUPPLY("MIC BIAS External2", SND_SOC_NOPM, 0, 0, NULL, 0),
921
922 SND_SOC_DAPM_SUPPLY("MIC BIAS Internal1", CDC_A_MICB_1_INT_RBIAS, 7, 0,
923 pm8916_wcd_analog_enable_micbias_int,
924 SND_SOC_DAPM_PRE_PMU),
925 SND_SOC_DAPM_SUPPLY("MIC BIAS Internal2", CDC_A_MICB_1_INT_RBIAS, 4, 0,
926 pm8916_wcd_analog_enable_micbias_int2,
927 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
928 SND_SOC_DAPM_POST_PMD),
929 SND_SOC_DAPM_SUPPLY("MIC BIAS Internal3", CDC_A_MICB_1_INT_RBIAS, 1, 0,
930 pm8916_wcd_analog_enable_micbias_int,
931 SND_SOC_DAPM_PRE_PMU),
932
933 SND_SOC_DAPM_ADC_E("ADC1", NULL, CDC_A_TX_1_EN, 7, 0,
934 pm8916_wcd_analog_enable_adc,
935 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
936 SND_SOC_DAPM_POST_PMD),
937 SND_SOC_DAPM_ADC_E("ADC2_INP2", NULL, CDC_A_TX_2_EN, 7, 0,
938 pm8916_wcd_analog_enable_adc,
939 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
940 SND_SOC_DAPM_POST_PMD),
941 SND_SOC_DAPM_ADC_E("ADC2_INP3", NULL, CDC_A_TX_3_EN, 7, 0,
942 pm8916_wcd_analog_enable_adc,
943 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
944 SND_SOC_DAPM_POST_PMD),
945
946 SND_SOC_DAPM_MIXER("ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
947 SND_SOC_DAPM_MIXER("ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
948
949 SND_SOC_DAPM_MUX("ADC2 MUX", SND_SOC_NOPM, 0, 0, &tx_adc2_mux),
950 SND_SOC_DAPM_MUX("RDAC2 MUX", SND_SOC_NOPM, 0, 0, &rdac2_mux),
951
952
953 SND_SOC_DAPM_SUPPLY("EAR_HPHR_CLK", CDC_D_CDC_ANA_CLK_CTL, 0, 0, NULL,
954 0),
955 SND_SOC_DAPM_SUPPLY("EAR_HPHL_CLK", CDC_D_CDC_ANA_CLK_CTL, 1, 0, NULL,
956 0),
957 SND_SOC_DAPM_SUPPLY("SPKR_CLK", CDC_D_CDC_ANA_CLK_CTL, 4, 0, NULL, 0),
958 SND_SOC_DAPM_SUPPLY("TXA_CLK25", CDC_D_CDC_ANA_CLK_CTL, 5, 0, NULL, 0),
959
960
961
962 SND_SOC_DAPM_SUPPLY("RXD1_CLK", CDC_D_CDC_DIG_CLK_CTL, 0, 0, NULL, 0),
963 SND_SOC_DAPM_SUPPLY("RXD2_CLK", CDC_D_CDC_DIG_CLK_CTL, 1, 0, NULL, 0),
964 SND_SOC_DAPM_SUPPLY("RXD3_CLK", CDC_D_CDC_DIG_CLK_CTL, 2, 0, NULL, 0),
965
966 SND_SOC_DAPM_SUPPLY("TXD_CLK", CDC_D_CDC_DIG_CLK_CTL, 4, 0, NULL, 0),
967 SND_SOC_DAPM_SUPPLY("NCP_CLK", CDC_D_CDC_DIG_CLK_CTL, 6, 0, NULL, 0),
968 SND_SOC_DAPM_SUPPLY("RXD_PDM_CLK", CDC_D_CDC_DIG_CLK_CTL, 7, 0, NULL,
969 0),
970
971
972 SND_SOC_DAPM_SUPPLY("A_MCLK", CDC_D_CDC_TOP_CLK_CTL, 2, 0, NULL, 0),
973
974 SND_SOC_DAPM_SUPPLY("A_MCLK2", CDC_D_CDC_TOP_CLK_CTL, 3, 0, NULL, 0),
975};
976
977static int pm8916_wcd_analog_set_jack(struct snd_soc_component *component,
978 struct snd_soc_jack *jack,
979 void *data)
980{
981 struct pm8916_wcd_analog_priv *wcd = snd_soc_component_get_drvdata(component);
982
983 wcd->jack = jack;
984
985 return 0;
986}
987
988static irqreturn_t mbhc_btn_release_irq_handler(int irq, void *arg)
989{
990 struct pm8916_wcd_analog_priv *priv = arg;
991
992 if (priv->detect_accessory_type) {
993 struct snd_soc_component *component = priv->component;
994 u32 val = snd_soc_component_read(component, CDC_A_MBHC_RESULT_1);
995
996
997 if ((val != -1) && !(val & CDC_A_MBHC_RESULT_1_BTN_RESULT_MASK))
998 priv->mbhc_btn0_released = true;
999
1000 } else {
1001 snd_soc_jack_report(priv->jack, 0, btn_mask);
1002 }
1003
1004 return IRQ_HANDLED;
1005}
1006
1007static irqreturn_t mbhc_btn_press_irq_handler(int irq, void *arg)
1008{
1009 struct pm8916_wcd_analog_priv *priv = arg;
1010 struct snd_soc_component *component = priv->component;
1011 u32 btn_result;
1012
1013 btn_result = snd_soc_component_read(component, CDC_A_MBHC_RESULT_1) &
1014 CDC_A_MBHC_RESULT_1_BTN_RESULT_MASK;
1015
1016 switch (btn_result) {
1017 case 0xf:
1018 snd_soc_jack_report(priv->jack, SND_JACK_BTN_4, btn_mask);
1019 break;
1020 case 0x7:
1021 snd_soc_jack_report(priv->jack, SND_JACK_BTN_3, btn_mask);
1022 break;
1023 case 0x3:
1024 snd_soc_jack_report(priv->jack, SND_JACK_BTN_2, btn_mask);
1025 break;
1026 case 0x1:
1027 snd_soc_jack_report(priv->jack, SND_JACK_BTN_1, btn_mask);
1028 break;
1029 case 0x0:
1030
1031 if (!priv->detect_accessory_type)
1032 snd_soc_jack_report(priv->jack,
1033 SND_JACK_BTN_0, btn_mask);
1034 break;
1035 default:
1036 dev_err(component->dev,
1037 "Unexpected button press result (%x)", btn_result);
1038 break;
1039 }
1040
1041 return IRQ_HANDLED;
1042}
1043
1044static irqreturn_t pm8916_mbhc_switch_irq_handler(int irq, void *arg)
1045{
1046 struct pm8916_wcd_analog_priv *priv = arg;
1047 struct snd_soc_component *component = priv->component;
1048 bool ins = false;
1049
1050 if (snd_soc_component_read(component, CDC_A_MBHC_DET_CTL_1) &
1051 CDC_A_MBHC_DET_CTL_MECH_DET_TYPE_MASK)
1052 ins = true;
1053
1054
1055 snd_soc_component_update_bits(component, CDC_A_MBHC_DET_CTL_1,
1056 CDC_A_MBHC_DET_CTL_MECH_DET_TYPE_MASK,
1057 (!ins << CDC_A_MBHC_DET_CTL_MECH_DET_TYPE_SHIFT));
1058
1059
1060 if (ins) {
1061 bool micbias_enabled = false;
1062
1063 if (snd_soc_component_read(component, CDC_A_MICB_2_EN) &
1064 CDC_A_MICB_2_EN_ENABLE)
1065 micbias_enabled = true;
1066
1067 pm8916_mbhc_configure_bias(priv, micbias_enabled);
1068
1069
1070
1071
1072
1073
1074
1075 if (priv->mbhc_btn0_released)
1076 snd_soc_jack_report(priv->jack,
1077 SND_JACK_HEADSET, hs_jack_mask);
1078 else
1079 snd_soc_jack_report(priv->jack,
1080 SND_JACK_HEADPHONE, hs_jack_mask);
1081
1082 priv->detect_accessory_type = false;
1083
1084 } else {
1085 snd_soc_jack_report(priv->jack, 0, hs_jack_mask);
1086 priv->detect_accessory_type = true;
1087 priv->mbhc_btn0_released = false;
1088 }
1089
1090 return IRQ_HANDLED;
1091}
1092
1093static struct snd_soc_dai_driver pm8916_wcd_analog_dai[] = {
1094 [0] = {
1095 .name = "pm8916_wcd_analog_pdm_rx",
1096 .id = 0,
1097 .playback = {
1098 .stream_name = "PDM Playback",
1099 .rates = MSM8916_WCD_ANALOG_RATES,
1100 .formats = MSM8916_WCD_ANALOG_FORMATS,
1101 .channels_min = 1,
1102 .channels_max = 3,
1103 },
1104 },
1105 [1] = {
1106 .name = "pm8916_wcd_analog_pdm_tx",
1107 .id = 1,
1108 .capture = {
1109 .stream_name = "PDM Capture",
1110 .rates = MSM8916_WCD_ANALOG_RATES,
1111 .formats = MSM8916_WCD_ANALOG_FORMATS,
1112 .channels_min = 1,
1113 .channels_max = 4,
1114 },
1115 },
1116};
1117
1118static const struct snd_soc_component_driver pm8916_wcd_analog = {
1119 .probe = pm8916_wcd_analog_probe,
1120 .remove = pm8916_wcd_analog_remove,
1121 .set_jack = pm8916_wcd_analog_set_jack,
1122 .controls = pm8916_wcd_analog_snd_controls,
1123 .num_controls = ARRAY_SIZE(pm8916_wcd_analog_snd_controls),
1124 .dapm_widgets = pm8916_wcd_analog_dapm_widgets,
1125 .num_dapm_widgets = ARRAY_SIZE(pm8916_wcd_analog_dapm_widgets),
1126 .dapm_routes = pm8916_wcd_analog_audio_map,
1127 .num_dapm_routes = ARRAY_SIZE(pm8916_wcd_analog_audio_map),
1128 .idle_bias_on = 1,
1129 .use_pmdown_time = 1,
1130 .endianness = 1,
1131 .non_legacy_dai_naming = 1,
1132};
1133
1134static int pm8916_wcd_analog_parse_dt(struct device *dev,
1135 struct pm8916_wcd_analog_priv *priv)
1136{
1137 int rval;
1138
1139 if (of_property_read_bool(dev->of_node, "qcom,micbias1-ext-cap"))
1140 priv->micbias1_cap_mode = MICB_1_EN_EXT_BYP_CAP;
1141 else
1142 priv->micbias1_cap_mode = MICB_1_EN_NO_EXT_BYP_CAP;
1143
1144 if (of_property_read_bool(dev->of_node, "qcom,micbias2-ext-cap"))
1145 priv->micbias2_cap_mode = MICB_1_EN_EXT_BYP_CAP;
1146 else
1147 priv->micbias2_cap_mode = MICB_1_EN_NO_EXT_BYP_CAP;
1148
1149 of_property_read_u32(dev->of_node, "qcom,micbias-lvl",
1150 &priv->micbias_mv);
1151
1152 if (of_property_read_bool(dev->of_node,
1153 "qcom,hphl-jack-type-normally-open"))
1154 priv->hphl_jack_type_normally_open = true;
1155 else
1156 priv->hphl_jack_type_normally_open = false;
1157
1158 if (of_property_read_bool(dev->of_node,
1159 "qcom,gnd-jack-type-normally-open"))
1160 priv->gnd_jack_type_normally_open = true;
1161 else
1162 priv->gnd_jack_type_normally_open = false;
1163
1164 priv->mbhc_btn_enabled = true;
1165 rval = of_property_read_u32_array(dev->of_node,
1166 "qcom,mbhc-vthreshold-low",
1167 &priv->vref_btn_cs[0],
1168 MBHC_MAX_BUTTONS);
1169 if (rval < 0) {
1170 priv->mbhc_btn_enabled = false;
1171 } else {
1172 rval = of_property_read_u32_array(dev->of_node,
1173 "qcom,mbhc-vthreshold-high",
1174 &priv->vref_btn_micb[0],
1175 MBHC_MAX_BUTTONS);
1176 if (rval < 0)
1177 priv->mbhc_btn_enabled = false;
1178 }
1179
1180 if (!priv->mbhc_btn_enabled)
1181 dev_err(dev,
1182 "DT property missing, MBHC btn detection disabled\n");
1183
1184
1185 return 0;
1186}
1187
1188static int pm8916_wcd_analog_spmi_probe(struct platform_device *pdev)
1189{
1190 struct pm8916_wcd_analog_priv *priv;
1191 struct device *dev = &pdev->dev;
1192 int ret, i, irq;
1193
1194 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
1195 if (!priv)
1196 return -ENOMEM;
1197
1198 ret = pm8916_wcd_analog_parse_dt(dev, priv);
1199 if (ret < 0)
1200 return ret;
1201
1202 priv->mclk = devm_clk_get(dev, "mclk");
1203 if (IS_ERR(priv->mclk)) {
1204 dev_err(dev, "failed to get mclk\n");
1205 return PTR_ERR(priv->mclk);
1206 }
1207
1208 for (i = 0; i < ARRAY_SIZE(supply_names); i++)
1209 priv->supplies[i].supply = supply_names[i];
1210
1211 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(priv->supplies),
1212 priv->supplies);
1213 if (ret) {
1214 dev_err(dev, "Failed to get regulator supplies %d\n", ret);
1215 return ret;
1216 }
1217
1218 ret = clk_prepare_enable(priv->mclk);
1219 if (ret < 0) {
1220 dev_err(dev, "failed to enable mclk %d\n", ret);
1221 return ret;
1222 }
1223
1224 irq = platform_get_irq_byname(pdev, "mbhc_switch_int");
1225 if (irq < 0) {
1226 ret = irq;
1227 goto err_disable_clk;
1228 }
1229
1230 ret = devm_request_threaded_irq(dev, irq, NULL,
1231 pm8916_mbhc_switch_irq_handler,
1232 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING |
1233 IRQF_ONESHOT,
1234 "mbhc switch irq", priv);
1235 if (ret)
1236 dev_err(dev, "cannot request mbhc switch irq\n");
1237
1238 if (priv->mbhc_btn_enabled) {
1239 irq = platform_get_irq_byname(pdev, "mbhc_but_press_det");
1240 if (irq < 0) {
1241 ret = irq;
1242 goto err_disable_clk;
1243 }
1244
1245 ret = devm_request_threaded_irq(dev, irq, NULL,
1246 mbhc_btn_press_irq_handler,
1247 IRQF_TRIGGER_RISING |
1248 IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
1249 "mbhc btn press irq", priv);
1250 if (ret)
1251 dev_err(dev, "cannot request mbhc button press irq\n");
1252
1253 irq = platform_get_irq_byname(pdev, "mbhc_but_rel_det");
1254 if (irq < 0) {
1255 ret = irq;
1256 goto err_disable_clk;
1257 }
1258
1259 ret = devm_request_threaded_irq(dev, irq, NULL,
1260 mbhc_btn_release_irq_handler,
1261 IRQF_TRIGGER_RISING |
1262 IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
1263 "mbhc btn release irq", priv);
1264 if (ret)
1265 dev_err(dev, "cannot request mbhc button release irq\n");
1266
1267 }
1268
1269 dev_set_drvdata(dev, priv);
1270
1271 return devm_snd_soc_register_component(dev, &pm8916_wcd_analog,
1272 pm8916_wcd_analog_dai,
1273 ARRAY_SIZE(pm8916_wcd_analog_dai));
1274
1275err_disable_clk:
1276 clk_disable_unprepare(priv->mclk);
1277 return ret;
1278}
1279
1280static int pm8916_wcd_analog_spmi_remove(struct platform_device *pdev)
1281{
1282 struct pm8916_wcd_analog_priv *priv = dev_get_drvdata(&pdev->dev);
1283
1284 clk_disable_unprepare(priv->mclk);
1285
1286 return 0;
1287}
1288
1289static const struct of_device_id pm8916_wcd_analog_spmi_match_table[] = {
1290 { .compatible = "qcom,pm8916-wcd-analog-codec", },
1291 { }
1292};
1293
1294MODULE_DEVICE_TABLE(of, pm8916_wcd_analog_spmi_match_table);
1295
1296static struct platform_driver pm8916_wcd_analog_spmi_driver = {
1297 .driver = {
1298 .name = "qcom,pm8916-wcd-spmi-codec",
1299 .of_match_table = pm8916_wcd_analog_spmi_match_table,
1300 },
1301 .probe = pm8916_wcd_analog_spmi_probe,
1302 .remove = pm8916_wcd_analog_spmi_remove,
1303};
1304
1305module_platform_driver(pm8916_wcd_analog_spmi_driver);
1306
1307MODULE_AUTHOR("Srinivas Kandagatla <srinivas.kandagatla@linaro.org>");
1308MODULE_DESCRIPTION("PMIC PM8916 WCD Analog Codec driver");
1309MODULE_LICENSE("GPL v2");
1310
