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8#include <linux/delay.h>
9#include <linux/device.h>
10#include <linux/pm_runtime.h>
11#include <linux/mod_devicetable.h>
12#include <linux/module.h>
13#include <linux/regmap.h>
14#include <sound/core.h>
15#include <sound/pcm.h>
16#include <sound/pcm_params.h>
17#include <sound/soc-dapm.h>
18#include <sound/initval.h>
19#include "rt1316-sdw.h"
20
21static const struct reg_default rt1316_reg_defaults[] = {
22 { 0x3004, 0x00 },
23 { 0x3005, 0x00 },
24 { 0x3206, 0x00 },
25 { 0xc001, 0x00 },
26 { 0xc002, 0x00 },
27 { 0xc003, 0x00 },
28 { 0xc004, 0x00 },
29 { 0xc005, 0x00 },
30 { 0xc006, 0x00 },
31 { 0xc007, 0x00 },
32 { 0xc008, 0x00 },
33 { 0xc009, 0x00 },
34 { 0xc00a, 0x00 },
35 { 0xc00b, 0x00 },
36 { 0xc00c, 0x00 },
37 { 0xc00d, 0x00 },
38 { 0xc00e, 0x00 },
39 { 0xc00f, 0x00 },
40 { 0xc010, 0xa5 },
41 { 0xc011, 0x00 },
42 { 0xc012, 0xff },
43 { 0xc013, 0xff },
44 { 0xc014, 0x40 },
45 { 0xc015, 0x00 },
46 { 0xc016, 0x00 },
47 { 0xc017, 0x00 },
48 { 0xc605, 0x30 },
49 { 0xc700, 0x0a },
50 { 0xc701, 0xaa },
51 { 0xc702, 0x1a },
52 { 0xc703, 0x0a },
53 { 0xc710, 0x80 },
54 { 0xc711, 0x00 },
55 { 0xc712, 0x3e },
56 { 0xc713, 0x80 },
57 { 0xc714, 0x80 },
58 { 0xc715, 0x06 },
59 { 0xd101, 0x00 },
60 { 0xd102, 0x30 },
61 { 0xd103, 0x00 },
62 { SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_UDMPU21, RT1316_SDCA_CTL_UDMPU_CLUSTER, 0), 0x00 },
63 { SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_FU21, RT1316_SDCA_CTL_FU_MUTE, CH_L), 0x01 },
64 { SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_FU21, RT1316_SDCA_CTL_FU_MUTE, CH_R), 0x01 },
65 { SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_XU24, RT1316_SDCA_CTL_BYPASS, 0), 0x01 },
66 { SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_PDE23, RT1316_SDCA_CTL_REQ_POWER_STATE, 0), 0x03 },
67 { SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_PDE22, RT1316_SDCA_CTL_REQ_POWER_STATE, 0), 0x03 },
68 { SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_PDE24, RT1316_SDCA_CTL_REQ_POWER_STATE, 0), 0x03 },
69};
70
71static const struct reg_sequence rt1316_blind_write[] = {
72 { 0xc710, 0x17 },
73 { 0xc711, 0x80 },
74 { 0xc712, 0x26 },
75 { 0xc713, 0x06 },
76 { 0xc714, 0x80 },
77 { 0xc715, 0x06 },
78 { 0xc702, 0x0a },
79 { 0xc703, 0x0a },
80 { 0xc001, 0x45 },
81 { 0xc003, 0x00 },
82 { 0xc004, 0x11 },
83 { 0xc005, 0x00 },
84 { 0xc006, 0x00 },
85 { 0xc106, 0x00 },
86 { 0xc007, 0x11 },
87 { 0xc008, 0x11 },
88 { 0xc009, 0x00 },
89
90 { 0x2f0a, 0x00 },
91 { 0xd101, 0xf0 },
92 { 0xd103, 0x9b },
93 { 0x2f36, 0x8e },
94 { 0x3206, 0x80 },
95 { 0x3211, 0x0b },
96 { 0x3216, 0x06 },
97 { 0xc614, 0x20 },
98 { 0xc615, 0x0a },
99 { 0xc616, 0x02 },
100 { 0xc617, 0x00 },
101 { 0xc60b, 0x10 },
102 { 0xc60e, 0x05 },
103 { 0xc102, 0x00 },
104 { 0xc090, 0xb0 },
105 { 0xc00f, 0x01 },
106 { 0xc09c, 0x7b },
107
108 { 0xc602, 0x07 },
109 { 0xc603, 0x07 },
110 { 0xc0a3, 0x71 },
111 { 0xc00b, 0x30 },
112 { 0xc093, 0x80 },
113 { 0xc09d, 0x80 },
114 { 0xc0b0, 0x77 },
115 { 0xc010, 0xa5 },
116 { 0xc050, 0x83 },
117 { 0x2f55, 0x03 },
118 { 0x3217, 0xb5 },
119 { 0x3202, 0x02 },
120
121 { SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_XU24, RT1316_SDCA_CTL_BYPASS, 0), 0x00 },
122
123
124 { 0x2232, 0x80 },
125 { 0xc0b0, 0x77 },
126 { 0xc011, 0x00 },
127 { 0xc020, 0x00 },
128 { 0xc023, 0x00 },
129 { 0x3101, 0x00 },
130 { 0x3004, 0xa0 },
131 { 0x3005, 0xb1 },
132 { 0xc007, 0x11 },
133 { 0xc008, 0x11 },
134 { 0xc009, 0x00 },
135 { 0xc022, 0xd6 },
136 { 0xc025, 0xd6 },
137
138 { 0xd001, 0x03 },
139 { 0xd002, 0xbf },
140 { 0xd003, 0x03 },
141 { 0xd004, 0xbf },
142};
143
144static bool rt1316_readable_register(struct device *dev, unsigned int reg)
145{
146 switch (reg) {
147 case 0x2f0a:
148 case 0x2f36:
149 case 0x3203 ... 0x320e:
150 case 0xc000 ... 0xc7b4:
151 case 0xcf00 ... 0xcf03:
152 case 0xd101 ... 0xd103:
153 case SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_UDMPU21, RT1316_SDCA_CTL_UDMPU_CLUSTER, 0):
154 case SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_FU21, RT1316_SDCA_CTL_FU_MUTE, CH_L):
155 case SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_FU21, RT1316_SDCA_CTL_FU_MUTE, CH_R):
156 case SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_PDE23, RT1316_SDCA_CTL_REQ_POWER_STATE, 0):
157 case SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_PDE27, RT1316_SDCA_CTL_REQ_POWER_STATE, 0):
158 case SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_PDE22, RT1316_SDCA_CTL_REQ_POWER_STATE, 0):
159 case SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_PDE24, RT1316_SDCA_CTL_REQ_POWER_STATE, 0):
160 return true;
161 default:
162 return false;
163 }
164}
165
166static bool rt1316_volatile_register(struct device *dev, unsigned int reg)
167{
168 switch (reg) {
169 case 0xc000:
170 case 0xc093:
171 case 0xc09d:
172 case 0xc0a3:
173 case 0xc201:
174 case 0xc427 ... 0xc428:
175 case 0xd102:
176 return true;
177 default:
178 return false;
179 }
180}
181
182static const struct regmap_config rt1316_sdw_regmap = {
183 .reg_bits = 32,
184 .val_bits = 8,
185 .readable_reg = rt1316_readable_register,
186 .volatile_reg = rt1316_volatile_register,
187 .max_register = 0x4108ffff,
188 .reg_defaults = rt1316_reg_defaults,
189 .num_reg_defaults = ARRAY_SIZE(rt1316_reg_defaults),
190 .cache_type = REGCACHE_RBTREE,
191 .use_single_read = true,
192 .use_single_write = true,
193};
194
195static int rt1316_read_prop(struct sdw_slave *slave)
196{
197 struct sdw_slave_prop *prop = &slave->prop;
198 int nval;
199 int i, j;
200 u32 bit;
201 unsigned long addr;
202 struct sdw_dpn_prop *dpn;
203
204 prop->scp_int1_mask = SDW_SCP_INT1_BUS_CLASH | SDW_SCP_INT1_PARITY;
205 prop->quirks = SDW_SLAVE_QUIRKS_INVALID_INITIAL_PARITY;
206 prop->is_sdca = true;
207
208 prop->paging_support = true;
209
210
211 prop->source_ports = 0x04;
212 prop->sink_ports = 0x2;
213
214 nval = hweight32(prop->source_ports);
215 prop->src_dpn_prop = devm_kcalloc(&slave->dev, nval,
216 sizeof(*prop->src_dpn_prop), GFP_KERNEL);
217 if (!prop->src_dpn_prop)
218 return -ENOMEM;
219
220 i = 0;
221 dpn = prop->src_dpn_prop;
222 addr = prop->source_ports;
223 for_each_set_bit(bit, &addr, 32) {
224 dpn[i].num = bit;
225 dpn[i].type = SDW_DPN_FULL;
226 dpn[i].simple_ch_prep_sm = true;
227 dpn[i].ch_prep_timeout = 10;
228 i++;
229 }
230
231
232 nval = hweight32(prop->sink_ports);
233 prop->sink_dpn_prop = devm_kcalloc(&slave->dev, nval,
234 sizeof(*prop->sink_dpn_prop), GFP_KERNEL);
235 if (!prop->sink_dpn_prop)
236 return -ENOMEM;
237
238 j = 0;
239 dpn = prop->sink_dpn_prop;
240 addr = prop->sink_ports;
241 for_each_set_bit(bit, &addr, 32) {
242 dpn[j].num = bit;
243 dpn[j].type = SDW_DPN_FULL;
244 dpn[j].simple_ch_prep_sm = true;
245 dpn[j].ch_prep_timeout = 10;
246 j++;
247 }
248
249
250 prop->clk_stop_timeout = 20;
251
252 dev_dbg(&slave->dev, "%s\n", __func__);
253
254 return 0;
255}
256
257static int rt1316_io_init(struct device *dev, struct sdw_slave *slave)
258{
259 struct rt1316_sdw_priv *rt1316 = dev_get_drvdata(dev);
260
261 if (rt1316->hw_init)
262 return 0;
263
264 if (rt1316->first_hw_init) {
265 regcache_cache_only(rt1316->regmap, false);
266 regcache_cache_bypass(rt1316->regmap, true);
267 } else {
268
269
270
271
272
273 pm_runtime_set_autosuspend_delay(&slave->dev, 3000);
274 pm_runtime_use_autosuspend(&slave->dev);
275
276
277 pm_runtime_set_active(&slave->dev);
278
279
280 pm_runtime_mark_last_busy(&slave->dev);
281
282 pm_runtime_enable(&slave->dev);
283 }
284
285 pm_runtime_get_noresume(&slave->dev);
286
287
288 regmap_write(rt1316->regmap, 0xc000, 0x02);
289
290
291 regmap_multi_reg_write(rt1316->regmap, rt1316_blind_write,
292 ARRAY_SIZE(rt1316_blind_write));
293
294 if (rt1316->first_hw_init) {
295 regcache_cache_bypass(rt1316->regmap, false);
296 regcache_mark_dirty(rt1316->regmap);
297 } else
298 rt1316->first_hw_init = true;
299
300
301 rt1316->hw_init = true;
302
303 pm_runtime_mark_last_busy(&slave->dev);
304 pm_runtime_put_autosuspend(&slave->dev);
305
306 dev_dbg(&slave->dev, "%s hw_init complete\n", __func__);
307 return 0;
308}
309
310static int rt1316_update_status(struct sdw_slave *slave,
311 enum sdw_slave_status status)
312{
313 struct rt1316_sdw_priv *rt1316 = dev_get_drvdata(&slave->dev);
314
315
316 rt1316->status = status;
317
318 if (status == SDW_SLAVE_UNATTACHED)
319 rt1316->hw_init = false;
320
321
322
323
324
325 if (rt1316->hw_init || rt1316->status != SDW_SLAVE_ATTACHED)
326 return 0;
327
328
329 return rt1316_io_init(&slave->dev, slave);
330}
331
332static int rt1316_classd_event(struct snd_soc_dapm_widget *w,
333 struct snd_kcontrol *kcontrol, int event)
334{
335 struct snd_soc_component *component =
336 snd_soc_dapm_to_component(w->dapm);
337 struct rt1316_sdw_priv *rt1316 = snd_soc_component_get_drvdata(component);
338 unsigned char ps0 = 0x0, ps3 = 0x3;
339
340 switch (event) {
341 case SND_SOC_DAPM_POST_PMU:
342 regmap_write(rt1316->regmap,
343 SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_PDE23,
344 RT1316_SDCA_CTL_REQ_POWER_STATE, 0),
345 ps0);
346 regmap_write(rt1316->regmap,
347 SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_PDE27,
348 RT1316_SDCA_CTL_REQ_POWER_STATE, 0),
349 ps0);
350 regmap_write(rt1316->regmap,
351 SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_PDE22,
352 RT1316_SDCA_CTL_REQ_POWER_STATE, 0),
353 ps0);
354 break;
355 case SND_SOC_DAPM_PRE_PMD:
356 regmap_write(rt1316->regmap,
357 SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_PDE23,
358 RT1316_SDCA_CTL_REQ_POWER_STATE, 0),
359 ps3);
360 regmap_write(rt1316->regmap,
361 SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_PDE27,
362 RT1316_SDCA_CTL_REQ_POWER_STATE, 0),
363 ps3);
364 regmap_write(rt1316->regmap,
365 SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_PDE22,
366 RT1316_SDCA_CTL_REQ_POWER_STATE, 0),
367 ps3);
368 break;
369
370 default:
371 break;
372 }
373
374 return 0;
375}
376
377static int rt1316_pde24_event(struct snd_soc_dapm_widget *w,
378 struct snd_kcontrol *kcontrol, int event)
379{
380 struct snd_soc_component *component =
381 snd_soc_dapm_to_component(w->dapm);
382 struct rt1316_sdw_priv *rt1316 = snd_soc_component_get_drvdata(component);
383 unsigned char ps0 = 0x0, ps3 = 0x3;
384
385 switch (event) {
386 case SND_SOC_DAPM_POST_PMU:
387 regmap_write(rt1316->regmap,
388 SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_PDE24,
389 RT1316_SDCA_CTL_REQ_POWER_STATE, 0),
390 ps0);
391 break;
392 case SND_SOC_DAPM_PRE_PMD:
393 regmap_write(rt1316->regmap,
394 SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_PDE24,
395 RT1316_SDCA_CTL_REQ_POWER_STATE, 0),
396 ps3);
397 break;
398 }
399 return 0;
400}
401
402static const char * const rt1316_rx_data_ch_select[] = {
403 "L,R",
404 "L,L",
405 "L,R",
406 "L,L+R",
407 "R,L",
408 "R,R",
409 "R,L+R",
410 "L+R,L",
411 "L+R,R",
412 "L+R,L+R",
413};
414
415static SOC_ENUM_SINGLE_DECL(rt1316_rx_data_ch_enum,
416 SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_UDMPU21, RT1316_SDCA_CTL_UDMPU_CLUSTER, 0), 0,
417 rt1316_rx_data_ch_select);
418
419static const struct snd_kcontrol_new rt1316_snd_controls[] = {
420
421
422 SOC_ENUM("RX Channel Select", rt1316_rx_data_ch_enum),
423
424
425 SOC_SINGLE("XU24 Bypass Switch",
426 SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_XU24, RT1316_SDCA_CTL_BYPASS, 0), 0, 1, 0),
427
428
429 SOC_SINGLE("Left V Tag Select", 0x3004, 0, 7, 0),
430 SOC_SINGLE("Left I Tag Select", 0x3004, 4, 7, 0),
431 SOC_SINGLE("Right V Tag Select", 0x3005, 0, 7, 0),
432 SOC_SINGLE("Right I Tag Select", 0x3005, 4, 7, 0),
433
434
435 SOC_DOUBLE("Isense Mixer Switch", 0xc605, 2, 0, 1, 1),
436 SOC_DOUBLE("Vsense Mixer Switch", 0xc605, 3, 1, 1, 1),
437};
438
439static const struct snd_kcontrol_new rt1316_sto_dac =
440 SOC_DAPM_DOUBLE_R("Switch",
441 SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_FU21, RT1316_SDCA_CTL_FU_MUTE, CH_L),
442 SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_FU21, RT1316_SDCA_CTL_FU_MUTE, CH_R),
443 0, 1, 1);
444
445static const struct snd_soc_dapm_widget rt1316_dapm_widgets[] = {
446
447 SND_SOC_DAPM_AIF_IN("DP1RX", "DP1 Playback", 0, SND_SOC_NOPM, 0, 0),
448 SND_SOC_DAPM_AIF_OUT("DP2TX", "DP2 Capture", 0, SND_SOC_NOPM, 0, 0),
449
450
451 SND_SOC_DAPM_SWITCH("DAC", SND_SOC_NOPM, 0, 0, &rt1316_sto_dac),
452
453
454 SND_SOC_DAPM_PGA_E("CLASS D", SND_SOC_NOPM, 0, 0, NULL, 0,
455 rt1316_classd_event,
456 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
457 SND_SOC_DAPM_OUTPUT("SPOL"),
458 SND_SOC_DAPM_OUTPUT("SPOR"),
459
460 SND_SOC_DAPM_SUPPLY("PDE 24", SND_SOC_NOPM, 0, 0,
461 rt1316_pde24_event,
462 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
463 SND_SOC_DAPM_PGA("I Sense", SND_SOC_NOPM, 0, 0, NULL, 0),
464 SND_SOC_DAPM_PGA("V Sense", SND_SOC_NOPM, 0, 0, NULL, 0),
465 SND_SOC_DAPM_SIGGEN("I Gen"),
466 SND_SOC_DAPM_SIGGEN("V Gen"),
467};
468
469static const struct snd_soc_dapm_route rt1316_dapm_routes[] = {
470 { "DAC", "Switch", "DP1RX" },
471 { "CLASS D", NULL, "DAC" },
472 { "SPOL", NULL, "CLASS D" },
473 { "SPOR", NULL, "CLASS D" },
474
475 { "I Sense", NULL, "I Gen" },
476 { "V Sense", NULL, "V Gen" },
477 { "I Sense", NULL, "PDE 24" },
478 { "V Sense", NULL, "PDE 24" },
479 { "DP2TX", NULL, "I Sense" },
480 { "DP2TX", NULL, "V Sense" },
481};
482
483static int rt1316_set_sdw_stream(struct snd_soc_dai *dai, void *sdw_stream,
484 int direction)
485{
486 struct sdw_stream_data *stream;
487
488 if (!sdw_stream)
489 return 0;
490
491 stream = kzalloc(sizeof(*stream), GFP_KERNEL);
492 if (!stream)
493 return -ENOMEM;
494
495 stream->sdw_stream = sdw_stream;
496
497
498 if (direction == SNDRV_PCM_STREAM_PLAYBACK)
499 dai->playback_dma_data = stream;
500 else
501 dai->capture_dma_data = stream;
502
503 return 0;
504}
505
506static void rt1316_sdw_shutdown(struct snd_pcm_substream *substream,
507 struct snd_soc_dai *dai)
508{
509 struct sdw_stream_data *stream;
510
511 stream = snd_soc_dai_get_dma_data(dai, substream);
512 snd_soc_dai_set_dma_data(dai, substream, NULL);
513 kfree(stream);
514}
515
516static int rt1316_sdw_hw_params(struct snd_pcm_substream *substream,
517 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
518{
519 struct snd_soc_component *component = dai->component;
520 struct rt1316_sdw_priv *rt1316 =
521 snd_soc_component_get_drvdata(component);
522 struct sdw_stream_config stream_config;
523 struct sdw_port_config port_config;
524 enum sdw_data_direction direction;
525 struct sdw_stream_data *stream;
526 int retval, port, num_channels, ch_mask;
527
528 dev_dbg(dai->dev, "%s %s", __func__, dai->name);
529 stream = snd_soc_dai_get_dma_data(dai, substream);
530
531 if (!stream)
532 return -EINVAL;
533
534 if (!rt1316->sdw_slave)
535 return -EINVAL;
536
537
538
539 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
540 direction = SDW_DATA_DIR_RX;
541 port = 1;
542 } else {
543 direction = SDW_DATA_DIR_TX;
544 port = 2;
545 }
546
547 num_channels = params_channels(params);
548 ch_mask = (1 << num_channels) - 1;
549
550 stream_config.frame_rate = params_rate(params);
551 stream_config.ch_count = num_channels;
552 stream_config.bps = snd_pcm_format_width(params_format(params));
553 stream_config.direction = direction;
554
555 port_config.ch_mask = ch_mask;
556 port_config.num = port;
557
558 retval = sdw_stream_add_slave(rt1316->sdw_slave, &stream_config,
559 &port_config, 1, stream->sdw_stream);
560 if (retval) {
561 dev_err(dai->dev, "Unable to configure port\n");
562 return retval;
563 }
564
565 return 0;
566}
567
568static int rt1316_sdw_pcm_hw_free(struct snd_pcm_substream *substream,
569 struct snd_soc_dai *dai)
570{
571 struct snd_soc_component *component = dai->component;
572 struct rt1316_sdw_priv *rt1316 =
573 snd_soc_component_get_drvdata(component);
574 struct sdw_stream_data *stream =
575 snd_soc_dai_get_dma_data(dai, substream);
576
577 if (!rt1316->sdw_slave)
578 return -EINVAL;
579
580 sdw_stream_remove_slave(rt1316->sdw_slave, stream->sdw_stream);
581 return 0;
582}
583
584
585
586
587
588static struct sdw_slave_ops rt1316_slave_ops = {
589 .read_prop = rt1316_read_prop,
590 .update_status = rt1316_update_status,
591};
592
593static const struct snd_soc_component_driver soc_component_sdw_rt1316 = {
594 .controls = rt1316_snd_controls,
595 .num_controls = ARRAY_SIZE(rt1316_snd_controls),
596 .dapm_widgets = rt1316_dapm_widgets,
597 .num_dapm_widgets = ARRAY_SIZE(rt1316_dapm_widgets),
598 .dapm_routes = rt1316_dapm_routes,
599 .num_dapm_routes = ARRAY_SIZE(rt1316_dapm_routes),
600 .endianness = 1,
601};
602
603static const struct snd_soc_dai_ops rt1316_aif_dai_ops = {
604 .hw_params = rt1316_sdw_hw_params,
605 .hw_free = rt1316_sdw_pcm_hw_free,
606 .set_stream = rt1316_set_sdw_stream,
607 .shutdown = rt1316_sdw_shutdown,
608};
609
610#define RT1316_STEREO_RATES SNDRV_PCM_RATE_48000
611#define RT1316_FORMATS (SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S16_LE | \
612 SNDRV_PCM_FMTBIT_S24_LE)
613
614static struct snd_soc_dai_driver rt1316_sdw_dai[] = {
615 {
616 .name = "rt1316-aif",
617 .playback = {
618 .stream_name = "DP1 Playback",
619 .channels_min = 1,
620 .channels_max = 2,
621 .rates = RT1316_STEREO_RATES,
622 .formats = RT1316_FORMATS,
623 },
624 .capture = {
625 .stream_name = "DP2 Capture",
626 .channels_min = 1,
627 .channels_max = 2,
628 .rates = RT1316_STEREO_RATES,
629 .formats = RT1316_FORMATS,
630 },
631 .ops = &rt1316_aif_dai_ops,
632 },
633};
634
635static int rt1316_sdw_init(struct device *dev, struct regmap *regmap,
636 struct sdw_slave *slave)
637{
638 struct rt1316_sdw_priv *rt1316;
639 int ret;
640
641 rt1316 = devm_kzalloc(dev, sizeof(*rt1316), GFP_KERNEL);
642 if (!rt1316)
643 return -ENOMEM;
644
645 dev_set_drvdata(dev, rt1316);
646 rt1316->sdw_slave = slave;
647 rt1316->regmap = regmap;
648
649
650
651
652
653 rt1316->hw_init = false;
654 rt1316->first_hw_init = false;
655
656 ret = devm_snd_soc_register_component(dev,
657 &soc_component_sdw_rt1316,
658 rt1316_sdw_dai,
659 ARRAY_SIZE(rt1316_sdw_dai));
660
661 dev_dbg(&slave->dev, "%s\n", __func__);
662
663 return ret;
664}
665
666static int rt1316_sdw_probe(struct sdw_slave *slave,
667 const struct sdw_device_id *id)
668{
669 struct regmap *regmap;
670
671
672 regmap = devm_regmap_init_sdw(slave, &rt1316_sdw_regmap);
673 if (IS_ERR(regmap))
674 return PTR_ERR(regmap);
675
676 return rt1316_sdw_init(&slave->dev, regmap, slave);
677}
678
679static int rt1316_sdw_remove(struct sdw_slave *slave)
680{
681 struct rt1316_sdw_priv *rt1316 = dev_get_drvdata(&slave->dev);
682
683 if (rt1316->first_hw_init)
684 pm_runtime_disable(&slave->dev);
685
686 return 0;
687}
688
689static const struct sdw_device_id rt1316_id[] = {
690 SDW_SLAVE_ENTRY_EXT(0x025d, 0x1316, 0x3, 0x1, 0),
691 {},
692};
693MODULE_DEVICE_TABLE(sdw, rt1316_id);
694
695static int __maybe_unused rt1316_dev_suspend(struct device *dev)
696{
697 struct rt1316_sdw_priv *rt1316 = dev_get_drvdata(dev);
698
699 if (!rt1316->hw_init)
700 return 0;
701
702 regcache_cache_only(rt1316->regmap, true);
703
704 return 0;
705}
706
707#define RT1316_PROBE_TIMEOUT 5000
708
709static int __maybe_unused rt1316_dev_resume(struct device *dev)
710{
711 struct sdw_slave *slave = dev_to_sdw_dev(dev);
712 struct rt1316_sdw_priv *rt1316 = dev_get_drvdata(dev);
713 unsigned long time;
714
715 if (!rt1316->first_hw_init)
716 return 0;
717
718 if (!slave->unattach_request)
719 goto regmap_sync;
720
721 time = wait_for_completion_timeout(&slave->initialization_complete,
722 msecs_to_jiffies(RT1316_PROBE_TIMEOUT));
723 if (!time) {
724 dev_err(&slave->dev, "Initialization not complete, timed out\n");
725 return -ETIMEDOUT;
726 }
727
728regmap_sync:
729 slave->unattach_request = 0;
730 regcache_cache_only(rt1316->regmap, false);
731 regcache_sync(rt1316->regmap);
732
733 return 0;
734}
735
736static const struct dev_pm_ops rt1316_pm = {
737 SET_SYSTEM_SLEEP_PM_OPS(rt1316_dev_suspend, rt1316_dev_resume)
738 SET_RUNTIME_PM_OPS(rt1316_dev_suspend, rt1316_dev_resume, NULL)
739};
740
741static struct sdw_driver rt1316_sdw_driver = {
742 .driver = {
743 .name = "rt1316-sdca",
744 .owner = THIS_MODULE,
745 .pm = &rt1316_pm,
746 },
747 .probe = rt1316_sdw_probe,
748 .remove = rt1316_sdw_remove,
749 .ops = &rt1316_slave_ops,
750 .id_table = rt1316_id,
751};
752module_sdw_driver(rt1316_sdw_driver);
753
754MODULE_DESCRIPTION("ASoC RT1316 driver SDCA SDW");
755MODULE_AUTHOR("Shuming Fan <shumingf@realtek.com>");
756MODULE_LICENSE("GPL");
757
