linux/sound/soc/sof/intel/hda.h
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   1/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
   2/*
   3 * This file is provided under a dual BSD/GPLv2 license.  When using or
   4 * redistributing this file, you may do so under either license.
   5 *
   6 * Copyright(c) 2017 Intel Corporation. All rights reserved.
   7 *
   8 * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
   9 */
  10
  11#ifndef __SOF_INTEL_HDA_H
  12#define __SOF_INTEL_HDA_H
  13
  14#include <linux/soundwire/sdw.h>
  15#include <linux/soundwire/sdw_intel.h>
  16#include <sound/compress_driver.h>
  17#include <sound/hda_codec.h>
  18#include <sound/hdaudio_ext.h>
  19#include "../sof-client-probes.h"
  20#include "../sof-audio.h"
  21#include "shim.h"
  22
  23/* PCI registers */
  24#define PCI_TCSEL                       0x44
  25#define PCI_PGCTL                       PCI_TCSEL
  26#define PCI_CGCTL                       0x48
  27
  28/* PCI_PGCTL bits */
  29#define PCI_PGCTL_ADSPPGD               BIT(2)
  30#define PCI_PGCTL_LSRMD_MASK            BIT(4)
  31
  32/* PCI_CGCTL bits */
  33#define PCI_CGCTL_MISCBDCGE_MASK        BIT(6)
  34#define PCI_CGCTL_ADSPDCGE              BIT(1)
  35
  36/* Legacy HDA registers and bits used - widths are variable */
  37#define SOF_HDA_GCAP                    0x0
  38#define SOF_HDA_GCTL                    0x8
  39/* accept unsol. response enable */
  40#define SOF_HDA_GCTL_UNSOL              BIT(8)
  41#define SOF_HDA_LLCH                    0x14
  42#define SOF_HDA_INTCTL                  0x20
  43#define SOF_HDA_INTSTS                  0x24
  44#define SOF_HDA_WAKESTS                 0x0E
  45#define SOF_HDA_WAKESTS_INT_MASK        ((1 << 8) - 1)
  46#define SOF_HDA_RIRBSTS                 0x5d
  47
  48/* SOF_HDA_GCTL register bist */
  49#define SOF_HDA_GCTL_RESET              BIT(0)
  50
  51/* SOF_HDA_INCTL regs */
  52#define SOF_HDA_INT_GLOBAL_EN           BIT(31)
  53#define SOF_HDA_INT_CTRL_EN             BIT(30)
  54#define SOF_HDA_INT_ALL_STREAM          0xff
  55
  56/* SOF_HDA_INTSTS regs */
  57#define SOF_HDA_INTSTS_GIS              BIT(31)
  58
  59#define SOF_HDA_MAX_CAPS                10
  60#define SOF_HDA_CAP_ID_OFF              16
  61#define SOF_HDA_CAP_ID_MASK             GENMASK(SOF_HDA_CAP_ID_OFF + 11,\
  62                                                SOF_HDA_CAP_ID_OFF)
  63#define SOF_HDA_CAP_NEXT_MASK           0xFFFF
  64
  65#define SOF_HDA_GTS_CAP_ID                      0x1
  66#define SOF_HDA_ML_CAP_ID                       0x2
  67
  68#define SOF_HDA_PP_CAP_ID               0x3
  69#define SOF_HDA_REG_PP_PPCH             0x10
  70#define SOF_HDA_REG_PP_PPCTL            0x04
  71#define SOF_HDA_REG_PP_PPSTS            0x08
  72#define SOF_HDA_PPCTL_PIE               BIT(31)
  73#define SOF_HDA_PPCTL_GPROCEN           BIT(30)
  74
  75/*Vendor Specific Registers*/
  76#define SOF_HDA_VS_D0I3C                0x104A
  77
  78/* D0I3C Register fields */
  79#define SOF_HDA_VS_D0I3C_CIP            BIT(0) /* Command-In-Progress */
  80#define SOF_HDA_VS_D0I3C_I3             BIT(2) /* D0i3 enable bit */
  81
  82/* DPIB entry size: 8 Bytes = 2 DWords */
  83#define SOF_HDA_DPIB_ENTRY_SIZE 0x8
  84
  85#define SOF_HDA_SPIB_CAP_ID             0x4
  86#define SOF_HDA_DRSM_CAP_ID             0x5
  87
  88#define SOF_HDA_SPIB_BASE               0x08
  89#define SOF_HDA_SPIB_INTERVAL           0x08
  90#define SOF_HDA_SPIB_SPIB               0x00
  91#define SOF_HDA_SPIB_MAXFIFO            0x04
  92
  93#define SOF_HDA_PPHC_BASE               0x10
  94#define SOF_HDA_PPHC_INTERVAL           0x10
  95
  96#define SOF_HDA_PPLC_BASE               0x10
  97#define SOF_HDA_PPLC_MULTI              0x10
  98#define SOF_HDA_PPLC_INTERVAL           0x10
  99
 100#define SOF_HDA_DRSM_BASE               0x08
 101#define SOF_HDA_DRSM_INTERVAL           0x08
 102
 103/* Descriptor error interrupt */
 104#define SOF_HDA_CL_DMA_SD_INT_DESC_ERR          0x10
 105
 106/* FIFO error interrupt */
 107#define SOF_HDA_CL_DMA_SD_INT_FIFO_ERR          0x08
 108
 109/* Buffer completion interrupt */
 110#define SOF_HDA_CL_DMA_SD_INT_COMPLETE          0x04
 111
 112#define SOF_HDA_CL_DMA_SD_INT_MASK \
 113        (SOF_HDA_CL_DMA_SD_INT_DESC_ERR | \
 114        SOF_HDA_CL_DMA_SD_INT_FIFO_ERR | \
 115        SOF_HDA_CL_DMA_SD_INT_COMPLETE)
 116#define SOF_HDA_SD_CTL_DMA_START                0x02 /* Stream DMA start bit */
 117
 118/* Intel HD Audio Code Loader DMA Registers */
 119#define SOF_HDA_ADSP_LOADER_BASE                0x80
 120#define SOF_HDA_ADSP_DPLBASE                    0x70
 121#define SOF_HDA_ADSP_DPUBASE                    0x74
 122#define SOF_HDA_ADSP_DPLBASE_ENABLE             0x01
 123
 124/* Stream Registers */
 125#define SOF_HDA_ADSP_REG_CL_SD_CTL              0x00
 126#define SOF_HDA_ADSP_REG_CL_SD_STS              0x03
 127#define SOF_HDA_ADSP_REG_CL_SD_LPIB             0x04
 128#define SOF_HDA_ADSP_REG_CL_SD_CBL              0x08
 129#define SOF_HDA_ADSP_REG_CL_SD_LVI              0x0C
 130#define SOF_HDA_ADSP_REG_CL_SD_FIFOW            0x0E
 131#define SOF_HDA_ADSP_REG_CL_SD_FIFOSIZE         0x10
 132#define SOF_HDA_ADSP_REG_CL_SD_FORMAT           0x12
 133#define SOF_HDA_ADSP_REG_CL_SD_FIFOL            0x14
 134#define SOF_HDA_ADSP_REG_CL_SD_BDLPL            0x18
 135#define SOF_HDA_ADSP_REG_CL_SD_BDLPU            0x1C
 136#define SOF_HDA_ADSP_SD_ENTRY_SIZE              0x20
 137
 138/* CL: Software Position Based FIFO Capability Registers */
 139#define SOF_DSP_REG_CL_SPBFIFO \
 140        (SOF_HDA_ADSP_LOADER_BASE + 0x20)
 141#define SOF_HDA_ADSP_REG_CL_SPBFIFO_SPBFCH      0x0
 142#define SOF_HDA_ADSP_REG_CL_SPBFIFO_SPBFCCTL    0x4
 143#define SOF_HDA_ADSP_REG_CL_SPBFIFO_SPIB        0x8
 144#define SOF_HDA_ADSP_REG_CL_SPBFIFO_MAXFIFOS    0xc
 145
 146/* Stream Number */
 147#define SOF_HDA_CL_SD_CTL_STREAM_TAG_SHIFT      20
 148#define SOF_HDA_CL_SD_CTL_STREAM_TAG_MASK \
 149        GENMASK(SOF_HDA_CL_SD_CTL_STREAM_TAG_SHIFT + 3,\
 150                SOF_HDA_CL_SD_CTL_STREAM_TAG_SHIFT)
 151
 152#define HDA_DSP_HDA_BAR                         0
 153#define HDA_DSP_PP_BAR                          1
 154#define HDA_DSP_SPIB_BAR                        2
 155#define HDA_DSP_DRSM_BAR                        3
 156#define HDA_DSP_BAR                             4
 157
 158#define SRAM_WINDOW_OFFSET(x)                   (0x80000 + (x) * 0x20000)
 159
 160#define HDA_DSP_MBOX_OFFSET                     SRAM_WINDOW_OFFSET(0)
 161
 162#define HDA_DSP_PANIC_OFFSET(x) \
 163        (((x) & 0xFFFFFF) + HDA_DSP_MBOX_OFFSET)
 164
 165/* SRAM window 0 FW "registers" */
 166#define HDA_DSP_SRAM_REG_ROM_STATUS             (HDA_DSP_MBOX_OFFSET + 0x0)
 167#define HDA_DSP_SRAM_REG_ROM_ERROR              (HDA_DSP_MBOX_OFFSET + 0x4)
 168/* FW and ROM share offset 4 */
 169#define HDA_DSP_SRAM_REG_FW_STATUS              (HDA_DSP_MBOX_OFFSET + 0x4)
 170#define HDA_DSP_SRAM_REG_FW_TRACEP              (HDA_DSP_MBOX_OFFSET + 0x8)
 171#define HDA_DSP_SRAM_REG_FW_END                 (HDA_DSP_MBOX_OFFSET + 0xc)
 172
 173#define HDA_DSP_MBOX_UPLINK_OFFSET              0x81000
 174
 175#define HDA_DSP_STREAM_RESET_TIMEOUT            300
 176/*
 177 * Timeout in us, for setting the stream RUN bit, during
 178 * start/stop the stream. The timeout expires if new RUN bit
 179 * value cannot be read back within the specified time.
 180 */
 181#define HDA_DSP_STREAM_RUN_TIMEOUT              300
 182
 183#define HDA_DSP_SPIB_ENABLE                     1
 184#define HDA_DSP_SPIB_DISABLE                    0
 185
 186#define SOF_HDA_MAX_BUFFER_SIZE                 (32 * PAGE_SIZE)
 187
 188#define HDA_DSP_STACK_DUMP_SIZE                 32
 189
 190/* ROM  status/error values */
 191#define HDA_DSP_ROM_STS_MASK                    GENMASK(23, 0)
 192#define HDA_DSP_ROM_INIT                        0x1
 193#define HDA_DSP_ROM_FW_MANIFEST_LOADED          0x3
 194#define HDA_DSP_ROM_FW_FW_LOADED                0x4
 195#define HDA_DSP_ROM_FW_ENTERED                  0x5
 196#define HDA_DSP_ROM_RFW_START                   0xf
 197#define HDA_DSP_ROM_CSE_ERROR                   40
 198#define HDA_DSP_ROM_CSE_WRONG_RESPONSE          41
 199#define HDA_DSP_ROM_IMR_TO_SMALL                42
 200#define HDA_DSP_ROM_BASE_FW_NOT_FOUND           43
 201#define HDA_DSP_ROM_CSE_VALIDATION_FAILED       44
 202#define HDA_DSP_ROM_IPC_FATAL_ERROR             45
 203#define HDA_DSP_ROM_L2_CACHE_ERROR              46
 204#define HDA_DSP_ROM_LOAD_OFFSET_TO_SMALL        47
 205#define HDA_DSP_ROM_API_PTR_INVALID             50
 206#define HDA_DSP_ROM_BASEFW_INCOMPAT             51
 207#define HDA_DSP_ROM_UNHANDLED_INTERRUPT         0xBEE00000
 208#define HDA_DSP_ROM_MEMORY_HOLE_ECC             0xECC00000
 209#define HDA_DSP_ROM_KERNEL_EXCEPTION            0xCAFE0000
 210#define HDA_DSP_ROM_USER_EXCEPTION              0xBEEF0000
 211#define HDA_DSP_ROM_UNEXPECTED_RESET            0xDECAF000
 212#define HDA_DSP_ROM_NULL_FW_ENTRY               0x4c4c4e55
 213
 214#define HDA_DSP_ROM_IPC_CONTROL                 0x01000000
 215#define HDA_DSP_ROM_IPC_PURGE_FW                0x00004000
 216
 217/* various timeout values */
 218#define HDA_DSP_PU_TIMEOUT              50
 219#define HDA_DSP_PD_TIMEOUT              50
 220#define HDA_DSP_RESET_TIMEOUT_US        50000
 221#define HDA_DSP_BASEFW_TIMEOUT_US       3000000
 222#define HDA_DSP_INIT_TIMEOUT_US 500000
 223#define HDA_DSP_CTRL_RESET_TIMEOUT              100
 224#define HDA_DSP_WAIT_TIMEOUT            500     /* 500 msec */
 225#define HDA_DSP_REG_POLL_INTERVAL_US            500     /* 0.5 msec */
 226#define HDA_DSP_REG_POLL_RETRY_COUNT            50
 227
 228#define HDA_DSP_ADSPIC_IPC                      BIT(0)
 229#define HDA_DSP_ADSPIS_IPC                      BIT(0)
 230
 231/* Intel HD Audio General DSP Registers */
 232#define HDA_DSP_GEN_BASE                0x0
 233#define HDA_DSP_REG_ADSPCS              (HDA_DSP_GEN_BASE + 0x04)
 234#define HDA_DSP_REG_ADSPIC              (HDA_DSP_GEN_BASE + 0x08)
 235#define HDA_DSP_REG_ADSPIS              (HDA_DSP_GEN_BASE + 0x0C)
 236#define HDA_DSP_REG_ADSPIC2             (HDA_DSP_GEN_BASE + 0x10)
 237#define HDA_DSP_REG_ADSPIS2             (HDA_DSP_GEN_BASE + 0x14)
 238
 239#define HDA_DSP_REG_ADSPIS2_SNDW        BIT(5)
 240
 241/* Intel HD Audio Inter-Processor Communication Registers */
 242#define HDA_DSP_IPC_BASE                0x40
 243#define HDA_DSP_REG_HIPCT               (HDA_DSP_IPC_BASE + 0x00)
 244#define HDA_DSP_REG_HIPCTE              (HDA_DSP_IPC_BASE + 0x04)
 245#define HDA_DSP_REG_HIPCI               (HDA_DSP_IPC_BASE + 0x08)
 246#define HDA_DSP_REG_HIPCIE              (HDA_DSP_IPC_BASE + 0x0C)
 247#define HDA_DSP_REG_HIPCCTL             (HDA_DSP_IPC_BASE + 0x10)
 248
 249/* Intel Vendor Specific Registers */
 250#define HDA_VS_INTEL_EM2                0x1030
 251#define HDA_VS_INTEL_EM2_L1SEN          BIT(13)
 252#define HDA_VS_INTEL_LTRP_GB_MASK       0x3F
 253
 254/*  HIPCI */
 255#define HDA_DSP_REG_HIPCI_BUSY          BIT(31)
 256#define HDA_DSP_REG_HIPCI_MSG_MASK      0x7FFFFFFF
 257
 258/* HIPCIE */
 259#define HDA_DSP_REG_HIPCIE_DONE BIT(30)
 260#define HDA_DSP_REG_HIPCIE_MSG_MASK     0x3FFFFFFF
 261
 262/* HIPCCTL */
 263#define HDA_DSP_REG_HIPCCTL_DONE        BIT(1)
 264#define HDA_DSP_REG_HIPCCTL_BUSY        BIT(0)
 265
 266/* HIPCT */
 267#define HDA_DSP_REG_HIPCT_BUSY          BIT(31)
 268#define HDA_DSP_REG_HIPCT_MSG_MASK      0x7FFFFFFF
 269
 270/* HIPCTE */
 271#define HDA_DSP_REG_HIPCTE_MSG_MASK     0x3FFFFFFF
 272
 273#define HDA_DSP_ADSPIC_CL_DMA           BIT(1)
 274#define HDA_DSP_ADSPIS_CL_DMA           BIT(1)
 275
 276/* Delay before scheduling D0i3 entry */
 277#define BXT_D0I3_DELAY 5000
 278
 279#define FW_CL_STREAM_NUMBER             0x1
 280#define HDA_FW_BOOT_ATTEMPTS            3
 281
 282/* ADSPCS - Audio DSP Control & Status */
 283
 284/*
 285 * Core Reset - asserted high
 286 * CRST Mask for a given core mask pattern, cm
 287 */
 288#define HDA_DSP_ADSPCS_CRST_SHIFT       0
 289#define HDA_DSP_ADSPCS_CRST_MASK(cm)    ((cm) << HDA_DSP_ADSPCS_CRST_SHIFT)
 290
 291/*
 292 * Core run/stall - when set to '1' core is stalled
 293 * CSTALL Mask for a given core mask pattern, cm
 294 */
 295#define HDA_DSP_ADSPCS_CSTALL_SHIFT     8
 296#define HDA_DSP_ADSPCS_CSTALL_MASK(cm)  ((cm) << HDA_DSP_ADSPCS_CSTALL_SHIFT)
 297
 298/*
 299 * Set Power Active - when set to '1' turn cores on
 300 * SPA Mask for a given core mask pattern, cm
 301 */
 302#define HDA_DSP_ADSPCS_SPA_SHIFT        16
 303#define HDA_DSP_ADSPCS_SPA_MASK(cm)     ((cm) << HDA_DSP_ADSPCS_SPA_SHIFT)
 304
 305/*
 306 * Current Power Active - power status of cores, set by hardware
 307 * CPA Mask for a given core mask pattern, cm
 308 */
 309#define HDA_DSP_ADSPCS_CPA_SHIFT        24
 310#define HDA_DSP_ADSPCS_CPA_MASK(cm)     ((cm) << HDA_DSP_ADSPCS_CPA_SHIFT)
 311
 312/*
 313 * Mask for a given number of cores
 314 * nc = number of supported cores
 315 */
 316#define SOF_DSP_CORES_MASK(nc)  GENMASK(((nc) - 1), 0)
 317
 318/* Intel HD Audio Inter-Processor Communication Registers for Cannonlake*/
 319#define CNL_DSP_IPC_BASE                0xc0
 320#define CNL_DSP_REG_HIPCTDR             (CNL_DSP_IPC_BASE + 0x00)
 321#define CNL_DSP_REG_HIPCTDA             (CNL_DSP_IPC_BASE + 0x04)
 322#define CNL_DSP_REG_HIPCTDD             (CNL_DSP_IPC_BASE + 0x08)
 323#define CNL_DSP_REG_HIPCIDR             (CNL_DSP_IPC_BASE + 0x10)
 324#define CNL_DSP_REG_HIPCIDA             (CNL_DSP_IPC_BASE + 0x14)
 325#define CNL_DSP_REG_HIPCIDD             (CNL_DSP_IPC_BASE + 0x18)
 326#define CNL_DSP_REG_HIPCCTL             (CNL_DSP_IPC_BASE + 0x28)
 327
 328/*  HIPCI */
 329#define CNL_DSP_REG_HIPCIDR_BUSY                BIT(31)
 330#define CNL_DSP_REG_HIPCIDR_MSG_MASK    0x7FFFFFFF
 331
 332/* HIPCIE */
 333#define CNL_DSP_REG_HIPCIDA_DONE        BIT(31)
 334#define CNL_DSP_REG_HIPCIDA_MSG_MASK    0x7FFFFFFF
 335
 336/* HIPCCTL */
 337#define CNL_DSP_REG_HIPCCTL_DONE        BIT(1)
 338#define CNL_DSP_REG_HIPCCTL_BUSY        BIT(0)
 339
 340/* HIPCT */
 341#define CNL_DSP_REG_HIPCTDR_BUSY                BIT(31)
 342#define CNL_DSP_REG_HIPCTDR_MSG_MASK    0x7FFFFFFF
 343
 344/* HIPCTDA */
 345#define CNL_DSP_REG_HIPCTDA_DONE        BIT(31)
 346#define CNL_DSP_REG_HIPCTDA_MSG_MASK    0x7FFFFFFF
 347
 348/* HIPCTDD */
 349#define CNL_DSP_REG_HIPCTDD_MSG_MASK    0x7FFFFFFF
 350
 351/* BDL */
 352#define HDA_DSP_BDL_SIZE                        4096
 353#define HDA_DSP_MAX_BDL_ENTRIES                 \
 354        (HDA_DSP_BDL_SIZE / sizeof(struct sof_intel_dsp_bdl))
 355
 356/* Number of DAIs */
 357#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
 358#define SOF_SKL_NUM_DAIS                15
 359#else
 360#define SOF_SKL_NUM_DAIS                8
 361#endif
 362
 363/* Intel HD Audio SRAM Window 0*/
 364#define HDA_ADSP_SRAM0_BASE_SKL         0x8000
 365
 366/* Firmware status window */
 367#define HDA_ADSP_FW_STATUS_SKL          HDA_ADSP_SRAM0_BASE_SKL
 368#define HDA_ADSP_ERROR_CODE_SKL         (HDA_ADSP_FW_STATUS_SKL + 0x4)
 369
 370/* Host Device Memory Space */
 371#define APL_SSP_BASE_OFFSET     0x2000
 372#define CNL_SSP_BASE_OFFSET     0x10000
 373
 374/* Host Device Memory Size of a Single SSP */
 375#define SSP_DEV_MEM_SIZE        0x1000
 376
 377/* SSP Count of the Platform */
 378#define APL_SSP_COUNT           6
 379#define CNL_SSP_COUNT           3
 380#define ICL_SSP_COUNT           6
 381
 382/* SSP Registers */
 383#define SSP_SSC1_OFFSET         0x4
 384#define SSP_SET_SCLK_CONSUMER   BIT(25)
 385#define SSP_SET_SFRM_CONSUMER   BIT(24)
 386#define SSP_SET_CBP_CFP         (SSP_SET_SCLK_CONSUMER | SSP_SET_SFRM_CONSUMER)
 387
 388#define HDA_IDISP_ADDR          2
 389#define HDA_IDISP_CODEC(x) ((x) & BIT(HDA_IDISP_ADDR))
 390
 391struct sof_intel_dsp_bdl {
 392        __le32 addr_l;
 393        __le32 addr_h;
 394        __le32 size;
 395        __le32 ioc;
 396} __attribute((packed));
 397
 398#define SOF_HDA_PLAYBACK_STREAMS        16
 399#define SOF_HDA_CAPTURE_STREAMS         16
 400#define SOF_HDA_PLAYBACK                0
 401#define SOF_HDA_CAPTURE                 1
 402
 403/* stream flags */
 404#define SOF_HDA_STREAM_DMI_L1_COMPATIBLE        1
 405
 406/*
 407 * Time in ms for opportunistic D0I3 entry delay.
 408 * This has been deliberately chosen to be long to avoid race conditions.
 409 * Could be optimized in future.
 410 */
 411#define SOF_HDA_D0I3_WORK_DELAY_MS      5000
 412
 413/* HDA DSP D0 substate */
 414enum sof_hda_D0_substate {
 415        SOF_HDA_DSP_PM_D0I0,    /* default D0 substate */
 416        SOF_HDA_DSP_PM_D0I3,    /* low power D0 substate */
 417};
 418
 419/* represents DSP HDA controller frontend - i.e. host facing control */
 420struct sof_intel_hda_dev {
 421        bool imrboot_supported;
 422
 423        int boot_iteration;
 424
 425        struct hda_bus hbus;
 426
 427        /* hw config */
 428        const struct sof_intel_dsp_desc *desc;
 429
 430        /* trace */
 431        struct hdac_ext_stream *dtrace_stream;
 432
 433        /* if position update IPC needed */
 434        u32 no_ipc_position;
 435
 436        /* the maximum number of streams (playback + capture) supported */
 437        u32 stream_max;
 438
 439        /* PM related */
 440        bool l1_support_changed;/* during suspend, is L1SEN changed or not */
 441
 442        /* DMIC device */
 443        struct platform_device *dmic_dev;
 444
 445        /* delayed work to enter D0I3 opportunistically */
 446        struct delayed_work d0i3_work;
 447
 448        /* ACPI information stored between scan and probe steps */
 449        struct sdw_intel_acpi_info info;
 450
 451        /* sdw context allocated by SoundWire driver */
 452        struct sdw_intel_ctx *sdw;
 453
 454        /* FW clock config, 0:HPRO, 1:LPRO */
 455        bool clk_config_lpro;
 456
 457        /* Intel NHLT information */
 458        struct nhlt_acpi_table *nhlt;
 459};
 460
 461static inline struct hdac_bus *sof_to_bus(struct snd_sof_dev *s)
 462{
 463        struct sof_intel_hda_dev *hda = s->pdata->hw_pdata;
 464
 465        return &hda->hbus.core;
 466}
 467
 468static inline struct hda_bus *sof_to_hbus(struct snd_sof_dev *s)
 469{
 470        struct sof_intel_hda_dev *hda = s->pdata->hw_pdata;
 471
 472        return &hda->hbus;
 473}
 474
 475struct sof_intel_hda_stream {
 476        struct snd_sof_dev *sdev;
 477        struct hdac_ext_stream hext_stream;
 478        struct sof_intel_stream sof_intel_stream;
 479        int host_reserved; /* reserve host DMA channel */
 480        u32 flags;
 481};
 482
 483#define hstream_to_sof_hda_stream(hstream) \
 484        container_of(hstream, struct sof_intel_hda_stream, hext_stream)
 485
 486#define bus_to_sof_hda(bus) \
 487        container_of(bus, struct sof_intel_hda_dev, hbus.core)
 488
 489#define SOF_STREAM_SD_OFFSET(s) \
 490        (SOF_HDA_ADSP_SD_ENTRY_SIZE * ((s)->index) \
 491         + SOF_HDA_ADSP_LOADER_BASE)
 492
 493#define SOF_STREAM_SD_OFFSET_CRST 0x1
 494
 495/*
 496 * DSP Core services.
 497 */
 498int hda_dsp_probe(struct snd_sof_dev *sdev);
 499int hda_dsp_remove(struct snd_sof_dev *sdev);
 500int hda_dsp_core_power_up(struct snd_sof_dev *sdev, unsigned int core_mask);
 501int hda_dsp_core_run(struct snd_sof_dev *sdev, unsigned int core_mask);
 502int hda_dsp_enable_core(struct snd_sof_dev *sdev, unsigned int core_mask);
 503int hda_dsp_core_reset_power_down(struct snd_sof_dev *sdev,
 504                                  unsigned int core_mask);
 505int hda_dsp_core_get(struct snd_sof_dev *sdev, int core);
 506void hda_dsp_ipc_int_enable(struct snd_sof_dev *sdev);
 507void hda_dsp_ipc_int_disable(struct snd_sof_dev *sdev);
 508
 509int hda_dsp_set_power_state(struct snd_sof_dev *sdev,
 510                            const struct sof_dsp_power_state *target_state);
 511
 512int hda_dsp_suspend(struct snd_sof_dev *sdev, u32 target_state);
 513int hda_dsp_resume(struct snd_sof_dev *sdev);
 514int hda_dsp_runtime_suspend(struct snd_sof_dev *sdev);
 515int hda_dsp_runtime_resume(struct snd_sof_dev *sdev);
 516int hda_dsp_runtime_idle(struct snd_sof_dev *sdev);
 517int hda_dsp_shutdown(struct snd_sof_dev *sdev);
 518int hda_dsp_set_hw_params_upon_resume(struct snd_sof_dev *sdev);
 519void hda_dsp_dump(struct snd_sof_dev *sdev, u32 flags);
 520void hda_ipc_dump(struct snd_sof_dev *sdev);
 521void hda_ipc_irq_dump(struct snd_sof_dev *sdev);
 522void hda_dsp_d0i3_work(struct work_struct *work);
 523
 524/*
 525 * DSP PCM Operations.
 526 */
 527u32 hda_dsp_get_mult_div(struct snd_sof_dev *sdev, int rate);
 528u32 hda_dsp_get_bits(struct snd_sof_dev *sdev, int sample_bits);
 529int hda_dsp_pcm_open(struct snd_sof_dev *sdev,
 530                     struct snd_pcm_substream *substream);
 531int hda_dsp_pcm_close(struct snd_sof_dev *sdev,
 532                      struct snd_pcm_substream *substream);
 533int hda_dsp_pcm_hw_params(struct snd_sof_dev *sdev,
 534                          struct snd_pcm_substream *substream,
 535                          struct snd_pcm_hw_params *params,
 536                          struct snd_sof_platform_stream_params *platform_params);
 537int hda_dsp_stream_hw_free(struct snd_sof_dev *sdev,
 538                           struct snd_pcm_substream *substream);
 539int hda_dsp_pcm_trigger(struct snd_sof_dev *sdev,
 540                        struct snd_pcm_substream *substream, int cmd);
 541snd_pcm_uframes_t hda_dsp_pcm_pointer(struct snd_sof_dev *sdev,
 542                                      struct snd_pcm_substream *substream);
 543int hda_dsp_pcm_ack(struct snd_sof_dev *sdev, struct snd_pcm_substream *substream);
 544
 545/*
 546 * DSP Stream Operations.
 547 */
 548
 549int hda_dsp_stream_init(struct snd_sof_dev *sdev);
 550void hda_dsp_stream_free(struct snd_sof_dev *sdev);
 551int hda_dsp_stream_hw_params(struct snd_sof_dev *sdev,
 552                             struct hdac_ext_stream *hext_stream,
 553                             struct snd_dma_buffer *dmab,
 554                             struct snd_pcm_hw_params *params);
 555int hda_dsp_iccmax_stream_hw_params(struct snd_sof_dev *sdev,
 556                                    struct hdac_ext_stream *hext_stream,
 557                                    struct snd_dma_buffer *dmab,
 558                                    struct snd_pcm_hw_params *params);
 559int hda_dsp_stream_trigger(struct snd_sof_dev *sdev,
 560                           struct hdac_ext_stream *hext_stream, int cmd);
 561irqreturn_t hda_dsp_stream_threaded_handler(int irq, void *context);
 562int hda_dsp_stream_setup_bdl(struct snd_sof_dev *sdev,
 563                             struct snd_dma_buffer *dmab,
 564                             struct hdac_stream *hstream);
 565bool hda_dsp_check_ipc_irq(struct snd_sof_dev *sdev);
 566bool hda_dsp_check_stream_irq(struct snd_sof_dev *sdev);
 567
 568snd_pcm_uframes_t hda_dsp_stream_get_position(struct hdac_stream *hstream,
 569                                              int direction, bool can_sleep);
 570
 571struct hdac_ext_stream *
 572        hda_dsp_stream_get(struct snd_sof_dev *sdev, int direction, u32 flags);
 573int hda_dsp_stream_put(struct snd_sof_dev *sdev, int direction, int stream_tag);
 574int hda_dsp_stream_spib_config(struct snd_sof_dev *sdev,
 575                               struct hdac_ext_stream *hext_stream,
 576                               int enable, u32 size);
 577
 578int hda_ipc_msg_data(struct snd_sof_dev *sdev,
 579                     struct snd_pcm_substream *substream,
 580                     void *p, size_t sz);
 581int hda_set_stream_data_offset(struct snd_sof_dev *sdev,
 582                               struct snd_pcm_substream *substream,
 583                               size_t posn_offset);
 584
 585/*
 586 * DSP IPC Operations.
 587 */
 588int hda_dsp_ipc_send_msg(struct snd_sof_dev *sdev,
 589                         struct snd_sof_ipc_msg *msg);
 590void hda_dsp_ipc_get_reply(struct snd_sof_dev *sdev);
 591int hda_dsp_ipc_get_mailbox_offset(struct snd_sof_dev *sdev);
 592int hda_dsp_ipc_get_window_offset(struct snd_sof_dev *sdev, u32 id);
 593
 594irqreturn_t hda_dsp_ipc_irq_thread(int irq, void *context);
 595int hda_dsp_ipc_cmd_done(struct snd_sof_dev *sdev, int dir);
 596
 597/*
 598 * DSP Code loader.
 599 */
 600int hda_dsp_cl_boot_firmware(struct snd_sof_dev *sdev);
 601int hda_dsp_cl_boot_firmware_iccmax(struct snd_sof_dev *sdev);
 602int hda_cl_copy_fw(struct snd_sof_dev *sdev, struct hdac_ext_stream *hext_stream);
 603struct hdac_ext_stream *hda_cl_stream_prepare(struct snd_sof_dev *sdev, unsigned int format,
 604                                              unsigned int size, struct snd_dma_buffer *dmab,
 605                                              int direction);
 606int hda_cl_cleanup(struct snd_sof_dev *sdev, struct snd_dma_buffer *dmab,
 607                   struct hdac_ext_stream *hext_stream);
 608#define HDA_CL_STREAM_FORMAT 0x40
 609
 610/* pre and post fw run ops */
 611int hda_dsp_pre_fw_run(struct snd_sof_dev *sdev);
 612int hda_dsp_post_fw_run(struct snd_sof_dev *sdev);
 613
 614/* parse platform specific ext manifest ops */
 615int hda_dsp_ext_man_get_cavs_config_data(struct snd_sof_dev *sdev,
 616                                         const struct sof_ext_man_elem_header *hdr);
 617
 618/*
 619 * HDA Controller Operations.
 620 */
 621int hda_dsp_ctrl_get_caps(struct snd_sof_dev *sdev);
 622void hda_dsp_ctrl_ppcap_enable(struct snd_sof_dev *sdev, bool enable);
 623void hda_dsp_ctrl_ppcap_int_enable(struct snd_sof_dev *sdev, bool enable);
 624int hda_dsp_ctrl_link_reset(struct snd_sof_dev *sdev, bool reset);
 625void hda_dsp_ctrl_misc_clock_gating(struct snd_sof_dev *sdev, bool enable);
 626int hda_dsp_ctrl_clock_power_gating(struct snd_sof_dev *sdev, bool enable);
 627int hda_dsp_ctrl_init_chip(struct snd_sof_dev *sdev, bool full_reset);
 628void hda_dsp_ctrl_stop_chip(struct snd_sof_dev *sdev);
 629/*
 630 * HDA bus operations.
 631 */
 632void sof_hda_bus_init(struct hdac_bus *bus, struct device *dev);
 633
 634#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
 635/*
 636 * HDA Codec operations.
 637 */
 638void hda_codec_probe_bus(struct snd_sof_dev *sdev,
 639                         bool hda_codec_use_common_hdmi);
 640void hda_codec_jack_wake_enable(struct snd_sof_dev *sdev, bool enable);
 641void hda_codec_jack_check(struct snd_sof_dev *sdev);
 642
 643#endif /* CONFIG_SND_SOC_SOF_HDA */
 644
 645#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA) && \
 646        (IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI) || \
 647         IS_ENABLED(CONFIG_SND_SOC_HDAC_HDMI))
 648
 649void hda_codec_i915_display_power(struct snd_sof_dev *sdev, bool enable);
 650int hda_codec_i915_init(struct snd_sof_dev *sdev);
 651int hda_codec_i915_exit(struct snd_sof_dev *sdev);
 652
 653#else
 654
 655static inline void hda_codec_i915_display_power(struct snd_sof_dev *sdev,
 656                                                bool enable) { }
 657static inline int hda_codec_i915_init(struct snd_sof_dev *sdev) { return 0; }
 658static inline int hda_codec_i915_exit(struct snd_sof_dev *sdev) { return 0; }
 659
 660#endif
 661
 662/*
 663 * Trace Control.
 664 */
 665int hda_dsp_trace_init(struct snd_sof_dev *sdev, struct snd_dma_buffer *dmab,
 666                       struct sof_ipc_dma_trace_params_ext *dtrace_params);
 667int hda_dsp_trace_release(struct snd_sof_dev *sdev);
 668int hda_dsp_trace_trigger(struct snd_sof_dev *sdev, int cmd);
 669
 670/*
 671 * SoundWire support
 672 */
 673#if IS_ENABLED(CONFIG_SND_SOC_SOF_INTEL_SOUNDWIRE)
 674
 675int hda_sdw_startup(struct snd_sof_dev *sdev);
 676void hda_sdw_int_enable(struct snd_sof_dev *sdev, bool enable);
 677void hda_sdw_process_wakeen(struct snd_sof_dev *sdev);
 678bool hda_common_check_sdw_irq(struct snd_sof_dev *sdev);
 679
 680#else
 681
 682static inline int hda_sdw_startup(struct snd_sof_dev *sdev)
 683{
 684        return 0;
 685}
 686
 687static inline void hda_sdw_int_enable(struct snd_sof_dev *sdev, bool enable)
 688{
 689}
 690
 691static inline void hda_sdw_process_wakeen(struct snd_sof_dev *sdev)
 692{
 693}
 694
 695static inline bool hda_common_check_sdw_irq(struct snd_sof_dev *sdev)
 696{
 697        return false;
 698}
 699
 700#endif
 701
 702/* common dai driver */
 703extern struct snd_soc_dai_driver skl_dai[];
 704int hda_dsp_dais_suspend(struct snd_sof_dev *sdev);
 705
 706/*
 707 * Platform Specific HW abstraction Ops.
 708 */
 709extern struct snd_sof_dsp_ops sof_hda_common_ops;
 710
 711extern struct snd_sof_dsp_ops sof_apl_ops;
 712int sof_apl_ops_init(struct snd_sof_dev *sdev);
 713extern struct snd_sof_dsp_ops sof_cnl_ops;
 714int sof_cnl_ops_init(struct snd_sof_dev *sdev);
 715extern struct snd_sof_dsp_ops sof_tgl_ops;
 716int sof_tgl_ops_init(struct snd_sof_dev *sdev);
 717extern struct snd_sof_dsp_ops sof_icl_ops;
 718int sof_icl_ops_init(struct snd_sof_dev *sdev);
 719
 720extern const struct sof_intel_dsp_desc apl_chip_info;
 721extern const struct sof_intel_dsp_desc cnl_chip_info;
 722extern const struct sof_intel_dsp_desc icl_chip_info;
 723extern const struct sof_intel_dsp_desc tgl_chip_info;
 724extern const struct sof_intel_dsp_desc tglh_chip_info;
 725extern const struct sof_intel_dsp_desc ehl_chip_info;
 726extern const struct sof_intel_dsp_desc jsl_chip_info;
 727extern const struct sof_intel_dsp_desc adls_chip_info;
 728
 729/* Probes support */
 730#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA_PROBES)
 731int hda_probes_register(struct snd_sof_dev *sdev);
 732void hda_probes_unregister(struct snd_sof_dev *sdev);
 733#else
 734static inline int hda_probes_register(struct snd_sof_dev *sdev)
 735{
 736        return 0;
 737}
 738
 739static inline void hda_probes_unregister(struct snd_sof_dev *sdev)
 740{
 741}
 742#endif /* CONFIG_SND_SOC_SOF_HDA_PROBES */
 743
 744/* SOF client registration for HDA platforms */
 745int hda_register_clients(struct snd_sof_dev *sdev);
 746void hda_unregister_clients(struct snd_sof_dev *sdev);
 747
 748/* machine driver select */
 749struct snd_soc_acpi_mach *hda_machine_select(struct snd_sof_dev *sdev);
 750void hda_set_mach_params(struct snd_soc_acpi_mach *mach,
 751                         struct snd_sof_dev *sdev);
 752
 753/* PCI driver selection and probe */
 754int hda_pci_intel_probe(struct pci_dev *pci, const struct pci_device_id *pci_id);
 755
 756struct snd_sof_dai;
 757struct sof_ipc_dai_config;
 758int hda_ctrl_dai_widget_setup(struct snd_soc_dapm_widget *w, unsigned int quirk_flags,
 759                              struct snd_sof_dai_config_data *data);
 760int hda_ctrl_dai_widget_free(struct snd_soc_dapm_widget *w, unsigned int quirk_flags,
 761                             struct snd_sof_dai_config_data *data);
 762
 763#define SOF_HDA_POSITION_QUIRK_USE_SKYLAKE_LEGACY       (0) /* previous implementation */
 764#define SOF_HDA_POSITION_QUIRK_USE_DPIB_REGISTERS       (1) /* recommended if VC0 only */
 765#define SOF_HDA_POSITION_QUIRK_USE_DPIB_DDR_UPDATE      (2) /* recommended with VC0 or VC1 */
 766
 767extern int sof_hda_position_quirk;
 768
 769void hda_set_dai_drv_ops(struct snd_sof_dev *sdev, struct snd_sof_dsp_ops *ops);
 770
 771/* IPC4 */
 772irqreturn_t cnl_ipc4_irq_thread(int irq, void *context);
 773int cnl_ipc4_send_msg(struct snd_sof_dev *sdev, struct snd_sof_ipc_msg *msg);
 774irqreturn_t hda_dsp_ipc4_irq_thread(int irq, void *context);
 775int hda_dsp_ipc4_send_msg(struct snd_sof_dev *sdev, struct snd_sof_ipc_msg *msg);
 776
 777#endif
 778
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