1/* SPDX-License-Identifier: GPL-2.0 */ 2 3/* 4 * Copyright (c) 2021 MediaTek Corporation. All rights reserved. 5 * 6 * Header file for the mt8195 DSP register definition 7 */ 8 9#ifndef __MT8195_H 10#define __MT8195_H 11 12struct mtk_adsp_chip_info; 13struct snd_sof_dev; 14 15#define DSP_REG_BASE 0x10803000 16#define SCP_CFGREG_BASE 0x10724000 17#define DSP_SYSAO_BASE 0x1080C000 18 19/***************************************************************************** 20 * R E G I S T E R TABLE 21 *****************************************************************************/ 22#define DSP_JTAGMUX 0x0000 23#define DSP_ALTRESETVEC 0x0004 24#define DSP_PDEBUGDATA 0x0008 25#define DSP_PDEBUGBUS0 0x000c 26#define PDEBUG_ENABLE BIT(0) 27#define DSP_PDEBUGBUS1 0x0010 28#define DSP_PDEBUGINST 0x0014 29#define DSP_PDEBUGLS0STAT 0x0018 30#define DSP_PDEBUGLS1STAT 0x001c 31#define DSP_PDEBUGPC 0x0020 32#define DSP_RESET_SW 0x0024 /*reset sw*/ 33#define ADSP_BRESET_SW BIT(0) 34#define ADSP_DRESET_SW BIT(1) 35#define ADSP_RUNSTALL BIT(3) 36#define STATVECTOR_SEL BIT(4) 37#define DSP_PFAULTBUS 0x0028 38#define DSP_PFAULTINFO 0x002c 39#define DSP_GPR00 0x0030 40#define DSP_GPR01 0x0034 41#define DSP_GPR02 0x0038 42#define DSP_GPR03 0x003c 43#define DSP_GPR04 0x0040 44#define DSP_GPR05 0x0044 45#define DSP_GPR06 0x0048 46#define DSP_GPR07 0x004c 47#define DSP_GPR08 0x0050 48#define DSP_GPR09 0x0054 49#define DSP_GPR0A 0x0058 50#define DSP_GPR0B 0x005c 51#define DSP_GPR0C 0x0060 52#define DSP_GPR0D 0x0064 53#define DSP_GPR0E 0x0068 54#define DSP_GPR0F 0x006c 55#define DSP_GPR10 0x0070 56#define DSP_GPR11 0x0074 57#define DSP_GPR12 0x0078 58#define DSP_GPR13 0x007c 59#define DSP_GPR14 0x0080 60#define DSP_GPR15 0x0084 61#define DSP_GPR16 0x0088 62#define DSP_GPR17 0x008c 63#define DSP_GPR18 0x0090 64#define DSP_GPR19 0x0094 65#define DSP_GPR1A 0x0098 66#define DSP_GPR1B 0x009c 67#define DSP_GPR1C 0x00a0 68#define DSP_GPR1D 0x00a4 69#define DSP_GPR1E 0x00a8 70#define DSP_GPR1F 0x00ac 71#define DSP_TCM_OFFSET 0x00b0 /* not used */ 72#define DSP_DDR_OFFSET 0x00b4 /* not used */ 73#define DSP_INTFDSP 0x00d0 74#define DSP_INTFDSP_CLR 0x00d4 75#define DSP_SRAM_PD_SW1 0x00d8 76#define DSP_SRAM_PD_SW2 0x00dc 77#define DSP_OCD 0x00e0 78#define DSP_RG_DSP_IRQ_POL 0x00f0 /* not used */ 79#define DSP_DSP_IRQ_EN 0x00f4 /* not used */ 80#define DSP_DSP_IRQ_LEVEL 0x00f8 /* not used */ 81#define DSP_DSP_IRQ_STATUS 0x00fc /* not used */ 82#define DSP_RG_INT2CIRQ 0x0114 83#define DSP_RG_INT_POL_CTL0 0x0120 84#define DSP_RG_INT_EN_CTL0 0x0130 85#define DSP_RG_INT_LV_CTL0 0x0140 86#define DSP_RG_INT_STATUS0 0x0150 87#define DSP_PDEBUGSTATUS0 0x0200 88#define DSP_PDEBUGSTATUS1 0x0204 89#define DSP_PDEBUGSTATUS2 0x0208 90#define DSP_PDEBUGSTATUS3 0x020c 91#define DSP_PDEBUGSTATUS4 0x0210 92#define DSP_PDEBUGSTATUS5 0x0214 93#define DSP_PDEBUGSTATUS6 0x0218 94#define DSP_PDEBUGSTATUS7 0x021c 95#define DSP_DSP2PSRAM_PRIORITY 0x0220 /* not used */ 96#define DSP_AUDIO_DSP2SPM_INT 0x0224 97#define DSP_AUDIO_DSP2SPM_INT_ACK 0x0228 98#define DSP_AUDIO_DSP_DEBUG_SEL 0x022C 99#define DSP_AUDIO_DSP_EMI_BASE_ADDR 0x02E0 /* not used */ 100#define DSP_AUDIO_DSP_SHARED_IRAM 0x02E4 101#define DSP_AUDIO_DSP_CKCTRL_P2P_CK_CON 0x02F0 102#define DSP_RG_SEMAPHORE00 0x0300 103#define DSP_RG_SEMAPHORE01 0x0304 104#define DSP_RG_SEMAPHORE02 0x0308 105#define DSP_RG_SEMAPHORE03 0x030C 106#define DSP_RG_SEMAPHORE04 0x0310 107#define DSP_RG_SEMAPHORE05 0x0314 108#define DSP_RG_SEMAPHORE06 0x0318 109#define DSP_RG_SEMAPHORE07 0x031C 110#define DSP_RESERVED_0 0x03F0 111#define DSP_RESERVED_1 0x03F4 112 113/* dsp wdt */ 114#define DSP_WDT_MODE 0x0400 115 116/* dsp mbox */ 117#define DSP_MBOX_IN_CMD 0x00 118#define DSP_MBOX_IN_CMD_CLR 0x04 119#define DSP_MBOX_OUT_CMD 0x1c 120#define DSP_MBOX_OUT_CMD_CLR 0x20 121#define DSP_MBOX_IN_MSG0 0x08 122#define DSP_MBOX_IN_MSG1 0x0C 123#define DSP_MBOX_OUT_MSG0 0x24 124#define DSP_MBOX_OUT_MSG1 0x28 125 126/*dsp sys ao*/ 127#define ADSP_SRAM_POOL_CON (DSP_SYSAO_BASE + 0x30) 128#define DSP_SRAM_POOL_PD_MASK 0xf 129#define DSP_EMI_MAP_ADDR (DSP_SYSAO_BASE + 0x81c) 130 131/* DSP memories */ 132#define MBOX_OFFSET 0x800000 /* DRAM */ 133#define MBOX_SIZE 0x1000 /* consistent with which in memory.h of sof fw */ 134#define DSP_DRAM_SIZE 0x1000000 /* 16M */ 135 136#define DSP_REG_BAR 4 137#define DSP_MBOX0_BAR 5 138#define DSP_MBOX1_BAR 6 139#define DSP_MBOX2_BAR 7 140 141#define TOTAL_SIZE_SHARED_SRAM_FROM_TAIL 0x0 142 143#define SIZE_SHARED_DRAM_DL 0x40000 /*Shared buffer for Downlink*/ 144#define SIZE_SHARED_DRAM_UL 0x40000 /*Shared buffer for Uplink*/ 145 146#define TOTAL_SIZE_SHARED_DRAM_FROM_TAIL \ 147 (SIZE_SHARED_DRAM_DL + SIZE_SHARED_DRAM_UL) 148 149#define SRAM_PHYS_BASE_FROM_DSP_VIEW 0x40000000 /* MT8195 DSP view */ 150#define DRAM_PHYS_BASE_FROM_DSP_VIEW 0x60000000 /* MT8195 DSP view */ 151 152/*remap dram between AP and DSP view, 4KB aligned*/ 153#define DRAM_REMAP_SHIFT 12 154#define DRAM_REMAP_MASK (BIT(DRAM_REMAP_SHIFT) - 1) 155 156void sof_hifixdsp_boot_sequence(struct snd_sof_dev *sdev, u32 boot_addr); 157void sof_hifixdsp_shutdown(struct snd_sof_dev *sdev); 158#endif 159