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23#ifndef __ARM_KVM_H__
24#define __ARM_KVM_H__
25
26#define KVM_SPSR_EL1 0
27#define KVM_SPSR_SVC KVM_SPSR_EL1
28#define KVM_SPSR_ABT 1
29#define KVM_SPSR_UND 2
30#define KVM_SPSR_IRQ 3
31#define KVM_SPSR_FIQ 4
32#define KVM_NR_SPSR 5
33
34#ifndef __ASSEMBLY__
35#include <linux/psci.h>
36#include <linux/types.h>
37#include <asm/ptrace.h>
38#include <asm/sve_context.h>
39
40#define __KVM_HAVE_GUEST_DEBUG
41#define __KVM_HAVE_IRQ_LINE
42#define __KVM_HAVE_READONLY_MEM
43#define __KVM_HAVE_VCPU_EVENTS
44
45#define KVM_COALESCED_MMIO_PAGE_OFFSET 1
46
47#define KVM_REG_SIZE(id) \
48 (1U << (((id) & KVM_REG_SIZE_MASK) >> KVM_REG_SIZE_SHIFT))
49
50struct kvm_regs {
51 struct user_pt_regs regs;
52
53 __u64 sp_el1;
54 __u64 elr_el1;
55
56 __u64 spsr[KVM_NR_SPSR];
57
58 struct user_fpsimd_state fp_regs;
59};
60
61
62
63
64
65
66#define KVM_ARM_TARGET_AEM_V8 0
67#define KVM_ARM_TARGET_FOUNDATION_V8 1
68#define KVM_ARM_TARGET_CORTEX_A57 2
69#define KVM_ARM_TARGET_XGENE_POTENZA 3
70#define KVM_ARM_TARGET_CORTEX_A53 4
71
72#define KVM_ARM_TARGET_GENERIC_V8 5
73
74#define KVM_ARM_NUM_TARGETS 6
75
76
77#define KVM_ARM_DEVICE_TYPE_SHIFT 0
78#define KVM_ARM_DEVICE_TYPE_MASK (0xffff << KVM_ARM_DEVICE_TYPE_SHIFT)
79#define KVM_ARM_DEVICE_ID_SHIFT 16
80#define KVM_ARM_DEVICE_ID_MASK (0xffff << KVM_ARM_DEVICE_ID_SHIFT)
81
82
83#define KVM_ARM_DEVICE_VGIC_V2 0
84
85
86#define KVM_VGIC_V2_ADDR_TYPE_DIST 0
87#define KVM_VGIC_V2_ADDR_TYPE_CPU 1
88
89#define KVM_VGIC_V2_DIST_SIZE 0x1000
90#define KVM_VGIC_V2_CPU_SIZE 0x2000
91
92
93#define KVM_VGIC_V3_ADDR_TYPE_DIST 2
94#define KVM_VGIC_V3_ADDR_TYPE_REDIST 3
95#define KVM_VGIC_ITS_ADDR_TYPE 4
96#define KVM_VGIC_V3_ADDR_TYPE_REDIST_REGION 5
97
98#define KVM_VGIC_V3_DIST_SIZE SZ_64K
99#define KVM_VGIC_V3_REDIST_SIZE (2 * SZ_64K)
100#define KVM_VGIC_V3_ITS_SIZE (2 * SZ_64K)
101
102#define KVM_ARM_VCPU_POWER_OFF 0
103#define KVM_ARM_VCPU_EL1_32BIT 1
104#define KVM_ARM_VCPU_PSCI_0_2 2
105#define KVM_ARM_VCPU_PMU_V3 3
106#define KVM_ARM_VCPU_SVE 4
107#define KVM_ARM_VCPU_PTRAUTH_ADDRESS 5
108#define KVM_ARM_VCPU_PTRAUTH_GENERIC 6
109
110struct kvm_vcpu_init {
111 __u32 target;
112 __u32 features[7];
113};
114
115struct kvm_sregs {
116};
117
118struct kvm_fpu {
119};
120
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132
133
134#define KVM_ARM_MAX_DBG_REGS 16
135struct kvm_guest_debug_arch {
136 __u64 dbg_bcr[KVM_ARM_MAX_DBG_REGS];
137 __u64 dbg_bvr[KVM_ARM_MAX_DBG_REGS];
138 __u64 dbg_wcr[KVM_ARM_MAX_DBG_REGS];
139 __u64 dbg_wvr[KVM_ARM_MAX_DBG_REGS];
140};
141
142#define KVM_DEBUG_ARCH_HSR_HIGH_VALID (1 << 0)
143struct kvm_debug_exit_arch {
144 __u32 hsr;
145 __u32 hsr_high;
146 __u64 far;
147};
148
149
150
151
152
153#define KVM_GUESTDBG_USE_SW_BP (1 << 16)
154#define KVM_GUESTDBG_USE_HW (1 << 17)
155
156struct kvm_sync_regs {
157
158 __u64 device_irq_level;
159};
160
161
162
163
164
165struct kvm_pmu_event_filter {
166 __u16 base_event;
167 __u16 nevents;
168
169#define KVM_PMU_EVENT_ALLOW 0
170#define KVM_PMU_EVENT_DENY 1
171
172 __u8 action;
173 __u8 pad[3];
174};
175
176
177struct kvm_vcpu_events {
178 struct {
179 __u8 serror_pending;
180 __u8 serror_has_esr;
181 __u8 ext_dabt_pending;
182
183 __u8 pad[5];
184 __u64 serror_esr;
185 } exception;
186 __u32 reserved[12];
187};
188
189struct kvm_arm_copy_mte_tags {
190 __u64 guest_ipa;
191 __u64 length;
192 void __user *addr;
193 __u64 flags;
194 __u64 reserved[2];
195};
196
197#define KVM_ARM_TAGS_TO_GUEST 0
198#define KVM_ARM_TAGS_FROM_GUEST 1
199
200
201#define KVM_REG_ARM_COPROC_MASK 0x000000000FFF0000
202#define KVM_REG_ARM_COPROC_SHIFT 16
203
204
205#define KVM_REG_ARM_CORE (0x0010 << KVM_REG_ARM_COPROC_SHIFT)
206#define KVM_REG_ARM_CORE_REG(name) (offsetof(struct kvm_regs, name) / sizeof(__u32))
207
208
209#define KVM_REG_ARM_DEMUX (0x0011 << KVM_REG_ARM_COPROC_SHIFT)
210#define KVM_REG_ARM_DEMUX_ID_MASK 0x000000000000FF00
211#define KVM_REG_ARM_DEMUX_ID_SHIFT 8
212#define KVM_REG_ARM_DEMUX_ID_CCSIDR (0x00 << KVM_REG_ARM_DEMUX_ID_SHIFT)
213#define KVM_REG_ARM_DEMUX_VAL_MASK 0x00000000000000FF
214#define KVM_REG_ARM_DEMUX_VAL_SHIFT 0
215
216
217#define KVM_REG_ARM64_SYSREG (0x0013 << KVM_REG_ARM_COPROC_SHIFT)
218#define KVM_REG_ARM64_SYSREG_OP0_MASK 0x000000000000c000
219#define KVM_REG_ARM64_SYSREG_OP0_SHIFT 14
220#define KVM_REG_ARM64_SYSREG_OP1_MASK 0x0000000000003800
221#define KVM_REG_ARM64_SYSREG_OP1_SHIFT 11
222#define KVM_REG_ARM64_SYSREG_CRN_MASK 0x0000000000000780
223#define KVM_REG_ARM64_SYSREG_CRN_SHIFT 7
224#define KVM_REG_ARM64_SYSREG_CRM_MASK 0x0000000000000078
225#define KVM_REG_ARM64_SYSREG_CRM_SHIFT 3
226#define KVM_REG_ARM64_SYSREG_OP2_MASK 0x0000000000000007
227#define KVM_REG_ARM64_SYSREG_OP2_SHIFT 0
228
229#define ARM64_SYS_REG_SHIFT_MASK(x,n) \
230 (((x) << KVM_REG_ARM64_SYSREG_ ## n ## _SHIFT) & \
231 KVM_REG_ARM64_SYSREG_ ## n ## _MASK)
232
233#define __ARM64_SYS_REG(op0,op1,crn,crm,op2) \
234 (KVM_REG_ARM64 | KVM_REG_ARM64_SYSREG | \
235 ARM64_SYS_REG_SHIFT_MASK(op0, OP0) | \
236 ARM64_SYS_REG_SHIFT_MASK(op1, OP1) | \
237 ARM64_SYS_REG_SHIFT_MASK(crn, CRN) | \
238 ARM64_SYS_REG_SHIFT_MASK(crm, CRM) | \
239 ARM64_SYS_REG_SHIFT_MASK(op2, OP2))
240
241#define ARM64_SYS_REG(...) (__ARM64_SYS_REG(__VA_ARGS__) | KVM_REG_SIZE_U64)
242
243
244#define KVM_REG_ARM_PTIMER_CTL ARM64_SYS_REG(3, 3, 14, 2, 1)
245#define KVM_REG_ARM_PTIMER_CVAL ARM64_SYS_REG(3, 3, 14, 2, 2)
246#define KVM_REG_ARM_PTIMER_CNT ARM64_SYS_REG(3, 3, 14, 0, 1)
247
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256
257#define KVM_REG_ARM_TIMER_CTL ARM64_SYS_REG(3, 3, 14, 3, 1)
258#define KVM_REG_ARM_TIMER_CVAL ARM64_SYS_REG(3, 3, 14, 0, 2)
259#define KVM_REG_ARM_TIMER_CNT ARM64_SYS_REG(3, 3, 14, 3, 2)
260
261
262#define KVM_REG_ARM_FW (0x0014 << KVM_REG_ARM_COPROC_SHIFT)
263#define KVM_REG_ARM_FW_REG(r) (KVM_REG_ARM64 | KVM_REG_SIZE_U64 | \
264 KVM_REG_ARM_FW | ((r) & 0xffff))
265#define KVM_REG_ARM_PSCI_VERSION KVM_REG_ARM_FW_REG(0)
266#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_1 KVM_REG_ARM_FW_REG(1)
267#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_1_NOT_AVAIL 0
268#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_1_AVAIL 1
269#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_1_NOT_REQUIRED 2
270
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278
279#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2 KVM_REG_ARM_FW_REG(2)
280#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_NOT_AVAIL 0
281#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_UNKNOWN 1
282#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_AVAIL 2
283#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_NOT_REQUIRED 3
284#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_ENABLED (1U << 4)
285
286#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_3 KVM_REG_ARM_FW_REG(3)
287#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_3_NOT_AVAIL 0
288#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_3_AVAIL 1
289#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_3_NOT_REQUIRED 2
290
291
292#define KVM_REG_ARM64_SVE (0x15 << KVM_REG_ARM_COPROC_SHIFT)
293
294
295#define KVM_REG_ARM64_SVE_ZREG_BASE 0
296#define KVM_REG_ARM64_SVE_PREG_BASE 0x400
297#define KVM_REG_ARM64_SVE_FFR_BASE 0x600
298
299#define KVM_ARM64_SVE_NUM_ZREGS __SVE_NUM_ZREGS
300#define KVM_ARM64_SVE_NUM_PREGS __SVE_NUM_PREGS
301
302#define KVM_ARM64_SVE_MAX_SLICES 32
303
304#define KVM_REG_ARM64_SVE_ZREG(n, i) \
305 (KVM_REG_ARM64 | KVM_REG_ARM64_SVE | KVM_REG_ARM64_SVE_ZREG_BASE | \
306 KVM_REG_SIZE_U2048 | \
307 (((n) & (KVM_ARM64_SVE_NUM_ZREGS - 1)) << 5) | \
308 ((i) & (KVM_ARM64_SVE_MAX_SLICES - 1)))
309
310#define KVM_REG_ARM64_SVE_PREG(n, i) \
311 (KVM_REG_ARM64 | KVM_REG_ARM64_SVE | KVM_REG_ARM64_SVE_PREG_BASE | \
312 KVM_REG_SIZE_U256 | \
313 (((n) & (KVM_ARM64_SVE_NUM_PREGS - 1)) << 5) | \
314 ((i) & (KVM_ARM64_SVE_MAX_SLICES - 1)))
315
316#define KVM_REG_ARM64_SVE_FFR(i) \
317 (KVM_REG_ARM64 | KVM_REG_ARM64_SVE | KVM_REG_ARM64_SVE_FFR_BASE | \
318 KVM_REG_SIZE_U256 | \
319 ((i) & (KVM_ARM64_SVE_MAX_SLICES - 1)))
320
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326
327
328#define KVM_ARM64_SVE_VQ_MIN __SVE_VQ_MIN
329#define KVM_ARM64_SVE_VQ_MAX __SVE_VQ_MAX
330
331
332#define KVM_REG_ARM64_SVE_VLS (KVM_REG_ARM64 | KVM_REG_ARM64_SVE | \
333 KVM_REG_SIZE_U512 | 0xffff)
334#define KVM_ARM64_SVE_VLS_WORDS \
335 ((KVM_ARM64_SVE_VQ_MAX - KVM_ARM64_SVE_VQ_MIN) / 64 + 1)
336
337
338#define KVM_REG_ARM_FW_FEAT_BMAP (0x0016 << KVM_REG_ARM_COPROC_SHIFT)
339#define KVM_REG_ARM_FW_FEAT_BMAP_REG(r) (KVM_REG_ARM64 | KVM_REG_SIZE_U64 | \
340 KVM_REG_ARM_FW_FEAT_BMAP | \
341 ((r) & 0xffff))
342
343#define KVM_REG_ARM_STD_BMAP KVM_REG_ARM_FW_FEAT_BMAP_REG(0)
344
345enum {
346 KVM_REG_ARM_STD_BIT_TRNG_V1_0 = 0,
347#ifdef __KERNEL__
348 KVM_REG_ARM_STD_BMAP_BIT_COUNT,
349#endif
350};
351
352#define KVM_REG_ARM_STD_HYP_BMAP KVM_REG_ARM_FW_FEAT_BMAP_REG(1)
353
354enum {
355 KVM_REG_ARM_STD_HYP_BIT_PV_TIME = 0,
356#ifdef __KERNEL__
357 KVM_REG_ARM_STD_HYP_BMAP_BIT_COUNT,
358#endif
359};
360
361#define KVM_REG_ARM_VENDOR_HYP_BMAP KVM_REG_ARM_FW_FEAT_BMAP_REG(2)
362
363enum {
364 KVM_REG_ARM_VENDOR_HYP_BIT_FUNC_FEAT = 0,
365 KVM_REG_ARM_VENDOR_HYP_BIT_PTP = 1,
366#ifdef __KERNEL__
367 KVM_REG_ARM_VENDOR_HYP_BMAP_BIT_COUNT,
368#endif
369};
370
371
372#define KVM_DEV_ARM_VGIC_GRP_ADDR 0
373#define KVM_DEV_ARM_VGIC_GRP_DIST_REGS 1
374#define KVM_DEV_ARM_VGIC_GRP_CPU_REGS 2
375#define KVM_DEV_ARM_VGIC_CPUID_SHIFT 32
376#define KVM_DEV_ARM_VGIC_CPUID_MASK (0xffULL << KVM_DEV_ARM_VGIC_CPUID_SHIFT)
377#define KVM_DEV_ARM_VGIC_V3_MPIDR_SHIFT 32
378#define KVM_DEV_ARM_VGIC_V3_MPIDR_MASK \
379 (0xffffffffULL << KVM_DEV_ARM_VGIC_V3_MPIDR_SHIFT)
380#define KVM_DEV_ARM_VGIC_OFFSET_SHIFT 0
381#define KVM_DEV_ARM_VGIC_OFFSET_MASK (0xffffffffULL << KVM_DEV_ARM_VGIC_OFFSET_SHIFT)
382#define KVM_DEV_ARM_VGIC_SYSREG_INSTR_MASK (0xffff)
383#define KVM_DEV_ARM_VGIC_GRP_NR_IRQS 3
384#define KVM_DEV_ARM_VGIC_GRP_CTRL 4
385#define KVM_DEV_ARM_VGIC_GRP_REDIST_REGS 5
386#define KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS 6
387#define KVM_DEV_ARM_VGIC_GRP_LEVEL_INFO 7
388#define KVM_DEV_ARM_VGIC_GRP_ITS_REGS 8
389#define KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_SHIFT 10
390#define KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_MASK \
391 (0x3fffffULL << KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_SHIFT)
392#define KVM_DEV_ARM_VGIC_LINE_LEVEL_INTID_MASK 0x3ff
393#define VGIC_LEVEL_INFO_LINE_LEVEL 0
394
395#define KVM_DEV_ARM_VGIC_CTRL_INIT 0
396#define KVM_DEV_ARM_ITS_SAVE_TABLES 1
397#define KVM_DEV_ARM_ITS_RESTORE_TABLES 2
398#define KVM_DEV_ARM_VGIC_SAVE_PENDING_TABLES 3
399#define KVM_DEV_ARM_ITS_CTRL_RESET 4
400
401
402#define KVM_ARM_VCPU_PMU_V3_CTRL 0
403#define KVM_ARM_VCPU_PMU_V3_IRQ 0
404#define KVM_ARM_VCPU_PMU_V3_INIT 1
405#define KVM_ARM_VCPU_PMU_V3_FILTER 2
406#define KVM_ARM_VCPU_PMU_V3_SET_PMU 3
407#define KVM_ARM_VCPU_TIMER_CTRL 1
408#define KVM_ARM_VCPU_TIMER_IRQ_VTIMER 0
409#define KVM_ARM_VCPU_TIMER_IRQ_PTIMER 1
410#define KVM_ARM_VCPU_PVTIME_CTRL 2
411#define KVM_ARM_VCPU_PVTIME_IPA 0
412
413
414#define KVM_ARM_IRQ_VCPU2_SHIFT 28
415#define KVM_ARM_IRQ_VCPU2_MASK 0xf
416#define KVM_ARM_IRQ_TYPE_SHIFT 24
417#define KVM_ARM_IRQ_TYPE_MASK 0xf
418#define KVM_ARM_IRQ_VCPU_SHIFT 16
419#define KVM_ARM_IRQ_VCPU_MASK 0xff
420#define KVM_ARM_IRQ_NUM_SHIFT 0
421#define KVM_ARM_IRQ_NUM_MASK 0xffff
422
423
424#define KVM_ARM_IRQ_TYPE_CPU 0
425#define KVM_ARM_IRQ_TYPE_SPI 1
426#define KVM_ARM_IRQ_TYPE_PPI 2
427
428
429#define KVM_ARM_IRQ_CPU_IRQ 0
430#define KVM_ARM_IRQ_CPU_FIQ 1
431
432
433
434
435
436
437#ifndef __KERNEL__
438#define KVM_ARM_IRQ_GIC_MAX 127
439#endif
440
441
442#define KVM_NR_IRQCHIPS 1
443
444
445#define KVM_PSCI_FN_BASE 0x95c1ba5e
446#define KVM_PSCI_FN(n) (KVM_PSCI_FN_BASE + (n))
447
448#define KVM_PSCI_FN_CPU_SUSPEND KVM_PSCI_FN(0)
449#define KVM_PSCI_FN_CPU_OFF KVM_PSCI_FN(1)
450#define KVM_PSCI_FN_CPU_ON KVM_PSCI_FN(2)
451#define KVM_PSCI_FN_MIGRATE KVM_PSCI_FN(3)
452
453#define KVM_PSCI_RET_SUCCESS PSCI_RET_SUCCESS
454#define KVM_PSCI_RET_NI PSCI_RET_NOT_SUPPORTED
455#define KVM_PSCI_RET_INVAL PSCI_RET_INVALID_PARAMS
456#define KVM_PSCI_RET_DENIED PSCI_RET_DENIED
457
458
459
460
461
462
463#define KVM_SYSTEM_EVENT_RESET_FLAG_PSCI_RESET2 (1ULL << 0)
464
465
466#define KVM_EXIT_FAIL_ENTRY_CPU_UNSUPPORTED (1ULL << 0)
467
468#endif
469
470#endif
471