Local variable in function mfc_dsisr_get at arch/powerpc/platforms/cell/spu_priv1_mmio.c, line 86 References: arch/powerpc/platforms/cell/spu_priv1_mmio.c, line 27 arch/powerpc/platforms/cell/spu_priv1_mmio.c, line 27 arch/powerpc/platforms/cell/spu_priv1_mmio.c, line 31 arch/powerpc/platforms/cell/spu_priv1_mmio.c, line 32 arch/powerpc/platforms/cell/spu_priv1_mmio.c, line 35 arch/powerpc/platforms/cell/spu_priv1_mmio.c, line 35 arch/powerpc/platforms/cell/spu_priv1_mmio.c, line 39 arch/powerpc/platforms/cell/spu_priv1_mmio.c, line 40 arch/powerpc/platforms/cell/spu_priv1_mmio.c, line 43 arch/powerpc/platforms/cell/spu_priv1_mmio.c, line 43 arch/powerpc/platforms/cell/spu_priv1_mmio.c, line 45 arch/powerpc/platforms/cell/spu_priv1_mmio.c, line 48 arch/powerpc/platforms/cell/spu_priv1_mmio.c, line 48 arch/powerpc/platforms/cell/spu_priv1_mmio.c, line 50 arch/powerpc/platforms/cell/spu_priv1_mmio.c, line 53 arch/powerpc/platforms/cell/spu_priv1_mmio.c, line 53 arch/powerpc/platforms/cell/spu_priv1_mmio.c, line 55 arch/powerpc/platforms/cell/spu_priv1_mmio.c, line 58 arch/powerpc/platforms/cell/spu_priv1_mmio.c, line 58 arch/powerpc/platforms/cell/spu_priv1_mmio.c, line 60 arch/powerpc/platforms/cell/spu_priv1_mmio.c, line 63 arch/powerpc/platforms/cell/spu_priv1_mmio.c, line 63 arch/powerpc/platforms/cell/spu_priv1_mmio.c, line 68 arch/powerpc/platforms/cell/spu_priv1_mmio.c, line 69 arch/powerpc/platforms/cell/spu_priv1_mmio.c, line 78 arch/powerpc/platforms/cell/spu_priv1_mmio.c, line 81 arch/powerpc/platforms/cell/spu_priv1_mmio.c, line 81 arch/powerpc/platforms/cell/spu_priv1_mmio.c, line 83 arch/powerpc/platforms/cell/spu_priv1_mmio.c, line 86 arch/powerpc/platforms/cell/spu_priv1_mmio.c, line 86 arch/powerpc/platforms/cell/spu_priv1_mmio.c, line 88 arch/powerpc/platforms/cell/spu_priv1_mmio.c, line 91 arch/powerpc/platforms/cell/spu_priv1_mmio.c, line 91 arch/powerpc/platforms/cell/spu_priv1_mmio.c, line 93 arch/powerpc/platforms/cell/spu_priv1_mmio.c, line 96 arch/powerpc/platforms/cell/spu_priv1_mmio.c, line 96 arch/powerpc/platforms/cell/spu_priv1_mmio.c, line 98 arch/powerpc/platforms/cell/spu_priv1_mmio.c, line 101 arch/powerpc/platforms/cell/spu_priv1_mmio.c, line 101 arch/powerpc/platforms/cell/spu_priv1_mmio.c, line 103 arch/powerpc/platforms/cell/spu_priv1_mmio.c, line 106 arch/powerpc/platforms/cell/spu_priv1_mmio.c, line 106 arch/powerpc/platforms/cell/spu_priv1_mmio.c, line 108 arch/powerpc/platforms/cell/spu_priv1_mmio.c, line 111 arch/powerpc/platforms/cell/spu_priv1_mmio.c, line 111 arch/powerpc/platforms/cell/spu_priv1_mmio.c, line 113 arch/powerpc/platforms/cell/spu_priv1_mmio.c, line 116 arch/powerpc/platforms/cell/spu_priv1_mmio.c, line 116 arch/powerpc/platforms/cell/spu_priv1_mmio.c, line 118 arch/powerpc/platforms/cell/spu_priv1_mmio.c, line 121 arch/powerpc/platforms/cell/spu_priv1_mmio.c, line 121 arch/powerpc/platforms/cell/spu_priv1_mmio.c, line 123 arch/powerpc/platforms/cell/spu_priv1_mmio.c, line 126 arch/powerpc/platforms/cell/spu_priv1_mmio.c, line 126 arch/powerpc/platforms/cell/spu_priv1_mmio.c, line 128 arch/powerpc/platforms/cell/spu_priv1_mmio.c, line 131 arch/powerpc/platforms/cell/spu_priv1_mmio.c, line 131 arch/powerpc/platforms/cell/spu_priv1_mmio.c, line 133 arch/powerpc/platforms/cell/spu_priv1_mmio.c, line 136 arch/powerpc/platforms/cell/spu_priv1_mmio.c, line 136 arch/powerpc/platforms/cell/spu_priv1_mmio.c, line 138 arch/powerpc/platforms/cell/spu_priv1_mmio.c, line 141 arch/powerpc/platforms/cell/spu_priv1_mmio.c, line 141 arch/powerpc/platforms/cell/spu_priv1_mmio.c, line 143