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12
13#define pr_fmt(fmt) "hw-breakpoint: " fmt
14
15#include <linux/errno.h>
16#include <linux/hardirq.h>
17#include <linux/perf_event.h>
18#include <linux/hw_breakpoint.h>
19#include <linux/smp.h>
20#include <linux/cpu_pm.h>
21#include <linux/coresight.h>
22
23#include <asm/cacheflush.h>
24#include <asm/cputype.h>
25#include <asm/current.h>
26#include <asm/hw_breakpoint.h>
27#include <asm/traps.h>
28
29
30static DEFINE_PER_CPU(struct perf_event *, bp_on_reg[ARM_MAX_BRP]);
31
32
33static DEFINE_PER_CPU(struct perf_event *, wp_on_reg[ARM_MAX_WRP]);
34
35
36static int core_num_brps __ro_after_init;
37static int core_num_wrps __ro_after_init;
38
39
40static u8 debug_arch __ro_after_init;
41
42
43static bool has_ossr __ro_after_init;
44
45
46static u8 max_watchpoint_len __ro_after_init;
47
48#define READ_WB_REG_CASE(OP2, M, VAL) \
49 case ((OP2 << 4) + M): \
50 ARM_DBG_READ(c0, c ## M, OP2, VAL); \
51 break
52
53#define WRITE_WB_REG_CASE(OP2, M, VAL) \
54 case ((OP2 << 4) + M): \
55 ARM_DBG_WRITE(c0, c ## M, OP2, VAL); \
56 break
57
58#define GEN_READ_WB_REG_CASES(OP2, VAL) \
59 READ_WB_REG_CASE(OP2, 0, VAL); \
60 READ_WB_REG_CASE(OP2, 1, VAL); \
61 READ_WB_REG_CASE(OP2, 2, VAL); \
62 READ_WB_REG_CASE(OP2, 3, VAL); \
63 READ_WB_REG_CASE(OP2, 4, VAL); \
64 READ_WB_REG_CASE(OP2, 5, VAL); \
65 READ_WB_REG_CASE(OP2, 6, VAL); \
66 READ_WB_REG_CASE(OP2, 7, VAL); \
67 READ_WB_REG_CASE(OP2, 8, VAL); \
68 READ_WB_REG_CASE(OP2, 9, VAL); \
69 READ_WB_REG_CASE(OP2, 10, VAL); \
70 READ_WB_REG_CASE(OP2, 11, VAL); \
71 READ_WB_REG_CASE(OP2, 12, VAL); \
72 READ_WB_REG_CASE(OP2, 13, VAL); \
73 READ_WB_REG_CASE(OP2, 14, VAL); \
74 READ_WB_REG_CASE(OP2, 15, VAL)
75
76#define GEN_WRITE_WB_REG_CASES(OP2, VAL) \
77 WRITE_WB_REG_CASE(OP2, 0, VAL); \
78 WRITE_WB_REG_CASE(OP2, 1, VAL); \
79 WRITE_WB_REG_CASE(OP2, 2, VAL); \
80 WRITE_WB_REG_CASE(OP2, 3, VAL); \
81 WRITE_WB_REG_CASE(OP2, 4, VAL); \
82 WRITE_WB_REG_CASE(OP2, 5, VAL); \
83 WRITE_WB_REG_CASE(OP2, 6, VAL); \
84 WRITE_WB_REG_CASE(OP2, 7, VAL); \
85 WRITE_WB_REG_CASE(OP2, 8, VAL); \
86 WRITE_WB_REG_CASE(OP2, 9, VAL); \
87 WRITE_WB_REG_CASE(OP2, 10, VAL); \
88 WRITE_WB_REG_CASE(OP2, 11, VAL); \
89 WRITE_WB_REG_CASE(OP2, 12, VAL); \
90 WRITE_WB_REG_CASE(OP2, 13, VAL); \
91 WRITE_WB_REG_CASE(OP2, 14, VAL); \
92 WRITE_WB_REG_CASE(OP2, 15, VAL)
93
94static u32 read_wb_reg(int n)
95{
96 u32 val = 0;
97
98 switch (n) {
99 GEN_READ_WB_REG_CASES(ARM_OP2_BVR, val);
100 GEN_READ_WB_REG_CASES(ARM_OP2_BCR, val);
101 GEN_READ_WB_REG_CASES(ARM_OP2_WVR, val);
102 GEN_READ_WB_REG_CASES(ARM_OP2_WCR, val);
103 default:
104 pr_warn("attempt to read from unknown breakpoint register %d\n",
105 n);
106 }
107
108 return val;
109}
110
111static void write_wb_reg(int n, u32 val)
112{
113 switch (n) {
114 GEN_WRITE_WB_REG_CASES(ARM_OP2_BVR, val);
115 GEN_WRITE_WB_REG_CASES(ARM_OP2_BCR, val);
116 GEN_WRITE_WB_REG_CASES(ARM_OP2_WVR, val);
117 GEN_WRITE_WB_REG_CASES(ARM_OP2_WCR, val);
118 default:
119 pr_warn("attempt to write to unknown breakpoint register %d\n",
120 n);
121 }
122 isb();
123}
124
125
126static u8 get_debug_arch(void)
127{
128 u32 didr;
129
130
131 if (((read_cpuid_id() >> 16) & 0xf) != 0xf) {
132 pr_warn_once("CPUID feature registers not supported. "
133 "Assuming v6 debug is present.\n");
134 return ARM_DEBUG_ARCH_V6;
135 }
136
137 ARM_DBG_READ(c0, c0, 0, didr);
138 return (didr >> 16) & 0xf;
139}
140
141u8 arch_get_debug_arch(void)
142{
143 return debug_arch;
144}
145
146static int debug_arch_supported(void)
147{
148 u8 arch = get_debug_arch();
149
150
151 return (arch >= ARM_DEBUG_ARCH_V6 && arch <= ARM_DEBUG_ARCH_V7_ECP14) ||
152 arch >= ARM_DEBUG_ARCH_V7_1;
153}
154
155
156static int debug_exception_updates_fsr(void)
157{
158 return get_debug_arch() >= ARM_DEBUG_ARCH_V8;
159}
160
161
162static int get_num_wrp_resources(void)
163{
164 u32 didr;
165 ARM_DBG_READ(c0, c0, 0, didr);
166 return ((didr >> 28) & 0xf) + 1;
167}
168
169
170static int get_num_brp_resources(void)
171{
172 u32 didr;
173 ARM_DBG_READ(c0, c0, 0, didr);
174 return ((didr >> 24) & 0xf) + 1;
175}
176
177
178static int core_has_mismatch_brps(void)
179{
180 return (get_debug_arch() >= ARM_DEBUG_ARCH_V7_ECP14 &&
181 get_num_brp_resources() > 1);
182}
183
184
185static int get_num_wrps(void)
186{
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205 if (get_debug_arch() < ARM_DEBUG_ARCH_V7_1)
206 return 1;
207
208 return get_num_wrp_resources();
209}
210
211
212static int get_num_brps(void)
213{
214 int brps = get_num_brp_resources();
215 return core_has_mismatch_brps() ? brps - 1 : brps;
216}
217
218
219
220
221
222
223
224static int monitor_mode_enabled(void)
225{
226 u32 dscr;
227 ARM_DBG_READ(c0, c1, 0, dscr);
228 return !!(dscr & ARM_DSCR_MDBGEN);
229}
230
231static int enable_monitor_mode(void)
232{
233 u32 dscr;
234 ARM_DBG_READ(c0, c1, 0, dscr);
235
236
237 if (dscr & ARM_DSCR_MDBGEN)
238 goto out;
239
240
241 switch (get_debug_arch()) {
242 case ARM_DEBUG_ARCH_V6:
243 case ARM_DEBUG_ARCH_V6_1:
244 ARM_DBG_WRITE(c0, c1, 0, (dscr | ARM_DSCR_MDBGEN));
245 break;
246 case ARM_DEBUG_ARCH_V7_ECP14:
247 case ARM_DEBUG_ARCH_V7_1:
248 case ARM_DEBUG_ARCH_V8:
249 ARM_DBG_WRITE(c0, c2, 2, (dscr | ARM_DSCR_MDBGEN));
250 isb();
251 break;
252 default:
253 return -ENODEV;
254 }
255
256
257 ARM_DBG_READ(c0, c1, 0, dscr);
258 if (!(dscr & ARM_DSCR_MDBGEN)) {
259 pr_warn_once("Failed to enable monitor mode on CPU %d.\n",
260 smp_processor_id());
261 return -EPERM;
262 }
263
264out:
265 return 0;
266}
267
268int hw_breakpoint_slots(int type)
269{
270 if (!debug_arch_supported())
271 return 0;
272
273
274
275
276
277 switch (type) {
278 case TYPE_INST:
279 return get_num_brps();
280 case TYPE_DATA:
281 return get_num_wrps();
282 default:
283 pr_warn("unknown slot type: %d\n", type);
284 return 0;
285 }
286}
287
288
289
290
291
292static u8 get_max_wp_len(void)
293{
294 u32 ctrl_reg;
295 struct arch_hw_breakpoint_ctrl ctrl;
296 u8 size = 4;
297
298 if (debug_arch < ARM_DEBUG_ARCH_V7_ECP14)
299 goto out;
300
301 memset(&ctrl, 0, sizeof(ctrl));
302 ctrl.len = ARM_BREAKPOINT_LEN_8;
303 ctrl_reg = encode_ctrl_reg(ctrl);
304
305 write_wb_reg(ARM_BASE_WVR, 0);
306 write_wb_reg(ARM_BASE_WCR, ctrl_reg);
307 if ((read_wb_reg(ARM_BASE_WCR) & ctrl_reg) == ctrl_reg)
308 size = 8;
309
310out:
311 return size;
312}
313
314u8 arch_get_max_wp_len(void)
315{
316 return max_watchpoint_len;
317}
318
319
320
321
322int arch_install_hw_breakpoint(struct perf_event *bp)
323{
324 struct arch_hw_breakpoint *info = counter_arch_bp(bp);
325 struct perf_event **slot, **slots;
326 int i, max_slots, ctrl_base, val_base;
327 u32 addr, ctrl;
328
329 addr = info->address;
330 ctrl = encode_ctrl_reg(info->ctrl) | 0x1;
331
332 if (info->ctrl.type == ARM_BREAKPOINT_EXECUTE) {
333
334 ctrl_base = ARM_BASE_BCR;
335 val_base = ARM_BASE_BVR;
336 slots = this_cpu_ptr(bp_on_reg);
337 max_slots = core_num_brps;
338 } else {
339
340 ctrl_base = ARM_BASE_WCR;
341 val_base = ARM_BASE_WVR;
342 slots = this_cpu_ptr(wp_on_reg);
343 max_slots = core_num_wrps;
344 }
345
346 for (i = 0; i < max_slots; ++i) {
347 slot = &slots[i];
348
349 if (!*slot) {
350 *slot = bp;
351 break;
352 }
353 }
354
355 if (i == max_slots) {
356 pr_warn("Can't find any breakpoint slot\n");
357 return -EBUSY;
358 }
359
360
361 if (info->step_ctrl.enabled) {
362 addr = info->trigger & ~0x3;
363 ctrl = encode_ctrl_reg(info->step_ctrl);
364 if (info->ctrl.type != ARM_BREAKPOINT_EXECUTE) {
365 i = 0;
366 ctrl_base = ARM_BASE_BCR + core_num_brps;
367 val_base = ARM_BASE_BVR + core_num_brps;
368 }
369 }
370
371
372 write_wb_reg(val_base + i, addr);
373
374
375 write_wb_reg(ctrl_base + i, ctrl);
376 return 0;
377}
378
379void arch_uninstall_hw_breakpoint(struct perf_event *bp)
380{
381 struct arch_hw_breakpoint *info = counter_arch_bp(bp);
382 struct perf_event **slot, **slots;
383 int i, max_slots, base;
384
385 if (info->ctrl.type == ARM_BREAKPOINT_EXECUTE) {
386
387 base = ARM_BASE_BCR;
388 slots = this_cpu_ptr(bp_on_reg);
389 max_slots = core_num_brps;
390 } else {
391
392 base = ARM_BASE_WCR;
393 slots = this_cpu_ptr(wp_on_reg);
394 max_slots = core_num_wrps;
395 }
396
397
398 for (i = 0; i < max_slots; ++i) {
399 slot = &slots[i];
400
401 if (*slot == bp) {
402 *slot = NULL;
403 break;
404 }
405 }
406
407 if (i == max_slots) {
408 pr_warn("Can't find any breakpoint slot\n");
409 return;
410 }
411
412
413 if (info->ctrl.type != ARM_BREAKPOINT_EXECUTE &&
414 info->step_ctrl.enabled) {
415 i = 0;
416 base = ARM_BASE_BCR + core_num_brps;
417 }
418
419
420 write_wb_reg(base + i, 0);
421}
422
423static int get_hbp_len(u8 hbp_len)
424{
425 unsigned int len_in_bytes = 0;
426
427 switch (hbp_len) {
428 case ARM_BREAKPOINT_LEN_1:
429 len_in_bytes = 1;
430 break;
431 case ARM_BREAKPOINT_LEN_2:
432 len_in_bytes = 2;
433 break;
434 case ARM_BREAKPOINT_LEN_4:
435 len_in_bytes = 4;
436 break;
437 case ARM_BREAKPOINT_LEN_8:
438 len_in_bytes = 8;
439 break;
440 }
441
442 return len_in_bytes;
443}
444
445
446
447
448int arch_check_bp_in_kernelspace(struct arch_hw_breakpoint *hw)
449{
450 unsigned int len;
451 unsigned long va;
452
453 va = hw->address;
454 len = get_hbp_len(hw->ctrl.len);
455
456 return (va >= TASK_SIZE) && ((va + len - 1) >= TASK_SIZE);
457}
458
459
460
461
462
463
464int arch_bp_generic_fields(struct arch_hw_breakpoint_ctrl ctrl,
465 int *gen_len, int *gen_type)
466{
467
468 switch (ctrl.type) {
469 case ARM_BREAKPOINT_EXECUTE:
470 *gen_type = HW_BREAKPOINT_X;
471 break;
472 case ARM_BREAKPOINT_LOAD:
473 *gen_type = HW_BREAKPOINT_R;
474 break;
475 case ARM_BREAKPOINT_STORE:
476 *gen_type = HW_BREAKPOINT_W;
477 break;
478 case ARM_BREAKPOINT_LOAD | ARM_BREAKPOINT_STORE:
479 *gen_type = HW_BREAKPOINT_RW;
480 break;
481 default:
482 return -EINVAL;
483 }
484
485
486 switch (ctrl.len) {
487 case ARM_BREAKPOINT_LEN_1:
488 *gen_len = HW_BREAKPOINT_LEN_1;
489 break;
490 case ARM_BREAKPOINT_LEN_2:
491 *gen_len = HW_BREAKPOINT_LEN_2;
492 break;
493 case ARM_BREAKPOINT_LEN_4:
494 *gen_len = HW_BREAKPOINT_LEN_4;
495 break;
496 case ARM_BREAKPOINT_LEN_8:
497 *gen_len = HW_BREAKPOINT_LEN_8;
498 break;
499 default:
500 return -EINVAL;
501 }
502
503 return 0;
504}
505
506
507
508
509static int arch_build_bp_info(struct perf_event *bp,
510 const struct perf_event_attr *attr,
511 struct arch_hw_breakpoint *hw)
512{
513
514 switch (attr->bp_type) {
515 case HW_BREAKPOINT_X:
516 hw->ctrl.type = ARM_BREAKPOINT_EXECUTE;
517 break;
518 case HW_BREAKPOINT_R:
519 hw->ctrl.type = ARM_BREAKPOINT_LOAD;
520 break;
521 case HW_BREAKPOINT_W:
522 hw->ctrl.type = ARM_BREAKPOINT_STORE;
523 break;
524 case HW_BREAKPOINT_RW:
525 hw->ctrl.type = ARM_BREAKPOINT_LOAD | ARM_BREAKPOINT_STORE;
526 break;
527 default:
528 return -EINVAL;
529 }
530
531
532 switch (attr->bp_len) {
533 case HW_BREAKPOINT_LEN_1:
534 hw->ctrl.len = ARM_BREAKPOINT_LEN_1;
535 break;
536 case HW_BREAKPOINT_LEN_2:
537 hw->ctrl.len = ARM_BREAKPOINT_LEN_2;
538 break;
539 case HW_BREAKPOINT_LEN_4:
540 hw->ctrl.len = ARM_BREAKPOINT_LEN_4;
541 break;
542 case HW_BREAKPOINT_LEN_8:
543 hw->ctrl.len = ARM_BREAKPOINT_LEN_8;
544 if ((hw->ctrl.type != ARM_BREAKPOINT_EXECUTE)
545 && max_watchpoint_len >= 8)
546 break;
547 default:
548 return -EINVAL;
549 }
550
551
552
553
554
555
556
557 if (hw->ctrl.type == ARM_BREAKPOINT_EXECUTE &&
558 hw->ctrl.len != ARM_BREAKPOINT_LEN_2 &&
559 hw->ctrl.len != ARM_BREAKPOINT_LEN_4)
560 return -EINVAL;
561
562
563 hw->address = attr->bp_addr;
564
565
566 hw->ctrl.privilege = ARM_BREAKPOINT_USER;
567 if (arch_check_bp_in_kernelspace(hw))
568 hw->ctrl.privilege |= ARM_BREAKPOINT_PRIV;
569
570
571 hw->ctrl.enabled = !attr->disabled;
572
573
574 hw->ctrl.mismatch = 0;
575
576 return 0;
577}
578
579
580
581
582int hw_breakpoint_arch_parse(struct perf_event *bp,
583 const struct perf_event_attr *attr,
584 struct arch_hw_breakpoint *hw)
585{
586 int ret = 0;
587 u32 offset, alignment_mask = 0x3;
588
589
590 if (!monitor_mode_enabled())
591 return -ENODEV;
592
593
594 ret = arch_build_bp_info(bp, attr, hw);
595 if (ret)
596 goto out;
597
598
599 if (hw->ctrl.len == ARM_BREAKPOINT_LEN_8)
600 alignment_mask = 0x7;
601 offset = hw->address & alignment_mask;
602 switch (offset) {
603 case 0:
604
605 break;
606 case 1:
607 case 2:
608
609 if (hw->ctrl.len == ARM_BREAKPOINT_LEN_2)
610 break;
611 case 3:
612
613 if (hw->ctrl.len == ARM_BREAKPOINT_LEN_1)
614 break;
615 default:
616 ret = -EINVAL;
617 goto out;
618 }
619
620 hw->address &= ~alignment_mask;
621 hw->ctrl.len <<= offset;
622
623 if (is_default_overflow_handler(bp)) {
624
625
626
627
628 if (!core_has_mismatch_brps())
629 return -EINVAL;
630
631
632 if (arch_check_bp_in_kernelspace(hw))
633 return -EPERM;
634
635
636
637
638
639 if (!bp->hw.target)
640 return -EINVAL;
641
642
643
644
645
646 if (!debug_exception_updates_fsr() &&
647 (hw->ctrl.type == ARM_BREAKPOINT_LOAD ||
648 hw->ctrl.type == ARM_BREAKPOINT_STORE))
649 return -EINVAL;
650 }
651
652out:
653 return ret;
654}
655
656
657
658
659static void enable_single_step(struct perf_event *bp, u32 addr)
660{
661 struct arch_hw_breakpoint *info = counter_arch_bp(bp);
662
663 arch_uninstall_hw_breakpoint(bp);
664 info->step_ctrl.mismatch = 1;
665 info->step_ctrl.len = ARM_BREAKPOINT_LEN_4;
666 info->step_ctrl.type = ARM_BREAKPOINT_EXECUTE;
667 info->step_ctrl.privilege = info->ctrl.privilege;
668 info->step_ctrl.enabled = 1;
669 info->trigger = addr;
670 arch_install_hw_breakpoint(bp);
671}
672
673static void disable_single_step(struct perf_event *bp)
674{
675 arch_uninstall_hw_breakpoint(bp);
676 counter_arch_bp(bp)->step_ctrl.enabled = 0;
677 arch_install_hw_breakpoint(bp);
678}
679
680static void watchpoint_handler(unsigned long addr, unsigned int fsr,
681 struct pt_regs *regs)
682{
683 int i, access;
684 u32 val, ctrl_reg, alignment_mask;
685 struct perf_event *wp, **slots;
686 struct arch_hw_breakpoint *info;
687 struct arch_hw_breakpoint_ctrl ctrl;
688
689 slots = this_cpu_ptr(wp_on_reg);
690
691 for (i = 0; i < core_num_wrps; ++i) {
692 rcu_read_lock();
693
694 wp = slots[i];
695
696 if (wp == NULL)
697 goto unlock;
698
699 info = counter_arch_bp(wp);
700
701
702
703
704
705
706 if (debug_arch < ARM_DEBUG_ARCH_V7_1) {
707 BUG_ON(i > 0);
708 info->trigger = wp->attr.bp_addr;
709 } else {
710 if (info->ctrl.len == ARM_BREAKPOINT_LEN_8)
711 alignment_mask = 0x7;
712 else
713 alignment_mask = 0x3;
714
715
716 val = read_wb_reg(ARM_BASE_WVR + i);
717 if (val != (addr & ~alignment_mask))
718 goto unlock;
719
720
721 ctrl_reg = read_wb_reg(ARM_BASE_WCR + i);
722 decode_ctrl_reg(ctrl_reg, &ctrl);
723 if (!((1 << (addr & alignment_mask)) & ctrl.len))
724 goto unlock;
725
726
727 if (debug_exception_updates_fsr()) {
728 access = (fsr & ARM_FSR_ACCESS_MASK) ?
729 HW_BREAKPOINT_W : HW_BREAKPOINT_R;
730 if (!(access & hw_breakpoint_type(wp)))
731 goto unlock;
732 }
733
734
735 info->trigger = addr;
736 }
737
738 pr_debug("watchpoint fired: address = 0x%x\n", info->trigger);
739 perf_bp_event(wp, regs);
740
741
742
743
744
745
746 if (is_default_overflow_handler(wp))
747 enable_single_step(wp, instruction_pointer(regs));
748
749unlock:
750 rcu_read_unlock();
751 }
752}
753
754static void watchpoint_single_step_handler(unsigned long pc)
755{
756 int i;
757 struct perf_event *wp, **slots;
758 struct arch_hw_breakpoint *info;
759
760 slots = this_cpu_ptr(wp_on_reg);
761
762 for (i = 0; i < core_num_wrps; ++i) {
763 rcu_read_lock();
764
765 wp = slots[i];
766
767 if (wp == NULL)
768 goto unlock;
769
770 info = counter_arch_bp(wp);
771 if (!info->step_ctrl.enabled)
772 goto unlock;
773
774
775
776
777
778 if (info->trigger != pc)
779 disable_single_step(wp);
780
781unlock:
782 rcu_read_unlock();
783 }
784}
785
786static void breakpoint_handler(unsigned long unknown, struct pt_regs *regs)
787{
788 int i;
789 u32 ctrl_reg, val, addr;
790 struct perf_event *bp, **slots;
791 struct arch_hw_breakpoint *info;
792 struct arch_hw_breakpoint_ctrl ctrl;
793
794 slots = this_cpu_ptr(bp_on_reg);
795
796
797 addr = regs->ARM_pc;
798
799
800 for (i = 0; i < core_num_brps; ++i) {
801 rcu_read_lock();
802
803 bp = slots[i];
804
805 if (bp == NULL)
806 goto unlock;
807
808 info = counter_arch_bp(bp);
809
810
811 val = read_wb_reg(ARM_BASE_BVR + i);
812 if (val != (addr & ~0x3))
813 goto mismatch;
814
815
816 ctrl_reg = read_wb_reg(ARM_BASE_BCR + i);
817 decode_ctrl_reg(ctrl_reg, &ctrl);
818 if ((1 << (addr & 0x3)) & ctrl.len) {
819 info->trigger = addr;
820 pr_debug("breakpoint fired: address = 0x%x\n", addr);
821 perf_bp_event(bp, regs);
822 if (!bp->overflow_handler)
823 enable_single_step(bp, addr);
824 goto unlock;
825 }
826
827mismatch:
828
829 if (info->step_ctrl.enabled)
830 disable_single_step(bp);
831unlock:
832 rcu_read_unlock();
833 }
834
835
836 watchpoint_single_step_handler(addr);
837}
838
839
840
841
842
843static int hw_breakpoint_pending(unsigned long addr, unsigned int fsr,
844 struct pt_regs *regs)
845{
846 int ret = 0;
847 u32 dscr;
848
849 preempt_disable();
850
851 if (interrupts_enabled(regs))
852 local_irq_enable();
853
854
855 ARM_DBG_READ(c0, c1, 0, dscr);
856
857
858 switch (ARM_DSCR_MOE(dscr)) {
859 case ARM_ENTRY_BREAKPOINT:
860 breakpoint_handler(addr, regs);
861 break;
862 case ARM_ENTRY_ASYNC_WATCHPOINT:
863 WARN(1, "Asynchronous watchpoint exception taken. Debugging results may be unreliable\n");
864 case ARM_ENTRY_SYNC_WATCHPOINT:
865 watchpoint_handler(addr, fsr, regs);
866 break;
867 default:
868 ret = 1;
869 }
870
871 preempt_enable();
872
873 return ret;
874}
875
876
877
878
879static cpumask_t debug_err_mask;
880
881static int debug_reg_trap(struct pt_regs *regs, unsigned int instr)
882{
883 int cpu = smp_processor_id();
884
885 pr_warn("Debug register access (0x%x) caused undefined instruction on CPU %d\n",
886 instr, cpu);
887
888
889 cpumask_set_cpu(cpu, &debug_err_mask);
890 instruction_pointer(regs) += 4;
891 return 0;
892}
893
894static struct undef_hook debug_reg_hook = {
895 .instr_mask = 0x0fe80f10,
896 .instr_val = 0x0e000e10,
897 .fn = debug_reg_trap,
898};
899
900
901static bool core_has_os_save_restore(void)
902{
903 u32 oslsr;
904
905 switch (get_debug_arch()) {
906 case ARM_DEBUG_ARCH_V7_1:
907 return true;
908 case ARM_DEBUG_ARCH_V7_ECP14:
909 ARM_DBG_READ(c1, c1, 4, oslsr);
910 if (oslsr & ARM_OSLSR_OSLM0)
911 return true;
912 default:
913 return false;
914 }
915}
916
917static void reset_ctrl_regs(unsigned int cpu)
918{
919 int i, raw_num_brps, err = 0;
920 u32 val;
921
922
923
924
925
926
927
928
929
930 switch (debug_arch) {
931 case ARM_DEBUG_ARCH_V6:
932 case ARM_DEBUG_ARCH_V6_1:
933
934 goto out_mdbgen;
935 case ARM_DEBUG_ARCH_V7_ECP14:
936
937
938
939
940 ARM_DBG_READ(c1, c5, 4, val);
941 if ((val & 0x1) == 0)
942 err = -EPERM;
943
944 if (!has_ossr)
945 goto clear_vcr;
946 break;
947 case ARM_DEBUG_ARCH_V7_1:
948
949
950
951 ARM_DBG_READ(c1, c3, 4, val);
952 if ((val & 0x1) == 1)
953 err = -EPERM;
954 break;
955 }
956
957 if (err) {
958 pr_warn_once("CPU %d debug is powered down!\n", cpu);
959 cpumask_or(&debug_err_mask, &debug_err_mask, cpumask_of(cpu));
960 return;
961 }
962
963
964
965
966
967 ARM_DBG_WRITE(c1, c0, 4, ~CORESIGHT_UNLOCK);
968 isb();
969
970
971
972
973
974clear_vcr:
975 ARM_DBG_WRITE(c0, c7, 0, 0);
976 isb();
977
978 if (cpumask_intersects(&debug_err_mask, cpumask_of(cpu))) {
979 pr_warn_once("CPU %d failed to disable vector catch\n", cpu);
980 return;
981 }
982
983
984
985
986
987 raw_num_brps = get_num_brp_resources();
988 for (i = 0; i < raw_num_brps; ++i) {
989 write_wb_reg(ARM_BASE_BCR + i, 0UL);
990 write_wb_reg(ARM_BASE_BVR + i, 0UL);
991 }
992
993 for (i = 0; i < core_num_wrps; ++i) {
994 write_wb_reg(ARM_BASE_WCR + i, 0UL);
995 write_wb_reg(ARM_BASE_WVR + i, 0UL);
996 }
997
998 if (cpumask_intersects(&debug_err_mask, cpumask_of(cpu))) {
999 pr_warn_once("CPU %d failed to clear debug register pairs\n", cpu);
1000 return;
1001 }
1002
1003
1004
1005
1006
1007out_mdbgen:
1008 if (enable_monitor_mode())
1009 cpumask_or(&debug_err_mask, &debug_err_mask, cpumask_of(cpu));
1010}
1011
1012static int dbg_reset_online(unsigned int cpu)
1013{
1014 local_irq_disable();
1015 reset_ctrl_regs(cpu);
1016 local_irq_enable();
1017 return 0;
1018}
1019
1020#ifdef CONFIG_CPU_PM
1021static int dbg_cpu_pm_notify(struct notifier_block *self, unsigned long action,
1022 void *v)
1023{
1024 if (action == CPU_PM_EXIT)
1025 reset_ctrl_regs(smp_processor_id());
1026
1027 return NOTIFY_OK;
1028}
1029
1030static struct notifier_block dbg_cpu_pm_nb = {
1031 .notifier_call = dbg_cpu_pm_notify,
1032};
1033
1034static void __init pm_init(void)
1035{
1036 cpu_pm_register_notifier(&dbg_cpu_pm_nb);
1037}
1038#else
1039static inline void pm_init(void)
1040{
1041}
1042#endif
1043
1044static int __init arch_hw_breakpoint_init(void)
1045{
1046 int ret;
1047
1048 debug_arch = get_debug_arch();
1049
1050 if (!debug_arch_supported()) {
1051 pr_info("debug architecture 0x%x unsupported.\n", debug_arch);
1052 return 0;
1053 }
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064
1065
1066 if (read_cpuid_part() == ARM_CPU_PART_SCORPION) {
1067 pr_info("Scorpion CPU detected. Hardware breakpoints and watchpoints disabled\n");
1068 return 0;
1069 }
1070
1071 has_ossr = core_has_os_save_restore();
1072
1073
1074 core_num_brps = get_num_brps();
1075 core_num_wrps = get_num_wrps();
1076
1077
1078
1079
1080
1081
1082 cpus_read_lock();
1083 register_undef_hook(&debug_reg_hook);
1084
1085
1086
1087
1088
1089
1090 ret = cpuhp_setup_state_cpuslocked(CPUHP_AP_ONLINE_DYN,
1091 "arm/hw_breakpoint:online",
1092 dbg_reset_online, NULL);
1093 unregister_undef_hook(&debug_reg_hook);
1094 if (WARN_ON(ret < 0) || !cpumask_empty(&debug_err_mask)) {
1095 core_num_brps = 0;
1096 core_num_wrps = 0;
1097 if (ret > 0)
1098 cpuhp_remove_state_nocalls_cpuslocked(ret);
1099 cpus_read_unlock();
1100 return 0;
1101 }
1102
1103 pr_info("found %d " "%s" "breakpoint and %d watchpoint registers.\n",
1104 core_num_brps, core_has_mismatch_brps() ? "(+1 reserved) " :
1105 "", core_num_wrps);
1106
1107
1108 max_watchpoint_len = get_max_wp_len();
1109 pr_info("maximum watchpoint size is %u bytes.\n",
1110 max_watchpoint_len);
1111
1112
1113 hook_fault_code(FAULT_CODE_DEBUG, hw_breakpoint_pending, SIGTRAP,
1114 TRAP_HWBKPT, "watchpoint debug exception");
1115 hook_ifault_code(FAULT_CODE_DEBUG, hw_breakpoint_pending, SIGTRAP,
1116 TRAP_HWBKPT, "breakpoint debug exception");
1117 cpus_read_unlock();
1118
1119
1120 pm_init();
1121 return 0;
1122}
1123arch_initcall(arch_hw_breakpoint_init);
1124
1125void hw_breakpoint_pmu_read(struct perf_event *bp)
1126{
1127}
1128
1129
1130
1131
1132int hw_breakpoint_exceptions_notify(struct notifier_block *unused,
1133 unsigned long val, void *data)
1134{
1135 return NOTIFY_DONE;
1136}
1137