1
2
3
4
5
6#include <linux/delay.h>
7#include <linux/dma-mapping.h>
8#include <linux/types.h>
9#include <linux/init.h>
10#include <linux/clk.h>
11#include <linux/irq.h>
12#include <linux/gpio.h>
13#include <linux/platform_device.h>
14#include <linux/mfd/mc13783.h>
15#include <linux/spi/spi.h>
16#include <linux/spi/l4f00242t03.h>
17#include <linux/regulator/machine.h>
18#include <linux/usb/otg.h>
19#include <linux/usb/ulpi.h>
20
21#include <asm/mach-types.h>
22#include <asm/mach/arch.h>
23#include <asm/mach/time.h>
24#include <asm/memory.h>
25#include <asm/mach/map.h>
26
27#include "3ds_debugboard.h"
28#include "common.h"
29#include "devices-imx31.h"
30#include "ehci.h"
31#include "hardware.h"
32#include "iomux-mx3.h"
33#include "ulpi.h"
34
35static int mx31_3ds_pins[] = {
36
37 MX31_PIN_CTS1__CTS1,
38 MX31_PIN_RTS1__RTS1,
39 MX31_PIN_TXD1__TXD1,
40 MX31_PIN_RXD1__RXD1,
41 IOMUX_MODE(MX31_PIN_GPIO1_1, IOMUX_CONFIG_GPIO),
42
43 IOMUX_MODE(MX31_PIN_DSR_DCE1, IOMUX_CONFIG_ALT1),
44 IOMUX_MODE(MX31_PIN_RI_DCE1, IOMUX_CONFIG_ALT1),
45
46 MX31_PIN_CSPI2_SCLK__SCLK,
47 MX31_PIN_CSPI2_MOSI__MOSI,
48 MX31_PIN_CSPI2_MISO__MISO,
49 MX31_PIN_CSPI2_SPI_RDY__SPI_RDY,
50 MX31_PIN_CSPI2_SS0__SS0,
51 MX31_PIN_CSPI2_SS2__SS2,
52
53 IOMUX_MODE(MX31_PIN_GPIO1_3, IOMUX_CONFIG_GPIO),
54
55 IOMUX_MODE(MX31_PIN_USB_PWR, IOMUX_CONFIG_GPIO),
56
57 MX31_PIN_USBOTG_DATA0__USBOTG_DATA0,
58 MX31_PIN_USBOTG_DATA1__USBOTG_DATA1,
59 MX31_PIN_USBOTG_DATA2__USBOTG_DATA2,
60 MX31_PIN_USBOTG_DATA3__USBOTG_DATA3,
61 MX31_PIN_USBOTG_DATA4__USBOTG_DATA4,
62 MX31_PIN_USBOTG_DATA5__USBOTG_DATA5,
63 MX31_PIN_USBOTG_DATA6__USBOTG_DATA6,
64 MX31_PIN_USBOTG_DATA7__USBOTG_DATA7,
65 MX31_PIN_USBOTG_CLK__USBOTG_CLK,
66 MX31_PIN_USBOTG_DIR__USBOTG_DIR,
67 MX31_PIN_USBOTG_NXT__USBOTG_NXT,
68 MX31_PIN_USBOTG_STP__USBOTG_STP,
69
70 MX31_PIN_KEY_ROW0_KEY_ROW0,
71 MX31_PIN_KEY_ROW1_KEY_ROW1,
72 MX31_PIN_KEY_ROW2_KEY_ROW2,
73 MX31_PIN_KEY_COL0_KEY_COL0,
74 MX31_PIN_KEY_COL1_KEY_COL1,
75 MX31_PIN_KEY_COL2_KEY_COL2,
76 MX31_PIN_KEY_COL3_KEY_COL3,
77
78 IOMUX_MODE(MX31_PIN_USBH2_CLK, IOMUX_CONFIG_FUNC),
79 IOMUX_MODE(MX31_PIN_USBH2_DIR, IOMUX_CONFIG_FUNC),
80 IOMUX_MODE(MX31_PIN_USBH2_NXT, IOMUX_CONFIG_FUNC),
81 IOMUX_MODE(MX31_PIN_USBH2_STP, IOMUX_CONFIG_FUNC),
82 IOMUX_MODE(MX31_PIN_USBH2_DATA0, IOMUX_CONFIG_FUNC),
83 IOMUX_MODE(MX31_PIN_USBH2_DATA1, IOMUX_CONFIG_FUNC),
84 IOMUX_MODE(MX31_PIN_PC_VS2, IOMUX_CONFIG_ALT1),
85 IOMUX_MODE(MX31_PIN_PC_BVD1, IOMUX_CONFIG_ALT1),
86 IOMUX_MODE(MX31_PIN_PC_BVD2, IOMUX_CONFIG_ALT1),
87 IOMUX_MODE(MX31_PIN_PC_RST, IOMUX_CONFIG_ALT1),
88 IOMUX_MODE(MX31_PIN_IOIS16, IOMUX_CONFIG_ALT1),
89 IOMUX_MODE(MX31_PIN_PC_RW_B, IOMUX_CONFIG_ALT1),
90
91 IOMUX_MODE(MX31_PIN_USB_BYP, IOMUX_CONFIG_GPIO),
92
93 MX31_PIN_I2C_CLK__I2C1_SCL,
94 MX31_PIN_I2C_DAT__I2C1_SDA,
95
96 MX31_PIN_SD1_DATA3__SD1_DATA3,
97 MX31_PIN_SD1_DATA2__SD1_DATA2,
98 MX31_PIN_SD1_DATA1__SD1_DATA1,
99 MX31_PIN_SD1_DATA0__SD1_DATA0,
100 MX31_PIN_SD1_CLK__SD1_CLK,
101 MX31_PIN_SD1_CMD__SD1_CMD,
102 MX31_PIN_GPIO3_1__GPIO3_1,
103 MX31_PIN_GPIO3_0__GPIO3_0,
104
105 MX31_PIN_LD0__LD0,
106 MX31_PIN_LD1__LD1,
107 MX31_PIN_LD2__LD2,
108 MX31_PIN_LD3__LD3,
109 MX31_PIN_LD4__LD4,
110 MX31_PIN_LD5__LD5,
111 MX31_PIN_LD6__LD6,
112 MX31_PIN_LD7__LD7,
113 MX31_PIN_LD8__LD8,
114 MX31_PIN_LD9__LD9,
115 MX31_PIN_LD10__LD10,
116 MX31_PIN_LD11__LD11,
117 MX31_PIN_LD12__LD12,
118 MX31_PIN_LD13__LD13,
119 MX31_PIN_LD14__LD14,
120 MX31_PIN_LD15__LD15,
121 MX31_PIN_LD16__LD16,
122 MX31_PIN_LD17__LD17,
123 MX31_PIN_VSYNC3__VSYNC3,
124 MX31_PIN_HSYNC__HSYNC,
125 MX31_PIN_FPSHIFT__FPSHIFT,
126 MX31_PIN_CONTRAST__CONTRAST,
127
128 MX31_PIN_STXD4__STXD4,
129 MX31_PIN_SRXD4__SRXD4,
130 MX31_PIN_SCK4__SCK4,
131 MX31_PIN_SFS4__SFS4,
132};
133
134
135
136
137static const struct fb_videomode fb_modedb[] = {
138 {
139 .name = "Epson-VGA",
140 .refresh = 60,
141 .xres = 480,
142 .yres = 640,
143 .pixclock = 41701,
144 .left_margin = 20,
145 .right_margin = 41,
146 .upper_margin = 10,
147 .lower_margin = 5,
148 .hsync_len = 20,
149 .vsync_len = 10,
150 .sync = FB_SYNC_OE_ACT_HIGH | FB_SYNC_CLK_INVERT,
151 .vmode = FB_VMODE_NONINTERLACED,
152 .flag = 0,
153 },
154};
155
156static struct mx3fb_platform_data mx3fb_pdata __initdata = {
157 .name = "Epson-VGA",
158 .mode = fb_modedb,
159 .num_modes = ARRAY_SIZE(fb_modedb),
160};
161
162
163static struct l4f00242t03_pdata mx31_3ds_l4f00242t03_pdata = {
164 .reset_gpio = IOMUX_TO_GPIO(MX31_PIN_LCS1),
165 .data_enable_gpio = IOMUX_TO_GPIO(MX31_PIN_SER_RS),
166};
167
168
169
170
171#define MX31_3DS_GPIO_SDHC1_CD IOMUX_TO_GPIO(MX31_PIN_GPIO3_1)
172#define MX31_3DS_GPIO_SDHC1_BE IOMUX_TO_GPIO(MX31_PIN_GPIO3_0)
173
174static struct gpio mx31_3ds_sdhc1_gpios[] = {
175 { MX31_3DS_GPIO_SDHC1_CD, GPIOF_IN, "sdhc1-card-detect" },
176 { MX31_3DS_GPIO_SDHC1_BE, GPIOF_OUT_INIT_LOW, "sdhc1-bus-en" },
177};
178
179static int mx31_3ds_sdhc1_init(struct device *dev,
180 irq_handler_t detect_irq,
181 void *data)
182{
183 int ret;
184
185 ret = gpio_request_array(mx31_3ds_sdhc1_gpios,
186 ARRAY_SIZE(mx31_3ds_sdhc1_gpios));
187 if (ret) {
188 pr_warn("Unable to request the SD/MMC GPIOs.\n");
189 return ret;
190 }
191
192 ret = request_irq(gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO3_1)),
193 detect_irq,
194 IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING,
195 "sdhc1-detect", data);
196 if (ret) {
197 pr_warn("Unable to request the SD/MMC card-detect IRQ.\n");
198 goto gpio_free;
199 }
200
201 return 0;
202
203gpio_free:
204 gpio_free_array(mx31_3ds_sdhc1_gpios,
205 ARRAY_SIZE(mx31_3ds_sdhc1_gpios));
206 return ret;
207}
208
209static void mx31_3ds_sdhc1_exit(struct device *dev, void *data)
210{
211 free_irq(gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO3_1)), data);
212 gpio_free_array(mx31_3ds_sdhc1_gpios,
213 ARRAY_SIZE(mx31_3ds_sdhc1_gpios));
214}
215
216static void mx31_3ds_sdhc1_setpower(struct device *dev, unsigned int vdd)
217{
218
219
220
221
222
223
224
225
226 if (vdd > 7)
227 gpio_set_value(MX31_3DS_GPIO_SDHC1_BE, 1);
228 else
229 gpio_set_value(MX31_3DS_GPIO_SDHC1_BE, 0);
230}
231
232static struct imxmmc_platform_data sdhc1_pdata = {
233 .init = mx31_3ds_sdhc1_init,
234 .exit = mx31_3ds_sdhc1_exit,
235 .setpower = mx31_3ds_sdhc1_setpower,
236};
237
238
239
240
241
242static const uint32_t mx31_3ds_keymap[] = {
243 KEY(0, 0, KEY_UP),
244 KEY(0, 1, KEY_DOWN),
245 KEY(1, 0, KEY_RIGHT),
246 KEY(1, 1, KEY_LEFT),
247 KEY(1, 2, KEY_ENTER),
248 KEY(2, 0, KEY_F6),
249 KEY(2, 1, KEY_F8),
250 KEY(2, 2, KEY_F9),
251 KEY(2, 3, KEY_F10),
252};
253
254static const struct matrix_keymap_data mx31_3ds_keymap_data __initconst = {
255 .keymap = mx31_3ds_keymap,
256 .keymap_size = ARRAY_SIZE(mx31_3ds_keymap),
257};
258
259
260static struct regulator_init_data pwgtx_init = {
261 .constraints = {
262 .boot_on = 1,
263 .always_on = 1,
264 },
265};
266
267static struct regulator_init_data gpo_init = {
268 .constraints = {
269 .boot_on = 1,
270 .always_on = 1,
271 }
272};
273
274static struct regulator_consumer_supply vmmc2_consumers[] = {
275 REGULATOR_SUPPLY("vmmc", "imx31-mmc.0"),
276};
277
278static struct regulator_init_data vmmc2_init = {
279 .constraints = {
280 .min_uV = 3000000,
281 .max_uV = 3000000,
282 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
283 REGULATOR_CHANGE_STATUS,
284 },
285 .num_consumer_supplies = ARRAY_SIZE(vmmc2_consumers),
286 .consumer_supplies = vmmc2_consumers,
287};
288
289static struct regulator_consumer_supply vmmc1_consumers[] = {
290 REGULATOR_SUPPLY("vcore", "spi0.0"),
291};
292
293static struct regulator_init_data vmmc1_init = {
294 .constraints = {
295 .min_uV = 2800000,
296 .max_uV = 2800000,
297 .apply_uV = 1,
298 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
299 REGULATOR_CHANGE_STATUS,
300 },
301 .num_consumer_supplies = ARRAY_SIZE(vmmc1_consumers),
302 .consumer_supplies = vmmc1_consumers,
303};
304
305static struct regulator_consumer_supply vgen_consumers[] = {
306 REGULATOR_SUPPLY("vdd", "spi0.0"),
307};
308
309static struct regulator_init_data vgen_init = {
310 .constraints = {
311 .min_uV = 1800000,
312 .max_uV = 1800000,
313 .apply_uV = 1,
314 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
315 REGULATOR_CHANGE_STATUS,
316 },
317 .num_consumer_supplies = ARRAY_SIZE(vgen_consumers),
318 .consumer_supplies = vgen_consumers,
319};
320
321static struct mc13xxx_regulator_init_data mx31_3ds_regulators[] = {
322 {
323 .id = MC13783_REG_PWGT1SPI,
324 .init_data = &pwgtx_init,
325 }, {
326 .id = MC13783_REG_PWGT2SPI,
327 .init_data = &pwgtx_init,
328 }, {
329
330 .id = MC13783_REG_GPO1,
331 .init_data = &gpo_init,
332 }, {
333 .id = MC13783_REG_GPO3,
334 .init_data = &gpo_init,
335 }, {
336 .id = MC13783_REG_VMMC2,
337 .init_data = &vmmc2_init,
338 }, {
339 .id = MC13783_REG_VMMC1,
340 .init_data = &vmmc1_init,
341 }, {
342 .id = MC13783_REG_VGEN,
343 .init_data = &vgen_init,
344 },
345};
346
347
348static struct mc13xxx_codec_platform_data mx31_3ds_codec = {
349 .dac_ssi_port = MC13783_SSI1_PORT,
350 .adc_ssi_port = MC13783_SSI1_PORT,
351};
352
353static struct mc13xxx_platform_data mc13783_pdata = {
354 .regulators = {
355 .regulators = mx31_3ds_regulators,
356 .num_regulators = ARRAY_SIZE(mx31_3ds_regulators),
357 },
358 .codec = &mx31_3ds_codec,
359 .flags = MC13XXX_USE_TOUCHSCREEN | MC13XXX_USE_RTC | MC13XXX_USE_CODEC,
360
361};
362
363static struct imx_ssi_platform_data mx31_3ds_ssi_pdata = {
364 .flags = IMX_SSI_DMA | IMX_SSI_NET,
365};
366
367
368static const struct spi_imx_master spi0_pdata __initconst = {
369 .num_chipselect = 3,
370};
371
372static const struct spi_imx_master spi1_pdata __initconst = {
373 .num_chipselect = 3,
374};
375
376static struct spi_board_info mx31_3ds_spi_devs[] __initdata = {
377 {
378 .modalias = "mc13783",
379 .max_speed_hz = 1000000,
380 .bus_num = 1,
381 .chip_select = 2,
382 .platform_data = &mc13783_pdata,
383
384 .mode = SPI_CS_HIGH,
385 }, {
386 .modalias = "l4f00242t03",
387 .max_speed_hz = 5000000,
388 .bus_num = 0,
389 .chip_select = 2,
390 .platform_data = &mx31_3ds_l4f00242t03_pdata,
391 },
392};
393
394
395
396
397static const struct mxc_nand_platform_data
398mx31_3ds_nand_board_info __initconst = {
399 .width = 1,
400 .hw_ecc = 1,
401#ifdef CONFIG_MACH_MX31_3DS_MXC_NAND_USE_BBT
402 .flash_bbt = 1,
403#endif
404};
405
406
407
408
409
410#define USB_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \
411 PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU)
412
413#define USBOTG_RST_B IOMUX_TO_GPIO(MX31_PIN_USB_PWR)
414#define USBH2_RST_B IOMUX_TO_GPIO(MX31_PIN_USB_BYP)
415
416static int mx31_3ds_usbotg_init(void)
417{
418 int err;
419
420 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA0, USB_PAD_CFG);
421 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA1, USB_PAD_CFG);
422 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA2, USB_PAD_CFG);
423 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA3, USB_PAD_CFG);
424 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA4, USB_PAD_CFG);
425 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA5, USB_PAD_CFG);
426 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA6, USB_PAD_CFG);
427 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA7, USB_PAD_CFG);
428 mxc_iomux_set_pad(MX31_PIN_USBOTG_CLK, USB_PAD_CFG);
429 mxc_iomux_set_pad(MX31_PIN_USBOTG_DIR, USB_PAD_CFG);
430 mxc_iomux_set_pad(MX31_PIN_USBOTG_NXT, USB_PAD_CFG);
431 mxc_iomux_set_pad(MX31_PIN_USBOTG_STP, USB_PAD_CFG);
432
433 err = gpio_request(USBOTG_RST_B, "otgusb-reset");
434 if (err) {
435 pr_err("Failed to request the USB OTG reset gpio\n");
436 return err;
437 }
438
439 err = gpio_direction_output(USBOTG_RST_B, 0);
440 if (err) {
441 pr_err("Failed to drive the USB OTG reset gpio\n");
442 goto usbotg_free_reset;
443 }
444
445 mdelay(1);
446 gpio_set_value(USBOTG_RST_B, 1);
447 return 0;
448
449usbotg_free_reset:
450 gpio_free(USBOTG_RST_B);
451 return err;
452}
453
454static int mx31_3ds_otg_init(struct platform_device *pdev)
455{
456 return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED);
457}
458
459static int mx31_3ds_host2_init(struct platform_device *pdev)
460{
461 int err;
462
463 mxc_iomux_set_pad(MX31_PIN_USBH2_CLK, USB_PAD_CFG);
464 mxc_iomux_set_pad(MX31_PIN_USBH2_DIR, USB_PAD_CFG);
465 mxc_iomux_set_pad(MX31_PIN_USBH2_NXT, USB_PAD_CFG);
466 mxc_iomux_set_pad(MX31_PIN_USBH2_STP, USB_PAD_CFG);
467 mxc_iomux_set_pad(MX31_PIN_USBH2_DATA0, USB_PAD_CFG);
468 mxc_iomux_set_pad(MX31_PIN_USBH2_DATA1, USB_PAD_CFG);
469 mxc_iomux_set_pad(MX31_PIN_PC_VS2, USB_PAD_CFG);
470 mxc_iomux_set_pad(MX31_PIN_PC_BVD1, USB_PAD_CFG);
471 mxc_iomux_set_pad(MX31_PIN_PC_BVD2, USB_PAD_CFG);
472 mxc_iomux_set_pad(MX31_PIN_PC_RST, USB_PAD_CFG);
473 mxc_iomux_set_pad(MX31_PIN_IOIS16, USB_PAD_CFG);
474 mxc_iomux_set_pad(MX31_PIN_PC_RW_B, USB_PAD_CFG);
475
476 err = gpio_request(USBH2_RST_B, "usbh2-reset");
477 if (err) {
478 pr_err("Failed to request the USB Host 2 reset gpio\n");
479 return err;
480 }
481
482 err = gpio_direction_output(USBH2_RST_B, 0);
483 if (err) {
484 pr_err("Failed to drive the USB Host 2 reset gpio\n");
485 goto usbotg_free_reset;
486 }
487
488 mdelay(1);
489 gpio_set_value(USBH2_RST_B, 1);
490
491 mdelay(10);
492
493 return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED);
494
495usbotg_free_reset:
496 gpio_free(USBH2_RST_B);
497 return err;
498}
499
500static struct mxc_usbh_platform_data otg_pdata __initdata = {
501 .init = mx31_3ds_otg_init,
502 .portsc = MXC_EHCI_MODE_ULPI,
503};
504
505static struct mxc_usbh_platform_data usbh2_pdata __initdata = {
506 .init = mx31_3ds_host2_init,
507 .portsc = MXC_EHCI_MODE_ULPI,
508};
509
510static const struct fsl_usb2_platform_data usbotg_pdata __initconst = {
511 .operating_mode = FSL_USB2_DR_DEVICE,
512 .phy_mode = FSL_USB2_PHY_ULPI,
513};
514
515static bool otg_mode_host __initdata;
516
517static int __init mx31_3ds_otg_mode(char *options)
518{
519 if (!strcmp(options, "host"))
520 otg_mode_host = true;
521 else if (!strcmp(options, "device"))
522 otg_mode_host = false;
523 else
524 pr_info("otg_mode neither \"host\" nor \"device\". "
525 "Defaulting to device\n");
526 return 1;
527}
528__setup("otg_mode=", mx31_3ds_otg_mode);
529
530static const struct imxuart_platform_data uart_pdata __initconst = {
531 .flags = IMXUART_HAVE_RTSCTS,
532};
533
534static const struct imxi2c_platform_data mx31_3ds_i2c0_data __initconst = {
535 .bitrate = 100000,
536};
537
538static void __init mx31_3ds_init(void)
539{
540 imx31_soc_init();
541
542
543 mxc_iomux_set_gpr(MUX_PGP_CSPI_BB, true);
544
545 mxc_iomux_setup_multiple_pins(mx31_3ds_pins, ARRAY_SIZE(mx31_3ds_pins),
546 "mx31_3ds");
547
548 imx31_add_imx_uart0(&uart_pdata);
549 imx31_add_mxc_nand(&mx31_3ds_nand_board_info);
550
551 imx31_add_spi_imx1(&spi1_pdata);
552
553 imx31_add_imx_keypad(&mx31_3ds_keymap_data);
554
555 imx31_add_imx2_wdt();
556 imx31_add_imx_i2c0(&mx31_3ds_i2c0_data);
557
558 imx31_add_spi_imx0(&spi0_pdata);
559 imx31_add_ipu_core();
560 imx31_add_mx3_sdc_fb(&mx3fb_pdata);
561
562 imx31_add_imx_ssi(0, &mx31_3ds_ssi_pdata);
563
564 imx_add_platform_device("imx_mc13783", 0, NULL, 0, NULL, 0);
565}
566
567static void __init mx31_3ds_late(void)
568{
569 mx31_3ds_spi_devs[0].irq = gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_3));
570 spi_register_board_info(mx31_3ds_spi_devs,
571 ARRAY_SIZE(mx31_3ds_spi_devs));
572
573 mx31_3ds_usbotg_init();
574 if (otg_mode_host) {
575 otg_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
576 ULPI_OTG_DRVVBUS_EXT);
577 if (otg_pdata.otg)
578 imx31_add_mxc_ehci_otg(&otg_pdata);
579 }
580 usbh2_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
581 ULPI_OTG_DRVVBUS_EXT);
582 if (usbh2_pdata.otg)
583 imx31_add_mxc_ehci_hs(2, &usbh2_pdata);
584
585 if (!otg_mode_host)
586 imx31_add_fsl_usb2_udc(&usbotg_pdata);
587
588 if (mxc_expio_init(MX31_CS5_BASE_ADDR, IOMUX_TO_GPIO(MX31_PIN_GPIO1_1)))
589 printk(KERN_WARNING "Init of the debug board failed, all "
590 "devices on the debug board are unusable.\n");
591
592 imx31_add_mxc_mmc(0, &sdhc1_pdata);
593}
594
595static void __init mx31_3ds_timer_init(void)
596{
597 mx31_clocks_init(26000000);
598}
599
600MACHINE_START(MX31_3DS, "Freescale MX31PDK (3DS)")
601
602 .atag_offset = 0x100,
603 .map_io = mx31_map_io,
604 .init_early = imx31_init_early,
605 .init_irq = mx31_init_irq,
606 .init_time = mx31_3ds_timer_init,
607 .init_machine = mx31_3ds_init,
608 .init_late = mx31_3ds_late,
609 .restart = mxc_restart,
610MACHINE_END
611
