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14#include <linux/kernel.h>
15#include <linux/types.h>
16#include <linux/init.h>
17#include <linux/gpio.h>
18#include <linux/platform_device.h>
19
20#include <asm/mach-types.h>
21#include <asm/mach/arch.h>
22#include <asm/mach/map.h>
23
24#include "board-mx31lilly.h"
25#include "common.h"
26#include "devices-imx31.h"
27#include "hardware.h"
28#include "iomux-mx3.h"
29
30
31
32
33
34
35
36static unsigned int lilly_db_board_pins[] __initdata = {
37 MX31_PIN_SD1_DATA3__SD1_DATA3,
38 MX31_PIN_SD1_DATA2__SD1_DATA2,
39 MX31_PIN_SD1_DATA1__SD1_DATA1,
40 MX31_PIN_SD1_DATA0__SD1_DATA0,
41 MX31_PIN_SD1_CLK__SD1_CLK,
42 MX31_PIN_SD1_CMD__SD1_CMD,
43 MX31_PIN_LD0__LD0,
44 MX31_PIN_LD1__LD1,
45 MX31_PIN_LD2__LD2,
46 MX31_PIN_LD3__LD3,
47 MX31_PIN_LD4__LD4,
48 MX31_PIN_LD5__LD5,
49 MX31_PIN_LD6__LD6,
50 MX31_PIN_LD7__LD7,
51 MX31_PIN_LD8__LD8,
52 MX31_PIN_LD9__LD9,
53 MX31_PIN_LD10__LD10,
54 MX31_PIN_LD11__LD11,
55 MX31_PIN_LD12__LD12,
56 MX31_PIN_LD13__LD13,
57 MX31_PIN_LD14__LD14,
58 MX31_PIN_LD15__LD15,
59 MX31_PIN_LD16__LD16,
60 MX31_PIN_LD17__LD17,
61 MX31_PIN_VSYNC3__VSYNC3,
62 MX31_PIN_HSYNC__HSYNC,
63 MX31_PIN_FPSHIFT__FPSHIFT,
64 MX31_PIN_DRDY0__DRDY0,
65 MX31_PIN_CONTRAST__CONTRAST,
66};
67
68
69
70static int mxc_mmc1_get_ro(struct device *dev)
71{
72 return gpio_get_value(IOMUX_TO_GPIO(MX31_PIN_LCS0));
73}
74
75static int gpio_det, gpio_wp;
76
77#define MMC_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \
78 PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU)
79
80static int mxc_mmc1_init(struct device *dev,
81 irq_handler_t detect_irq, void *data)
82{
83 int ret;
84
85 gpio_det = IOMUX_TO_GPIO(MX31_PIN_GPIO1_1);
86 gpio_wp = IOMUX_TO_GPIO(MX31_PIN_LCS0);
87
88 mxc_iomux_set_pad(MX31_PIN_SD1_DATA0, MMC_PAD_CFG);
89 mxc_iomux_set_pad(MX31_PIN_SD1_DATA1, MMC_PAD_CFG);
90 mxc_iomux_set_pad(MX31_PIN_SD1_DATA2, MMC_PAD_CFG);
91 mxc_iomux_set_pad(MX31_PIN_SD1_DATA3, MMC_PAD_CFG);
92 mxc_iomux_set_pad(MX31_PIN_SD1_CLK, MMC_PAD_CFG);
93 mxc_iomux_set_pad(MX31_PIN_SD1_CMD, MMC_PAD_CFG);
94
95 ret = gpio_request(gpio_det, "MMC detect");
96 if (ret)
97 return ret;
98
99 ret = gpio_request(gpio_wp, "MMC w/p");
100 if (ret)
101 goto exit_free_det;
102
103 gpio_direction_input(gpio_det);
104 gpio_direction_input(gpio_wp);
105
106 ret = request_irq(gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_1)),
107 detect_irq, IRQF_TRIGGER_FALLING,
108 "MMC detect", data);
109 if (ret)
110 goto exit_free_wp;
111
112 return 0;
113
114exit_free_wp:
115 gpio_free(gpio_wp);
116
117exit_free_det:
118 gpio_free(gpio_det);
119
120 return ret;
121}
122
123static void mxc_mmc1_exit(struct device *dev, void *data)
124{
125 gpio_free(gpio_det);
126 gpio_free(gpio_wp);
127 free_irq(gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_1)), data);
128}
129
130static const struct imxmmc_platform_data mmc_pdata __initconst = {
131 .get_ro = mxc_mmc1_get_ro,
132 .init = mxc_mmc1_init,
133 .exit = mxc_mmc1_exit,
134};
135
136
137static const struct fb_videomode fb_modedb = {
138
139 .name = "CRT-VGA",
140 .refresh = 64,
141 .xres = 640,
142 .yres = 480,
143 .pixclock = 30000,
144 .left_margin = 200,
145 .right_margin = 2,
146 .upper_margin = 2,
147 .lower_margin = 2,
148 .hsync_len = 3,
149 .vsync_len = 1,
150 .sync = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_OE_ACT_HIGH,
151 .vmode = FB_VMODE_NONINTERLACED,
152 .flag = 0,
153};
154
155static struct mx3fb_platform_data fb_pdata __initdata = {
156 .name = "CRT-VGA",
157 .mode = &fb_modedb,
158 .num_modes = 1,
159};
160
161#define LCD_VCC_EN_GPIO (7)
162
163static void __init mx31lilly_init_fb(void)
164{
165 if (gpio_request(LCD_VCC_EN_GPIO, "LCD enable") != 0) {
166 printk(KERN_WARNING "unable to request LCD_VCC_EN pin.\n");
167 return;
168 }
169
170 imx31_add_ipu_core();
171 imx31_add_mx3_sdc_fb(&fb_pdata);
172 gpio_direction_output(LCD_VCC_EN_GPIO, 1);
173}
174
175void __init mx31lilly_db_init(void)
176{
177 mxc_iomux_setup_multiple_pins(lilly_db_board_pins,
178 ARRAY_SIZE(lilly_db_board_pins),
179 "development board pins");
180 imx31_add_mxc_mmc(0, &mmc_pdata);
181 mx31lilly_init_fb();
182}
183
