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6#include <linux/linkage.h>
7#include <asm/assembler.h>
8#include <asm/asm-offsets.h>
9#include <asm/hardware/cache-l2x0.h>
10#include "hardware.h"
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40#define PM_INFO_PBASE_OFFSET 0x0
41#define PM_INFO_RESUME_ADDR_OFFSET 0x4
42#define PM_INFO_DDR_TYPE_OFFSET 0x8
43#define PM_INFO_PM_INFO_SIZE_OFFSET 0xC
44#define PM_INFO_MX6Q_MMDC_P_OFFSET 0x10
45#define PM_INFO_MX6Q_MMDC_V_OFFSET 0x14
46#define PM_INFO_MX6Q_SRC_P_OFFSET 0x18
47#define PM_INFO_MX6Q_SRC_V_OFFSET 0x1C
48#define PM_INFO_MX6Q_IOMUXC_P_OFFSET 0x20
49#define PM_INFO_MX6Q_IOMUXC_V_OFFSET 0x24
50#define PM_INFO_MX6Q_CCM_P_OFFSET 0x28
51#define PM_INFO_MX6Q_CCM_V_OFFSET 0x2C
52#define PM_INFO_MX6Q_GPC_P_OFFSET 0x30
53#define PM_INFO_MX6Q_GPC_V_OFFSET 0x34
54#define PM_INFO_MX6Q_L2_P_OFFSET 0x38
55#define PM_INFO_MX6Q_L2_V_OFFSET 0x3C
56#define PM_INFO_MMDC_IO_NUM_OFFSET 0x40
57#define PM_INFO_MMDC_IO_VAL_OFFSET 0x44
58
59#define MX6Q_SRC_GPR1 0x20
60#define MX6Q_SRC_GPR2 0x24
61#define MX6Q_MMDC_MAPSR 0x404
62#define MX6Q_MMDC_MPDGCTRL0 0x83c
63#define MX6Q_GPC_IMR1 0x08
64#define MX6Q_GPC_IMR2 0x0c
65#define MX6Q_GPC_IMR3 0x10
66#define MX6Q_GPC_IMR4 0x14
67#define MX6Q_CCM_CCR 0x0
68
69 .align 3
70
71 .macro sync_l2_cache
72
73
74#ifdef CONFIG_CACHE_L2X0
75 ldr r11, [r0,
76 teq r11,
77 beq 6f
78 mov r6,
79 str r6, [r11,
801:
81 ldr r6, [r11,
82 ands r6, r6,
83 bne 1b
846:
85#endif
86
87 .endm
88
89 .macro resume_mmdc
90
91
92 cmp r5,
93 ldreq r11, [r0,
94 ldrne r11, [r0,
95
96 ldr r6, [r0,
97 ldr r7, =PM_INFO_MMDC_IO_VAL_OFFSET
98 add r7, r7, r0
991:
100 ldr r8, [r7],
101 ldr r9, [r7],
102 str r9, [r11, r8]
103 subs r6, r6,
104 bne 1b
105
106 cmp r5,
107 ldreq r11, [r0,
108 ldrne r11, [r0,
109
110 cmp r3,
111 bne 4f
112
113
114 ldr r7, =MX6Q_MMDC_MPDGCTRL0
115 ldr r6, [r11, r7]
116 orr r6, r6,
117 str r6, [r11, r7]
1182:
119 ldr r6, [r11, r7]
120 ands r6, r6,
121 bne 2b
122
123
124 ldr r6, [r11, r7]
125 orr r6, r6,
126 str r6, [r11, r7]
1273:
128 ldr r6, [r11, r7]
129 ands r6, r6,
130 bne 3b
1314:
132
133 ldr r7, [r11,
134 bic r7, r7,
135 str r7, [r11,
1365:
137 ldr r7, [r11,
138 ands r7, r7,
139 bne 5b
140
141
142 ldr r7, [r11,
143 bic r7, r7,
144 str r7, [r11,
145
146 .endm
147
148ENTRY(imx6_suspend)
149 ldr r1, [r0,
150 ldr r2, [r0,
151 ldr r3, [r0,
152 ldr r4, [r0,
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157
158 ldr r6, =imx6_suspend
159 ldr r7, =resume
160 sub r7, r7, r6
161 add r8, r1, r4
162 add r9, r8, r7
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168
169 ldr r11, [r0,
170 ldr r6, [r11,
171 ldr r11, [r0,
172 ldr r6, [r11,
173 ldr r11, [r0,
174 ldr r6, [r11,
175
176
177 ldr r11, [r0,
178
179 str r9, [r11,
180 str r1, [r11,
181
182
183 sync_l2_cache
184
185 ldr r11, [r0,
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189
190 ldr r7, [r11,
191 orr r7, r7,
192 str r7, [r11,
193
194
195 ldr r7, [r11,
196 orr r7, r7,
197 str r7, [r11,
198
199poll_dvfs_set:
200 ldr r7, [r11,
201 ands r7, r7,
202 beq poll_dvfs_set
203
204 ldr r11, [r0,
205 ldr r6, =0x0
206 ldr r7, [r0,
207 ldr r8, =PM_INFO_MMDC_IO_VAL_OFFSET
208 add r8, r8, r0
209
210 cmp r3,
211 subeq r7, r7,
212set_mmdc_io_lpm:
213 ldr r9, [r8],
214 str r6, [r11, r9]
215 subs r7, r7,
216 bne set_mmdc_io_lpm
217
218 cmp r3,
219 bne set_mmdc_io_lpm_done
220 ldr r6, =0x1000
221 ldr r9, [r8],
222 str r6, [r11, r9]
223 ldr r9, [r8],
224 str r6, [r11, r9]
225 ldr r6, =0x80000
226 ldr r9, [r8]
227 str r6, [r11, r9]
228set_mmdc_io_lpm_done:
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237 ldr r11, [r0,
238 ldr r6, [r11,
239 ldr r7, [r11,
240 ldr r8, [r11,
241 ldr r9, [r11,
242
243 ldr r10, =0xffffffff
244 str r10, [r11,
245 str r10, [r11,
246 str r10, [r11,
247 str r10, [r11,
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255 ldr r11, [r0,
256 ldr r10, [r11,
257 bic r10, r10,
258 orr r10, r10,
259 str r10, [r11,
260
261
262 ldr r10, [r11,
263 orr r10, r10,
264 str r10, [r11,
265
266
267 ldr r11, [r0,
268 str r6, [r11,
269 str r7, [r11,
270 str r8, [r11,
271 str r9, [r11,
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282
283 ldr r6, =2000
284rbc_loop:
285 subs r6, r6,
286 bne rbc_loop
287
288
289 wfi
290 nop
291 nop
292 nop
293 nop
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300 mov r5,
301 resume_mmdc
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304 ret lr
305
306resume:
307
308 mov r6,
309 mcr p15, 0, r6, c7, c5, 0
310 mcr p15, 0, r6, c7, c5, 6
311
312 mov r6,
313 mcr p15, 0, r6, c1, c0, 0
314 isb
315
316
317 ldr lr, [r0,
318
319 ldr r11, [r0,
320 mov r7,
321 str r7, [r11,
322 str r7, [r11,
323
324 ldr r3, [r0,
325 mov r5,
326 resume_mmdc
327
328 ret lr
329ENDPROC(imx6_suspend)
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336
337ENTRY(v7_cpu_resume)
338 bl v7_invalidate_l1
339#ifdef CONFIG_CACHE_L2X0
340 bl l2c310_early_resume
341#endif
342 b cpu_resume
343ENDPROC(v7_cpu_resume)
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