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10#include <linux/kernel.h>
11#include <linux/init.h>
12#include <linux/io.h>
13#include <linux/irq.h>
14#include <linux/irqchip.h>
15#include <linux/platform_device.h>
16#include <linux/memblock.h>
17#include <linux/of_irq.h>
18#include <linux/of_platform.h>
19#include <linux/export.h>
20#include <linux/irqchip/arm-gic.h>
21#include <linux/of_address.h>
22#include <linux/reboot.h>
23#include <linux/genalloc.h>
24
25#include <asm/hardware/cache-l2x0.h>
26#include <asm/mach/map.h>
27#include <asm/memblock.h>
28#include <asm/smp_twd.h>
29
30#include "omap-wakeupgen.h"
31#include "soc.h"
32#include "iomap.h"
33#include "common.h"
34#include "prminst44xx.h"
35#include "prcm_mpu44xx.h"
36#include "omap4-sar-layout.h"
37#include "omap-secure.h"
38#include "sram.h"
39
40#ifdef CONFIG_CACHE_L2X0
41static void __iomem *l2cache_base;
42#endif
43
44static void __iomem *sar_ram_base;
45static void __iomem *gic_dist_base_addr;
46static void __iomem *twd_base;
47
48#define IRQ_LOCALTIMER 29
49
50#ifdef CONFIG_OMAP_INTERCONNECT_BARRIER
51
52
53#define OMAP4_DRAM_BARRIER_VA 0xfe600000
54
55static void __iomem *dram_sync, *sram_sync;
56static phys_addr_t dram_sync_paddr;
57static u32 dram_sync_size;
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81static void omap4_mb(void)
82{
83 if (dram_sync)
84 writel_relaxed(0, dram_sync);
85}
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116void omap_interconnect_sync(void)
117{
118 if (dram_sync && sram_sync) {
119 writel_relaxed(readl_relaxed(dram_sync), dram_sync);
120 writel_relaxed(readl_relaxed(sram_sync), sram_sync);
121 isb();
122 }
123}
124
125static int __init omap4_sram_init(void)
126{
127 struct device_node *np;
128 struct gen_pool *sram_pool;
129
130 np = of_find_compatible_node(NULL, NULL, "ti,omap4-mpu");
131 if (!np)
132 pr_warn("%s:Unable to allocate sram needed to handle errata I688\n",
133 __func__);
134 sram_pool = of_gen_pool_get(np, "sram", 0);
135 if (!sram_pool)
136 pr_warn("%s:Unable to get sram pool needed to handle errata I688\n",
137 __func__);
138 else
139 sram_sync = (void *)gen_pool_alloc(sram_pool, PAGE_SIZE);
140
141 return 0;
142}
143omap_arch_initcall(omap4_sram_init);
144
145
146void __init omap_barrier_reserve_memblock(void)
147{
148 dram_sync_size = ALIGN(PAGE_SIZE, SZ_1M);
149 dram_sync_paddr = arm_memblock_steal(dram_sync_size, SZ_1M);
150}
151
152void __init omap_barriers_init(void)
153{
154 struct map_desc dram_io_desc[1];
155
156 dram_io_desc[0].virtual = OMAP4_DRAM_BARRIER_VA;
157 dram_io_desc[0].pfn = __phys_to_pfn(dram_sync_paddr);
158 dram_io_desc[0].length = dram_sync_size;
159 dram_io_desc[0].type = MT_MEMORY_RW_SO;
160 iotable_init(dram_io_desc, ARRAY_SIZE(dram_io_desc));
161 dram_sync = (void __iomem *) dram_io_desc[0].virtual;
162
163 pr_info("OMAP4: Map %pa to %p for dram barrier\n",
164 &dram_sync_paddr, dram_sync);
165
166 soc_mb = omap4_mb;
167}
168
169#endif
170
171void gic_dist_disable(void)
172{
173 if (gic_dist_base_addr)
174 writel_relaxed(0x0, gic_dist_base_addr + GIC_DIST_CTRL);
175}
176
177void gic_dist_enable(void)
178{
179 if (gic_dist_base_addr)
180 writel_relaxed(0x1, gic_dist_base_addr + GIC_DIST_CTRL);
181}
182
183bool gic_dist_disabled(void)
184{
185 return !(readl_relaxed(gic_dist_base_addr + GIC_DIST_CTRL) & 0x1);
186}
187
188void gic_timer_retrigger(void)
189{
190 u32 twd_int = readl_relaxed(twd_base + TWD_TIMER_INTSTAT);
191 u32 gic_int = readl_relaxed(gic_dist_base_addr + GIC_DIST_PENDING_SET);
192 u32 twd_ctrl = readl_relaxed(twd_base + TWD_TIMER_CONTROL);
193
194 if (twd_int && !(gic_int & BIT(IRQ_LOCALTIMER))) {
195
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197
198
199 pr_warn("%s: lost localtimer interrupt\n", __func__);
200 writel_relaxed(1, twd_base + TWD_TIMER_INTSTAT);
201 if (!(twd_ctrl & TWD_TIMER_CONTROL_PERIODIC)) {
202 writel_relaxed(1, twd_base + TWD_TIMER_COUNTER);
203 twd_ctrl |= TWD_TIMER_CONTROL_ENABLE;
204 writel_relaxed(twd_ctrl, twd_base + TWD_TIMER_CONTROL);
205 }
206 }
207}
208
209#ifdef CONFIG_CACHE_L2X0
210
211void __iomem *omap4_get_l2cache_base(void)
212{
213 return l2cache_base;
214}
215
216void omap4_l2c310_write_sec(unsigned long val, unsigned reg)
217{
218 unsigned smc_op;
219
220 switch (reg) {
221 case L2X0_CTRL:
222 smc_op = OMAP4_MON_L2X0_CTRL_INDEX;
223 break;
224
225 case L2X0_AUX_CTRL:
226 smc_op = OMAP4_MON_L2X0_AUXCTRL_INDEX;
227 break;
228
229 case L2X0_DEBUG_CTRL:
230 smc_op = OMAP4_MON_L2X0_DBG_CTRL_INDEX;
231 break;
232
233 case L310_PREFETCH_CTRL:
234 smc_op = OMAP4_MON_L2X0_PREFETCH_INDEX;
235 break;
236
237 case L310_POWER_CTRL:
238 pr_info_once("OMAP L2C310: ROM does not support power control setting\n");
239 return;
240
241 default:
242 WARN_ONCE(1, "OMAP L2C310: ignoring write to reg 0x%x\n", reg);
243 return;
244 }
245
246 omap_smc1(smc_op, val);
247}
248
249int __init omap_l2_cache_init(void)
250{
251
252 l2cache_base = ioremap(OMAP44XX_L2CACHE_BASE, SZ_4K);
253 if (WARN_ON(!l2cache_base))
254 return -ENOMEM;
255 return 0;
256}
257#endif
258
259void __iomem *omap4_get_sar_ram_base(void)
260{
261 return sar_ram_base;
262}
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269void __init omap4_sar_ram_init(void)
270{
271 unsigned long sar_base;
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276
277 if (cpu_is_omap44xx())
278 sar_base = OMAP44XX_SAR_RAM_BASE;
279 else if (soc_is_omap54xx())
280 sar_base = OMAP54XX_SAR_RAM_BASE;
281 else
282 return;
283
284
285 sar_ram_base = ioremap(sar_base, SZ_16K);
286 if (WARN_ON(!sar_ram_base))
287 return;
288}
289
290static const struct of_device_id intc_match[] = {
291 { .compatible = "ti,omap4-wugen-mpu", },
292 { .compatible = "ti,omap5-wugen-mpu", },
293 { },
294};
295
296static struct device_node *intc_node;
297
298void __init omap_gic_of_init(void)
299{
300 struct device_node *np;
301
302 intc_node = of_find_matching_node(NULL, intc_match);
303 if (WARN_ON(!intc_node)) {
304 pr_err("No WUGEN found in DT, system will misbehave.\n");
305 pr_err("UPDATE YOUR DEVICE TREE!\n");
306 }
307
308
309 if (!cpu_is_omap446x())
310 goto skip_errata_init;
311
312 np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-gic");
313 gic_dist_base_addr = of_iomap(np, 0);
314 WARN_ON(!gic_dist_base_addr);
315
316 np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-twd-timer");
317 twd_base = of_iomap(np, 0);
318 WARN_ON(!twd_base);
319
320skip_errata_init:
321 irqchip_init();
322}
323