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35#include <linux/kernel.h>
36#include <linux/init.h>
37#include <linux/linkage.h>
38#include <linux/interrupt.h>
39#include <linux/mm.h>
40#include <linux/slab.h>
41#include <linux/irq.h>
42
43#include <linux/irqdomain.h>
44#include <linux/of_address.h>
45#include <linux/of_irq.h>
46
47#include <asm/errno.h>
48#include <asm/signal.h>
49#include <asm/ptrace.h>
50#include <asm/mipsregs.h>
51#include <asm/thread_info.h>
52
53#include <asm/netlogic/mips-extns.h>
54#include <asm/netlogic/interrupt.h>
55#include <asm/netlogic/haldefs.h>
56#include <asm/netlogic/common.h>
57
58#if defined(CONFIG_CPU_XLP)
59#include <asm/netlogic/xlp-hal/iomap.h>
60#include <asm/netlogic/xlp-hal/xlp.h>
61#include <asm/netlogic/xlp-hal/pic.h>
62#elif defined(CONFIG_CPU_XLR)
63#include <asm/netlogic/xlr/iomap.h>
64#include <asm/netlogic/xlr/pic.h>
65#include <asm/netlogic/xlr/fmn.h>
66#else
67#error "Unknown CPU"
68#endif
69
70#ifdef CONFIG_SMP
71#define SMP_IRQ_MASK ((1ULL << IRQ_IPI_SMP_FUNCTION) | \
72 (1ULL << IRQ_IPI_SMP_RESCHEDULE))
73#else
74#define SMP_IRQ_MASK 0
75#endif
76#define PERCPU_IRQ_MASK (SMP_IRQ_MASK | (1ull << IRQ_TIMER) | \
77 (1ull << IRQ_FMN))
78
79struct nlm_pic_irq {
80 void (*extra_ack)(struct irq_data *);
81 struct nlm_soc_info *node;
82 int picirq;
83 int irt;
84 int flags;
85};
86
87static void xlp_pic_enable(struct irq_data *d)
88{
89 unsigned long flags;
90 struct nlm_pic_irq *pd = irq_data_get_irq_chip_data(d);
91
92 BUG_ON(!pd);
93 spin_lock_irqsave(&pd->node->piclock, flags);
94 nlm_pic_enable_irt(pd->node->picbase, pd->irt);
95 spin_unlock_irqrestore(&pd->node->piclock, flags);
96}
97
98static void xlp_pic_disable(struct irq_data *d)
99{
100 struct nlm_pic_irq *pd = irq_data_get_irq_chip_data(d);
101 unsigned long flags;
102
103 BUG_ON(!pd);
104 spin_lock_irqsave(&pd->node->piclock, flags);
105 nlm_pic_disable_irt(pd->node->picbase, pd->irt);
106 spin_unlock_irqrestore(&pd->node->piclock, flags);
107}
108
109static void xlp_pic_mask_ack(struct irq_data *d)
110{
111 struct nlm_pic_irq *pd = irq_data_get_irq_chip_data(d);
112
113 clear_c0_eimr(pd->picirq);
114 ack_c0_eirr(pd->picirq);
115}
116
117static void xlp_pic_unmask(struct irq_data *d)
118{
119 struct nlm_pic_irq *pd = irq_data_get_irq_chip_data(d);
120
121 BUG_ON(!pd);
122
123 if (pd->extra_ack)
124 pd->extra_ack(d);
125
126
127 set_c0_eimr(pd->picirq);
128
129
130 nlm_pic_ack(pd->node->picbase, pd->irt);
131}
132
133static struct irq_chip xlp_pic = {
134 .name = "XLP-PIC",
135 .irq_enable = xlp_pic_enable,
136 .irq_disable = xlp_pic_disable,
137 .irq_mask_ack = xlp_pic_mask_ack,
138 .irq_unmask = xlp_pic_unmask,
139};
140
141static void cpuintr_disable(struct irq_data *d)
142{
143 clear_c0_eimr(d->irq);
144}
145
146static void cpuintr_enable(struct irq_data *d)
147{
148 set_c0_eimr(d->irq);
149}
150
151static void cpuintr_ack(struct irq_data *d)
152{
153 ack_c0_eirr(d->irq);
154}
155
156
157
158
159
160struct irq_chip nlm_cpu_intr = {
161 .name = "XLP-CPU-INTR",
162 .irq_enable = cpuintr_enable,
163 .irq_disable = cpuintr_disable,
164 .irq_mask = cpuintr_disable,
165 .irq_ack = cpuintr_ack,
166 .irq_eoi = cpuintr_enable,
167};
168
169static void __init nlm_init_percpu_irqs(void)
170{
171 int i;
172
173 for (i = 0; i < PIC_IRT_FIRST_IRQ; i++)
174 irq_set_chip_and_handler(i, &nlm_cpu_intr, handle_percpu_irq);
175#ifdef CONFIG_SMP
176 irq_set_chip_and_handler(IRQ_IPI_SMP_FUNCTION, &nlm_cpu_intr,
177 nlm_smp_function_ipi_handler);
178 irq_set_chip_and_handler(IRQ_IPI_SMP_RESCHEDULE, &nlm_cpu_intr,
179 nlm_smp_resched_ipi_handler);
180#endif
181}
182
183
184void nlm_setup_pic_irq(int node, int picirq, int irq, int irt)
185{
186 struct nlm_pic_irq *pic_data;
187 int xirq;
188
189 xirq = nlm_irq_to_xirq(node, irq);
190 pic_data = kzalloc(sizeof(*pic_data), GFP_KERNEL);
191 BUG_ON(pic_data == NULL);
192 pic_data->irt = irt;
193 pic_data->picirq = picirq;
194 pic_data->node = nlm_get_node(node);
195 irq_set_chip_and_handler(xirq, &xlp_pic, handle_level_irq);
196 irq_set_chip_data(xirq, pic_data);
197}
198
199void nlm_set_pic_extra_ack(int node, int irq, void (*xack)(struct irq_data *))
200{
201 struct nlm_pic_irq *pic_data;
202 int xirq;
203
204 xirq = nlm_irq_to_xirq(node, irq);
205 pic_data = irq_get_chip_data(xirq);
206 if (WARN_ON(!pic_data))
207 return;
208 pic_data->extra_ack = xack;
209}
210
211static void nlm_init_node_irqs(int node)
212{
213 struct nlm_soc_info *nodep;
214 int i, irt;
215
216 pr_info("Init IRQ for node %d\n", node);
217 nodep = nlm_get_node(node);
218 nodep->irqmask = PERCPU_IRQ_MASK;
219 for (i = PIC_IRT_FIRST_IRQ; i <= PIC_IRT_LAST_IRQ; i++) {
220 irt = nlm_irq_to_irt(i);
221 if (irt == -1)
222 continue;
223 nodep->irqmask |= 1ull << i;
224 if (irt == -2)
225 continue;
226
227 nlm_pic_init_irt(nodep->picbase, irt, i,
228 node * nlm_threads_per_node(), 0);
229 nlm_setup_pic_irq(node, i, i, irt);
230 }
231}
232
233void nlm_smp_irq_init(int hwtid)
234{
235 int cpu, node;
236
237 cpu = hwtid % nlm_threads_per_node();
238 node = hwtid / nlm_threads_per_node();
239
240 if (cpu == 0 && node != 0)
241 nlm_init_node_irqs(node);
242 write_c0_eimr(nlm_get_node(node)->irqmask);
243}
244
245asmlinkage void plat_irq_dispatch(void)
246{
247 uint64_t eirr;
248 int i, node;
249
250 node = nlm_nodeid();
251 eirr = read_c0_eirr_and_eimr();
252 if (eirr == 0)
253 return;
254
255 i = __ffs64(eirr);
256
257 if (i < PIC_IRQ_BASE) {
258 do_IRQ(i);
259 return;
260 }
261
262#if defined(CONFIG_PCI_MSI) && defined(CONFIG_CPU_XLP)
263
264 if (i >= PIC_PCIE_LINK_MSI_IRQ(0) && i <= PIC_PCIE_LINK_MSI_IRQ(3)) {
265 nlm_dispatch_msi(node, i);
266 return;
267 }
268 if (i >= PIC_PCIE_MSIX_IRQ(0) && i <= PIC_PCIE_MSIX_IRQ(3)) {
269 nlm_dispatch_msix(node, i);
270 return;
271 }
272
273#endif
274
275 do_IRQ(nlm_irq_to_xirq(node, i));
276}
277
278#ifdef CONFIG_CPU_XLP
279static const struct irq_domain_ops xlp_pic_irq_domain_ops = {
280 .xlate = irq_domain_xlate_onetwocell,
281};
282
283static int __init xlp_of_pic_init(struct device_node *node,
284 struct device_node *parent)
285{
286 const int n_picirqs = PIC_IRT_LAST_IRQ - PIC_IRQ_BASE + 1;
287 struct irq_domain *xlp_pic_domain;
288 struct resource res;
289 int socid, ret, bus;
290
291
292 ret = of_address_to_resource(node, 0, &res);
293 if (ret < 0) {
294 pr_err("PIC %pOFn: reg property not found!\n", node);
295 return -EINVAL;
296 }
297
298 if (cpu_is_xlp9xx()) {
299 bus = (res.start >> 20) & 0xf;
300 for (socid = 0; socid < NLM_NR_NODES; socid++) {
301 if (!nlm_node_present(socid))
302 continue;
303 if (nlm_get_node(socid)->socbus == bus)
304 break;
305 }
306 if (socid == NLM_NR_NODES) {
307 pr_err("PIC %pOFn: Node mapping for bus %d not found!\n",
308 node, bus);
309 return -EINVAL;
310 }
311 } else {
312 socid = (res.start >> 18) & 0x3;
313 if (!nlm_node_present(socid)) {
314 pr_err("PIC %pOFn: node %d does not exist!\n",
315 node, socid);
316 return -EINVAL;
317 }
318 }
319
320 if (!nlm_node_present(socid)) {
321 pr_err("PIC %pOFn: node %d does not exist!\n", node, socid);
322 return -EINVAL;
323 }
324
325 xlp_pic_domain = irq_domain_add_legacy(node, n_picirqs,
326 nlm_irq_to_xirq(socid, PIC_IRQ_BASE), PIC_IRQ_BASE,
327 &xlp_pic_irq_domain_ops, NULL);
328 if (xlp_pic_domain == NULL) {
329 pr_err("PIC %pOFn: Creating legacy domain failed!\n", node);
330 return -EINVAL;
331 }
332 pr_info("Node %d: IRQ domain created for PIC@%pR\n", socid, &res);
333 return 0;
334}
335
336static struct of_device_id __initdata xlp_pic_irq_ids[] = {
337 { .compatible = "netlogic,xlp-pic", .data = xlp_of_pic_init },
338 {},
339};
340#endif
341
342void __init arch_init_irq(void)
343{
344
345 nlm_init_percpu_irqs();
346 nlm_init_node_irqs(0);
347 write_c0_eimr(nlm_current_node()->irqmask);
348#if defined(CONFIG_CPU_XLR)
349 nlm_setup_fmn_irq();
350#endif
351#ifdef CONFIG_CPU_XLP
352 of_irq_init(xlp_pic_irq_ids);
353#endif
354}
355
