LXR linux/arch/powerpc/kernel/cpu_setup

   1/* SPDX-License-Identifier: GPL-2.0-or-later */
   2/*
   3 * This file contains low level CPU setup functions.
   4 *    Copyright (C) 2003 Benjamin Herrenschmidt (benh@kernel.crashing.org)
   5 */
   6
   7#include <asm/processor.h>
   8#include <asm/page.h>
   9#include <asm/cputable.h>
  10#include <asm/ppc_asm.h>
  11#include <asm/asm-offsets.h>
  12#include <asm/cache.h>
  13#include <asm/book3s/64/mmu-hash.h>
  14
  15/* Entry: r3 = crap, r4 = ptr to cputable entry
  16 *
  17 * Note that we can be called twice for pseudo-PVRs
  18 */
  19_GLOBAL(__setup_cpu_power7)
  20        mflr    r11
  21        bl      __init_hvmode_206
  22        mtlr    r11
  23        beqlr
  24        li      r0,0
  25        mtspr   SPRN_LPID,r0
  26        mtspr   SPRN_PCR,r0
  27        mfspr   r3,SPRN_LPCR
  28        li      r4,(LPCR_LPES1 >> LPCR_LPES_SH)
  29        bl      __init_LPCR_ISA206
  30        mtlr    r11
  31        blr
  32
  33_GLOBAL(__restore_cpu_power7)
  34        mflr    r11
  35        mfmsr   r3
  36        rldicl. r0,r3,4,63
  37        beqlr
  38        li      r0,0
  39        mtspr   SPRN_LPID,r0
  40        mtspr   SPRN_PCR,r0
  41        mfspr   r3,SPRN_LPCR
  42        li      r4,(LPCR_LPES1 >> LPCR_LPES_SH)
  43        bl      __init_LPCR_ISA206
  44        mtlr    r11
  45        blr
  46
  47_GLOBAL(__setup_cpu_power8)
  48        mflr    r11
  49        bl      __init_FSCR
  50        bl      __init_PMU
  51        bl      __init_PMU_ISA207
  52        bl      __init_hvmode_206
  53        mtlr    r11
  54        beqlr
  55        li      r0,0
  56        mtspr   SPRN_LPID,r0
  57        mtspr   SPRN_PCR,r0
  58        mfspr   r3,SPRN_LPCR
  59        ori     r3, r3, LPCR_PECEDH
  60        li      r4,0 /* LPES = 0 */
  61        bl      __init_LPCR_ISA206
  62        bl      __init_HFSCR
  63        bl      __init_PMU_HV
  64        bl      __init_PMU_HV_ISA207
  65        mtlr    r11
  66        blr
  67
  68_GLOBAL(__restore_cpu_power8)
  69        mflr    r11
  70        bl      __init_FSCR
  71        bl      __init_PMU
  72        bl      __init_PMU_ISA207
  73        mfmsr   r3
  74        rldicl. r0,r3,4,63
  75        mtlr    r11
  76        beqlr
  77        li      r0,0
  78        mtspr   SPRN_LPID,r0
  79        mtspr   SPRN_PCR,r0
  80        mfspr   r3,SPRN_LPCR
  81        ori     r3, r3, LPCR_PECEDH
  82        li      r4,0 /* LPES = 0 */
  83        bl      __init_LPCR_ISA206
  84        bl      __init_HFSCR
  85        bl      __init_PMU_HV
  86        bl      __init_PMU_HV_ISA207
  87        mtlr    r11
  88        blr
  89
  90_GLOBAL(__setup_cpu_power9)
  91        mflr    r11
  92        bl      __init_FSCR
  93        bl      __init_PMU
  94        bl      __init_hvmode_206
  95        mtlr    r11
  96        beqlr
  97        li      r0,0
  98        mtspr   SPRN_PSSCR,r0
  99        mtspr   SPRN_LPID,r0
 100        mtspr   SPRN_PID,r0
 101        mtspr   SPRN_PCR,r0
 102        mfspr   r3,SPRN_LPCR
 103        LOAD_REG_IMMEDIATE(r4, LPCR_PECEDH | LPCR_PECE_HVEE | LPCR_HVICE  | LPCR_HEIC)
 104        or      r3, r3, r4
 105        LOAD_REG_IMMEDIATE(r4, LPCR_UPRT | LPCR_HR)
 106        andc    r3, r3, r4
 107        li      r4,0 /* LPES = 0 */
 108        bl      __init_LPCR_ISA300
 109        bl      __init_HFSCR
 110        bl      __init_PMU_HV
 111        mtlr    r11
 112        blr
 113
 114_GLOBAL(__restore_cpu_power9)
 115        mflr    r11
 116        bl      __init_FSCR
 117        bl      __init_PMU
 118        mfmsr   r3
 119        rldicl. r0,r3,4,63
 120        mtlr    r11
 121        beqlr
 122        li      r0,0
 123        mtspr   SPRN_PSSCR,r0
 124        mtspr   SPRN_LPID,r0
 125        mtspr   SPRN_PID,r0
 126        mtspr   SPRN_PCR,r0
 127        mfspr   r3,SPRN_LPCR
 128        LOAD_REG_IMMEDIATE(r4, LPCR_PECEDH | LPCR_PECE_HVEE | LPCR_HVICE | LPCR_HEIC)
 129        or      r3, r3, r4
 130        LOAD_REG_IMMEDIATE(r4, LPCR_UPRT | LPCR_HR)
 131        andc    r3, r3, r4
 132        li      r4,0 /* LPES = 0 */
 133        bl      __init_LPCR_ISA300
 134        bl      __init_HFSCR
 135        bl      __init_PMU_HV
 136        mtlr    r11
 137        blr
 138
 139__init_hvmode_206:
 140        /* Disable CPU_FTR_HVMODE and exit if MSR:HV is not set */
 141        mfmsr   r3
 142        rldicl. r0,r3,4,63
 143        bnelr
 144        ld      r5,CPU_SPEC_FEATURES(r4)
 145        LOAD_REG_IMMEDIATE(r6,CPU_FTR_HVMODE | CPU_FTR_P9_TM_HV_ASSIST)
 146        andc    r5,r5,r6
 147        std     r5,CPU_SPEC_FEATURES(r4)
 148        blr
 149
 150__init_LPCR_ISA206:
 151        /* Setup a sane LPCR:
 152         *   Called with initial LPCR in R3 and desired LPES 2-bit value in R4
 153         *
 154         *   LPES = 0b01 (HSRR0/1 used for 0x500)
 155         *   PECE = 0b111
 156         *   DPFD = 4
 157         *   HDICE = 0
 158         *   VC = 0b100 (VPM0=1, VPM1=0, ISL=0)
 159         *   VRMASD = 0b10000 (L=1, LP=00)
 160         *
 161         * Other bits untouched for now
 162         */
 163        li      r5,0x10
 164        rldimi  r3,r5, LPCR_VRMASD_SH, 64-LPCR_VRMASD_SH-5
 165
 166        /* POWER9 has no VRMASD */
 167__init_LPCR_ISA300:
 168        rldimi  r3,r4, LPCR_LPES_SH, 64-LPCR_LPES_SH-2
 169        ori     r3,r3,(LPCR_PECE0|LPCR_PECE1|LPCR_PECE2)
 170        li      r5,4
 171        rldimi  r3,r5, LPCR_DPFD_SH, 64-LPCR_DPFD_SH-3
 172        clrrdi  r3,r3,1         /* clear HDICE */
 173        li      r5,4
 174        rldimi  r3,r5, LPCR_VC_SH, 0
 175        mtspr   SPRN_LPCR,r3
 176        isync
 177        blr
 178
 179__init_FSCR:
 180        mfspr   r3,SPRN_FSCR
 181        ori     r3,r3,FSCR_TAR|FSCR_DSCR|FSCR_EBB
 182        mtspr   SPRN_FSCR,r3
 183        blr
 184
 185__init_HFSCR:
 186        mfspr   r3,SPRN_HFSCR
 187        ori     r3,r3,HFSCR_TAR|HFSCR_TM|HFSCR_BHRB|HFSCR_PM|\
 188                      HFSCR_DSCR|HFSCR_VECVSX|HFSCR_FP|HFSCR_EBB|HFSCR_MSGP
 189        mtspr   SPRN_HFSCR,r3
 190        blr
 191
 192__init_PMU_HV:
 193        li      r5,0
 194        mtspr   SPRN_MMCRC,r5
 195        blr
 196
 197__init_PMU_HV_ISA207:
 198        li      r5,0
 199        mtspr   SPRN_MMCRH,r5
 200        blr
 201
 202__init_PMU:
 203        li      r5,0
 204        mtspr   SPRN_MMCRA,r5
 205        mtspr   SPRN_MMCR0,r5
 206        mtspr   SPRN_MMCR1,r5
 207        mtspr   SPRN_MMCR2,r5
 208        blr
 209
 210__init_PMU_ISA207:
 211        li      r5,0
 212        mtspr   SPRN_MMCRS,r5
 213        blr
 214