1
2
3
4
5
6
7
8
9
10
11
12#include <linux/thread_info.h>
13#include <linux/capability.h>
14#include <linux/miscdevice.h>
15#include <linux/ratelimit.h>
16#include <linux/rcupdate.h>
17#include <linux/kobject.h>
18#include <linux/uaccess.h>
19#include <linux/kdebug.h>
20#include <linux/kernel.h>
21#include <linux/percpu.h>
22#include <linux/string.h>
23#include <linux/device.h>
24#include <linux/syscore_ops.h>
25#include <linux/delay.h>
26#include <linux/ctype.h>
27#include <linux/sched.h>
28#include <linux/sysfs.h>
29#include <linux/types.h>
30#include <linux/slab.h>
31#include <linux/init.h>
32#include <linux/kmod.h>
33#include <linux/poll.h>
34#include <linux/nmi.h>
35#include <linux/cpu.h>
36#include <linux/ras.h>
37#include <linux/smp.h>
38#include <linux/fs.h>
39#include <linux/mm.h>
40#include <linux/debugfs.h>
41#include <linux/irq_work.h>
42#include <linux/export.h>
43#include <linux/jump_label.h>
44#include <linux/set_memory.h>
45
46#include <asm/intel-family.h>
47#include <asm/processor.h>
48#include <asm/traps.h>
49#include <asm/tlbflush.h>
50#include <asm/mce.h>
51#include <asm/msr.h>
52#include <asm/reboot.h>
53
54#include "internal.h"
55
56static DEFINE_MUTEX(mce_log_mutex);
57
58
59static DEFINE_MUTEX(mce_sysfs_mutex);
60
61#define CREATE_TRACE_POINTS
62#include <trace/events/mce.h>
63
64#define SPINUNIT 100
65
66DEFINE_PER_CPU(unsigned, mce_exception_count);
67
68struct mce_bank *mce_banks __read_mostly;
69struct mce_vendor_flags mce_flags __read_mostly;
70
71struct mca_config mca_cfg __read_mostly = {
72 .bootlog = -1,
73
74
75
76
77
78
79
80 .tolerant = 1,
81 .monarch_timeout = -1
82};
83
84static DEFINE_PER_CPU(struct mce, mces_seen);
85static unsigned long mce_need_notify;
86static int cpu_missing;
87
88
89
90
91
92DEFINE_PER_CPU(mce_banks_t, mce_poll_banks) = {
93 [0 ... BITS_TO_LONGS(MAX_NR_BANKS)-1] = ~0UL
94};
95
96
97
98
99
100
101
102
103mce_banks_t mce_banks_ce_disabled;
104
105static struct work_struct mce_work;
106static struct irq_work mce_irq_work;
107
108static void (*quirk_no_way_out)(int bank, struct mce *m, struct pt_regs *regs);
109
110
111
112
113
114BLOCKING_NOTIFIER_HEAD(x86_mce_decoder_chain);
115
116
117void mce_setup(struct mce *m)
118{
119 memset(m, 0, sizeof(struct mce));
120 m->cpu = m->extcpu = smp_processor_id();
121
122 m->time = __ktime_get_real_seconds();
123 m->cpuvendor = boot_cpu_data.x86_vendor;
124 m->cpuid = cpuid_eax(1);
125 m->socketid = cpu_data(m->extcpu).phys_proc_id;
126 m->apicid = cpu_data(m->extcpu).initial_apicid;
127 rdmsrl(MSR_IA32_MCG_CAP, m->mcgcap);
128
129 if (this_cpu_has(X86_FEATURE_INTEL_PPIN))
130 rdmsrl(MSR_PPIN, m->ppin);
131
132 m->microcode = boot_cpu_data.microcode;
133}
134
135DEFINE_PER_CPU(struct mce, injectm);
136EXPORT_PER_CPU_SYMBOL_GPL(injectm);
137
138void mce_log(struct mce *m)
139{
140 if (!mce_gen_pool_add(m))
141 irq_work_queue(&mce_irq_work);
142}
143
144void mce_inject_log(struct mce *m)
145{
146 mutex_lock(&mce_log_mutex);
147 mce_log(m);
148 mutex_unlock(&mce_log_mutex);
149}
150EXPORT_SYMBOL_GPL(mce_inject_log);
151
152static struct notifier_block mce_srao_nb;
153
154
155
156
157
158
159#define NUM_DEFAULT_NOTIFIERS 3
160static atomic_t num_notifiers;
161
162void mce_register_decode_chain(struct notifier_block *nb)
163{
164 if (WARN_ON(nb->priority > MCE_PRIO_MCELOG && nb->priority < MCE_PRIO_EDAC))
165 return;
166
167 atomic_inc(&num_notifiers);
168
169 blocking_notifier_chain_register(&x86_mce_decoder_chain, nb);
170}
171EXPORT_SYMBOL_GPL(mce_register_decode_chain);
172
173void mce_unregister_decode_chain(struct notifier_block *nb)
174{
175 atomic_dec(&num_notifiers);
176
177 blocking_notifier_chain_unregister(&x86_mce_decoder_chain, nb);
178}
179EXPORT_SYMBOL_GPL(mce_unregister_decode_chain);
180
181static inline u32 ctl_reg(int bank)
182{
183 return MSR_IA32_MCx_CTL(bank);
184}
185
186static inline u32 status_reg(int bank)
187{
188 return MSR_IA32_MCx_STATUS(bank);
189}
190
191static inline u32 addr_reg(int bank)
192{
193 return MSR_IA32_MCx_ADDR(bank);
194}
195
196static inline u32 misc_reg(int bank)
197{
198 return MSR_IA32_MCx_MISC(bank);
199}
200
201static inline u32 smca_ctl_reg(int bank)
202{
203 return MSR_AMD64_SMCA_MCx_CTL(bank);
204}
205
206static inline u32 smca_status_reg(int bank)
207{
208 return MSR_AMD64_SMCA_MCx_STATUS(bank);
209}
210
211static inline u32 smca_addr_reg(int bank)
212{
213 return MSR_AMD64_SMCA_MCx_ADDR(bank);
214}
215
216static inline u32 smca_misc_reg(int bank)
217{
218 return MSR_AMD64_SMCA_MCx_MISC(bank);
219}
220
221struct mca_msr_regs msr_ops = {
222 .ctl = ctl_reg,
223 .status = status_reg,
224 .addr = addr_reg,
225 .misc = misc_reg
226};
227
228static void __print_mce(struct mce *m)
229{
230 pr_emerg(HW_ERR "CPU %d: Machine Check%s: %Lx Bank %d: %016Lx\n",
231 m->extcpu,
232 (m->mcgstatus & MCG_STATUS_MCIP ? " Exception" : ""),
233 m->mcgstatus, m->bank, m->status);
234
235 if (m->ip) {
236 pr_emerg(HW_ERR "RIP%s %02x:<%016Lx> ",
237 !(m->mcgstatus & MCG_STATUS_EIPV) ? " !INEXACT!" : "",
238 m->cs, m->ip);
239
240 if (m->cs == __KERNEL_CS)
241 pr_cont("{%pS}", (void *)(unsigned long)m->ip);
242 pr_cont("\n");
243 }
244
245 pr_emerg(HW_ERR "TSC %llx ", m->tsc);
246 if (m->addr)
247 pr_cont("ADDR %llx ", m->addr);
248 if (m->misc)
249 pr_cont("MISC %llx ", m->misc);
250
251 if (mce_flags.smca) {
252 if (m->synd)
253 pr_cont("SYND %llx ", m->synd);
254 if (m->ipid)
255 pr_cont("IPID %llx ", m->ipid);
256 }
257
258 pr_cont("\n");
259
260
261
262
263 pr_emerg(HW_ERR "PROCESSOR %u:%x TIME %llu SOCKET %u APIC %x microcode %x\n",
264 m->cpuvendor, m->cpuid, m->time, m->socketid, m->apicid,
265 m->microcode);
266}
267
268static void print_mce(struct mce *m)
269{
270 __print_mce(m);
271
272 if (m->cpuvendor != X86_VENDOR_AMD && m->cpuvendor != X86_VENDOR_HYGON)
273 pr_emerg_ratelimited(HW_ERR "Run the above through 'mcelog --ascii'\n");
274}
275
276#define PANIC_TIMEOUT 5
277
278static atomic_t mce_panicked;
279
280static int fake_panic;
281static atomic_t mce_fake_panicked;
282
283
284static void wait_for_panic(void)
285{
286 long timeout = PANIC_TIMEOUT*USEC_PER_SEC;
287
288 preempt_disable();
289 local_irq_enable();
290 while (timeout-- > 0)
291 udelay(1);
292 if (panic_timeout == 0)
293 panic_timeout = mca_cfg.panic_timeout;
294 panic("Panicing machine check CPU died");
295}
296
297static void mce_panic(const char *msg, struct mce *final, char *exp)
298{
299 int apei_err = 0;
300 struct llist_node *pending;
301 struct mce_evt_llist *l;
302
303 if (!fake_panic) {
304
305
306
307 if (atomic_inc_return(&mce_panicked) > 1)
308 wait_for_panic();
309 barrier();
310
311 bust_spinlocks(1);
312 console_verbose();
313 } else {
314
315 if (atomic_inc_return(&mce_fake_panicked) > 1)
316 return;
317 }
318 pending = mce_gen_pool_prepare_records();
319
320 llist_for_each_entry(l, pending, llnode) {
321 struct mce *m = &l->mce;
322 if (!(m->status & MCI_STATUS_UC)) {
323 print_mce(m);
324 if (!apei_err)
325 apei_err = apei_write_mce(m);
326 }
327 }
328
329 llist_for_each_entry(l, pending, llnode) {
330 struct mce *m = &l->mce;
331 if (!(m->status & MCI_STATUS_UC))
332 continue;
333 if (!final || mce_cmp(m, final)) {
334 print_mce(m);
335 if (!apei_err)
336 apei_err = apei_write_mce(m);
337 }
338 }
339 if (final) {
340 print_mce(final);
341 if (!apei_err)
342 apei_err = apei_write_mce(final);
343 }
344 if (cpu_missing)
345 pr_emerg(HW_ERR "Some CPUs didn't answer in synchronization\n");
346 if (exp)
347 pr_emerg(HW_ERR "Machine check: %s\n", exp);
348 if (!fake_panic) {
349 if (panic_timeout == 0)
350 panic_timeout = mca_cfg.panic_timeout;
351 panic(msg);
352 } else
353 pr_emerg(HW_ERR "Fake kernel panic: %s\n", msg);
354}
355
356
357
358static int msr_to_offset(u32 msr)
359{
360 unsigned bank = __this_cpu_read(injectm.bank);
361
362 if (msr == mca_cfg.rip_msr)
363 return offsetof(struct mce, ip);
364 if (msr == msr_ops.status(bank))
365 return offsetof(struct mce, status);
366 if (msr == msr_ops.addr(bank))
367 return offsetof(struct mce, addr);
368 if (msr == msr_ops.misc(bank))
369 return offsetof(struct mce, misc);
370 if (msr == MSR_IA32_MCG_STATUS)
371 return offsetof(struct mce, mcgstatus);
372 return -1;
373}
374
375
376static u64 mce_rdmsrl(u32 msr)
377{
378 u64 v;
379
380 if (__this_cpu_read(injectm.finished)) {
381 int offset = msr_to_offset(msr);
382
383 if (offset < 0)
384 return 0;
385 return *(u64 *)((char *)this_cpu_ptr(&injectm) + offset);
386 }
387
388 if (rdmsrl_safe(msr, &v)) {
389 WARN_ONCE(1, "mce: Unable to read MSR 0x%x!\n", msr);
390
391
392
393
394
395 v = 0;
396 }
397
398 return v;
399}
400
401static void mce_wrmsrl(u32 msr, u64 v)
402{
403 if (__this_cpu_read(injectm.finished)) {
404 int offset = msr_to_offset(msr);
405
406 if (offset >= 0)
407 *(u64 *)((char *)this_cpu_ptr(&injectm) + offset) = v;
408 return;
409 }
410 wrmsrl(msr, v);
411}
412
413
414
415
416
417
418static inline void mce_gather_info(struct mce *m, struct pt_regs *regs)
419{
420 mce_setup(m);
421
422 m->mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS);
423 if (regs) {
424
425
426
427
428 if (m->mcgstatus & (MCG_STATUS_RIPV|MCG_STATUS_EIPV)) {
429 m->ip = regs->ip;
430 m->cs = regs->cs;
431
432
433
434
435
436
437 if (v8086_mode(regs))
438 m->cs |= 3;
439 }
440
441 if (mca_cfg.rip_msr)
442 m->ip = mce_rdmsrl(mca_cfg.rip_msr);
443 }
444}
445
446int mce_available(struct cpuinfo_x86 *c)
447{
448 if (mca_cfg.disabled)
449 return 0;
450 return cpu_has(c, X86_FEATURE_MCE) && cpu_has(c, X86_FEATURE_MCA);
451}
452
453static void mce_schedule_work(void)
454{
455 if (!mce_gen_pool_empty())
456 schedule_work(&mce_work);
457}
458
459static void mce_irq_work_cb(struct irq_work *entry)
460{
461 mce_schedule_work();
462}
463
464
465
466
467
468
469
470int mce_usable_address(struct mce *m)
471{
472 if (!(m->status & MCI_STATUS_ADDRV))
473 return 0;
474
475
476 if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL)
477 return 1;
478
479 if (!(m->status & MCI_STATUS_MISCV))
480 return 0;
481
482 if (MCI_MISC_ADDR_LSB(m->misc) > PAGE_SHIFT)
483 return 0;
484
485 if (MCI_MISC_ADDR_MODE(m->misc) != MCI_MISC_ADDR_PHYS)
486 return 0;
487
488 return 1;
489}
490EXPORT_SYMBOL_GPL(mce_usable_address);
491
492bool mce_is_memory_error(struct mce *m)
493{
494 if (m->cpuvendor == X86_VENDOR_AMD ||
495 m->cpuvendor == X86_VENDOR_HYGON) {
496 return amd_mce_is_memory_error(m);
497 } else if (m->cpuvendor == X86_VENDOR_INTEL) {
498
499
500
501
502
503
504
505
506
507
508
509
510
511 return (m->status & 0xef80) == BIT(7) ||
512 (m->status & 0xef00) == BIT(8) ||
513 (m->status & 0xeffc) == 0xc;
514 }
515
516 return false;
517}
518EXPORT_SYMBOL_GPL(mce_is_memory_error);
519
520bool mce_is_correctable(struct mce *m)
521{
522 if (m->cpuvendor == X86_VENDOR_AMD && m->status & MCI_STATUS_DEFERRED)
523 return false;
524
525 if (m->cpuvendor == X86_VENDOR_HYGON && m->status & MCI_STATUS_DEFERRED)
526 return false;
527
528 if (m->status & MCI_STATUS_UC)
529 return false;
530
531 return true;
532}
533EXPORT_SYMBOL_GPL(mce_is_correctable);
534
535static bool cec_add_mce(struct mce *m)
536{
537 if (!m)
538 return false;
539
540
541 if (mce_is_memory_error(m) &&
542 mce_is_correctable(m) &&
543 mce_usable_address(m))
544 if (!cec_add_elem(m->addr >> PAGE_SHIFT))
545 return true;
546
547 return false;
548}
549
550static int mce_first_notifier(struct notifier_block *nb, unsigned long val,
551 void *data)
552{
553 struct mce *m = (struct mce *)data;
554
555 if (!m)
556 return NOTIFY_DONE;
557
558 if (cec_add_mce(m))
559 return NOTIFY_STOP;
560
561
562 trace_mce_record(m);
563
564 set_bit(0, &mce_need_notify);
565
566 mce_notify_irq();
567
568 return NOTIFY_DONE;
569}
570
571static struct notifier_block first_nb = {
572 .notifier_call = mce_first_notifier,
573 .priority = MCE_PRIO_FIRST,
574};
575
576static int srao_decode_notifier(struct notifier_block *nb, unsigned long val,
577 void *data)
578{
579 struct mce *mce = (struct mce *)data;
580 unsigned long pfn;
581
582 if (!mce)
583 return NOTIFY_DONE;
584
585 if (mce_usable_address(mce) && (mce->severity == MCE_AO_SEVERITY)) {
586 pfn = mce->addr >> PAGE_SHIFT;
587 if (!memory_failure(pfn, 0))
588 set_mce_nospec(pfn);
589 }
590
591 return NOTIFY_OK;
592}
593static struct notifier_block mce_srao_nb = {
594 .notifier_call = srao_decode_notifier,
595 .priority = MCE_PRIO_SRAO,
596};
597
598static int mce_default_notifier(struct notifier_block *nb, unsigned long val,
599 void *data)
600{
601 struct mce *m = (struct mce *)data;
602
603 if (!m)
604 return NOTIFY_DONE;
605
606 if (atomic_read(&num_notifiers) > NUM_DEFAULT_NOTIFIERS)
607 return NOTIFY_DONE;
608
609 __print_mce(m);
610
611 return NOTIFY_DONE;
612}
613
614static struct notifier_block mce_default_nb = {
615 .notifier_call = mce_default_notifier,
616
617 .priority = MCE_PRIO_LOWEST,
618};
619
620
621
622
623static void mce_read_aux(struct mce *m, int i)
624{
625 if (m->status & MCI_STATUS_MISCV)
626 m->misc = mce_rdmsrl(msr_ops.misc(i));
627
628 if (m->status & MCI_STATUS_ADDRV) {
629 m->addr = mce_rdmsrl(msr_ops.addr(i));
630
631
632
633
634 if (mca_cfg.ser && (m->status & MCI_STATUS_MISCV)) {
635 u8 shift = MCI_MISC_ADDR_LSB(m->misc);
636 m->addr >>= shift;
637 m->addr <<= shift;
638 }
639
640
641
642
643
644 if (mce_flags.smca) {
645 u8 lsb = (m->addr >> 56) & 0x3f;
646
647 m->addr &= GENMASK_ULL(55, lsb);
648 }
649 }
650
651 if (mce_flags.smca) {
652 m->ipid = mce_rdmsrl(MSR_AMD64_SMCA_MCx_IPID(i));
653
654 if (m->status & MCI_STATUS_SYNDV)
655 m->synd = mce_rdmsrl(MSR_AMD64_SMCA_MCx_SYND(i));
656 }
657}
658
659DEFINE_PER_CPU(unsigned, mce_poll_count);
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676bool machine_check_poll(enum mcp_flags flags, mce_banks_t *b)
677{
678 bool error_seen = false;
679 struct mce m;
680 int i;
681
682 this_cpu_inc(mce_poll_count);
683
684 mce_gather_info(&m, NULL);
685
686 if (flags & MCP_TIMESTAMP)
687 m.tsc = rdtsc();
688
689 for (i = 0; i < mca_cfg.banks; i++) {
690 if (!mce_banks[i].ctl || !test_bit(i, *b))
691 continue;
692
693 m.misc = 0;
694 m.addr = 0;
695 m.bank = i;
696
697 barrier();
698 m.status = mce_rdmsrl(msr_ops.status(i));
699
700
701 if (!(m.status & MCI_STATUS_VAL))
702 continue;
703
704
705
706
707
708 if ((flags & MCP_UC) || !(m.status & MCI_STATUS_UC))
709 goto log_it;
710
711
712
713
714
715
716
717 if (!mca_cfg.ser) {
718 if (m.status & MCI_STATUS_UC)
719 continue;
720 goto log_it;
721 }
722
723
724 if (!(m.status & MCI_STATUS_EN))
725 goto log_it;
726
727
728
729
730
731 if (!(m.status & MCI_STATUS_PCC) && !(m.status & MCI_STATUS_S))
732 goto log_it;
733
734
735
736
737
738
739 continue;
740
741log_it:
742 error_seen = true;
743
744 mce_read_aux(&m, i);
745
746 m.severity = mce_severity(&m, mca_cfg.tolerant, NULL, false);
747
748
749
750
751
752 if (!(flags & MCP_DONTLOG) && !mca_cfg.dont_log_ce)
753 mce_log(&m);
754 else if (mce_usable_address(&m)) {
755
756
757
758
759
760 if (!mce_gen_pool_add(&m))
761 mce_schedule_work();
762 }
763
764
765
766
767 mce_wrmsrl(msr_ops.status(i), 0);
768 }
769
770
771
772
773
774
775 sync_core();
776
777 return error_seen;
778}
779EXPORT_SYMBOL_GPL(machine_check_poll);
780
781
782
783
784
785static int mce_no_way_out(struct mce *m, char **msg, unsigned long *validp,
786 struct pt_regs *regs)
787{
788 char *tmp;
789 int i;
790
791 for (i = 0; i < mca_cfg.banks; i++) {
792 m->status = mce_rdmsrl(msr_ops.status(i));
793 if (!(m->status & MCI_STATUS_VAL))
794 continue;
795
796 __set_bit(i, validp);
797 if (quirk_no_way_out)
798 quirk_no_way_out(i, m, regs);
799
800 if (mce_severity(m, mca_cfg.tolerant, &tmp, true) >= MCE_PANIC_SEVERITY) {
801 m->bank = i;
802 mce_read_aux(m, i);
803 *msg = tmp;
804 return 1;
805 }
806 }
807 return 0;
808}
809
810
811
812
813
814static atomic_t mce_executing;
815
816
817
818
819static atomic_t mce_callin;
820
821
822
823
824static int mce_timed_out(u64 *t, const char *msg)
825{
826
827
828
829
830
831
832 rmb();
833 if (atomic_read(&mce_panicked))
834 wait_for_panic();
835 if (!mca_cfg.monarch_timeout)
836 goto out;
837 if ((s64)*t < SPINUNIT) {
838 if (mca_cfg.tolerant <= 1)
839 mce_panic(msg, NULL, NULL);
840 cpu_missing = 1;
841 return 1;
842 }
843 *t -= SPINUNIT;
844out:
845 touch_nmi_watchdog();
846 return 0;
847}
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873static void mce_reign(void)
874{
875 int cpu;
876 struct mce *m = NULL;
877 int global_worst = 0;
878 char *msg = NULL;
879 char *nmsg = NULL;
880
881
882
883
884
885
886 for_each_possible_cpu(cpu) {
887 int severity = mce_severity(&per_cpu(mces_seen, cpu),
888 mca_cfg.tolerant,
889 &nmsg, true);
890 if (severity > global_worst) {
891 msg = nmsg;
892 global_worst = severity;
893 m = &per_cpu(mces_seen, cpu);
894 }
895 }
896
897
898
899
900
901
902 if (m && global_worst >= MCE_PANIC_SEVERITY && mca_cfg.tolerant < 3)
903 mce_panic("Fatal machine check", m, msg);
904
905
906
907
908
909
910
911
912
913
914
915 if (global_worst <= MCE_KEEP_SEVERITY && mca_cfg.tolerant < 3)
916 mce_panic("Fatal machine check from unknown source", NULL, NULL);
917
918
919
920
921
922 for_each_possible_cpu(cpu)
923 memset(&per_cpu(mces_seen, cpu), 0, sizeof(struct mce));
924}
925
926static atomic_t global_nwo;
927
928
929
930
931
932
933
934
935static int mce_start(int *no_way_out)
936{
937 int order;
938 int cpus = num_online_cpus();
939 u64 timeout = (u64)mca_cfg.monarch_timeout * NSEC_PER_USEC;
940
941 if (!timeout)
942 return -1;
943
944 atomic_add(*no_way_out, &global_nwo);
945
946
947
948
949 order = atomic_inc_return(&mce_callin);
950
951
952
953
954 while (atomic_read(&mce_callin) != cpus) {
955 if (mce_timed_out(&timeout,
956 "Timeout: Not all CPUs entered broadcast exception handler")) {
957 atomic_set(&global_nwo, 0);
958 return -1;
959 }
960 ndelay(SPINUNIT);
961 }
962
963
964
965
966 smp_rmb();
967
968 if (order == 1) {
969
970
971
972 atomic_set(&mce_executing, 1);
973 } else {
974
975
976
977
978
979
980 while (atomic_read(&mce_executing) < order) {
981 if (mce_timed_out(&timeout,
982 "Timeout: Subject CPUs unable to finish machine check processing")) {
983 atomic_set(&global_nwo, 0);
984 return -1;
985 }
986 ndelay(SPINUNIT);
987 }
988 }
989
990
991
992
993 *no_way_out = atomic_read(&global_nwo);
994
995 return order;
996}
997
998
999
1000
1001
1002static int mce_end(int order)
1003{
1004 int ret = -1;
1005 u64 timeout = (u64)mca_cfg.monarch_timeout * NSEC_PER_USEC;
1006
1007 if (!timeout)
1008 goto reset;
1009 if (order < 0)
1010 goto reset;
1011
1012
1013
1014
1015 atomic_inc(&mce_executing);
1016
1017 if (order == 1) {
1018
1019 int cpus = num_online_cpus();
1020
1021
1022
1023
1024
1025 while (atomic_read(&mce_executing) <= cpus) {
1026 if (mce_timed_out(&timeout,
1027 "Timeout: Monarch CPU unable to finish machine check processing"))
1028 goto reset;
1029 ndelay(SPINUNIT);
1030 }
1031
1032 mce_reign();
1033 barrier();
1034 ret = 0;
1035 } else {
1036
1037
1038
1039 while (atomic_read(&mce_executing) != 0) {
1040 if (mce_timed_out(&timeout,
1041 "Timeout: Monarch CPU did not finish machine check processing"))
1042 goto reset;
1043 ndelay(SPINUNIT);
1044 }
1045
1046
1047
1048
1049 return 0;
1050 }
1051
1052
1053
1054
1055reset:
1056 atomic_set(&global_nwo, 0);
1057 atomic_set(&mce_callin, 0);
1058 barrier();
1059
1060
1061
1062
1063 atomic_set(&mce_executing, 0);
1064 return ret;
1065}
1066
1067static void mce_clear_state(unsigned long *toclear)
1068{
1069 int i;
1070
1071 for (i = 0; i < mca_cfg.banks; i++) {
1072 if (test_bit(i, toclear))
1073 mce_wrmsrl(msr_ops.status(i), 0);
1074 }
1075}
1076
1077static int do_memory_failure(struct mce *m)
1078{
1079 int flags = MF_ACTION_REQUIRED;
1080 int ret;
1081
1082 pr_err("Uncorrected hardware memory error in user-access at %llx", m->addr);
1083 if (!(m->mcgstatus & MCG_STATUS_RIPV))
1084 flags |= MF_MUST_KILL;
1085 ret = memory_failure(m->addr >> PAGE_SHIFT, flags);
1086 if (ret)
1087 pr_err("Memory error not recovered");
1088 else
1089 set_mce_nospec(m->addr >> PAGE_SHIFT);
1090 return ret;
1091}
1092
1093
1094
1095
1096
1097
1098
1099
1100
1101
1102
1103
1104
1105
1106static bool __mc_check_crashing_cpu(int cpu)
1107{
1108 if (cpu_is_offline(cpu) ||
1109 (crashing_cpu != -1 && crashing_cpu != cpu)) {
1110 u64 mcgstatus;
1111
1112 mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS);
1113 if (mcgstatus & MCG_STATUS_RIPV) {
1114 mce_wrmsrl(MSR_IA32_MCG_STATUS, 0);
1115 return true;
1116 }
1117 }
1118 return false;
1119}
1120
1121static void __mc_scan_banks(struct mce *m, struct mce *final,
1122 unsigned long *toclear, unsigned long *valid_banks,
1123 int no_way_out, int *worst)
1124{
1125 struct mca_config *cfg = &mca_cfg;
1126 int severity, i;
1127
1128 for (i = 0; i < cfg->banks; i++) {
1129 __clear_bit(i, toclear);
1130 if (!test_bit(i, valid_banks))
1131 continue;
1132
1133 if (!mce_banks[i].ctl)
1134 continue;
1135
1136 m->misc = 0;
1137 m->addr = 0;
1138 m->bank = i;
1139
1140 m->status = mce_rdmsrl(msr_ops.status(i));
1141 if (!(m->status & MCI_STATUS_VAL))
1142 continue;
1143
1144
1145
1146
1147
1148 if (!(m->status & (cfg->ser ? MCI_STATUS_S : MCI_STATUS_UC)) &&
1149 !no_way_out)
1150 continue;
1151
1152
1153 add_taint(TAINT_MACHINE_CHECK, LOCKDEP_NOW_UNRELIABLE);
1154
1155 severity = mce_severity(m, cfg->tolerant, NULL, true);
1156
1157
1158
1159
1160
1161 if ((severity == MCE_KEEP_SEVERITY ||
1162 severity == MCE_UCNA_SEVERITY) && !no_way_out)
1163 continue;
1164
1165 __set_bit(i, toclear);
1166
1167
1168 if (severity == MCE_NO_SEVERITY)
1169 continue;
1170
1171 mce_read_aux(m, i);
1172
1173
1174 m->severity = severity;
1175
1176 mce_log(m);
1177
1178 if (severity > *worst) {
1179 *final = *m;
1180 *worst = severity;
1181 }
1182 }
1183
1184
1185 *m = *final;
1186}
1187
1188
1189
1190
1191
1192
1193
1194
1195
1196
1197
1198
1199
1200void do_machine_check(struct pt_regs *regs, long error_code)
1201{
1202 DECLARE_BITMAP(valid_banks, MAX_NR_BANKS);
1203 DECLARE_BITMAP(toclear, MAX_NR_BANKS);
1204 struct mca_config *cfg = &mca_cfg;
1205 int cpu = smp_processor_id();
1206 char *msg = "Unknown";
1207 struct mce m, *final;
1208 int worst = 0;
1209
1210
1211
1212
1213
1214 int order = -1;
1215
1216
1217
1218
1219
1220 int no_way_out = 0;
1221
1222
1223
1224
1225
1226 int kill_it = 0;
1227
1228
1229
1230
1231
1232 int lmce = 1;
1233
1234 if (__mc_check_crashing_cpu(cpu))
1235 return;
1236
1237 ist_enter(regs);
1238
1239 this_cpu_inc(mce_exception_count);
1240
1241 mce_gather_info(&m, regs);
1242 m.tsc = rdtsc();
1243
1244 final = this_cpu_ptr(&mces_seen);
1245 *final = m;
1246
1247 memset(valid_banks, 0, sizeof(valid_banks));
1248 no_way_out = mce_no_way_out(&m, &msg, valid_banks, regs);
1249
1250 barrier();
1251
1252
1253
1254
1255
1256
1257 if (!(m.mcgstatus & MCG_STATUS_RIPV))
1258 kill_it = 1;
1259
1260
1261
1262
1263
1264 if (m.cpuvendor == X86_VENDOR_INTEL)
1265 lmce = m.mcgstatus & MCG_STATUS_LMCES;
1266
1267
1268
1269
1270
1271
1272
1273
1274 if (lmce) {
1275 if (no_way_out)
1276 mce_panic("Fatal local machine check", &m, msg);
1277 } else {
1278 order = mce_start(&no_way_out);
1279 }
1280
1281 __mc_scan_banks(&m, final, toclear, valid_banks, no_way_out, &worst);
1282
1283 if (!no_way_out)
1284 mce_clear_state(toclear);
1285
1286
1287
1288
1289
1290 if (!lmce) {
1291 if (mce_end(order) < 0)
1292 no_way_out = worst >= MCE_PANIC_SEVERITY;
1293 } else {
1294
1295
1296
1297
1298
1299
1300
1301
1302 if (worst >= MCE_PANIC_SEVERITY && mca_cfg.tolerant < 3) {
1303 mce_severity(&m, cfg->tolerant, &msg, true);
1304 mce_panic("Local fatal machine check!", &m, msg);
1305 }
1306 }
1307
1308
1309
1310
1311
1312 if (cfg->tolerant == 3)
1313 kill_it = 0;
1314 else if (no_way_out)
1315 mce_panic("Fatal machine check on current CPU", &m, msg);
1316
1317 if (worst > 0)
1318 irq_work_queue(&mce_irq_work);
1319
1320 mce_wrmsrl(MSR_IA32_MCG_STATUS, 0);
1321
1322 sync_core();
1323
1324 if (worst != MCE_AR_SEVERITY && !kill_it)
1325 goto out_ist;
1326
1327
1328 if ((m.cs & 3) == 3) {
1329 ist_begin_non_atomic(regs);
1330 local_irq_enable();
1331
1332 if (kill_it || do_memory_failure(&m))
1333 force_sig(SIGBUS, current);
1334 local_irq_disable();
1335 ist_end_non_atomic();
1336 } else {
1337 if (!fixup_exception(regs, X86_TRAP_MC, error_code, 0))
1338 mce_panic("Failed kernel mode recovery", &m, NULL);
1339 }
1340
1341out_ist:
1342 ist_exit(regs);
1343}
1344EXPORT_SYMBOL_GPL(do_machine_check);
1345
1346#ifndef CONFIG_MEMORY_FAILURE
1347int memory_failure(unsigned long pfn, int flags)
1348{
1349
1350 BUG_ON(flags & MF_ACTION_REQUIRED);
1351 pr_err("Uncorrected memory error in page 0x%lx ignored\n"
1352 "Rebuild kernel with CONFIG_MEMORY_FAILURE=y for smarter handling\n",
1353 pfn);
1354
1355 return 0;
1356}
1357#endif
1358
1359
1360
1361
1362
1363
1364static unsigned long check_interval = INITIAL_CHECK_INTERVAL;
1365
1366static DEFINE_PER_CPU(unsigned long, mce_next_interval);
1367static DEFINE_PER_CPU(struct timer_list, mce_timer);
1368
1369static unsigned long mce_adjust_timer_default(unsigned long interval)
1370{
1371 return interval;
1372}
1373
1374static unsigned long (*mce_adjust_timer)(unsigned long interval) = mce_adjust_timer_default;
1375
1376static void __start_timer(struct timer_list *t, unsigned long interval)
1377{
1378 unsigned long when = jiffies + interval;
1379 unsigned long flags;
1380
1381 local_irq_save(flags);
1382
1383 if (!timer_pending(t) || time_before(when, t->expires))
1384 mod_timer(t, round_jiffies(when));
1385
1386 local_irq_restore(flags);
1387}
1388
1389static void mce_timer_fn(struct timer_list *t)
1390{
1391 struct timer_list *cpu_t = this_cpu_ptr(&mce_timer);
1392 unsigned long iv;
1393
1394 WARN_ON(cpu_t != t);
1395
1396 iv = __this_cpu_read(mce_next_interval);
1397
1398 if (mce_available(this_cpu_ptr(&cpu_info))) {
1399 machine_check_poll(0, this_cpu_ptr(&mce_poll_banks));
1400
1401 if (mce_intel_cmci_poll()) {
1402 iv = mce_adjust_timer(iv);
1403 goto done;
1404 }
1405 }
1406
1407
1408
1409
1410
1411 if (mce_notify_irq())
1412 iv = max(iv / 2, (unsigned long) HZ/100);
1413 else
1414 iv = min(iv * 2, round_jiffies_relative(check_interval * HZ));
1415
1416done:
1417 __this_cpu_write(mce_next_interval, iv);
1418 __start_timer(t, iv);
1419}
1420
1421
1422
1423
1424void mce_timer_kick(unsigned long interval)
1425{
1426 struct timer_list *t = this_cpu_ptr(&mce_timer);
1427 unsigned long iv = __this_cpu_read(mce_next_interval);
1428
1429 __start_timer(t, interval);
1430
1431 if (interval < iv)
1432 __this_cpu_write(mce_next_interval, interval);
1433}
1434
1435
1436static void mce_timer_delete_all(void)
1437{
1438 int cpu;
1439
1440 for_each_online_cpu(cpu)
1441 del_timer_sync(&per_cpu(mce_timer, cpu));
1442}
1443
1444
1445
1446
1447
1448
1449int mce_notify_irq(void)
1450{
1451
1452 static DEFINE_RATELIMIT_STATE(ratelimit, 60*HZ, 2);
1453
1454 if (test_and_clear_bit(0, &mce_need_notify)) {
1455 mce_work_trigger();
1456
1457 if (__ratelimit(&ratelimit))
1458 pr_info(HW_ERR "Machine check events logged\n");
1459
1460 return 1;
1461 }
1462 return 0;
1463}
1464EXPORT_SYMBOL_GPL(mce_notify_irq);
1465
1466static int __mcheck_cpu_mce_banks_init(void)
1467{
1468 int i;
1469
1470 mce_banks = kcalloc(MAX_NR_BANKS, sizeof(struct mce_bank), GFP_KERNEL);
1471 if (!mce_banks)
1472 return -ENOMEM;
1473
1474 for (i = 0; i < MAX_NR_BANKS; i++) {
1475 struct mce_bank *b = &mce_banks[i];
1476
1477 b->ctl = -1ULL;
1478 b->init = 1;
1479 }
1480 return 0;
1481}
1482
1483
1484
1485
1486static int __mcheck_cpu_cap_init(void)
1487{
1488 u64 cap;
1489 u8 b;
1490
1491 rdmsrl(MSR_IA32_MCG_CAP, cap);
1492
1493 b = cap & MCG_BANKCNT_MASK;
1494 if (WARN_ON_ONCE(b > MAX_NR_BANKS))
1495 b = MAX_NR_BANKS;
1496
1497 mca_cfg.banks = max(mca_cfg.banks, b);
1498
1499 if (!mce_banks) {
1500 int err = __mcheck_cpu_mce_banks_init();
1501 if (err)
1502 return err;
1503 }
1504
1505
1506 if ((cap & MCG_EXT_P) && MCG_EXT_CNT(cap) >= 9)
1507 mca_cfg.rip_msr = MSR_IA32_MCG_EIP;
1508
1509 if (cap & MCG_SER_P)
1510 mca_cfg.ser = 1;
1511
1512 return 0;
1513}
1514
1515static void __mcheck_cpu_init_generic(void)
1516{
1517 enum mcp_flags m_fl = 0;
1518 mce_banks_t all_banks;
1519 u64 cap;
1520
1521 if (!mca_cfg.bootlog)
1522 m_fl = MCP_DONTLOG;
1523
1524
1525
1526
1527 bitmap_fill(all_banks, MAX_NR_BANKS);
1528 machine_check_poll(MCP_UC | m_fl, &all_banks);
1529
1530 cr4_set_bits(X86_CR4_MCE);
1531
1532 rdmsrl(MSR_IA32_MCG_CAP, cap);
1533 if (cap & MCG_CTL_P)
1534 wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff);
1535}
1536
1537static void __mcheck_cpu_init_clear_banks(void)
1538{
1539 int i;
1540
1541 for (i = 0; i < mca_cfg.banks; i++) {
1542 struct mce_bank *b = &mce_banks[i];
1543
1544 if (!b->init)
1545 continue;
1546 wrmsrl(msr_ops.ctl(i), b->ctl);
1547 wrmsrl(msr_ops.status(i), 0);
1548 }
1549}
1550
1551
1552
1553
1554
1555
1556
1557
1558
1559static void quirk_sandybridge_ifu(int bank, struct mce *m, struct pt_regs *regs)
1560{
1561 if (bank != 0)
1562 return;
1563 if ((m->mcgstatus & (MCG_STATUS_EIPV|MCG_STATUS_RIPV)) != 0)
1564 return;
1565 if ((m->status & (MCI_STATUS_OVER|MCI_STATUS_UC|
1566 MCI_STATUS_EN|MCI_STATUS_MISCV|MCI_STATUS_ADDRV|
1567 MCI_STATUS_PCC|MCI_STATUS_S|MCI_STATUS_AR|
1568 MCACOD)) !=
1569 (MCI_STATUS_UC|MCI_STATUS_EN|
1570 MCI_STATUS_MISCV|MCI_STATUS_ADDRV|MCI_STATUS_S|
1571 MCI_STATUS_AR|MCACOD_INSTR))
1572 return;
1573
1574 m->mcgstatus |= MCG_STATUS_EIPV;
1575 m->ip = regs->ip;
1576 m->cs = regs->cs;
1577}
1578
1579
1580static int __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c)
1581{
1582 struct mca_config *cfg = &mca_cfg;
1583
1584 if (c->x86_vendor == X86_VENDOR_UNKNOWN) {
1585 pr_info("unknown CPU type - not enabling MCE support\n");
1586 return -EOPNOTSUPP;
1587 }
1588
1589
1590 if (c->x86_vendor == X86_VENDOR_AMD) {
1591 if (c->x86 == 15 && cfg->banks > 4) {
1592
1593
1594
1595
1596
1597 clear_bit(10, (unsigned long *)&mce_banks[4].ctl);
1598 }
1599 if (c->x86 < 0x11 && cfg->bootlog < 0) {
1600
1601
1602
1603
1604 cfg->bootlog = 0;
1605 }
1606
1607
1608
1609
1610 if (c->x86 == 6 && cfg->banks > 0)
1611 mce_banks[0].ctl = 0;
1612
1613
1614
1615
1616
1617 if (c->x86 == 0x15 && c->x86_model <= 0xf)
1618 mce_flags.overflow_recov = 1;
1619
1620 }
1621
1622 if (c->x86_vendor == X86_VENDOR_INTEL) {
1623
1624
1625
1626
1627
1628
1629
1630
1631
1632 if (c->x86 == 6 && c->x86_model < 0x1A && cfg->banks > 0)
1633 mce_banks[0].init = 0;
1634
1635
1636
1637
1638
1639 if ((c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xe)) &&
1640 cfg->monarch_timeout < 0)
1641 cfg->monarch_timeout = USEC_PER_SEC;
1642
1643
1644
1645
1646
1647 if (c->x86 == 6 && c->x86_model <= 13 && cfg->bootlog < 0)
1648 cfg->bootlog = 0;
1649
1650 if (c->x86 == 6 && c->x86_model == 45)
1651 quirk_no_way_out = quirk_sandybridge_ifu;
1652 }
1653 if (cfg->monarch_timeout < 0)
1654 cfg->monarch_timeout = 0;
1655 if (cfg->bootlog != 0)
1656 cfg->panic_timeout = 30;
1657
1658 return 0;
1659}
1660
1661static int __mcheck_cpu_ancient_init(struct cpuinfo_x86 *c)
1662{
1663 if (c->x86 != 5)
1664 return 0;
1665
1666 switch (c->x86_vendor) {
1667 case X86_VENDOR_INTEL:
1668 intel_p5_mcheck_init(c);
1669 return 1;
1670 break;
1671 case X86_VENDOR_CENTAUR:
1672 winchip_mcheck_init(c);
1673 return 1;
1674 break;
1675 default:
1676 return 0;
1677 }
1678
1679 return 0;
1680}
1681
1682
1683
1684
1685static void __mcheck_cpu_init_early(struct cpuinfo_x86 *c)
1686{
1687 if (c->x86_vendor == X86_VENDOR_AMD || c->x86_vendor == X86_VENDOR_HYGON) {
1688 mce_flags.overflow_recov = !!cpu_has(c, X86_FEATURE_OVERFLOW_RECOV);
1689 mce_flags.succor = !!cpu_has(c, X86_FEATURE_SUCCOR);
1690 mce_flags.smca = !!cpu_has(c, X86_FEATURE_SMCA);
1691
1692 if (mce_flags.smca) {
1693 msr_ops.ctl = smca_ctl_reg;
1694 msr_ops.status = smca_status_reg;
1695 msr_ops.addr = smca_addr_reg;
1696 msr_ops.misc = smca_misc_reg;
1697 }
1698 }
1699}
1700
1701static void mce_centaur_feature_init(struct cpuinfo_x86 *c)
1702{
1703 struct mca_config *cfg = &mca_cfg;
1704
1705
1706
1707
1708
1709 if ((c->x86 == 6 && c->x86_model == 0xf && c->x86_stepping >= 0xe) ||
1710 c->x86 > 6) {
1711 if (cfg->monarch_timeout < 0)
1712 cfg->monarch_timeout = USEC_PER_SEC;
1713 }
1714}
1715
1716static void __mcheck_cpu_init_vendor(struct cpuinfo_x86 *c)
1717{
1718 switch (c->x86_vendor) {
1719 case X86_VENDOR_INTEL:
1720 mce_intel_feature_init(c);
1721 mce_adjust_timer = cmci_intel_adjust_timer;
1722 break;
1723
1724 case X86_VENDOR_AMD: {
1725 mce_amd_feature_init(c);
1726 break;
1727 }
1728
1729 case X86_VENDOR_HYGON:
1730 mce_hygon_feature_init(c);
1731 break;
1732
1733 case X86_VENDOR_CENTAUR:
1734 mce_centaur_feature_init(c);
1735 break;
1736
1737 default:
1738 break;
1739 }
1740}
1741
1742static void __mcheck_cpu_clear_vendor(struct cpuinfo_x86 *c)
1743{
1744 switch (c->x86_vendor) {
1745 case X86_VENDOR_INTEL:
1746 mce_intel_feature_clear(c);
1747 break;
1748 default:
1749 break;
1750 }
1751}
1752
1753static void mce_start_timer(struct timer_list *t)
1754{
1755 unsigned long iv = check_interval * HZ;
1756
1757 if (mca_cfg.ignore_ce || !iv)
1758 return;
1759
1760 this_cpu_write(mce_next_interval, iv);
1761 __start_timer(t, iv);
1762}
1763
1764static void __mcheck_cpu_setup_timer(void)
1765{
1766 struct timer_list *t = this_cpu_ptr(&mce_timer);
1767
1768 timer_setup(t, mce_timer_fn, TIMER_PINNED);
1769}
1770
1771static void __mcheck_cpu_init_timer(void)
1772{
1773 struct timer_list *t = this_cpu_ptr(&mce_timer);
1774
1775 timer_setup(t, mce_timer_fn, TIMER_PINNED);
1776 mce_start_timer(t);
1777}
1778
1779bool filter_mce(struct mce *m)
1780{
1781 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
1782 return amd_filter_mce(m);
1783
1784 return false;
1785}
1786
1787
1788static void unexpected_machine_check(struct pt_regs *regs, long error_code)
1789{
1790 pr_err("CPU#%d: Unexpected int18 (Machine Check)\n",
1791 smp_processor_id());
1792}
1793
1794
1795void (*machine_check_vector)(struct pt_regs *, long error_code) =
1796 unexpected_machine_check;
1797
1798dotraplinkage void do_mce(struct pt_regs *regs, long error_code)
1799{
1800 machine_check_vector(regs, error_code);
1801}
1802
1803
1804
1805
1806
1807void mcheck_cpu_init(struct cpuinfo_x86 *c)
1808{
1809 if (mca_cfg.disabled)
1810 return;
1811
1812 if (__mcheck_cpu_ancient_init(c))
1813 return;
1814
1815 if (!mce_available(c))
1816 return;
1817
1818 if (__mcheck_cpu_cap_init() < 0 || __mcheck_cpu_apply_quirks(c) < 0) {
1819 mca_cfg.disabled = 1;
1820 return;
1821 }
1822
1823 if (mce_gen_pool_init()) {
1824 mca_cfg.disabled = 1;
1825 pr_emerg("Couldn't allocate MCE records pool!\n");
1826 return;
1827 }
1828
1829 machine_check_vector = do_machine_check;
1830
1831 __mcheck_cpu_init_early(c);
1832 __mcheck_cpu_init_generic();
1833 __mcheck_cpu_init_vendor(c);
1834 __mcheck_cpu_init_clear_banks();
1835 __mcheck_cpu_setup_timer();
1836}
1837
1838
1839
1840
1841void mcheck_cpu_clear(struct cpuinfo_x86 *c)
1842{
1843 if (mca_cfg.disabled)
1844 return;
1845
1846 if (!mce_available(c))
1847 return;
1848
1849
1850
1851
1852
1853 __mcheck_cpu_clear_vendor(c);
1854
1855}
1856
1857static void __mce_disable_bank(void *arg)
1858{
1859 int bank = *((int *)arg);
1860 __clear_bit(bank, this_cpu_ptr(mce_poll_banks));
1861 cmci_disable_bank(bank);
1862}
1863
1864void mce_disable_bank(int bank)
1865{
1866 if (bank >= mca_cfg.banks) {
1867 pr_warn(FW_BUG
1868 "Ignoring request to disable invalid MCA bank %d.\n",
1869 bank);
1870 return;
1871 }
1872 set_bit(bank, mce_banks_ce_disabled);
1873 on_each_cpu(__mce_disable_bank, &bank, 1);
1874}
1875
1876
1877
1878
1879
1880
1881
1882
1883
1884
1885
1886
1887
1888
1889
1890
1891static int __init mcheck_enable(char *str)
1892{
1893 struct mca_config *cfg = &mca_cfg;
1894
1895 if (*str == 0) {
1896 enable_p5_mce();
1897 return 1;
1898 }
1899 if (*str == '=')
1900 str++;
1901 if (!strcmp(str, "off"))
1902 cfg->disabled = 1;
1903 else if (!strcmp(str, "no_cmci"))
1904 cfg->cmci_disabled = true;
1905 else if (!strcmp(str, "no_lmce"))
1906 cfg->lmce_disabled = 1;
1907 else if (!strcmp(str, "dont_log_ce"))
1908 cfg->dont_log_ce = true;
1909 else if (!strcmp(str, "ignore_ce"))
1910 cfg->ignore_ce = true;
1911 else if (!strcmp(str, "bootlog") || !strcmp(str, "nobootlog"))
1912 cfg->bootlog = (str[0] == 'b');
1913 else if (!strcmp(str, "bios_cmci_threshold"))
1914 cfg->bios_cmci_threshold = 1;
1915 else if (!strcmp(str, "recovery"))
1916 cfg->recovery = 1;
1917 else if (isdigit(str[0])) {
1918 if (get_option(&str, &cfg->tolerant) == 2)
1919 get_option(&str, &(cfg->monarch_timeout));
1920 } else {
1921 pr_info("mce argument %s ignored. Please use /sys\n", str);
1922 return 0;
1923 }
1924 return 1;
1925}
1926__setup("mce", mcheck_enable);
1927
1928int __init mcheck_init(void)
1929{
1930 mcheck_intel_therm_init();
1931 mce_register_decode_chain(&first_nb);
1932 mce_register_decode_chain(&mce_srao_nb);
1933 mce_register_decode_chain(&mce_default_nb);
1934 mcheck_vendor_init_severity();
1935
1936 INIT_WORK(&mce_work, mce_gen_pool_process);
1937 init_irq_work(&mce_irq_work, mce_irq_work_cb);
1938
1939 return 0;
1940}
1941
1942
1943
1944
1945
1946
1947
1948
1949
1950static void mce_disable_error_reporting(void)
1951{
1952 int i;
1953
1954 for (i = 0; i < mca_cfg.banks; i++) {
1955 struct mce_bank *b = &mce_banks[i];
1956
1957 if (b->init)
1958 wrmsrl(msr_ops.ctl(i), 0);
1959 }
1960 return;
1961}
1962
1963static void vendor_disable_error_reporting(void)
1964{
1965
1966
1967
1968
1969
1970
1971
1972 if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL ||
1973 boot_cpu_data.x86_vendor == X86_VENDOR_HYGON ||
1974 boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
1975 return;
1976
1977 mce_disable_error_reporting();
1978}
1979
1980static int mce_syscore_suspend(void)
1981{
1982 vendor_disable_error_reporting();
1983 return 0;
1984}
1985
1986static void mce_syscore_shutdown(void)
1987{
1988 vendor_disable_error_reporting();
1989}
1990
1991
1992
1993
1994
1995
1996static void mce_syscore_resume(void)
1997{
1998 __mcheck_cpu_init_generic();
1999 __mcheck_cpu_init_vendor(raw_cpu_ptr(&cpu_info));
2000 __mcheck_cpu_init_clear_banks();
2001}
2002
2003static struct syscore_ops mce_syscore_ops = {
2004 .suspend = mce_syscore_suspend,
2005 .shutdown = mce_syscore_shutdown,
2006 .resume = mce_syscore_resume,
2007};
2008
2009
2010
2011
2012
2013static void mce_cpu_restart(void *data)
2014{
2015 if (!mce_available(raw_cpu_ptr(&cpu_info)))
2016 return;
2017 __mcheck_cpu_init_generic();
2018 __mcheck_cpu_init_clear_banks();
2019 __mcheck_cpu_init_timer();
2020}
2021
2022
2023static void mce_restart(void)
2024{
2025 mce_timer_delete_all();
2026 on_each_cpu(mce_cpu_restart, NULL, 1);
2027}
2028
2029
2030static void mce_disable_cmci(void *data)
2031{
2032 if (!mce_available(raw_cpu_ptr(&cpu_info)))
2033 return;
2034 cmci_clear();
2035}
2036
2037static void mce_enable_ce(void *all)
2038{
2039 if (!mce_available(raw_cpu_ptr(&cpu_info)))
2040 return;
2041 cmci_reenable();
2042 cmci_recheck();
2043 if (all)
2044 __mcheck_cpu_init_timer();
2045}
2046
2047static struct bus_type mce_subsys = {
2048 .name = "machinecheck",
2049 .dev_name = "machinecheck",
2050};
2051
2052DEFINE_PER_CPU(struct device *, mce_device);
2053
2054static inline struct mce_bank *attr_to_bank(struct device_attribute *attr)
2055{
2056 return container_of(attr, struct mce_bank, attr);
2057}
2058
2059static ssize_t show_bank(struct device *s, struct device_attribute *attr,
2060 char *buf)
2061{
2062 return sprintf(buf, "%llx\n", attr_to_bank(attr)->ctl);
2063}
2064
2065static ssize_t set_bank(struct device *s, struct device_attribute *attr,
2066 const char *buf, size_t size)
2067{
2068 u64 new;
2069
2070 if (kstrtou64(buf, 0, &new) < 0)
2071 return -EINVAL;
2072
2073 attr_to_bank(attr)->ctl = new;
2074 mce_restart();
2075
2076 return size;
2077}
2078
2079static ssize_t set_ignore_ce(struct device *s,
2080 struct device_attribute *attr,
2081 const char *buf, size_t size)
2082{
2083 u64 new;
2084
2085 if (kstrtou64(buf, 0, &new) < 0)
2086 return -EINVAL;
2087
2088 mutex_lock(&mce_sysfs_mutex);
2089 if (mca_cfg.ignore_ce ^ !!new) {
2090 if (new) {
2091
2092 mce_timer_delete_all();
2093 on_each_cpu(mce_disable_cmci, NULL, 1);
2094 mca_cfg.ignore_ce = true;
2095 } else {
2096
2097 mca_cfg.ignore_ce = false;
2098 on_each_cpu(mce_enable_ce, (void *)1, 1);
2099 }
2100 }
2101 mutex_unlock(&mce_sysfs_mutex);
2102
2103 return size;
2104}
2105
2106static ssize_t set_cmci_disabled(struct device *s,
2107 struct device_attribute *attr,
2108 const char *buf, size_t size)
2109{
2110 u64 new;
2111
2112 if (kstrtou64(buf, 0, &new) < 0)
2113 return -EINVAL;
2114
2115 mutex_lock(&mce_sysfs_mutex);
2116 if (mca_cfg.cmci_disabled ^ !!new) {
2117 if (new) {
2118
2119 on_each_cpu(mce_disable_cmci, NULL, 1);
2120 mca_cfg.cmci_disabled = true;
2121 } else {
2122
2123 mca_cfg.cmci_disabled = false;
2124 on_each_cpu(mce_enable_ce, NULL, 1);
2125 }
2126 }
2127 mutex_unlock(&mce_sysfs_mutex);
2128
2129 return size;
2130}
2131
2132static ssize_t store_int_with_restart(struct device *s,
2133 struct device_attribute *attr,
2134 const char *buf, size_t size)
2135{
2136 unsigned long old_check_interval = check_interval;
2137 ssize_t ret = device_store_ulong(s, attr, buf, size);
2138
2139 if (check_interval == old_check_interval)
2140 return ret;
2141
2142 mutex_lock(&mce_sysfs_mutex);
2143 mce_restart();
2144 mutex_unlock(&mce_sysfs_mutex);
2145
2146 return ret;
2147}
2148
2149static DEVICE_INT_ATTR(tolerant, 0644, mca_cfg.tolerant);
2150static DEVICE_INT_ATTR(monarch_timeout, 0644, mca_cfg.monarch_timeout);
2151static DEVICE_BOOL_ATTR(dont_log_ce, 0644, mca_cfg.dont_log_ce);
2152
2153static struct dev_ext_attribute dev_attr_check_interval = {
2154 __ATTR(check_interval, 0644, device_show_int, store_int_with_restart),
2155 &check_interval
2156};
2157
2158static struct dev_ext_attribute dev_attr_ignore_ce = {
2159 __ATTR(ignore_ce, 0644, device_show_bool, set_ignore_ce),
2160 &mca_cfg.ignore_ce
2161};
2162
2163static struct dev_ext_attribute dev_attr_cmci_disabled = {
2164 __ATTR(cmci_disabled, 0644, device_show_bool, set_cmci_disabled),
2165 &mca_cfg.cmci_disabled
2166};
2167
2168static struct device_attribute *mce_device_attrs[] = {
2169 &dev_attr_tolerant.attr,
2170 &dev_attr_check_interval.attr,
2171#ifdef CONFIG_X86_MCELOG_LEGACY
2172 &dev_attr_trigger,
2173#endif
2174 &dev_attr_monarch_timeout.attr,
2175 &dev_attr_dont_log_ce.attr,
2176 &dev_attr_ignore_ce.attr,
2177 &dev_attr_cmci_disabled.attr,
2178 NULL
2179};
2180
2181static cpumask_var_t mce_device_initialized;
2182
2183static void mce_device_release(struct device *dev)
2184{
2185 kfree(dev);
2186}
2187
2188
2189static int mce_device_create(unsigned int cpu)
2190{
2191 struct device *dev;
2192 int err;
2193 int i, j;
2194
2195 if (!mce_available(&boot_cpu_data))
2196 return -EIO;
2197
2198 dev = per_cpu(mce_device, cpu);
2199 if (dev)
2200 return 0;
2201
2202 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
2203 if (!dev)
2204 return -ENOMEM;
2205 dev->id = cpu;
2206 dev->bus = &mce_subsys;
2207 dev->release = &mce_device_release;
2208
2209 err = device_register(dev);
2210 if (err) {
2211 put_device(dev);
2212 return err;
2213 }
2214
2215 for (i = 0; mce_device_attrs[i]; i++) {
2216 err = device_create_file(dev, mce_device_attrs[i]);
2217 if (err)
2218 goto error;
2219 }
2220 for (j = 0; j < mca_cfg.banks; j++) {
2221 err = device_create_file(dev, &mce_banks[j].attr);
2222 if (err)
2223 goto error2;
2224 }
2225 cpumask_set_cpu(cpu, mce_device_initialized);
2226 per_cpu(mce_device, cpu) = dev;
2227
2228 return 0;
2229error2:
2230 while (--j >= 0)
2231 device_remove_file(dev, &mce_banks[j].attr);
2232error:
2233 while (--i >= 0)
2234 device_remove_file(dev, mce_device_attrs[i]);
2235
2236 device_unregister(dev);
2237
2238 return err;
2239}
2240
2241static void mce_device_remove(unsigned int cpu)
2242{
2243 struct device *dev = per_cpu(mce_device, cpu);
2244 int i;
2245
2246 if (!cpumask_test_cpu(cpu, mce_device_initialized))
2247 return;
2248
2249 for (i = 0; mce_device_attrs[i]; i++)
2250 device_remove_file(dev, mce_device_attrs[i]);
2251
2252 for (i = 0; i < mca_cfg.banks; i++)
2253 device_remove_file(dev, &mce_banks[i].attr);
2254
2255 device_unregister(dev);
2256 cpumask_clear_cpu(cpu, mce_device_initialized);
2257 per_cpu(mce_device, cpu) = NULL;
2258}
2259
2260
2261static void mce_disable_cpu(void)
2262{
2263 if (!mce_available(raw_cpu_ptr(&cpu_info)))
2264 return;
2265
2266 if (!cpuhp_tasks_frozen)
2267 cmci_clear();
2268
2269 vendor_disable_error_reporting();
2270}
2271
2272static void mce_reenable_cpu(void)
2273{
2274 int i;
2275
2276 if (!mce_available(raw_cpu_ptr(&cpu_info)))
2277 return;
2278
2279 if (!cpuhp_tasks_frozen)
2280 cmci_reenable();
2281 for (i = 0; i < mca_cfg.banks; i++) {
2282 struct mce_bank *b = &mce_banks[i];
2283
2284 if (b->init)
2285 wrmsrl(msr_ops.ctl(i), b->ctl);
2286 }
2287}
2288
2289static int mce_cpu_dead(unsigned int cpu)
2290{
2291 mce_intel_hcpu_update(cpu);
2292
2293
2294 if (!cpuhp_tasks_frozen)
2295 cmci_rediscover();
2296 return 0;
2297}
2298
2299static int mce_cpu_online(unsigned int cpu)
2300{
2301 struct timer_list *t = this_cpu_ptr(&mce_timer);
2302 int ret;
2303
2304 mce_device_create(cpu);
2305
2306 ret = mce_threshold_create_device(cpu);
2307 if (ret) {
2308 mce_device_remove(cpu);
2309 return ret;
2310 }
2311 mce_reenable_cpu();
2312 mce_start_timer(t);
2313 return 0;
2314}
2315
2316static int mce_cpu_pre_down(unsigned int cpu)
2317{
2318 struct timer_list *t = this_cpu_ptr(&mce_timer);
2319
2320 mce_disable_cpu();
2321 del_timer_sync(t);
2322 mce_threshold_remove_device(cpu);
2323 mce_device_remove(cpu);
2324 return 0;
2325}
2326
2327static __init void mce_init_banks(void)
2328{
2329 int i;
2330
2331 for (i = 0; i < mca_cfg.banks; i++) {
2332 struct mce_bank *b = &mce_banks[i];
2333 struct device_attribute *a = &b->attr;
2334
2335 sysfs_attr_init(&a->attr);
2336 a->attr.name = b->attrname;
2337 snprintf(b->attrname, ATTR_LEN, "bank%d", i);
2338
2339 a->attr.mode = 0644;
2340 a->show = show_bank;
2341 a->store = set_bank;
2342 }
2343}
2344
2345static __init int mcheck_init_device(void)
2346{
2347 int err;
2348
2349
2350
2351
2352
2353 MAYBE_BUILD_BUG_ON(__VIRTUAL_MASK_SHIFT >= 63);
2354
2355 if (!mce_available(&boot_cpu_data)) {
2356 err = -EIO;
2357 goto err_out;
2358 }
2359
2360 if (!zalloc_cpumask_var(&mce_device_initialized, GFP_KERNEL)) {
2361 err = -ENOMEM;
2362 goto err_out;
2363 }
2364
2365 mce_init_banks();
2366
2367 err = subsys_system_register(&mce_subsys, NULL);
2368 if (err)
2369 goto err_out_mem;
2370
2371 err = cpuhp_setup_state(CPUHP_X86_MCE_DEAD, "x86/mce:dead", NULL,
2372 mce_cpu_dead);
2373 if (err)
2374 goto err_out_mem;
2375
2376 err = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "x86/mce:online",
2377 mce_cpu_online, mce_cpu_pre_down);
2378 if (err < 0)
2379 goto err_out_online;
2380
2381 register_syscore_ops(&mce_syscore_ops);
2382
2383 return 0;
2384
2385err_out_online:
2386 cpuhp_remove_state(CPUHP_X86_MCE_DEAD);
2387
2388err_out_mem:
2389 free_cpumask_var(mce_device_initialized);
2390
2391err_out:
2392 pr_err("Unable to init MCE device (rc: %d)\n", err);
2393
2394 return err;
2395}
2396device_initcall_sync(mcheck_init_device);
2397
2398
2399
2400
2401static int __init mcheck_disable(char *str)
2402{
2403 mca_cfg.disabled = 1;
2404 return 1;
2405}
2406__setup("nomce", mcheck_disable);
2407
2408#ifdef CONFIG_DEBUG_FS
2409struct dentry *mce_get_debugfs_dir(void)
2410{
2411 static struct dentry *dmce;
2412
2413 if (!dmce)
2414 dmce = debugfs_create_dir("mce", NULL);
2415
2416 return dmce;
2417}
2418
2419static void mce_reset(void)
2420{
2421 cpu_missing = 0;
2422 atomic_set(&mce_fake_panicked, 0);
2423 atomic_set(&mce_executing, 0);
2424 atomic_set(&mce_callin, 0);
2425 atomic_set(&global_nwo, 0);
2426}
2427
2428static int fake_panic_get(void *data, u64 *val)
2429{
2430 *val = fake_panic;
2431 return 0;
2432}
2433
2434static int fake_panic_set(void *data, u64 val)
2435{
2436 mce_reset();
2437 fake_panic = val;
2438 return 0;
2439}
2440
2441DEFINE_DEBUGFS_ATTRIBUTE(fake_panic_fops, fake_panic_get, fake_panic_set,
2442 "%llu\n");
2443
2444static int __init mcheck_debugfs_init(void)
2445{
2446 struct dentry *dmce, *ffake_panic;
2447
2448 dmce = mce_get_debugfs_dir();
2449 if (!dmce)
2450 return -ENOMEM;
2451 ffake_panic = debugfs_create_file_unsafe("fake_panic", 0444, dmce,
2452 NULL, &fake_panic_fops);
2453 if (!ffake_panic)
2454 return -ENOMEM;
2455
2456 return 0;
2457}
2458#else
2459static int __init mcheck_debugfs_init(void) { return -EINVAL; }
2460#endif
2461
2462DEFINE_STATIC_KEY_FALSE(mcsafe_key);
2463EXPORT_SYMBOL_GPL(mcsafe_key);
2464
2465static int __init mcheck_late_init(void)
2466{
2467 pr_info("Using %d MCE banks\n", mca_cfg.banks);
2468
2469 if (mca_cfg.recovery)
2470 static_branch_inc(&mcsafe_key);
2471
2472 mcheck_debugfs_init();
2473 cec_init();
2474
2475
2476
2477
2478
2479 mce_schedule_work();
2480
2481 return 0;
2482}
2483late_initcall(mcheck_late_init);
2484