1
2
3
4
5
6#include <linux/interrupt.h>
7#include <linux/kernel.h>
8#include <linux/types.h>
9#include <linux/smp.h>
10
11#include <asm/processor.h>
12#include <asm/traps.h>
13#include <asm/tlbflush.h>
14#include <asm/mce.h>
15#include <asm/msr.h>
16
17#include "internal.h"
18
19
20int mce_p5_enabled __read_mostly;
21
22
23static void pentium_machine_check(struct pt_regs *regs, long error_code)
24{
25 u32 loaddr, hi, lotype;
26
27 ist_enter(regs);
28
29 rdmsr(MSR_IA32_P5_MC_ADDR, loaddr, hi);
30 rdmsr(MSR_IA32_P5_MC_TYPE, lotype, hi);
31
32 pr_emerg("CPU#%d: Machine Check Exception: 0x%8X (type 0x%8X).\n",
33 smp_processor_id(), loaddr, lotype);
34
35 if (lotype & (1<<5)) {
36 pr_emerg("CPU#%d: Possible thermal failure (CPU on fire ?).\n",
37 smp_processor_id());
38 }
39
40 add_taint(TAINT_MACHINE_CHECK, LOCKDEP_NOW_UNRELIABLE);
41
42 ist_exit(regs);
43}
44
45
46void intel_p5_mcheck_init(struct cpuinfo_x86 *c)
47{
48 u32 l, h;
49
50
51 if (!mce_p5_enabled)
52 return;
53
54
55 if (!cpu_has(c, X86_FEATURE_MCE))
56 return;
57
58 machine_check_vector = pentium_machine_check;
59
60 wmb();
61
62
63 rdmsr(MSR_IA32_P5_MC_ADDR, l, h);
64 rdmsr(MSR_IA32_P5_MC_TYPE, l, h);
65 pr_info("Intel old style machine check architecture supported.\n");
66
67
68 cr4_set_bits(X86_CR4_MCE);
69 pr_info("Intel old style machine check reporting enabled on CPU#%d.\n",
70 smp_processor_id());
71}
72