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69#include <linux/kernel.h>
70#include <linux/module.h>
71#include <linux/pci.h>
72#include <linux/init.h>
73#include <linux/blkdev.h>
74#include <linux/delay.h>
75#include <linux/device.h>
76#include <linux/gfp.h>
77#include <scsi/scsi_host.h>
78#include <linux/libata.h>
79#include <linux/dmi.h>
80
81#define DRV_NAME "ata_piix"
82#define DRV_VERSION "2.13"
83
84enum {
85 PIIX_IOCFG = 0x54,
86 ICH5_PMR = 0x90,
87 ICH5_PCS = 0x92,
88 PIIX_SIDPR_BAR = 5,
89 PIIX_SIDPR_LEN = 16,
90 PIIX_SIDPR_IDX = 0,
91 PIIX_SIDPR_DATA = 4,
92
93 PIIX_FLAG_CHECKINTR = (1 << 28),
94 PIIX_FLAG_SIDPR = (1 << 29),
95
96 PIIX_PATA_FLAGS = ATA_FLAG_SLAVE_POSS,
97 PIIX_SATA_FLAGS = ATA_FLAG_SATA | PIIX_FLAG_CHECKINTR,
98
99 PIIX_FLAG_PIO16 = (1 << 30),
100
101 PIIX_80C_PRI = (1 << 5) | (1 << 4),
102 PIIX_80C_SEC = (1 << 7) | (1 << 6),
103
104
105 P0 = 0,
106 P1 = 1,
107 P2 = 2,
108 P3 = 3,
109 IDE = -1,
110 NA = -2,
111 RV = -3,
112
113 PIIX_AHCI_DEVICE = 6,
114
115
116 PIIX_HOST_BROKEN_SUSPEND = (1 << 24),
117};
118
119enum piix_controller_ids {
120
121 piix_pata_mwdma,
122 piix_pata_33,
123 ich_pata_33,
124 ich_pata_66,
125 ich_pata_100,
126 ich_pata_100_nomwdma1,
127 ich5_sata,
128 ich6_sata,
129 ich6m_sata,
130 ich8_sata,
131 ich8_2port_sata,
132 ich8m_apple_sata,
133 tolapai_sata,
134 piix_pata_vmw,
135 ich8_sata_snb,
136 ich8_2port_sata_snb,
137 ich8_2port_sata_byt,
138};
139
140struct piix_map_db {
141 const u32 mask;
142 const u16 port_enable;
143 const int map[][4];
144};
145
146struct piix_host_priv {
147 const int *map;
148 u32 saved_iocfg;
149 void __iomem *sidpr;
150};
151
152static unsigned int in_module_init = 1;
153
154static const struct pci_device_id piix_pci_tbl[] = {
155
156 { 0x8086, 0x7010, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_mwdma },
157
158 { 0x8086, 0x7111, 0x15ad, 0x1976, 0, 0, piix_pata_vmw },
159
160
161 { 0x8086, 0x7111, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
162
163 { 0x8086, 0x7199, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
164
165 { 0x8086, 0x7601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
166
167 { 0x8086, 0x84CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
168
169 { 0x8086, 0x2411, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_66 },
170
171 { 0x8086, 0x2421, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_33 },
172
173 { 0x8086, 0x244A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
174
175 { 0x8086, 0x244B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
176
177 { 0x8086, 0x248A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
178
179 { 0x8086, 0x248B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
180
181 { 0x8086, 0x24C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
182
183 { 0x8086, 0x24CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
184 { 0x8086, 0x24CB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
185
186 { 0x8086, 0x24DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
187
188 { 0x8086, 0x245B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
189
190 { 0x8086, 0x25A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
191
192 { 0x8086, 0x266F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
193
194 { 0x8086, 0x27DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100_nomwdma1 },
195 { 0x8086, 0x269E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100_nomwdma1 },
196
197 { 0x8086, 0x2850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
198
199
200
201
202 { 0x8086, 0x24d1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
203
204 { 0x8086, 0x24df, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
205
206 { 0x8086, 0x25a3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
207
208 { 0x8086, 0x25b0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
209
210 { 0x8086, 0x2651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
211
212 { 0x8086, 0x2652, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
213
214
215 { 0x8086, 0x2653, PCI_ANY_ID, PCI_ANY_ID,
216 PCI_CLASS_STORAGE_IDE << 8, 0xffff00, ich6m_sata },
217
218 { 0x8086, 0x27c0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
219
220 { 0x8086, 0x27c4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata },
221
222 { 0x8086, 0x2680, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
223
224 { 0x8086, 0x2820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
225
226 { 0x8086, 0x2825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
227
228 { 0x8086, 0x2828, 0x106b, 0x00a0, 0, 0, ich8m_apple_sata },
229 { 0x8086, 0x2828, 0x106b, 0x00a1, 0, 0, ich8m_apple_sata },
230 { 0x8086, 0x2828, 0x106b, 0x00a3, 0, 0, ich8m_apple_sata },
231
232 { 0x8086, 0x2828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
233
234 { 0x8086, 0x2920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
235
236 { 0x8086, 0x2921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
237
238 { 0x8086, 0x2926, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
239
240 { 0x8086, 0x2928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
241
242 { 0x8086, 0x292d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
243
244 { 0x8086, 0x292e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
245
246 { 0x8086, 0x5028, PCI_ANY_ID, PCI_ANY_ID, 0, 0, tolapai_sata },
247
248 { 0x8086, 0x3a00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
249
250 { 0x8086, 0x3a06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
251
252 { 0x8086, 0x3a20, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
253
254 { 0x8086, 0x3a26, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
255
256 { 0x8086, 0x3b20, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
257
258 { 0x8086, 0x3b21, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
259
260 { 0x8086, 0x3b26, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
261
262 { 0x8086, 0x3b28, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
263
264 { 0x8086, 0x3b2d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
265
266 { 0x8086, 0x3b2e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
267
268 { 0x8086, 0x1c00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
269
270 { 0x8086, 0x1c01, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
271
272 { 0x8086, 0x1c08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
273
274 { 0x8086, 0x1c09, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
275
276 { 0x8086, 0x1d00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
277
278 { 0x8086, 0x1d08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
279
280 { 0x8086, 0x1e00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
281
282 { 0x8086, 0x1e01, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
283
284 { 0x8086, 0x1e08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
285
286 { 0x8086, 0x1e09, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
287
288 { 0x8086, 0x8c00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
289
290 { 0x8086, 0x8c01, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
291
292 { 0x8086, 0x8c08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata_snb },
293
294 { 0x8086, 0x8c09, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
295
296 { 0x8086, 0x9c00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
297
298 { 0x8086, 0x9c01, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
299
300 { 0x8086, 0x9c08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
301
302 { 0x8086, 0x9c09, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
303
304 { 0x8086, 0x2326, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
305
306 { 0x8086, 0x1f20, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
307
308 { 0x8086, 0x1f21, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
309
310 { 0x8086, 0x1f30, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
311
312 { 0x8086, 0x1f31, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
313
314 { 0x8086, 0x8d00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
315
316 { 0x8086, 0x8d08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata_snb },
317
318 { 0x8086, 0x8d60, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
319
320 { 0x8086, 0x8d68, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
321
322 { 0x8086, 0x0F20, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata_byt },
323 { 0x8086, 0x0F21, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata_byt },
324
325 { 0x8086, 0x23a6, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
326
327 { 0x8086, 0x8c88, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata_snb },
328
329 { 0x8086, 0x8c89, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata_snb },
330
331 { 0x8086, 0x8c80, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
332
333 { 0x8086, 0x8c81, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
334
335 { }
336};
337
338static const struct piix_map_db ich5_map_db = {
339 .mask = 0x7,
340 .port_enable = 0x3,
341 .map = {
342
343 { P0, NA, P1, NA },
344 { P1, NA, P0, NA },
345 { RV, RV, RV, RV },
346 { RV, RV, RV, RV },
347 { P0, P1, IDE, IDE },
348 { P1, P0, IDE, IDE },
349 { IDE, IDE, P0, P1 },
350 { IDE, IDE, P1, P0 },
351 },
352};
353
354static const struct piix_map_db ich6_map_db = {
355 .mask = 0x3,
356 .port_enable = 0xf,
357 .map = {
358
359 { P0, P2, P1, P3 },
360 { IDE, IDE, P1, P3 },
361 { P0, P2, IDE, IDE },
362 { RV, RV, RV, RV },
363 },
364};
365
366static const struct piix_map_db ich6m_map_db = {
367 .mask = 0x3,
368 .port_enable = 0x5,
369
370
371
372
373
374 .map = {
375
376 { P0, P2, NA, NA },
377 { IDE, IDE, P1, P3 },
378 { P0, P2, IDE, IDE },
379 { RV, RV, RV, RV },
380 },
381};
382
383static const struct piix_map_db ich8_map_db = {
384 .mask = 0x3,
385 .port_enable = 0xf,
386 .map = {
387
388 { P0, P2, P1, P3 },
389 { RV, RV, RV, RV },
390 { P0, P2, IDE, IDE },
391 { RV, RV, RV, RV },
392 },
393};
394
395static const struct piix_map_db ich8_2port_map_db = {
396 .mask = 0x3,
397 .port_enable = 0x3,
398 .map = {
399
400 { P0, NA, P1, NA },
401 { RV, RV, RV, RV },
402 { RV, RV, RV, RV },
403 { RV, RV, RV, RV },
404 },
405};
406
407static const struct piix_map_db ich8m_apple_map_db = {
408 .mask = 0x3,
409 .port_enable = 0x1,
410 .map = {
411
412 { P0, NA, NA, NA },
413 { RV, RV, RV, RV },
414 { P0, P2, IDE, IDE },
415 { RV, RV, RV, RV },
416 },
417};
418
419static const struct piix_map_db tolapai_map_db = {
420 .mask = 0x3,
421 .port_enable = 0x3,
422 .map = {
423
424 { P0, NA, P1, NA },
425 { RV, RV, RV, RV },
426 { RV, RV, RV, RV },
427 { RV, RV, RV, RV },
428 },
429};
430
431static const struct piix_map_db *piix_map_db_table[] = {
432 [ich5_sata] = &ich5_map_db,
433 [ich6_sata] = &ich6_map_db,
434 [ich6m_sata] = &ich6m_map_db,
435 [ich8_sata] = &ich8_map_db,
436 [ich8_2port_sata] = &ich8_2port_map_db,
437 [ich8m_apple_sata] = &ich8m_apple_map_db,
438 [tolapai_sata] = &tolapai_map_db,
439 [ich8_sata_snb] = &ich8_map_db,
440 [ich8_2port_sata_snb] = &ich8_2port_map_db,
441 [ich8_2port_sata_byt] = &ich8_2port_map_db,
442};
443
444static const struct pci_bits piix_enable_bits[] = {
445 { 0x41U, 1U, 0x80UL, 0x80UL },
446 { 0x43U, 1U, 0x80UL, 0x80UL },
447};
448
449MODULE_AUTHOR("Andre Hedrick, Alan Cox, Andrzej Krzysztofowicz, Jeff Garzik");
450MODULE_DESCRIPTION("SCSI low-level driver for Intel PIIX/ICH ATA controllers");
451MODULE_LICENSE("GPL");
452MODULE_DEVICE_TABLE(pci, piix_pci_tbl);
453MODULE_VERSION(DRV_VERSION);
454
455struct ich_laptop {
456 u16 device;
457 u16 subvendor;
458 u16 subdevice;
459};
460
461
462
463
464
465static const struct ich_laptop ich_laptop[] = {
466
467 { 0x27DF, 0x0005, 0x0280 },
468 { 0x27DF, 0x1025, 0x0102 },
469 { 0x27DF, 0x1025, 0x0110 },
470 { 0x27DF, 0x1028, 0x02b0 },
471 { 0x27DF, 0x1043, 0x1267 },
472 { 0x27DF, 0x103C, 0x30A1 },
473 { 0x27DF, 0x103C, 0x361a },
474 { 0x27DF, 0x1071, 0xD221 },
475 { 0x27DF, 0x152D, 0x0778 },
476 { 0x24CA, 0x1025, 0x0061 },
477 { 0x24CA, 0x1025, 0x003d },
478 { 0x24CA, 0x10CF, 0x11AB },
479 { 0x266F, 0x1025, 0x0066 },
480 { 0x2653, 0x1043, 0x82D8 },
481 { 0x27df, 0x104d, 0x900e },
482
483 { 0, }
484};
485
486static int piix_port_start(struct ata_port *ap)
487{
488 if (!(ap->flags & PIIX_FLAG_PIO16))
489 ap->pflags |= ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE;
490
491 return ata_bmdma_port_start(ap);
492}
493
494
495
496
497
498
499
500
501
502
503
504
505static int ich_pata_cable_detect(struct ata_port *ap)
506{
507 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
508 struct piix_host_priv *hpriv = ap->host->private_data;
509 const struct ich_laptop *lap = &ich_laptop[0];
510 u8 mask;
511
512
513 while (lap->device) {
514 if (lap->device == pdev->device &&
515 lap->subvendor == pdev->subsystem_vendor &&
516 lap->subdevice == pdev->subsystem_device)
517 return ATA_CBL_PATA40_SHORT;
518
519 lap++;
520 }
521
522
523 mask = ap->port_no == 0 ? PIIX_80C_PRI : PIIX_80C_SEC;
524 if ((hpriv->saved_iocfg & mask) == 0)
525 return ATA_CBL_PATA40;
526 return ATA_CBL_PATA80;
527}
528
529
530
531
532
533
534
535
536
537static int piix_pata_prereset(struct ata_link *link, unsigned long deadline)
538{
539 struct ata_port *ap = link->ap;
540 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
541
542 if (!pci_test_config_bits(pdev, &piix_enable_bits[ap->port_no]))
543 return -ENOENT;
544 return ata_sff_prereset(link, deadline);
545}
546
547static DEFINE_SPINLOCK(piix_lock);
548
549static void piix_set_timings(struct ata_port *ap, struct ata_device *adev,
550 u8 pio)
551{
552 struct pci_dev *dev = to_pci_dev(ap->host->dev);
553 unsigned long flags;
554 unsigned int is_slave = (adev->devno != 0);
555 unsigned int master_port= ap->port_no ? 0x42 : 0x40;
556 unsigned int slave_port = 0x44;
557 u16 master_data;
558 u8 slave_data;
559 u8 udma_enable;
560 int control = 0;
561
562
563
564
565
566
567 static const
568 u8 timings[][2] = { { 0, 0 },
569 { 0, 0 },
570 { 1, 0 },
571 { 2, 1 },
572 { 2, 3 }, };
573
574 if (pio >= 2)
575 control |= 1;
576 if (ata_pio_need_iordy(adev))
577 control |= 2;
578
579 if (adev->class == ATA_DEV_ATA)
580 control |= 4;
581
582
583
584
585 if (adev->pio_mode < XFER_PIO_0 + pio)
586
587 control |= 8;
588
589 spin_lock_irqsave(&piix_lock, flags);
590
591
592
593
594
595 pci_read_config_word(dev, master_port, &master_data);
596 if (is_slave) {
597
598 master_data &= 0xff0f;
599
600 master_data |= (control << 4);
601 pci_read_config_byte(dev, slave_port, &slave_data);
602 slave_data &= (ap->port_no ? 0x0f : 0xf0);
603
604 slave_data |= ((timings[pio][0] << 2) | timings[pio][1])
605 << (ap->port_no ? 4 : 0);
606 } else {
607
608 master_data &= 0xccf0;
609
610 master_data |= control;
611
612 master_data |=
613 (timings[pio][0] << 12) |
614 (timings[pio][1] << 8);
615 }
616
617
618 master_data |= 0x4000;
619 pci_write_config_word(dev, master_port, master_data);
620 if (is_slave)
621 pci_write_config_byte(dev, slave_port, slave_data);
622
623
624
625
626 if (ap->udma_mask) {
627 pci_read_config_byte(dev, 0x48, &udma_enable);
628 udma_enable &= ~(1 << (2 * ap->port_no + adev->devno));
629 pci_write_config_byte(dev, 0x48, udma_enable);
630 }
631
632 spin_unlock_irqrestore(&piix_lock, flags);
633}
634
635
636
637
638
639
640
641
642
643
644
645
646static void piix_set_piomode(struct ata_port *ap, struct ata_device *adev)
647{
648 piix_set_timings(ap, adev, adev->pio_mode - XFER_PIO_0);
649}
650
651
652
653
654
655
656
657
658
659
660
661
662
663static void do_pata_set_dmamode(struct ata_port *ap, struct ata_device *adev, int isich)
664{
665 struct pci_dev *dev = to_pci_dev(ap->host->dev);
666 unsigned long flags;
667 u8 speed = adev->dma_mode;
668 int devid = adev->devno + 2 * ap->port_no;
669 u8 udma_enable = 0;
670
671 if (speed >= XFER_UDMA_0) {
672 unsigned int udma = speed - XFER_UDMA_0;
673 u16 udma_timing;
674 u16 ideconf;
675 int u_clock, u_speed;
676
677 spin_lock_irqsave(&piix_lock, flags);
678
679 pci_read_config_byte(dev, 0x48, &udma_enable);
680
681
682
683
684
685
686
687
688 u_speed = min(2 - (udma & 1), udma);
689 if (udma == 5)
690 u_clock = 0x1000;
691 else if (udma > 2)
692 u_clock = 1;
693 else
694 u_clock = 0;
695
696 udma_enable |= (1 << devid);
697
698
699 pci_read_config_word(dev, 0x4A, &udma_timing);
700 udma_timing &= ~(3 << (4 * devid));
701 udma_timing |= u_speed << (4 * devid);
702 pci_write_config_word(dev, 0x4A, udma_timing);
703
704 if (isich) {
705
706 pci_read_config_word(dev, 0x54, &ideconf);
707 ideconf &= ~(0x1001 << devid);
708 ideconf |= u_clock << devid;
709
710
711 pci_write_config_word(dev, 0x54, ideconf);
712 }
713
714 pci_write_config_byte(dev, 0x48, udma_enable);
715
716 spin_unlock_irqrestore(&piix_lock, flags);
717 } else {
718
719 unsigned int mwdma = speed - XFER_MW_DMA_0;
720 const unsigned int needed_pio[3] = {
721 XFER_PIO_0, XFER_PIO_3, XFER_PIO_4
722 };
723 int pio = needed_pio[mwdma] - XFER_PIO_0;
724
725
726 piix_set_timings(ap, adev, pio);
727 }
728}
729
730
731
732
733
734
735
736
737
738
739
740
741static void piix_set_dmamode(struct ata_port *ap, struct ata_device *adev)
742{
743 do_pata_set_dmamode(ap, adev, 0);
744}
745
746
747
748
749
750
751
752
753
754
755
756
757static void ich_set_dmamode(struct ata_port *ap, struct ata_device *adev)
758{
759 do_pata_set_dmamode(ap, adev, 1);
760}
761
762
763
764
765
766
767
768
769
770static const int piix_sidx_map[] = {
771 [SCR_STATUS] = 0,
772 [SCR_ERROR] = 2,
773 [SCR_CONTROL] = 1,
774};
775
776static void piix_sidpr_sel(struct ata_link *link, unsigned int reg)
777{
778 struct ata_port *ap = link->ap;
779 struct piix_host_priv *hpriv = ap->host->private_data;
780
781 iowrite32(((ap->port_no * 2 + link->pmp) << 8) | piix_sidx_map[reg],
782 hpriv->sidpr + PIIX_SIDPR_IDX);
783}
784
785static int piix_sidpr_scr_read(struct ata_link *link,
786 unsigned int reg, u32 *val)
787{
788 struct piix_host_priv *hpriv = link->ap->host->private_data;
789
790 if (reg >= ARRAY_SIZE(piix_sidx_map))
791 return -EINVAL;
792
793 piix_sidpr_sel(link, reg);
794 *val = ioread32(hpriv->sidpr + PIIX_SIDPR_DATA);
795 return 0;
796}
797
798static int piix_sidpr_scr_write(struct ata_link *link,
799 unsigned int reg, u32 val)
800{
801 struct piix_host_priv *hpriv = link->ap->host->private_data;
802
803 if (reg >= ARRAY_SIZE(piix_sidx_map))
804 return -EINVAL;
805
806 piix_sidpr_sel(link, reg);
807 iowrite32(val, hpriv->sidpr + PIIX_SIDPR_DATA);
808 return 0;
809}
810
811static int piix_sidpr_set_lpm(struct ata_link *link, enum ata_lpm_policy policy,
812 unsigned hints)
813{
814 return sata_link_scr_lpm(link, policy, false);
815}
816
817static bool piix_irq_check(struct ata_port *ap)
818{
819 if (unlikely(!ap->ioaddr.bmdma_addr))
820 return false;
821
822 return ap->ops->bmdma_status(ap) & ATA_DMA_INTR;
823}
824
825#ifdef CONFIG_PM_SLEEP
826static int piix_broken_suspend(void)
827{
828 static const struct dmi_system_id sysids[] = {
829 {
830 .ident = "TECRA M3",
831 .matches = {
832 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
833 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M3"),
834 },
835 },
836 {
837 .ident = "TECRA M3",
838 .matches = {
839 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
840 DMI_MATCH(DMI_PRODUCT_NAME, "Tecra M3"),
841 },
842 },
843 {
844 .ident = "TECRA M4",
845 .matches = {
846 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
847 DMI_MATCH(DMI_PRODUCT_NAME, "Tecra M4"),
848 },
849 },
850 {
851 .ident = "TECRA M4",
852 .matches = {
853 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
854 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M4"),
855 },
856 },
857 {
858 .ident = "TECRA M5",
859 .matches = {
860 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
861 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M5"),
862 },
863 },
864 {
865 .ident = "TECRA M6",
866 .matches = {
867 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
868 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M6"),
869 },
870 },
871 {
872 .ident = "TECRA M7",
873 .matches = {
874 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
875 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M7"),
876 },
877 },
878 {
879 .ident = "TECRA A8",
880 .matches = {
881 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
882 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA A8"),
883 },
884 },
885 {
886 .ident = "Satellite R20",
887 .matches = {
888 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
889 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite R20"),
890 },
891 },
892 {
893 .ident = "Satellite R25",
894 .matches = {
895 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
896 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite R25"),
897 },
898 },
899 {
900 .ident = "Satellite U200",
901 .matches = {
902 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
903 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite U200"),
904 },
905 },
906 {
907 .ident = "Satellite U200",
908 .matches = {
909 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
910 DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE U200"),
911 },
912 },
913 {
914 .ident = "Satellite Pro U200",
915 .matches = {
916 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
917 DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE PRO U200"),
918 },
919 },
920 {
921 .ident = "Satellite U205",
922 .matches = {
923 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
924 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite U205"),
925 },
926 },
927 {
928 .ident = "SATELLITE U205",
929 .matches = {
930 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
931 DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE U205"),
932 },
933 },
934 {
935 .ident = "Satellite Pro A120",
936 .matches = {
937 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
938 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite Pro A120"),
939 },
940 },
941 {
942 .ident = "Portege M500",
943 .matches = {
944 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
945 DMI_MATCH(DMI_PRODUCT_NAME, "PORTEGE M500"),
946 },
947 },
948 {
949 .ident = "VGN-BX297XP",
950 .matches = {
951 DMI_MATCH(DMI_SYS_VENDOR, "Sony Corporation"),
952 DMI_MATCH(DMI_PRODUCT_NAME, "VGN-BX297XP"),
953 },
954 },
955
956 { }
957 };
958 static const char *oemstrs[] = {
959 "Tecra M3,",
960 };
961 int i;
962
963 if (dmi_check_system(sysids))
964 return 1;
965
966 for (i = 0; i < ARRAY_SIZE(oemstrs); i++)
967 if (dmi_find_device(DMI_DEV_TYPE_OEM_STRING, oemstrs[i], NULL))
968 return 1;
969
970
971
972
973
974
975
976 if (dmi_match(DMI_SYS_VENDOR, "TOSHIBA") &&
977 dmi_match(DMI_PRODUCT_NAME, "000000") &&
978 dmi_match(DMI_PRODUCT_VERSION, "000000") &&
979 dmi_match(DMI_PRODUCT_SERIAL, "000000") &&
980 dmi_match(DMI_BOARD_VENDOR, "TOSHIBA") &&
981 dmi_match(DMI_BOARD_NAME, "Portable PC") &&
982 dmi_match(DMI_BOARD_VERSION, "Version A0"))
983 return 1;
984
985 return 0;
986}
987
988static int piix_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
989{
990 struct ata_host *host = pci_get_drvdata(pdev);
991 unsigned long flags;
992 int rc = 0;
993
994 rc = ata_host_suspend(host, mesg);
995 if (rc)
996 return rc;
997
998
999
1000
1001
1002
1003 if (piix_broken_suspend() && (mesg.event & PM_EVENT_SLEEP)) {
1004 pci_save_state(pdev);
1005
1006
1007
1008
1009
1010 if (pdev->current_state == PCI_D0)
1011 pdev->current_state = PCI_UNKNOWN;
1012
1013
1014 spin_lock_irqsave(&host->lock, flags);
1015 host->flags |= PIIX_HOST_BROKEN_SUSPEND;
1016 spin_unlock_irqrestore(&host->lock, flags);
1017 } else
1018 ata_pci_device_do_suspend(pdev, mesg);
1019
1020 return 0;
1021}
1022
1023static int piix_pci_device_resume(struct pci_dev *pdev)
1024{
1025 struct ata_host *host = pci_get_drvdata(pdev);
1026 unsigned long flags;
1027 int rc;
1028
1029 if (host->flags & PIIX_HOST_BROKEN_SUSPEND) {
1030 spin_lock_irqsave(&host->lock, flags);
1031 host->flags &= ~PIIX_HOST_BROKEN_SUSPEND;
1032 spin_unlock_irqrestore(&host->lock, flags);
1033
1034 pci_set_power_state(pdev, PCI_D0);
1035 pci_restore_state(pdev);
1036
1037
1038
1039
1040
1041 rc = pci_reenable_device(pdev);
1042 if (rc)
1043 dev_err(&pdev->dev,
1044 "failed to enable device after resume (%d)\n",
1045 rc);
1046 } else
1047 rc = ata_pci_device_do_resume(pdev);
1048
1049 if (rc == 0)
1050 ata_host_resume(host);
1051
1052 return rc;
1053}
1054#endif
1055
1056static u8 piix_vmw_bmdma_status(struct ata_port *ap)
1057{
1058 return ata_bmdma_status(ap) & ~ATA_DMA_ERR;
1059}
1060
1061static struct scsi_host_template piix_sht = {
1062 ATA_BMDMA_SHT(DRV_NAME),
1063};
1064
1065static struct ata_port_operations piix_sata_ops = {
1066 .inherits = &ata_bmdma32_port_ops,
1067 .sff_irq_check = piix_irq_check,
1068 .port_start = piix_port_start,
1069};
1070
1071static struct ata_port_operations piix_pata_ops = {
1072 .inherits = &piix_sata_ops,
1073 .cable_detect = ata_cable_40wire,
1074 .set_piomode = piix_set_piomode,
1075 .set_dmamode = piix_set_dmamode,
1076 .prereset = piix_pata_prereset,
1077};
1078
1079static struct ata_port_operations piix_vmw_ops = {
1080 .inherits = &piix_pata_ops,
1081 .bmdma_status = piix_vmw_bmdma_status,
1082};
1083
1084static struct ata_port_operations ich_pata_ops = {
1085 .inherits = &piix_pata_ops,
1086 .cable_detect = ich_pata_cable_detect,
1087 .set_dmamode = ich_set_dmamode,
1088};
1089
1090static struct device_attribute *piix_sidpr_shost_attrs[] = {
1091 &dev_attr_link_power_management_policy,
1092 NULL
1093};
1094
1095static struct scsi_host_template piix_sidpr_sht = {
1096 ATA_BMDMA_SHT(DRV_NAME),
1097 .shost_attrs = piix_sidpr_shost_attrs,
1098};
1099
1100static struct ata_port_operations piix_sidpr_sata_ops = {
1101 .inherits = &piix_sata_ops,
1102 .hardreset = sata_std_hardreset,
1103 .scr_read = piix_sidpr_scr_read,
1104 .scr_write = piix_sidpr_scr_write,
1105 .set_lpm = piix_sidpr_set_lpm,
1106};
1107
1108static struct ata_port_info piix_port_info[] = {
1109 [piix_pata_mwdma] =
1110 {
1111 .flags = PIIX_PATA_FLAGS,
1112 .pio_mask = ATA_PIO4,
1113 .mwdma_mask = ATA_MWDMA12_ONLY,
1114 .port_ops = &piix_pata_ops,
1115 },
1116
1117 [piix_pata_33] =
1118 {
1119 .flags = PIIX_PATA_FLAGS,
1120 .pio_mask = ATA_PIO4,
1121 .mwdma_mask = ATA_MWDMA12_ONLY,
1122 .udma_mask = ATA_UDMA2,
1123 .port_ops = &piix_pata_ops,
1124 },
1125
1126 [ich_pata_33] =
1127 {
1128 .flags = PIIX_PATA_FLAGS,
1129 .pio_mask = ATA_PIO4,
1130 .mwdma_mask = ATA_MWDMA12_ONLY,
1131 .udma_mask = ATA_UDMA2,
1132 .port_ops = &ich_pata_ops,
1133 },
1134
1135 [ich_pata_66] =
1136 {
1137 .flags = PIIX_PATA_FLAGS,
1138 .pio_mask = ATA_PIO4,
1139 .mwdma_mask = ATA_MWDMA12_ONLY,
1140 .udma_mask = ATA_UDMA4,
1141 .port_ops = &ich_pata_ops,
1142 },
1143
1144 [ich_pata_100] =
1145 {
1146 .flags = PIIX_PATA_FLAGS | PIIX_FLAG_CHECKINTR,
1147 .pio_mask = ATA_PIO4,
1148 .mwdma_mask = ATA_MWDMA12_ONLY,
1149 .udma_mask = ATA_UDMA5,
1150 .port_ops = &ich_pata_ops,
1151 },
1152
1153 [ich_pata_100_nomwdma1] =
1154 {
1155 .flags = PIIX_PATA_FLAGS | PIIX_FLAG_CHECKINTR,
1156 .pio_mask = ATA_PIO4,
1157 .mwdma_mask = ATA_MWDMA2_ONLY,
1158 .udma_mask = ATA_UDMA5,
1159 .port_ops = &ich_pata_ops,
1160 },
1161
1162 [ich5_sata] =
1163 {
1164 .flags = PIIX_SATA_FLAGS,
1165 .pio_mask = ATA_PIO4,
1166 .mwdma_mask = ATA_MWDMA2,
1167 .udma_mask = ATA_UDMA6,
1168 .port_ops = &piix_sata_ops,
1169 },
1170
1171 [ich6_sata] =
1172 {
1173 .flags = PIIX_SATA_FLAGS,
1174 .pio_mask = ATA_PIO4,
1175 .mwdma_mask = ATA_MWDMA2,
1176 .udma_mask = ATA_UDMA6,
1177 .port_ops = &piix_sata_ops,
1178 },
1179
1180 [ich6m_sata] =
1181 {
1182 .flags = PIIX_SATA_FLAGS,
1183 .pio_mask = ATA_PIO4,
1184 .mwdma_mask = ATA_MWDMA2,
1185 .udma_mask = ATA_UDMA6,
1186 .port_ops = &piix_sata_ops,
1187 },
1188
1189 [ich8_sata] =
1190 {
1191 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SIDPR,
1192 .pio_mask = ATA_PIO4,
1193 .mwdma_mask = ATA_MWDMA2,
1194 .udma_mask = ATA_UDMA6,
1195 .port_ops = &piix_sata_ops,
1196 },
1197
1198 [ich8_2port_sata] =
1199 {
1200 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SIDPR,
1201 .pio_mask = ATA_PIO4,
1202 .mwdma_mask = ATA_MWDMA2,
1203 .udma_mask = ATA_UDMA6,
1204 .port_ops = &piix_sata_ops,
1205 },
1206
1207 [tolapai_sata] =
1208 {
1209 .flags = PIIX_SATA_FLAGS,
1210 .pio_mask = ATA_PIO4,
1211 .mwdma_mask = ATA_MWDMA2,
1212 .udma_mask = ATA_UDMA6,
1213 .port_ops = &piix_sata_ops,
1214 },
1215
1216 [ich8m_apple_sata] =
1217 {
1218 .flags = PIIX_SATA_FLAGS,
1219 .pio_mask = ATA_PIO4,
1220 .mwdma_mask = ATA_MWDMA2,
1221 .udma_mask = ATA_UDMA6,
1222 .port_ops = &piix_sata_ops,
1223 },
1224
1225 [piix_pata_vmw] =
1226 {
1227 .flags = PIIX_PATA_FLAGS,
1228 .pio_mask = ATA_PIO4,
1229 .mwdma_mask = ATA_MWDMA12_ONLY,
1230 .udma_mask = ATA_UDMA2,
1231 .port_ops = &piix_vmw_ops,
1232 },
1233
1234
1235
1236
1237
1238 [ich8_sata_snb] =
1239 {
1240 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SIDPR | PIIX_FLAG_PIO16,
1241 .pio_mask = ATA_PIO4,
1242 .mwdma_mask = ATA_MWDMA2,
1243 .udma_mask = ATA_UDMA6,
1244 .port_ops = &piix_sata_ops,
1245 },
1246
1247 [ich8_2port_sata_snb] =
1248 {
1249 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SIDPR
1250 | PIIX_FLAG_PIO16,
1251 .pio_mask = ATA_PIO4,
1252 .mwdma_mask = ATA_MWDMA2,
1253 .udma_mask = ATA_UDMA6,
1254 .port_ops = &piix_sata_ops,
1255 },
1256
1257 [ich8_2port_sata_byt] =
1258 {
1259 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SIDPR | PIIX_FLAG_PIO16,
1260 .pio_mask = ATA_PIO4,
1261 .mwdma_mask = ATA_MWDMA2,
1262 .udma_mask = ATA_UDMA6,
1263 .port_ops = &piix_sata_ops,
1264 },
1265
1266};
1267
1268#define AHCI_PCI_BAR 5
1269#define AHCI_GLOBAL_CTL 0x04
1270#define AHCI_ENABLE (1 << 31)
1271static int piix_disable_ahci(struct pci_dev *pdev)
1272{
1273 void __iomem *mmio;
1274 u32 tmp;
1275 int rc = 0;
1276
1277
1278
1279
1280
1281 if (!pci_resource_start(pdev, AHCI_PCI_BAR) ||
1282 !pci_resource_len(pdev, AHCI_PCI_BAR))
1283 return 0;
1284
1285 mmio = pci_iomap(pdev, AHCI_PCI_BAR, 64);
1286 if (!mmio)
1287 return -ENOMEM;
1288
1289 tmp = ioread32(mmio + AHCI_GLOBAL_CTL);
1290 if (tmp & AHCI_ENABLE) {
1291 tmp &= ~AHCI_ENABLE;
1292 iowrite32(tmp, mmio + AHCI_GLOBAL_CTL);
1293
1294 tmp = ioread32(mmio + AHCI_GLOBAL_CTL);
1295 if (tmp & AHCI_ENABLE)
1296 rc = -EIO;
1297 }
1298
1299 pci_iounmap(pdev, mmio);
1300 return rc;
1301}
1302
1303
1304
1305
1306
1307
1308
1309
1310
1311static int piix_check_450nx_errata(struct pci_dev *ata_dev)
1312{
1313 struct pci_dev *pdev = NULL;
1314 u16 cfg;
1315 int no_piix_dma = 0;
1316
1317 while ((pdev = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, pdev)) != NULL) {
1318
1319
1320 pci_read_config_word(pdev, 0x41, &cfg);
1321
1322 if (pdev->revision == 0x00)
1323 no_piix_dma = 1;
1324
1325 else if (cfg & (1<<14) && pdev->revision < 5)
1326 no_piix_dma = 2;
1327 }
1328 if (no_piix_dma)
1329 dev_warn(&ata_dev->dev,
1330 "450NX errata present, disabling IDE DMA%s\n",
1331 no_piix_dma == 2 ? " - a BIOS update may resolve this"
1332 : "");
1333
1334 return no_piix_dma;
1335}
1336
1337static void piix_init_pcs(struct ata_host *host,
1338 const struct piix_map_db *map_db)
1339{
1340 struct pci_dev *pdev = to_pci_dev(host->dev);
1341 u16 pcs, new_pcs;
1342
1343 pci_read_config_word(pdev, ICH5_PCS, &pcs);
1344
1345 new_pcs = pcs | map_db->port_enable;
1346
1347 if (new_pcs != pcs) {
1348 DPRINTK("updating PCS from 0x%x to 0x%x\n", pcs, new_pcs);
1349 pci_write_config_word(pdev, ICH5_PCS, new_pcs);
1350 msleep(150);
1351 }
1352}
1353
1354static const int *piix_init_sata_map(struct pci_dev *pdev,
1355 struct ata_port_info *pinfo,
1356 const struct piix_map_db *map_db)
1357{
1358 const int *map;
1359 int i, invalid_map = 0;
1360 u8 map_value;
1361 char buf[32];
1362 char *p = buf, *end = buf + sizeof(buf);
1363
1364 pci_read_config_byte(pdev, ICH5_PMR, &map_value);
1365
1366 map = map_db->map[map_value & map_db->mask];
1367
1368 for (i = 0; i < 4; i++) {
1369 switch (map[i]) {
1370 case RV:
1371 invalid_map = 1;
1372 p += scnprintf(p, end - p, " XX");
1373 break;
1374
1375 case NA:
1376 p += scnprintf(p, end - p, " --");
1377 break;
1378
1379 case IDE:
1380 WARN_ON((i & 1) || map[i + 1] != IDE);
1381 pinfo[i / 2] = piix_port_info[ich_pata_100];
1382 i++;
1383 p += scnprintf(p, end - p, " IDE IDE");
1384 break;
1385
1386 default:
1387 p += scnprintf(p, end - p, " P%d", map[i]);
1388 if (i & 1)
1389 pinfo[i / 2].flags |= ATA_FLAG_SLAVE_POSS;
1390 break;
1391 }
1392 }
1393 dev_info(&pdev->dev, "MAP [%s ]\n", buf);
1394
1395 if (invalid_map)
1396 dev_err(&pdev->dev, "invalid MAP value %u\n", map_value);
1397
1398 return map;
1399}
1400
1401static bool piix_no_sidpr(struct ata_host *host)
1402{
1403 struct pci_dev *pdev = to_pci_dev(host->dev);
1404
1405
1406
1407
1408
1409
1410
1411
1412
1413
1414
1415
1416
1417
1418
1419
1420
1421
1422
1423 if (pdev->vendor == PCI_VENDOR_ID_INTEL && pdev->device == 0x2920 &&
1424 pdev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG &&
1425 pdev->subsystem_device == 0xb049) {
1426 dev_warn(host->dev,
1427 "Samsung DB-P70 detected, disabling SIDPR\n");
1428 return true;
1429 }
1430
1431 return false;
1432}
1433
1434static int piix_init_sidpr(struct ata_host *host)
1435{
1436 struct pci_dev *pdev = to_pci_dev(host->dev);
1437 struct piix_host_priv *hpriv = host->private_data;
1438 struct ata_link *link0 = &host->ports[0]->link;
1439 u32 scontrol;
1440 int i, rc;
1441
1442
1443 for (i = 0; i < 4; i++)
1444 if (hpriv->map[i] == IDE)
1445 return 0;
1446
1447
1448 if (piix_no_sidpr(host))
1449 return 0;
1450
1451 if (!(host->ports[0]->flags & PIIX_FLAG_SIDPR))
1452 return 0;
1453
1454 if (pci_resource_start(pdev, PIIX_SIDPR_BAR) == 0 ||
1455 pci_resource_len(pdev, PIIX_SIDPR_BAR) != PIIX_SIDPR_LEN)
1456 return 0;
1457
1458 if (pcim_iomap_regions(pdev, 1 << PIIX_SIDPR_BAR, DRV_NAME))
1459 return 0;
1460
1461 hpriv->sidpr = pcim_iomap_table(pdev)[PIIX_SIDPR_BAR];
1462
1463
1464
1465
1466
1467 piix_sidpr_scr_read(link0, SCR_CONTROL, &scontrol);
1468
1469
1470
1471
1472
1473 if ((scontrol & 0xf00) != 0x300) {
1474 scontrol |= 0x300;
1475 piix_sidpr_scr_write(link0, SCR_CONTROL, scontrol);
1476 piix_sidpr_scr_read(link0, SCR_CONTROL, &scontrol);
1477
1478 if ((scontrol & 0xf00) != 0x300) {
1479 dev_info(host->dev,
1480 "SCR access via SIDPR is available but doesn't work\n");
1481 return 0;
1482 }
1483 }
1484
1485
1486 for (i = 0; i < 2; i++) {
1487 struct ata_port *ap = host->ports[i];
1488
1489 ap->ops = &piix_sidpr_sata_ops;
1490
1491 if (ap->flags & ATA_FLAG_SLAVE_POSS) {
1492 rc = ata_slave_link_init(ap);
1493 if (rc)
1494 return rc;
1495 }
1496 }
1497
1498 return 0;
1499}
1500
1501static void piix_iocfg_bit18_quirk(struct ata_host *host)
1502{
1503 static const struct dmi_system_id sysids[] = {
1504 {
1505
1506
1507
1508
1509 .ident = "M570U",
1510 .matches = {
1511 DMI_MATCH(DMI_SYS_VENDOR, "Clevo Co."),
1512 DMI_MATCH(DMI_PRODUCT_NAME, "M570U"),
1513 },
1514 },
1515
1516 { }
1517 };
1518 struct pci_dev *pdev = to_pci_dev(host->dev);
1519 struct piix_host_priv *hpriv = host->private_data;
1520
1521 if (!dmi_check_system(sysids))
1522 return;
1523
1524
1525
1526
1527
1528 if (hpriv->saved_iocfg & (1 << 18)) {
1529 dev_info(&pdev->dev, "applying IOCFG bit18 quirk\n");
1530 pci_write_config_dword(pdev, PIIX_IOCFG,
1531 hpriv->saved_iocfg & ~(1 << 18));
1532 }
1533}
1534
1535static bool piix_broken_system_poweroff(struct pci_dev *pdev)
1536{
1537 static const struct dmi_system_id broken_systems[] = {
1538 {
1539 .ident = "HP Compaq 2510p",
1540 .matches = {
1541 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1542 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 2510p"),
1543 },
1544
1545 .driver_data = (void *)0x1FUL,
1546 },
1547 {
1548 .ident = "HP Compaq nc6000",
1549 .matches = {
1550 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1551 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nc6000"),
1552 },
1553
1554 .driver_data = (void *)0x1FUL,
1555 },
1556
1557 { }
1558 };
1559 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
1560
1561 if (dmi) {
1562 unsigned long slot = (unsigned long)dmi->driver_data;
1563
1564 return slot == PCI_SLOT(pdev->devfn);
1565 }
1566
1567 return false;
1568}
1569
1570static int prefer_ms_hyperv = 1;
1571module_param(prefer_ms_hyperv, int, 0);
1572MODULE_PARM_DESC(prefer_ms_hyperv,
1573 "Prefer Hyper-V paravirtualization drivers instead of ATA, "
1574 "0 - Use ATA drivers, "
1575 "1 (Default) - Use the paravirtualization drivers.");
1576
1577static void piix_ignore_devices_quirk(struct ata_host *host)
1578{
1579#if IS_ENABLED(CONFIG_HYPERV_STORAGE)
1580 static const struct dmi_system_id ignore_hyperv[] = {
1581 {
1582
1583
1584
1585
1586
1587
1588 .ident = "Hyper-V Virtual Machine",
1589 .matches = {
1590 DMI_MATCH(DMI_SYS_VENDOR,
1591 "Microsoft Corporation"),
1592 DMI_MATCH(DMI_PRODUCT_NAME, "Virtual Machine"),
1593 },
1594 },
1595 { }
1596 };
1597 static const struct dmi_system_id allow_virtual_pc[] = {
1598 {
1599
1600
1601
1602
1603
1604
1605 .ident = "MS Virtual PC 2007",
1606 .matches = {
1607 DMI_MATCH(DMI_SYS_VENDOR,
1608 "Microsoft Corporation"),
1609 DMI_MATCH(DMI_PRODUCT_NAME, "Virtual Machine"),
1610 DMI_MATCH(DMI_PRODUCT_VERSION, "VS2005R2"),
1611 },
1612 },
1613 { }
1614 };
1615 const struct dmi_system_id *ignore = dmi_first_match(ignore_hyperv);
1616 const struct dmi_system_id *allow = dmi_first_match(allow_virtual_pc);
1617
1618 if (ignore && !allow && prefer_ms_hyperv) {
1619 host->flags |= ATA_HOST_IGNORE_ATA;
1620 dev_info(host->dev, "%s detected, ATA device ignore set\n",
1621 ignore->ident);
1622 }
1623#endif
1624}
1625
1626
1627
1628
1629
1630
1631
1632
1633
1634
1635
1636
1637
1638
1639
1640
1641static int piix_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1642{
1643 struct device *dev = &pdev->dev;
1644 struct ata_port_info port_info[2];
1645 const struct ata_port_info *ppi[] = { &port_info[0], &port_info[1] };
1646 struct scsi_host_template *sht = &piix_sht;
1647 unsigned long port_flags;
1648 struct ata_host *host;
1649 struct piix_host_priv *hpriv;
1650 int rc;
1651
1652 ata_print_version_once(&pdev->dev, DRV_VERSION);
1653
1654
1655 if (!in_module_init && ent->driver_data >= ich5_sata)
1656 return -ENODEV;
1657
1658 if (piix_broken_system_poweroff(pdev)) {
1659 piix_port_info[ent->driver_data].flags |=
1660 ATA_FLAG_NO_POWEROFF_SPINDOWN |
1661 ATA_FLAG_NO_HIBERNATE_SPINDOWN;
1662 dev_info(&pdev->dev, "quirky BIOS, skipping spindown "
1663 "on poweroff and hibernation\n");
1664 }
1665
1666 port_info[0] = piix_port_info[ent->driver_data];
1667 port_info[1] = piix_port_info[ent->driver_data];
1668
1669 port_flags = port_info[0].flags;
1670
1671
1672 rc = pcim_enable_device(pdev);
1673 if (rc)
1674 return rc;
1675
1676 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1677 if (!hpriv)
1678 return -ENOMEM;
1679
1680
1681
1682
1683
1684
1685 pci_read_config_dword(pdev, PIIX_IOCFG, &hpriv->saved_iocfg);
1686
1687
1688
1689
1690
1691 if (pdev->vendor == PCI_VENDOR_ID_INTEL && pdev->device == 0x2652) {
1692 rc = piix_disable_ahci(pdev);
1693 if (rc)
1694 return rc;
1695 }
1696
1697
1698 if (port_flags & ATA_FLAG_SATA)
1699 hpriv->map = piix_init_sata_map(pdev, port_info,
1700 piix_map_db_table[ent->driver_data]);
1701
1702 rc = ata_pci_bmdma_prepare_host(pdev, ppi, &host);
1703 if (rc)
1704 return rc;
1705 host->private_data = hpriv;
1706
1707
1708 if (port_flags & ATA_FLAG_SATA) {
1709 piix_init_pcs(host, piix_map_db_table[ent->driver_data]);
1710 rc = piix_init_sidpr(host);
1711 if (rc)
1712 return rc;
1713 if (host->ports[0]->ops == &piix_sidpr_sata_ops)
1714 sht = &piix_sidpr_sht;
1715 }
1716
1717
1718 piix_iocfg_bit18_quirk(host);
1719
1720
1721
1722
1723
1724
1725
1726 if (port_flags & PIIX_FLAG_CHECKINTR)
1727 pci_intx(pdev, 1);
1728
1729 if (piix_check_450nx_errata(pdev)) {
1730
1731
1732
1733 host->ports[0]->mwdma_mask = 0;
1734 host->ports[0]->udma_mask = 0;
1735 host->ports[1]->mwdma_mask = 0;
1736 host->ports[1]->udma_mask = 0;
1737 }
1738 host->flags |= ATA_HOST_PARALLEL_SCAN;
1739
1740
1741 piix_ignore_devices_quirk(host);
1742
1743 pci_set_master(pdev);
1744 return ata_pci_sff_activate_host(host, ata_bmdma_interrupt, sht);
1745}
1746
1747static void piix_remove_one(struct pci_dev *pdev)
1748{
1749 struct ata_host *host = pci_get_drvdata(pdev);
1750 struct piix_host_priv *hpriv = host->private_data;
1751
1752 pci_write_config_dword(pdev, PIIX_IOCFG, hpriv->saved_iocfg);
1753
1754 ata_pci_remove_one(pdev);
1755}
1756
1757static struct pci_driver piix_pci_driver = {
1758 .name = DRV_NAME,
1759 .id_table = piix_pci_tbl,
1760 .probe = piix_init_one,
1761 .remove = piix_remove_one,
1762#ifdef CONFIG_PM_SLEEP
1763 .suspend = piix_pci_device_suspend,
1764 .resume = piix_pci_device_resume,
1765#endif
1766};
1767
1768static int __init piix_init(void)
1769{
1770 int rc;
1771
1772 DPRINTK("pci_register_driver\n");
1773 rc = pci_register_driver(&piix_pci_driver);
1774 if (rc)
1775 return rc;
1776
1777 in_module_init = 0;
1778
1779 DPRINTK("done\n");
1780 return 0;
1781}
1782
1783static void __exit piix_exit(void)
1784{
1785 pci_unregister_driver(&piix_pci_driver);
1786}
1787
1788module_init(piix_init);
1789module_exit(piix_exit);
1790
