LXR linux/drivers/clk/mediatek/clk-mt8183-mfgcfg.c

   1// SPDX-License-Identifier: GPL-2.0
   2//
   3// Copyright (c) 2018 MediaTek Inc.
   4// Author: Weiyi Lu <weiyi.lu@mediatek.com>
   5
   6#include <linux/clk-provider.h>
   7#include <linux/platform_device.h>
   8
   9#include "clk-mtk.h"
  10#include "clk-gate.h"
  11
  12#include <dt-bindings/clock/mt8183-clk.h>
  13
  14static const struct mtk_gate_regs mfg_cg_regs = {
  15        .set_ofs = 0x4,
  16        .clr_ofs = 0x8,
  17        .sta_ofs = 0x0,
  18};
  19
  20#define GATE_MFG(_id, _name, _parent, _shift)                   \
  21        GATE_MTK(_id, _name, _parent, &mfg_cg_regs, _shift,     \
  22                &mtk_clk_gate_ops_setclr)
  23
  24static const struct mtk_gate mfg_clks[] = {
  25        GATE_MFG(CLK_MFG_BG3D, "mfg_bg3d", "mfg_sel", 0)
  26};
  27
  28static int clk_mt8183_mfg_probe(struct platform_device *pdev)
  29{
  30        struct clk_onecell_data *clk_data;
  31        struct device_node *node = pdev->dev.of_node;
  32
  33        clk_data = mtk_alloc_clk_data(CLK_MFG_NR_CLK);
  34
  35        mtk_clk_register_gates(node, mfg_clks, ARRAY_SIZE(mfg_clks),
  36                        clk_data);
  37
  38        return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
  39}
  40
  41static const struct of_device_id of_match_clk_mt8183_mfg[] = {
  42        { .compatible = "mediatek,mt8183-mfgcfg", },
  43        {}
  44};
  45
  46static struct platform_driver clk_mt8183_mfg_drv = {
  47        .probe = clk_mt8183_mfg_probe,
  48        .driver = {
  49                .name = "clk-mt8183-mfg",
  50                .of_match_table = of_match_clk_mt8183_mfg,
  51        },
  52};
  53
  54builtin_platform_driver(clk_mt8183_mfg_drv);
  55