linux/drivers/clk/sunxi-ng/ccu-sun6i-a31.c
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   1// SPDX-License-Identifier: GPL-2.0-only
   2/*
   3 * Copyright (c) 2016 Chen-Yu Tsai
   4 *
   5 * Chen-Yu Tsai <wens@csie.org>
   6 *
   7 * Based on ccu-sun8i-h3.c by Maxime Ripard.
   8 */
   9
  10#include <linux/clk-provider.h>
  11#include <linux/io.h>
  12#include <linux/of_address.h>
  13
  14#include "ccu_common.h"
  15#include "ccu_reset.h"
  16
  17#include "ccu_div.h"
  18#include "ccu_gate.h"
  19#include "ccu_mp.h"
  20#include "ccu_mult.h"
  21#include "ccu_mux.h"
  22#include "ccu_nk.h"
  23#include "ccu_nkm.h"
  24#include "ccu_nkmp.h"
  25#include "ccu_nm.h"
  26#include "ccu_phase.h"
  27#include "ccu_sdm.h"
  28
  29#include "ccu-sun6i-a31.h"
  30
  31static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_cpu_clk, "pll-cpu",
  32                                     "osc24M", 0x000,
  33                                     8, 5,      /* N */
  34                                     4, 2,      /* K */
  35                                     0, 2,      /* M */
  36                                     BIT(31),   /* gate */
  37                                     BIT(28),   /* lock */
  38                                     0);
  39
  40/*
  41 * The Audio PLL is supposed to have 4 outputs: 3 fixed factors from
  42 * the base (2x, 4x and 8x), and one variable divider (the one true
  43 * pll audio).
  44 *
  45 * With sigma-delta modulation for fractional-N on the audio PLL,
  46 * we have to use specific dividers. This means the variable divider
  47 * can no longer be used, as the audio codec requests the exact clock
  48 * rates we support through this mechanism. So we now hard code the
  49 * variable divider to 1. This means the clock rates will no longer
  50 * match the clock names.
  51 */
  52#define SUN6I_A31_PLL_AUDIO_REG 0x008
  53
  54static struct ccu_sdm_setting pll_audio_sdm_table[] = {
  55        { .rate = 22579200, .pattern = 0xc0010d84, .m = 8, .n = 7 },
  56        { .rate = 24576000, .pattern = 0xc000ac02, .m = 14, .n = 14 },
  57};
  58
  59static SUNXI_CCU_NM_WITH_SDM_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
  60                                       "osc24M", 0x008,
  61                                       8, 7,    /* N */
  62                                       0, 5,    /* M */
  63                                       pll_audio_sdm_table, BIT(24),
  64                                       0x284, BIT(31),
  65                                       BIT(31), /* gate */
  66                                       BIT(28), /* lock */
  67                                       CLK_SET_RATE_UNGATE);
  68
  69static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video0_clk, "pll-video0",
  70                                        "osc24M", 0x010,
  71                                        8, 7,           /* N */
  72                                        0, 4,           /* M */
  73                                        BIT(24),        /* frac enable */
  74                                        BIT(25),        /* frac select */
  75                                        270000000,      /* frac rate 0 */
  76                                        297000000,      /* frac rate 1 */
  77                                        BIT(31),        /* gate */
  78                                        BIT(28),        /* lock */
  79                                        CLK_SET_RATE_UNGATE);
  80
  81static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve",
  82                                        "osc24M", 0x018,
  83                                        8, 7,           /* N */
  84                                        0, 4,           /* M */
  85                                        BIT(24),        /* frac enable */
  86                                        BIT(25),        /* frac select */
  87                                        270000000,      /* frac rate 0 */
  88                                        297000000,      /* frac rate 1 */
  89                                        BIT(31),        /* gate */
  90                                        BIT(28),        /* lock */
  91                                        CLK_SET_RATE_UNGATE);
  92
  93static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_ddr_clk, "pll-ddr",
  94                                    "osc24M", 0x020,
  95                                    8, 5,       /* N */
  96                                    4, 2,       /* K */
  97                                    0, 2,       /* M */
  98                                    BIT(31),    /* gate */
  99                                    BIT(28),    /* lock */
 100                                    CLK_SET_RATE_UNGATE);
 101
 102static SUNXI_CCU_NK_WITH_GATE_LOCK_POSTDIV(pll_periph_clk, "pll-periph",
 103                                           "osc24M", 0x028,
 104                                           8, 5,        /* N */
 105                                           4, 2,        /* K */
 106                                           BIT(31),     /* gate */
 107                                           BIT(28),     /* lock */
 108                                           2,           /* post-div */
 109                                           CLK_SET_RATE_UNGATE);
 110
 111static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video1_clk, "pll-video1",
 112                                        "osc24M", 0x030,
 113                                        8, 7,           /* N */
 114                                        0, 4,           /* M */
 115                                        BIT(24),        /* frac enable */
 116                                        BIT(25),        /* frac select */
 117                                        270000000,      /* frac rate 0 */
 118                                        297000000,      /* frac rate 1 */
 119                                        BIT(31),        /* gate */
 120                                        BIT(28),        /* lock */
 121                                        CLK_SET_RATE_UNGATE);
 122
 123static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_gpu_clk, "pll-gpu",
 124                                        "osc24M", 0x038,
 125                                        8, 7,           /* N */
 126                                        0, 4,           /* M */
 127                                        BIT(24),        /* frac enable */
 128                                        BIT(25),        /* frac select */
 129                                        270000000,      /* frac rate 0 */
 130                                        297000000,      /* frac rate 1 */
 131                                        BIT(31),        /* gate */
 132                                        BIT(28),        /* lock */
 133                                        CLK_SET_RATE_UNGATE);
 134
 135/*
 136 * The MIPI PLL has 2 modes: "MIPI" and "HDMI".
 137 *
 138 * The MIPI mode is a standard NKM-style clock. The HDMI mode is an
 139 * integer / fractional clock with switchable multipliers and dividers.
 140 * This is not supported here. We hardcode the PLL to MIPI mode.
 141 */
 142#define SUN6I_A31_PLL_MIPI_REG  0x040
 143
 144static const char * const pll_mipi_parents[] = { "pll-video0", "pll-video1" };
 145static SUNXI_CCU_NKM_WITH_MUX_GATE_LOCK(pll_mipi_clk, "pll-mipi",
 146                                        pll_mipi_parents, 0x040,
 147                                        8, 4,   /* N */
 148                                        4, 2,   /* K */
 149                                        0, 4,   /* M */
 150                                        21, 0,  /* mux */
 151                                        BIT(31) | BIT(23) | BIT(22), /* gate */
 152                                        BIT(28),        /* lock */
 153                                        CLK_SET_RATE_UNGATE);
 154
 155static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll9_clk, "pll9",
 156                                        "osc24M", 0x044,
 157                                        8, 7,           /* N */
 158                                        0, 4,           /* M */
 159                                        BIT(24),        /* frac enable */
 160                                        BIT(25),        /* frac select */
 161                                        270000000,      /* frac rate 0 */
 162                                        297000000,      /* frac rate 1 */
 163                                        BIT(31),        /* gate */
 164                                        BIT(28),        /* lock */
 165                                        CLK_SET_RATE_UNGATE);
 166
 167static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll10_clk, "pll10",
 168                                        "osc24M", 0x048,
 169                                        8, 7,           /* N */
 170                                        0, 4,           /* M */
 171                                        BIT(24),        /* frac enable */
 172                                        BIT(25),        /* frac select */
 173                                        270000000,      /* frac rate 0 */
 174                                        297000000,      /* frac rate 1 */
 175                                        BIT(31),        /* gate */
 176                                        BIT(28),        /* lock */
 177                                        CLK_SET_RATE_UNGATE);
 178
 179static const char * const cpux_parents[] = { "osc32k", "osc24M",
 180                                             "pll-cpu", "pll-cpu" };
 181static SUNXI_CCU_MUX(cpu_clk, "cpu", cpux_parents,
 182                     0x050, 16, 2, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL);
 183
 184static struct clk_div_table axi_div_table[] = {
 185        { .val = 0, .div = 1 },
 186        { .val = 1, .div = 2 },
 187        { .val = 2, .div = 3 },
 188        { .val = 3, .div = 4 },
 189        { .val = 4, .div = 4 },
 190        { .val = 5, .div = 4 },
 191        { .val = 6, .div = 4 },
 192        { .val = 7, .div = 4 },
 193        { /* Sentinel */ },
 194};
 195
 196static SUNXI_CCU_DIV_TABLE(axi_clk, "axi", "cpu",
 197                           0x050, 0, 3, axi_div_table, 0);
 198
 199#define SUN6I_A31_AHB1_REG  0x054
 200
 201static const char * const ahb1_parents[] = { "osc32k", "osc24M",
 202                                             "axi", "pll-periph" };
 203static const struct ccu_mux_var_prediv ahb1_predivs[] = {
 204        { .index = 3, .shift = 6, .width = 2 },
 205};
 206
 207static struct ccu_div ahb1_clk = {
 208        .div            = _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO),
 209
 210        .mux            = {
 211                .shift  = 12,
 212                .width  = 2,
 213
 214                .var_predivs    = ahb1_predivs,
 215                .n_var_predivs  = ARRAY_SIZE(ahb1_predivs),
 216        },
 217
 218        .common         = {
 219                .reg            = 0x054,
 220                .features       = CCU_FEATURE_VARIABLE_PREDIV,
 221                .hw.init        = CLK_HW_INIT_PARENTS("ahb1",
 222                                                      ahb1_parents,
 223                                                      &ccu_div_ops,
 224                                                      0),
 225        },
 226};
 227
 228static struct clk_div_table apb1_div_table[] = {
 229        { .val = 0, .div = 2 },
 230        { .val = 1, .div = 2 },
 231        { .val = 2, .div = 4 },
 232        { .val = 3, .div = 8 },
 233        { /* Sentinel */ },
 234};
 235
 236static SUNXI_CCU_DIV_TABLE(apb1_clk, "apb1", "ahb1",
 237                           0x054, 8, 2, apb1_div_table, 0);
 238
 239static const char * const apb2_parents[] = { "osc32k", "osc24M",
 240                                             "pll-periph", "pll-periph" };
 241static SUNXI_CCU_MP_WITH_MUX(apb2_clk, "apb2", apb2_parents, 0x058,
 242                             0, 5,      /* M */
 243                             16, 2,     /* P */
 244                             24, 2,     /* mux */
 245                             0);
 246
 247static SUNXI_CCU_GATE(ahb1_mipidsi_clk, "ahb1-mipidsi", "ahb1",
 248                      0x060, BIT(1), 0);
 249static SUNXI_CCU_GATE(ahb1_ss_clk,      "ahb1-ss",      "ahb1",
 250                      0x060, BIT(5), 0);
 251static SUNXI_CCU_GATE(ahb1_dma_clk,     "ahb1-dma",     "ahb1",
 252                      0x060, BIT(6), 0);
 253static SUNXI_CCU_GATE(ahb1_mmc0_clk,    "ahb1-mmc0",    "ahb1",
 254                      0x060, BIT(8), 0);
 255static SUNXI_CCU_GATE(ahb1_mmc1_clk,    "ahb1-mmc1",    "ahb1",
 256                      0x060, BIT(9), 0);
 257static SUNXI_CCU_GATE(ahb1_mmc2_clk,    "ahb1-mmc2",    "ahb1",
 258                      0x060, BIT(10), 0);
 259static SUNXI_CCU_GATE(ahb1_mmc3_clk,    "ahb1-mmc3",    "ahb1",
 260                      0x060, BIT(11), 0);
 261static SUNXI_CCU_GATE(ahb1_nand1_clk,   "ahb1-nand1",   "ahb1",
 262                      0x060, BIT(12), 0);
 263static SUNXI_CCU_GATE(ahb1_nand0_clk,   "ahb1-nand0",   "ahb1",
 264                      0x060, BIT(13), 0);
 265static SUNXI_CCU_GATE(ahb1_sdram_clk,   "ahb1-sdram",   "ahb1",
 266                      0x060, BIT(14), 0);
 267static SUNXI_CCU_GATE(ahb1_emac_clk,    "ahb1-emac",    "ahb1",
 268                      0x060, BIT(17), 0);
 269static SUNXI_CCU_GATE(ahb1_ts_clk,      "ahb1-ts",      "ahb1",
 270                      0x060, BIT(18), 0);
 271static SUNXI_CCU_GATE(ahb1_hstimer_clk, "ahb1-hstimer", "ahb1",
 272                      0x060, BIT(19), 0);
 273static SUNXI_CCU_GATE(ahb1_spi0_clk,    "ahb1-spi0",    "ahb1",
 274                      0x060, BIT(20), 0);
 275static SUNXI_CCU_GATE(ahb1_spi1_clk,    "ahb1-spi1",    "ahb1",
 276                      0x060, BIT(21), 0);
 277static SUNXI_CCU_GATE(ahb1_spi2_clk,    "ahb1-spi2",    "ahb1",
 278                      0x060, BIT(22), 0);
 279static SUNXI_CCU_GATE(ahb1_spi3_clk,    "ahb1-spi3",    "ahb1",
 280                      0x060, BIT(23), 0);
 281static SUNXI_CCU_GATE(ahb1_otg_clk,     "ahb1-otg",     "ahb1",
 282                      0x060, BIT(24), 0);
 283static SUNXI_CCU_GATE(ahb1_ehci0_clk,   "ahb1-ehci0",   "ahb1",
 284                      0x060, BIT(26), 0);
 285static SUNXI_CCU_GATE(ahb1_ehci1_clk,   "ahb1-ehci1",   "ahb1",
 286                      0x060, BIT(27), 0);
 287static SUNXI_CCU_GATE(ahb1_ohci0_clk,   "ahb1-ohci0",   "ahb1",
 288                      0x060, BIT(29), 0);
 289static SUNXI_CCU_GATE(ahb1_ohci1_clk,   "ahb1-ohci1",   "ahb1",
 290                      0x060, BIT(30), 0);
 291static SUNXI_CCU_GATE(ahb1_ohci2_clk,   "ahb1-ohci2",   "ahb1",
 292                      0x060, BIT(31), 0);
 293
 294static SUNXI_CCU_GATE(ahb1_ve_clk,      "ahb1-ve",      "ahb1",
 295                      0x064, BIT(0), 0);
 296static SUNXI_CCU_GATE(ahb1_lcd0_clk,    "ahb1-lcd0",    "ahb1",
 297                      0x064, BIT(4), 0);
 298static SUNXI_CCU_GATE(ahb1_lcd1_clk,    "ahb1-lcd1",    "ahb1",
 299                      0x064, BIT(5), 0);
 300static SUNXI_CCU_GATE(ahb1_csi_clk,     "ahb1-csi",     "ahb1",
 301                      0x064, BIT(8), 0);
 302static SUNXI_CCU_GATE(ahb1_hdmi_clk,    "ahb1-hdmi",    "ahb1",
 303                      0x064, BIT(11), 0);
 304static SUNXI_CCU_GATE(ahb1_be0_clk,     "ahb1-be0",     "ahb1",
 305                      0x064, BIT(12), 0);
 306static SUNXI_CCU_GATE(ahb1_be1_clk,     "ahb1-be1",     "ahb1",
 307                      0x064, BIT(13), 0);
 308static SUNXI_CCU_GATE(ahb1_fe0_clk,     "ahb1-fe0",     "ahb1",
 309                      0x064, BIT(14), 0);
 310static SUNXI_CCU_GATE(ahb1_fe1_clk,     "ahb1-fe1",     "ahb1",
 311                      0x064, BIT(15), 0);
 312static SUNXI_CCU_GATE(ahb1_mp_clk,      "ahb1-mp",      "ahb1",
 313                      0x064, BIT(18), 0);
 314static SUNXI_CCU_GATE(ahb1_gpu_clk,     "ahb1-gpu",     "ahb1",
 315                      0x064, BIT(20), 0);
 316static SUNXI_CCU_GATE(ahb1_deu0_clk,    "ahb1-deu0",    "ahb1",
 317                      0x064, BIT(23), 0);
 318static SUNXI_CCU_GATE(ahb1_deu1_clk,    "ahb1-deu1",    "ahb1",
 319                      0x064, BIT(24), 0);
 320static SUNXI_CCU_GATE(ahb1_drc0_clk,    "ahb1-drc0",    "ahb1",
 321                      0x064, BIT(25), 0);
 322static SUNXI_CCU_GATE(ahb1_drc1_clk,    "ahb1-drc1",    "ahb1",
 323                      0x064, BIT(26), 0);
 324
 325static SUNXI_CCU_GATE(apb1_codec_clk,   "apb1-codec",   "apb1",
 326                      0x068, BIT(0), 0);
 327static SUNXI_CCU_GATE(apb1_spdif_clk,   "apb1-spdif",   "apb1",
 328                      0x068, BIT(1), 0);
 329static SUNXI_CCU_GATE(apb1_digital_mic_clk,     "apb1-digital-mic",     "apb1",
 330                      0x068, BIT(4), 0);
 331static SUNXI_CCU_GATE(apb1_pio_clk,     "apb1-pio",     "apb1",
 332                      0x068, BIT(5), 0);
 333static SUNXI_CCU_GATE(apb1_daudio0_clk, "apb1-daudio0", "apb1",
 334                      0x068, BIT(12), 0);
 335static SUNXI_CCU_GATE(apb1_daudio1_clk, "apb1-daudio1", "apb1",
 336                      0x068, BIT(13), 0);
 337
 338static SUNXI_CCU_GATE(apb2_i2c0_clk,    "apb2-i2c0",    "apb2",
 339                      0x06c, BIT(0), 0);
 340static SUNXI_CCU_GATE(apb2_i2c1_clk,    "apb2-i2c1",    "apb2",
 341                      0x06c, BIT(1), 0);
 342static SUNXI_CCU_GATE(apb2_i2c2_clk,    "apb2-i2c2",    "apb2",
 343                      0x06c, BIT(2), 0);
 344static SUNXI_CCU_GATE(apb2_i2c3_clk,    "apb2-i2c3",    "apb2",
 345                      0x06c, BIT(3), 0);
 346static SUNXI_CCU_GATE(apb2_uart0_clk,   "apb2-uart0",   "apb2",
 347                      0x06c, BIT(16), 0);
 348static SUNXI_CCU_GATE(apb2_uart1_clk,   "apb2-uart1",   "apb2",
 349                      0x06c, BIT(17), 0);
 350static SUNXI_CCU_GATE(apb2_uart2_clk,   "apb2-uart2",   "apb2",
 351                      0x06c, BIT(18), 0);
 352static SUNXI_CCU_GATE(apb2_uart3_clk,   "apb2-uart3",   "apb2",
 353                      0x06c, BIT(19), 0);
 354static SUNXI_CCU_GATE(apb2_uart4_clk,   "apb2-uart4",   "apb2",
 355                      0x06c, BIT(20), 0);
 356static SUNXI_CCU_GATE(apb2_uart5_clk,   "apb2-uart5",   "apb2",
 357                      0x06c, BIT(21), 0);
 358
 359static const char * const mod0_default_parents[] = { "osc24M", "pll-periph" };
 360static SUNXI_CCU_MP_WITH_MUX_GATE(nand0_clk, "nand0", mod0_default_parents,
 361                                  0x080,
 362                                  0, 4,         /* M */
 363                                  16, 2,        /* P */
 364                                  24, 2,        /* mux */
 365                                  BIT(31),      /* gate */
 366                                  0);
 367
 368static SUNXI_CCU_MP_WITH_MUX_GATE(nand1_clk, "nand1", mod0_default_parents,
 369                                  0x084,
 370                                  0, 4,         /* M */
 371                                  16, 2,        /* P */
 372                                  24, 2,        /* mux */
 373                                  BIT(31),      /* gate */
 374                                  0);
 375
 376static SUNXI_CCU_MP_WITH_MUX_GATE(mmc0_clk, "mmc0", mod0_default_parents,
 377                                  0x088,
 378                                  0, 4,         /* M */
 379                                  16, 2,        /* P */
 380                                  24, 2,        /* mux */
 381                                  BIT(31),      /* gate */
 382                                  0);
 383
 384static SUNXI_CCU_PHASE(mmc0_sample_clk, "mmc0_sample", "mmc0",
 385                       0x088, 20, 3, 0);
 386static SUNXI_CCU_PHASE(mmc0_output_clk, "mmc0_output", "mmc0",
 387                       0x088, 8, 3, 0);
 388
 389static SUNXI_CCU_MP_WITH_MUX_GATE(mmc1_clk, "mmc1", mod0_default_parents,
 390                                  0x08c,
 391                                  0, 4,         /* M */
 392                                  16, 2,        /* P */
 393                                  24, 2,        /* mux */
 394                                  BIT(31),      /* gate */
 395                                  0);
 396
 397static SUNXI_CCU_PHASE(mmc1_sample_clk, "mmc1_sample", "mmc1",
 398                       0x08c, 20, 3, 0);
 399static SUNXI_CCU_PHASE(mmc1_output_clk, "mmc1_output", "mmc1",
 400                       0x08c, 8, 3, 0);
 401
 402static SUNXI_CCU_MP_WITH_MUX_GATE(mmc2_clk, "mmc2", mod0_default_parents,
 403                                  0x090,
 404                                  0, 4,         /* M */
 405                                  16, 2,        /* P */
 406                                  24, 2,        /* mux */
 407                                  BIT(31),      /* gate */
 408                                  0);
 409
 410static SUNXI_CCU_PHASE(mmc2_sample_clk, "mmc2_sample", "mmc2",
 411                       0x090, 20, 3, 0);
 412static SUNXI_CCU_PHASE(mmc2_output_clk, "mmc2_output", "mmc2",
 413                       0x090, 8, 3, 0);
 414
 415static SUNXI_CCU_MP_WITH_MUX_GATE(mmc3_clk, "mmc3", mod0_default_parents,
 416                                  0x094,
 417                                  0, 4,         /* M */
 418                                  16, 2,        /* P */
 419                                  24, 2,        /* mux */
 420                                  BIT(31),      /* gate */
 421                                  0);
 422
 423static SUNXI_CCU_PHASE(mmc3_sample_clk, "mmc3_sample", "mmc3",
 424                       0x094, 20, 3, 0);
 425static SUNXI_CCU_PHASE(mmc3_output_clk, "mmc3_output", "mmc3",
 426                       0x094, 8, 3, 0);
 427
 428static SUNXI_CCU_MP_WITH_MUX_GATE(ts_clk, "ts", mod0_default_parents, 0x098,
 429                                  0, 4,         /* M */
 430                                  16, 2,        /* P */
 431                                  24, 2,        /* mux */
 432                                  BIT(31),      /* gate */
 433                                  0);
 434
 435static SUNXI_CCU_MP_WITH_MUX_GATE(ss_clk, "ss", mod0_default_parents, 0x09c,
 436                                  0, 4,         /* M */
 437                                  16, 2,        /* P */
 438                                  24, 2,        /* mux */
 439                                  BIT(31),      /* gate */
 440                                  0);
 441
 442static SUNXI_CCU_MP_WITH_MUX_GATE(spi0_clk, "spi0", mod0_default_parents, 0x0a0,
 443                                  0, 4,         /* M */
 444                                  16, 2,        /* P */
 445                                  24, 2,        /* mux */
 446                                  BIT(31),      /* gate */
 447                                  0);
 448
 449static SUNXI_CCU_MP_WITH_MUX_GATE(spi1_clk, "spi1", mod0_default_parents, 0x0a4,
 450                                  0, 4,         /* M */
 451                                  16, 2,        /* P */
 452                                  24, 2,        /* mux */
 453                                  BIT(31),      /* gate */
 454                                  0);
 455static SUNXI_CCU_MP_WITH_MUX_GATE(spi2_clk, "spi2", mod0_default_parents, 0x0a8,
 456                                  0, 4,         /* M */
 457                                  16, 2,        /* P */
 458                                  24, 2,        /* mux */
 459                                  BIT(31),      /* gate */
 460                                  0);
 461
 462static SUNXI_CCU_MP_WITH_MUX_GATE(spi3_clk, "spi3", mod0_default_parents, 0x0ac,
 463                                  0, 4,         /* M */
 464                                  16, 2,        /* P */
 465                                  24, 2,        /* mux */
 466                                  BIT(31),      /* gate */
 467                                  0);
 468
 469static const char * const daudio_parents[] = { "pll-audio-8x", "pll-audio-4x",
 470                                               "pll-audio-2x", "pll-audio" };
 471static SUNXI_CCU_MUX_WITH_GATE(daudio0_clk, "daudio0", daudio_parents,
 472                               0x0b0, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
 473static SUNXI_CCU_MUX_WITH_GATE(daudio1_clk, "daudio1", daudio_parents,
 474                               0x0b4, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
 475
 476static SUNXI_CCU_MUX_WITH_GATE(spdif_clk, "spdif", daudio_parents,
 477                               0x0c0, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
 478
 479static SUNXI_CCU_GATE(usb_phy0_clk,     "usb-phy0",     "osc24M",
 480                      0x0cc, BIT(8), 0);
 481static SUNXI_CCU_GATE(usb_phy1_clk,     "usb-phy1",     "osc24M",
 482                      0x0cc, BIT(9), 0);
 483static SUNXI_CCU_GATE(usb_phy2_clk,     "usb-phy2",     "osc24M",
 484                      0x0cc, BIT(10), 0);
 485static SUNXI_CCU_GATE(usb_ohci0_clk,    "usb-ohci0",    "osc24M",
 486                      0x0cc, BIT(16), 0);
 487static SUNXI_CCU_GATE(usb_ohci1_clk,    "usb-ohci1",    "osc24M",
 488                      0x0cc, BIT(17), 0);
 489static SUNXI_CCU_GATE(usb_ohci2_clk,    "usb-ohci2",    "osc24M",
 490                      0x0cc, BIT(18), 0);
 491
 492/* TODO emac clk not supported yet */
 493
 494static const char * const dram_parents[] = { "pll-ddr", "pll-periph" };
 495static SUNXI_CCU_MP_WITH_MUX_GATE(mdfs_clk, "mdfs", dram_parents, 0x0f0,
 496                                  0, 4,         /* M */
 497                                  16, 2,        /* P */
 498                                  24, 2,        /* mux */
 499                                  BIT(31),      /* gate */
 500                                  CLK_IS_CRITICAL);
 501
 502static SUNXI_CCU_M_WITH_MUX(sdram0_clk, "sdram0", dram_parents,
 503                            0x0f4, 0, 4, 4, 1, CLK_IS_CRITICAL);
 504static SUNXI_CCU_M_WITH_MUX(sdram1_clk, "sdram1", dram_parents,
 505                            0x0f4, 8, 4, 12, 1, CLK_IS_CRITICAL);
 506
 507static SUNXI_CCU_GATE(dram_ve_clk,      "dram-ve",      "mdfs",
 508                      0x100, BIT(0), 0);
 509static SUNXI_CCU_GATE(dram_csi_isp_clk, "dram-csi-isp", "mdfs",
 510                      0x100, BIT(1), 0);
 511static SUNXI_CCU_GATE(dram_ts_clk,      "dram-ts",      "mdfs",
 512                      0x100, BIT(3), 0);
 513static SUNXI_CCU_GATE(dram_drc0_clk,    "dram-drc0",    "mdfs",
 514                      0x100, BIT(16), 0);
 515static SUNXI_CCU_GATE(dram_drc1_clk,    "dram-drc1",    "mdfs",
 516                      0x100, BIT(17), 0);
 517static SUNXI_CCU_GATE(dram_deu0_clk,    "dram-deu0",    "mdfs",
 518                      0x100, BIT(18), 0);
 519static SUNXI_CCU_GATE(dram_deu1_clk,    "dram-deu1",    "mdfs",
 520                      0x100, BIT(19), 0);
 521static SUNXI_CCU_GATE(dram_fe0_clk,     "dram-fe0",     "mdfs",
 522                      0x100, BIT(24), 0);
 523static SUNXI_CCU_GATE(dram_fe1_clk,     "dram-fe1",     "mdfs",
 524                      0x100, BIT(25), 0);
 525static SUNXI_CCU_GATE(dram_be0_clk,     "dram-be0",     "mdfs",
 526                      0x100, BIT(26), 0);
 527static SUNXI_CCU_GATE(dram_be1_clk,     "dram-be1",     "mdfs",
 528                      0x100, BIT(27), 0);
 529static SUNXI_CCU_GATE(dram_mp_clk,      "dram-mp",      "mdfs",
 530                      0x100, BIT(28), 0);
 531
 532static const char * const de_parents[] = { "pll-video0", "pll-video1",
 533                                           "pll-periph-2x", "pll-gpu",
 534                                           "pll9", "pll10" };
 535static SUNXI_CCU_M_WITH_MUX_GATE(be0_clk, "be0", de_parents,
 536                                 0x104, 0, 4, 24, 3, BIT(31), 0);
 537static SUNXI_CCU_M_WITH_MUX_GATE(be1_clk, "be1", de_parents,
 538                                 0x108, 0, 4, 24, 3, BIT(31), 0);
 539static SUNXI_CCU_M_WITH_MUX_GATE(fe0_clk, "fe0", de_parents,
 540                                 0x10c, 0, 4, 24, 3, BIT(31), 0);
 541static SUNXI_CCU_M_WITH_MUX_GATE(fe1_clk, "fe1", de_parents,
 542                                 0x110, 0, 4, 24, 3, BIT(31), 0);
 543
 544static const char * const mp_parents[] = { "pll-video0", "pll-video1",
 545                                           "pll9", "pll10" };
 546static SUNXI_CCU_M_WITH_MUX_GATE(mp_clk, "mp", mp_parents,
 547                                 0x114, 0, 4, 24, 3, BIT(31), 0);
 548
 549static const char * const lcd_ch0_parents[] = { "pll-video0", "pll-video1",
 550                                                "pll-video0-2x",
 551                                                "pll-video1-2x", "pll-mipi" };
 552static SUNXI_CCU_MUX_WITH_GATE(lcd0_ch0_clk, "lcd0-ch0", lcd_ch0_parents,
 553                               0x118, 24, 2, BIT(31), CLK_SET_RATE_PARENT);
 554static SUNXI_CCU_MUX_WITH_GATE(lcd1_ch0_clk, "lcd1-ch0", lcd_ch0_parents,
 555                               0x11c, 24, 2, BIT(31), CLK_SET_RATE_PARENT);
 556
 557static const char * const lcd_ch1_parents[] = { "pll-video0", "pll-video1",
 558                                                "pll-video0-2x",
 559                                                "pll-video1-2x" };
 560static SUNXI_CCU_M_WITH_MUX_GATE(lcd0_ch1_clk, "lcd0-ch1", lcd_ch1_parents,
 561                                 0x12c, 0, 4, 24, 3, BIT(31),
 562                                 CLK_SET_RATE_PARENT);
 563static SUNXI_CCU_M_WITH_MUX_GATE(lcd1_ch1_clk, "lcd1-ch1", lcd_ch1_parents,
 564                                 0x130, 0, 4, 24, 3, BIT(31),
 565                                 CLK_SET_RATE_PARENT);
 566
 567static const char * const csi_sclk_parents[] = { "pll-video0", "pll-video1",
 568                                                 "pll9", "pll10", "pll-mipi",
 569                                                 "pll-ve" };
 570static SUNXI_CCU_M_WITH_MUX_GATE(csi0_sclk_clk, "csi0-sclk", csi_sclk_parents,
 571                                 0x134, 16, 4, 24, 3, BIT(31), 0);
 572
 573static const char * const csi_mclk_parents[] = { "pll-video0", "pll-video1",
 574                                                 "osc24M" };
 575static const u8 csi_mclk_table[] = { 0, 1, 5 };
 576static struct ccu_div csi0_mclk_clk = {
 577        .enable         = BIT(15),
 578        .div            = _SUNXI_CCU_DIV(0, 4),
 579        .mux            = _SUNXI_CCU_MUX_TABLE(8, 3, csi_mclk_table),
 580        .common         = {
 581                .reg            = 0x134,
 582                .hw.init        = CLK_HW_INIT_PARENTS("csi0-mclk",
 583                                                      csi_mclk_parents,
 584                                                      &ccu_div_ops,
 585                                                      0),
 586        },
 587};
 588
 589static struct ccu_div csi1_mclk_clk = {
 590        .enable         = BIT(15),
 591        .div            = _SUNXI_CCU_DIV(0, 4),
 592        .mux            = _SUNXI_CCU_MUX_TABLE(8, 3, csi_mclk_table),
 593        .common         = {
 594                .reg            = 0x138,
 595                .hw.init        = CLK_HW_INIT_PARENTS("csi1-mclk",
 596                                                      csi_mclk_parents,
 597                                                      &ccu_div_ops,
 598                                                      0),
 599        },
 600};
 601
 602static SUNXI_CCU_M_WITH_GATE(ve_clk, "ve", "pll-ve",
 603                             0x13c, 16, 3, BIT(31), 0);
 604
 605static SUNXI_CCU_GATE(codec_clk,        "codec",        "pll-audio",
 606                      0x140, BIT(31), CLK_SET_RATE_PARENT);
 607static SUNXI_CCU_GATE(avs_clk,          "avs",          "osc24M",
 608                      0x144, BIT(31), 0);
 609static SUNXI_CCU_GATE(digital_mic_clk,  "digital-mic",  "pll-audio",
 610                      0x148, BIT(31), CLK_SET_RATE_PARENT);
 611
 612static SUNXI_CCU_M_WITH_MUX_GATE(hdmi_clk, "hdmi", lcd_ch1_parents,
 613                                 0x150, 0, 4, 24, 2, BIT(31),
 614                                 CLK_SET_RATE_PARENT);
 615
 616static SUNXI_CCU_GATE(hdmi_ddc_clk, "ddc", "osc24M", 0x150, BIT(30), 0);
 617
 618static SUNXI_CCU_GATE(ps_clk, "ps", "lcd1-ch1", 0x140, BIT(31), 0);
 619
 620static const char * const mbus_parents[] = { "osc24M", "pll-periph",
 621                                             "pll-ddr" };
 622static SUNXI_CCU_MP_WITH_MUX_GATE(mbus0_clk, "mbus0", mbus_parents, 0x15c,
 623                                  0, 3,         /* M */
 624                                  16, 2,        /* P */
 625                                  24, 2,        /* mux */
 626                                  BIT(31),      /* gate */
 627                                  CLK_IS_CRITICAL);
 628
 629static SUNXI_CCU_MP_WITH_MUX_GATE(mbus1_clk, "mbus1", mbus_parents, 0x160,
 630                                  0, 3,         /* M */
 631                                  16, 2,        /* P */
 632                                  24, 2,        /* mux */
 633                                  BIT(31),      /* gate */
 634                                  CLK_IS_CRITICAL);
 635
 636static SUNXI_CCU_M_WITH_MUX_GATE(mipi_dsi_clk, "mipi-dsi", lcd_ch1_parents,
 637                                 0x168, 16, 3, 24, 2, BIT(31),
 638                                 CLK_SET_RATE_PARENT);
 639static SUNXI_CCU_M_WITH_MUX_GATE(mipi_dsi_dphy_clk, "mipi-dsi-dphy",
 640                                 lcd_ch1_parents, 0x168, 0, 3, 8, 2,
 641                                 BIT(15), CLK_SET_RATE_PARENT);
 642static SUNXI_CCU_M_WITH_MUX_GATE(mipi_csi_dphy_clk, "mipi-csi-dphy",
 643                                 lcd_ch1_parents, 0x16c, 0, 3, 8, 2,
 644                                 BIT(15), 0);
 645
 646static SUNXI_CCU_M_WITH_MUX_GATE(iep_drc0_clk, "iep-drc0", de_parents,
 647                                 0x180, 0, 3, 24, 2, BIT(31), 0);
 648static SUNXI_CCU_M_WITH_MUX_GATE(iep_drc1_clk, "iep-drc1", de_parents,
 649                                 0x184, 0, 3, 24, 2, BIT(31), 0);
 650static SUNXI_CCU_M_WITH_MUX_GATE(iep_deu0_clk, "iep-deu0", de_parents,
 651                                 0x188, 0, 3, 24, 2, BIT(31), 0);
 652static SUNXI_CCU_M_WITH_MUX_GATE(iep_deu1_clk, "iep-deu1", de_parents,
 653                                 0x18c, 0, 3, 24, 2, BIT(31), 0);
 654
 655static const char * const gpu_parents[] = { "pll-gpu", "pll-periph-2x",
 656                                            "pll-video0", "pll-video1",
 657                                            "pll9", "pll10" };
 658static const struct ccu_mux_fixed_prediv gpu_predivs[] = {
 659        { .index = 1, .div = 3, },
 660};
 661
 662static struct ccu_div gpu_core_clk = {
 663        .enable         = BIT(31),
 664        .div            = _SUNXI_CCU_DIV(0, 3),
 665        .mux            = {
 666                .shift          = 24,
 667                .width          = 3,
 668                .fixed_predivs  = gpu_predivs,
 669                .n_predivs      = ARRAY_SIZE(gpu_predivs),
 670        },
 671        .common         = {
 672                .reg            = 0x1a0,
 673                .features       = CCU_FEATURE_FIXED_PREDIV,
 674                .hw.init        = CLK_HW_INIT_PARENTS("gpu-core",
 675                                                      gpu_parents,
 676                                                      &ccu_div_ops,
 677                                                      0),
 678        },
 679};
 680
 681static struct ccu_div gpu_memory_clk = {
 682        .enable         = BIT(31),
 683        .div            = _SUNXI_CCU_DIV(0, 3),
 684        .mux            = {
 685                .shift          = 24,
 686                .width          = 3,
 687                .fixed_predivs  = gpu_predivs,
 688                .n_predivs      = ARRAY_SIZE(gpu_predivs),
 689        },
 690        .common         = {
 691                .reg            = 0x1a4,
 692                .features       = CCU_FEATURE_FIXED_PREDIV,
 693                .hw.init        = CLK_HW_INIT_PARENTS("gpu-memory",
 694                                                      gpu_parents,
 695                                                      &ccu_div_ops,
 696                                                      0),
 697        },
 698};
 699
 700static struct ccu_div gpu_hyd_clk = {
 701        .enable         = BIT(31),
 702        .div            = _SUNXI_CCU_DIV(0, 3),
 703        .mux            = {
 704                .shift          = 24,
 705                .width          = 3,
 706                .fixed_predivs  = gpu_predivs,
 707                .n_predivs      = ARRAY_SIZE(gpu_predivs),
 708        },
 709        .common         = {
 710                .reg            = 0x1a8,
 711                .features       = CCU_FEATURE_FIXED_PREDIV,
 712                .hw.init        = CLK_HW_INIT_PARENTS("gpu-hyd",
 713                                                      gpu_parents,
 714                                                      &ccu_div_ops,
 715                                                      0),
 716        },
 717};
 718
 719static SUNXI_CCU_M_WITH_MUX_GATE(ats_clk, "ats", mod0_default_parents, 0x1b0,
 720                                 0, 3,          /* M */
 721                                 24, 2,         /* mux */
 722                                 BIT(31),       /* gate */
 723                                 0);
 724
 725static SUNXI_CCU_M_WITH_MUX_GATE(trace_clk, "trace", mod0_default_parents,
 726                                 0x1b0,
 727                                 0, 3,          /* M */
 728                                 24, 2,         /* mux */
 729                                 BIT(31),       /* gate */
 730                                 0);
 731
 732static const char * const clk_out_parents[] = { "osc24M", "osc32k", "osc24M",
 733                                                "axi", "ahb1" };
 734static const u8 clk_out_table[] = { 0, 1, 2, 11, 13 };
 735
 736static const struct ccu_mux_fixed_prediv clk_out_predivs[] = {
 737        { .index = 0, .div = 750, },
 738        { .index = 3, .div = 4, },
 739        { .index = 4, .div = 4, },
 740};
 741
 742static struct ccu_mp out_a_clk = {
 743        .enable         = BIT(31),
 744        .m              = _SUNXI_CCU_DIV(8, 5),
 745        .p              = _SUNXI_CCU_DIV(20, 2),
 746        .mux            = {
 747                .shift          = 24,
 748                .width          = 4,
 749                .table          = clk_out_table,
 750                .fixed_predivs  = clk_out_predivs,
 751                .n_predivs      = ARRAY_SIZE(clk_out_predivs),
 752        },
 753        .common         = {
 754                .reg            = 0x300,
 755                .features       = CCU_FEATURE_FIXED_PREDIV,
 756                .hw.init        = CLK_HW_INIT_PARENTS("out-a",
 757                                                      clk_out_parents,
 758                                                      &ccu_mp_ops,
 759                                                      0),
 760        },
 761};
 762
 763static struct ccu_mp out_b_clk = {
 764        .enable         = BIT(31),
 765        .m              = _SUNXI_CCU_DIV(8, 5),
 766        .p              = _SUNXI_CCU_DIV(20, 2),
 767        .mux            = {
 768                .shift          = 24,
 769                .width          = 4,
 770                .table          = clk_out_table,
 771                .fixed_predivs  = clk_out_predivs,
 772                .n_predivs      = ARRAY_SIZE(clk_out_predivs),
 773        },
 774        .common         = {
 775                .reg            = 0x304,
 776                .features       = CCU_FEATURE_FIXED_PREDIV,
 777                .hw.init        = CLK_HW_INIT_PARENTS("out-b",
 778                                                      clk_out_parents,
 779                                                      &ccu_mp_ops,
 780                                                      0),
 781        },
 782};
 783
 784static struct ccu_mp out_c_clk = {
 785        .enable         = BIT(31),
 786        .m              = _SUNXI_CCU_DIV(8, 5),
 787        .p              = _SUNXI_CCU_DIV(20, 2),
 788        .mux            = {
 789                .shift          = 24,
 790                .width          = 4,
 791                .table          = clk_out_table,
 792                .fixed_predivs  = clk_out_predivs,
 793                .n_predivs      = ARRAY_SIZE(clk_out_predivs),
 794        },
 795        .common         = {
 796                .reg            = 0x308,
 797                .features       = CCU_FEATURE_FIXED_PREDIV,
 798                .hw.init        = CLK_HW_INIT_PARENTS("out-c",
 799                                                      clk_out_parents,
 800                                                      &ccu_mp_ops,
 801                                                      0),
 802        },
 803};
 804
 805static struct ccu_common *sun6i_a31_ccu_clks[] = {
 806        &pll_cpu_clk.common,
 807        &pll_audio_base_clk.common,
 808        &pll_video0_clk.common,
 809        &pll_ve_clk.common,
 810        &pll_ddr_clk.common,
 811        &pll_periph_clk.common,
 812        &pll_video1_clk.common,
 813        &pll_gpu_clk.common,
 814        &pll_mipi_clk.common,
 815        &pll9_clk.common,
 816        &pll10_clk.common,
 817        &cpu_clk.common,
 818        &axi_clk.common,
 819        &ahb1_clk.common,
 820        &apb1_clk.common,
 821        &apb2_clk.common,
 822        &ahb1_mipidsi_clk.common,
 823        &ahb1_ss_clk.common,
 824        &ahb1_dma_clk.common,
 825        &ahb1_mmc0_clk.common,
 826        &ahb1_mmc1_clk.common,
 827        &ahb1_mmc2_clk.common,
 828        &ahb1_mmc3_clk.common,
 829        &ahb1_nand1_clk.common,
 830        &ahb1_nand0_clk.common,
 831        &ahb1_sdram_clk.common,
 832        &ahb1_emac_clk.common,
 833        &ahb1_ts_clk.common,
 834        &ahb1_hstimer_clk.common,
 835        &ahb1_spi0_clk.common,
 836        &ahb1_spi1_clk.common,
 837        &ahb1_spi2_clk.common,
 838        &ahb1_spi3_clk.common,
 839        &ahb1_otg_clk.common,
 840        &ahb1_ehci0_clk.common,
 841        &ahb1_ehci1_clk.common,
 842        &ahb1_ohci0_clk.common,
 843        &ahb1_ohci1_clk.common,
 844        &ahb1_ohci2_clk.common,
 845        &ahb1_ve_clk.common,
 846        &ahb1_lcd0_clk.common,
 847        &ahb1_lcd1_clk.common,
 848        &ahb1_csi_clk.common,
 849        &ahb1_hdmi_clk.common,
 850        &ahb1_be0_clk.common,
 851        &ahb1_be1_clk.common,
 852        &ahb1_fe0_clk.common,
 853        &ahb1_fe1_clk.common,
 854        &ahb1_mp_clk.common,
 855        &ahb1_gpu_clk.common,
 856        &ahb1_deu0_clk.common,
 857        &ahb1_deu1_clk.common,
 858        &ahb1_drc0_clk.common,
 859        &ahb1_drc1_clk.common,
 860        &apb1_codec_clk.common,
 861        &apb1_spdif_clk.common,
 862        &apb1_digital_mic_clk.common,
 863        &apb1_pio_clk.common,
 864        &apb1_daudio0_clk.common,
 865        &apb1_daudio1_clk.common,
 866        &apb2_i2c0_clk.common,
 867        &apb2_i2c1_clk.common,
 868        &apb2_i2c2_clk.common,
 869        &apb2_i2c3_clk.common,
 870        &apb2_uart0_clk.common,
 871        &apb2_uart1_clk.common,
 872        &apb2_uart2_clk.common,
 873        &apb2_uart3_clk.common,
 874        &apb2_uart4_clk.common,
 875        &apb2_uart5_clk.common,
 876        &nand0_clk.common,
 877        &nand1_clk.common,
 878        &mmc0_clk.common,
 879        &mmc0_sample_clk.common,
 880        &mmc0_output_clk.common,
 881        &mmc1_clk.common,
 882        &mmc1_sample_clk.common,
 883        &mmc1_output_clk.common,
 884        &mmc2_clk.common,
 885        &mmc2_sample_clk.common,
 886        &mmc2_output_clk.common,
 887        &mmc3_clk.common,
 888        &mmc3_sample_clk.common,
 889        &mmc3_output_clk.common,
 890        &ts_clk.common,
 891        &ss_clk.common,
 892        &spi0_clk.common,
 893        &spi1_clk.common,
 894        &spi2_clk.common,
 895        &spi3_clk.common,
 896        &daudio0_clk.common,
 897        &daudio1_clk.common,
 898        &spdif_clk.common,
 899        &usb_phy0_clk.common,
 900        &usb_phy1_clk.common,
 901        &usb_phy2_clk.common,
 902        &usb_ohci0_clk.common,
 903        &usb_ohci1_clk.common,
 904        &usb_ohci2_clk.common,
 905        &mdfs_clk.common,
 906        &sdram0_clk.common,
 907        &sdram1_clk.common,
 908        &dram_ve_clk.common,
 909        &dram_csi_isp_clk.common,
 910        &dram_ts_clk.common,
 911        &dram_drc0_clk.common,
 912        &dram_drc1_clk.common,
 913        &dram_deu0_clk.common,
 914        &dram_deu1_clk.common,
 915        &dram_fe0_clk.common,
 916        &dram_fe1_clk.common,
 917        &dram_be0_clk.common,
 918        &dram_be1_clk.common,
 919        &dram_mp_clk.common,
 920        &be0_clk.common,
 921        &be1_clk.common,
 922        &fe0_clk.common,
 923        &fe1_clk.common,
 924        &mp_clk.common,
 925        &lcd0_ch0_clk.common,
 926        &lcd1_ch0_clk.common,
 927        &lcd0_ch1_clk.common,
 928        &lcd1_ch1_clk.common,
 929        &csi0_sclk_clk.common,
 930        &csi0_mclk_clk.common,
 931        &csi1_mclk_clk.common,
 932        &ve_clk.common,
 933        &codec_clk.common,
 934        &avs_clk.common,
 935        &digital_mic_clk.common,
 936        &hdmi_clk.common,
 937        &hdmi_ddc_clk.common,
 938        &ps_clk.common,
 939        &mbus0_clk.common,
 940        &mbus1_clk.common,
 941        &mipi_dsi_clk.common,
 942        &mipi_dsi_dphy_clk.common,
 943        &mipi_csi_dphy_clk.common,
 944        &iep_drc0_clk.common,
 945        &iep_drc1_clk.common,
 946        &iep_deu0_clk.common,
 947        &iep_deu1_clk.common,
 948        &gpu_core_clk.common,
 949        &gpu_memory_clk.common,
 950        &gpu_hyd_clk.common,
 951        &ats_clk.common,
 952        &trace_clk.common,
 953        &out_a_clk.common,
 954        &out_b_clk.common,
 955        &out_c_clk.common,
 956};
 957
 958/* We hardcode the divider to 1 for now */
 959static CLK_FIXED_FACTOR(pll_audio_clk, "pll-audio",
 960                        "pll-audio-base", 1, 1, CLK_SET_RATE_PARENT);
 961static CLK_FIXED_FACTOR(pll_audio_2x_clk, "pll-audio-2x",
 962                        "pll-audio-base", 2, 1, CLK_SET_RATE_PARENT);
 963static CLK_FIXED_FACTOR(pll_audio_4x_clk, "pll-audio-4x",
 964                        "pll-audio-base", 1, 1, CLK_SET_RATE_PARENT);
 965static CLK_FIXED_FACTOR(pll_audio_8x_clk, "pll-audio-8x",
 966                        "pll-audio-base", 1, 2, CLK_SET_RATE_PARENT);
 967static CLK_FIXED_FACTOR(pll_periph_2x_clk, "pll-periph-2x",
 968                        "pll-periph", 1, 2, 0);
 969static CLK_FIXED_FACTOR(pll_video0_2x_clk, "pll-video0-2x",
 970                        "pll-video0", 1, 2, CLK_SET_RATE_PARENT);
 971static CLK_FIXED_FACTOR(pll_video1_2x_clk, "pll-video1-2x",
 972                        "pll-video1", 1, 2, CLK_SET_RATE_PARENT);
 973
 974static struct clk_hw_onecell_data sun6i_a31_hw_clks = {
 975        .hws    = {
 976                [CLK_PLL_CPU]           = &pll_cpu_clk.common.hw,
 977                [CLK_PLL_AUDIO_BASE]    = &pll_audio_base_clk.common.hw,
 978                [CLK_PLL_AUDIO]         = &pll_audio_clk.hw,
 979                [CLK_PLL_AUDIO_2X]      = &pll_audio_2x_clk.hw,
 980                [CLK_PLL_AUDIO_4X]      = &pll_audio_4x_clk.hw,
 981                [CLK_PLL_AUDIO_8X]      = &pll_audio_8x_clk.hw,
 982                [CLK_PLL_VIDEO0]        = &pll_video0_clk.common.hw,
 983                [CLK_PLL_VIDEO0_2X]     = &pll_video0_2x_clk.hw,
 984                [CLK_PLL_VE]            = &pll_ve_clk.common.hw,
 985                [CLK_PLL_DDR]           = &pll_ddr_clk.common.hw,
 986                [CLK_PLL_PERIPH]        = &pll_periph_clk.common.hw,
 987                [CLK_PLL_PERIPH_2X]     = &pll_periph_2x_clk.hw,
 988                [CLK_PLL_VIDEO1]        = &pll_video1_clk.common.hw,
 989                [CLK_PLL_VIDEO1_2X]     = &pll_video1_2x_clk.hw,
 990                [CLK_PLL_GPU]           = &pll_gpu_clk.common.hw,
 991                [CLK_PLL_MIPI]          = &pll_mipi_clk.common.hw,
 992                [CLK_PLL9]              = &pll9_clk.common.hw,
 993                [CLK_PLL10]             = &pll10_clk.common.hw,
 994                [CLK_CPU]               = &cpu_clk.common.hw,
 995                [CLK_AXI]               = &axi_clk.common.hw,
 996                [CLK_AHB1]              = &ahb1_clk.common.hw,
 997                [CLK_APB1]              = &apb1_clk.common.hw,
 998                [CLK_APB2]              = &apb2_clk.common.hw,
 999                [CLK_AHB1_MIPIDSI]      = &ahb1_mipidsi_clk.common.hw,
1000                [CLK_AHB1_SS]           = &ahb1_ss_clk.common.hw,
1001                [CLK_AHB1_DMA]          = &ahb1_dma_clk.common.hw,
1002                [CLK_AHB1_MMC0]         = &ahb1_mmc0_clk.common.hw,
1003                [CLK_AHB1_MMC1]         = &ahb1_mmc1_clk.common.hw,
1004                [CLK_AHB1_MMC2]         = &ahb1_mmc2_clk.common.hw,
1005                [CLK_AHB1_MMC3]         = &ahb1_mmc3_clk.common.hw,
1006                [CLK_AHB1_NAND1]        = &ahb1_nand1_clk.common.hw,
1007                [CLK_AHB1_NAND0]        = &ahb1_nand0_clk.common.hw,
1008                [CLK_AHB1_SDRAM]        = &ahb1_sdram_clk.common.hw,
1009                [CLK_AHB1_EMAC]         = &ahb1_emac_clk.common.hw,
1010                [CLK_AHB1_TS]           = &ahb1_ts_clk.common.hw,
1011                [CLK_AHB1_HSTIMER]      = &ahb1_hstimer_clk.common.hw,
1012                [CLK_AHB1_SPI0]         = &ahb1_spi0_clk.common.hw,
1013                [CLK_AHB1_SPI1]         = &ahb1_spi1_clk.common.hw,
1014                [CLK_AHB1_SPI2]         = &ahb1_spi2_clk.common.hw,
1015                [CLK_AHB1_SPI3]         = &ahb1_spi3_clk.common.hw,
1016                [CLK_AHB1_OTG]          = &ahb1_otg_clk.common.hw,
1017                [CLK_AHB1_EHCI0]        = &ahb1_ehci0_clk.common.hw,
1018                [CLK_AHB1_EHCI1]        = &ahb1_ehci1_clk.common.hw,
1019                [CLK_AHB1_OHCI0]        = &ahb1_ohci0_clk.common.hw,
1020                [CLK_AHB1_OHCI1]        = &ahb1_ohci1_clk.common.hw,
1021                [CLK_AHB1_OHCI2]        = &ahb1_ohci2_clk.common.hw,
1022                [CLK_AHB1_VE]           = &ahb1_ve_clk.common.hw,
1023                [CLK_AHB1_LCD0]         = &ahb1_lcd0_clk.common.hw,
1024                [CLK_AHB1_LCD1]         = &ahb1_lcd1_clk.common.hw,
1025                [CLK_AHB1_CSI]          = &ahb1_csi_clk.common.hw,
1026                [CLK_AHB1_HDMI]         = &ahb1_hdmi_clk.common.hw,
1027                [CLK_AHB1_BE0]          = &ahb1_be0_clk.common.hw,
1028                [CLK_AHB1_BE1]          = &ahb1_be1_clk.common.hw,
1029                [CLK_AHB1_FE0]          = &ahb1_fe0_clk.common.hw,
1030                [CLK_AHB1_FE1]          = &ahb1_fe1_clk.common.hw,
1031                [CLK_AHB1_MP]           = &ahb1_mp_clk.common.hw,
1032                [CLK_AHB1_GPU]          = &ahb1_gpu_clk.common.hw,
1033                [CLK_AHB1_DEU0]         = &ahb1_deu0_clk.common.hw,
1034                [CLK_AHB1_DEU1]         = &ahb1_deu1_clk.common.hw,
1035                [CLK_AHB1_DRC0]         = &ahb1_drc0_clk.common.hw,
1036                [CLK_AHB1_DRC1]         = &ahb1_drc1_clk.common.hw,
1037                [CLK_APB1_CODEC]        = &apb1_codec_clk.common.hw,
1038                [CLK_APB1_SPDIF]        = &apb1_spdif_clk.common.hw,
1039                [CLK_APB1_DIGITAL_MIC]  = &apb1_digital_mic_clk.common.hw,
1040                [CLK_APB1_PIO]          = &apb1_pio_clk.common.hw,
1041                [CLK_APB1_DAUDIO0]      = &apb1_daudio0_clk.common.hw,
1042                [CLK_APB1_DAUDIO1]      = &apb1_daudio1_clk.common.hw,
1043                [CLK_APB2_I2C0]         = &apb2_i2c0_clk.common.hw,
1044                [CLK_APB2_I2C1]         = &apb2_i2c1_clk.common.hw,
1045                [CLK_APB2_I2C2]         = &apb2_i2c2_clk.common.hw,
1046                [CLK_APB2_I2C3]         = &apb2_i2c3_clk.common.hw,
1047                [CLK_APB2_UART0]        = &apb2_uart0_clk.common.hw,
1048                [CLK_APB2_UART1]        = &apb2_uart1_clk.common.hw,
1049                [CLK_APB2_UART2]        = &apb2_uart2_clk.common.hw,
1050                [CLK_APB2_UART3]        = &apb2_uart3_clk.common.hw,
1051                [CLK_APB2_UART4]        = &apb2_uart4_clk.common.hw,
1052                [CLK_APB2_UART5]        = &apb2_uart5_clk.common.hw,
1053                [CLK_NAND0]             = &nand0_clk.common.hw,
1054                [CLK_NAND1]             = &nand1_clk.common.hw,
1055                [CLK_MMC0]              = &mmc0_clk.common.hw,
1056                [CLK_MMC0_SAMPLE]       = &mmc0_sample_clk.common.hw,
1057                [CLK_MMC0_OUTPUT]       = &mmc0_output_clk.common.hw,
1058                [CLK_MMC1]              = &mmc1_clk.common.hw,
1059                [CLK_MMC1_SAMPLE]       = &mmc1_sample_clk.common.hw,
1060                [CLK_MMC1_OUTPUT]       = &mmc1_output_clk.common.hw,
1061                [CLK_MMC2]              = &mmc2_clk.common.hw,
1062                [CLK_MMC2_SAMPLE]       = &mmc2_sample_clk.common.hw,
1063                [CLK_MMC2_OUTPUT]       = &mmc2_output_clk.common.hw,
1064                [CLK_MMC3]              = &mmc3_clk.common.hw,
1065                [CLK_MMC3_SAMPLE]       = &mmc3_sample_clk.common.hw,
1066                [CLK_MMC3_OUTPUT]       = &mmc3_output_clk.common.hw,
1067                [CLK_TS]                = &ts_clk.common.hw,
1068                [CLK_SS]                = &ss_clk.common.hw,
1069                [CLK_SPI0]              = &spi0_clk.common.hw,
1070                [CLK_SPI1]              = &spi1_clk.common.hw,
1071                [CLK_SPI2]              = &spi2_clk.common.hw,
1072                [CLK_SPI3]              = &spi3_clk.common.hw,
1073                [CLK_DAUDIO0]           = &daudio0_clk.common.hw,
1074                [CLK_DAUDIO1]           = &daudio1_clk.common.hw,
1075                [CLK_SPDIF]             = &spdif_clk.common.hw,
1076                [CLK_USB_PHY0]          = &usb_phy0_clk.common.hw,
1077                [CLK_USB_PHY1]          = &usb_phy1_clk.common.hw,
1078                [CLK_USB_PHY2]          = &usb_phy2_clk.common.hw,
1079                [CLK_USB_OHCI0]         = &usb_ohci0_clk.common.hw,
1080                [CLK_USB_OHCI1]         = &usb_ohci1_clk.common.hw,
1081                [CLK_USB_OHCI2]         = &usb_ohci2_clk.common.hw,
1082                [CLK_MDFS]              = &mdfs_clk.common.hw,
1083                [CLK_SDRAM0]            = &sdram0_clk.common.hw,
1084                [CLK_SDRAM1]            = &sdram1_clk.common.hw,
1085                [CLK_DRAM_VE]           = &dram_ve_clk.common.hw,
1086                [CLK_DRAM_CSI_ISP]      = &dram_csi_isp_clk.common.hw,
1087                [CLK_DRAM_TS]           = &dram_ts_clk.common.hw,
1088                [CLK_DRAM_DRC0]         = &dram_drc0_clk.common.hw,
1089                [CLK_DRAM_DRC1]         = &dram_drc1_clk.common.hw,
1090                [CLK_DRAM_DEU0]         = &dram_deu0_clk.common.hw,
1091                [CLK_DRAM_DEU1]         = &dram_deu1_clk.common.hw,
1092                [CLK_DRAM_FE0]          = &dram_fe0_clk.common.hw,
1093                [CLK_DRAM_FE1]          = &dram_fe1_clk.common.hw,
1094                [CLK_DRAM_BE0]          = &dram_be0_clk.common.hw,
1095                [CLK_DRAM_BE1]          = &dram_be1_clk.common.hw,
1096                [CLK_DRAM_MP]           = &dram_mp_clk.common.hw,
1097                [CLK_BE0]               = &be0_clk.common.hw,
1098                [CLK_BE1]               = &be1_clk.common.hw,
1099                [CLK_FE0]               = &fe0_clk.common.hw,
1100                [CLK_FE1]               = &fe1_clk.common.hw,
1101                [CLK_MP]                = &mp_clk.common.hw,
1102                [CLK_LCD0_CH0]          = &lcd0_ch0_clk.common.hw,
1103                [CLK_LCD1_CH0]          = &lcd1_ch0_clk.common.hw,
1104                [CLK_LCD0_CH1]          = &lcd0_ch1_clk.common.hw,
1105                [CLK_LCD1_CH1]          = &lcd1_ch1_clk.common.hw,
1106                [CLK_CSI0_SCLK]         = &csi0_sclk_clk.common.hw,
1107                [CLK_CSI0_MCLK]         = &csi0_mclk_clk.common.hw,
1108                [CLK_CSI1_MCLK]         = &csi1_mclk_clk.common.hw,
1109                [CLK_VE]                = &ve_clk.common.hw,
1110                [CLK_CODEC]             = &codec_clk.common.hw,
1111                [CLK_AVS]               = &avs_clk.common.hw,
1112                [CLK_DIGITAL_MIC]       = &digital_mic_clk.common.hw,
1113                [CLK_HDMI]              = &hdmi_clk.common.hw,
1114                [CLK_HDMI_DDC]          = &hdmi_ddc_clk.common.hw,
1115                [CLK_PS]                = &ps_clk.common.hw,
1116                [CLK_MBUS0]             = &mbus0_clk.common.hw,
1117                [CLK_MBUS1]             = &mbus1_clk.common.hw,
1118                [CLK_MIPI_DSI]          = &mipi_dsi_clk.common.hw,
1119                [CLK_MIPI_DSI_DPHY]     = &mipi_dsi_dphy_clk.common.hw,
1120                [CLK_MIPI_CSI_DPHY]     = &mipi_csi_dphy_clk.common.hw,
1121                [CLK_IEP_DRC0]          = &iep_drc0_clk.common.hw,
1122                [CLK_IEP_DRC1]          = &iep_drc1_clk.common.hw,
1123                [CLK_IEP_DEU0]          = &iep_deu0_clk.common.hw,
1124                [CLK_IEP_DEU1]          = &iep_deu1_clk.common.hw,
1125                [CLK_GPU_CORE]          = &gpu_core_clk.common.hw,
1126                [CLK_GPU_MEMORY]        = &gpu_memory_clk.common.hw,
1127                [CLK_GPU_HYD]           = &gpu_hyd_clk.common.hw,
1128                [CLK_ATS]               = &ats_clk.common.hw,
1129                [CLK_TRACE]             = &trace_clk.common.hw,
1130                [CLK_OUT_A]             = &out_a_clk.common.hw,
1131                [CLK_OUT_B]             = &out_b_clk.common.hw,
1132                [CLK_OUT_C]             = &out_c_clk.common.hw,
1133        },
1134        .num    = CLK_NUMBER,
1135};
1136
1137static struct ccu_reset_map sun6i_a31_ccu_resets[] = {
1138        [RST_USB_PHY0]          = { 0x0cc, BIT(0) },
1139        [RST_USB_PHY1]          = { 0x0cc, BIT(1) },
1140        [RST_USB_PHY2]          = { 0x0cc, BIT(2) },
1141
1142        [RST_AHB1_MIPI_DSI]     = { 0x2c0, BIT(1) },
1143        [RST_AHB1_SS]           = { 0x2c0, BIT(5) },
1144        [RST_AHB1_DMA]          = { 0x2c0, BIT(6) },
1145        [RST_AHB1_MMC0]         = { 0x2c0, BIT(8) },
1146        [RST_AHB1_MMC1]         = { 0x2c0, BIT(9) },
1147        [RST_AHB1_MMC2]         = { 0x2c0, BIT(10) },
1148        [RST_AHB1_MMC3]         = { 0x2c0, BIT(11) },
1149        [RST_AHB1_NAND1]        = { 0x2c0, BIT(12) },
1150        [RST_AHB1_NAND0]        = { 0x2c0, BIT(13) },
1151        [RST_AHB1_SDRAM]        = { 0x2c0, BIT(14) },
1152        [RST_AHB1_EMAC]         = { 0x2c0, BIT(17) },
1153        [RST_AHB1_TS]           = { 0x2c0, BIT(18) },
1154        [RST_AHB1_HSTIMER]      = { 0x2c0, BIT(19) },
1155        [RST_AHB1_SPI0]         = { 0x2c0, BIT(20) },
1156        [RST_AHB1_SPI1]         = { 0x2c0, BIT(21) },
1157        [RST_AHB1_SPI2]         = { 0x2c0, BIT(22) },
1158        [RST_AHB1_SPI3]         = { 0x2c0, BIT(23) },
1159        [RST_AHB1_OTG]          = { 0x2c0, BIT(24) },
1160        [RST_AHB1_EHCI0]        = { 0x2c0, BIT(26) },
1161        [RST_AHB1_EHCI1]        = { 0x2c0, BIT(27) },
1162        [RST_AHB1_OHCI0]        = { 0x2c0, BIT(29) },
1163        [RST_AHB1_OHCI1]        = { 0x2c0, BIT(30) },
1164        [RST_AHB1_OHCI2]        = { 0x2c0, BIT(31) },
1165
1166        [RST_AHB1_VE]           = { 0x2c4, BIT(0) },
1167        [RST_AHB1_LCD0]         = { 0x2c4, BIT(4) },
1168        [RST_AHB1_LCD1]         = { 0x2c4, BIT(5) },
1169        [RST_AHB1_CSI]          = { 0x2c4, BIT(8) },
1170        [RST_AHB1_HDMI]         = { 0x2c4, BIT(11) },
1171        [RST_AHB1_BE0]          = { 0x2c4, BIT(12) },
1172        [RST_AHB1_BE1]          = { 0x2c4, BIT(13) },
1173        [RST_AHB1_FE0]          = { 0x2c4, BIT(14) },
1174        [RST_AHB1_FE1]          = { 0x2c4, BIT(15) },
1175        [RST_AHB1_MP]           = { 0x2c4, BIT(18) },
1176        [RST_AHB1_GPU]          = { 0x2c4, BIT(20) },
1177        [RST_AHB1_DEU0]         = { 0x2c4, BIT(23) },
1178        [RST_AHB1_DEU1]         = { 0x2c4, BIT(24) },
1179        [RST_AHB1_DRC0]         = { 0x2c4, BIT(25) },
1180        [RST_AHB1_DRC1]         = { 0x2c4, BIT(26) },
1181        [RST_AHB1_LVDS]         = { 0x2c8, BIT(0) },
1182
1183        [RST_APB1_CODEC]        = { 0x2d0, BIT(0) },
1184        [RST_APB1_SPDIF]        = { 0x2d0, BIT(1) },
1185        [RST_APB1_DIGITAL_MIC]  = { 0x2d0, BIT(4) },
1186        [RST_APB1_DAUDIO0]      = { 0x2d0, BIT(12) },
1187        [RST_APB1_DAUDIO1]      = { 0x2d0, BIT(13) },
1188
1189        [RST_APB2_I2C0]         = { 0x2d8, BIT(0) },
1190        [RST_APB2_I2C1]         = { 0x2d8, BIT(1) },
1191        [RST_APB2_I2C2]         = { 0x2d8, BIT(2) },
1192        [RST_APB2_I2C3]         = { 0x2d8, BIT(3) },
1193        [RST_APB2_UART0]        = { 0x2d8, BIT(16) },
1194        [RST_APB2_UART1]        = { 0x2d8, BIT(17) },
1195        [RST_APB2_UART2]        = { 0x2d8, BIT(18) },
1196        [RST_APB2_UART3]        = { 0x2d8, BIT(19) },
1197        [RST_APB2_UART4]        = { 0x2d8, BIT(20) },
1198        [RST_APB2_UART5]        = { 0x2d8, BIT(21) },
1199};
1200
1201static const struct sunxi_ccu_desc sun6i_a31_ccu_desc = {
1202        .ccu_clks       = sun6i_a31_ccu_clks,
1203        .num_ccu_clks   = ARRAY_SIZE(sun6i_a31_ccu_clks),
1204
1205        .hw_clks        = &sun6i_a31_hw_clks,
1206
1207        .resets         = sun6i_a31_ccu_resets,
1208        .num_resets     = ARRAY_SIZE(sun6i_a31_ccu_resets),
1209};
1210
1211static struct ccu_mux_nb sun6i_a31_cpu_nb = {
1212        .common         = &cpu_clk.common,
1213        .cm             = &cpu_clk.mux,
1214        .delay_us       = 1, /* > 8 clock cycles at 24 MHz */
1215        .bypass_index   = 1, /* index of 24 MHz oscillator */
1216};
1217
1218static void __init sun6i_a31_ccu_setup(struct device_node *node)
1219{
1220        void __iomem *reg;
1221        u32 val;
1222
1223        reg = of_io_request_and_map(node, 0, of_node_full_name(node));
1224        if (IS_ERR(reg)) {
1225                pr_err("%pOF: Could not map the clock registers\n", node);
1226                return;
1227        }
1228
1229        /* Force the PLL-Audio-1x divider to 1 */
1230        val = readl(reg + SUN6I_A31_PLL_AUDIO_REG);
1231        val &= ~GENMASK(19, 16);
1232        writel(val | (0 << 16), reg + SUN6I_A31_PLL_AUDIO_REG);
1233
1234        /* Force PLL-MIPI to MIPI mode */
1235        val = readl(reg + SUN6I_A31_PLL_MIPI_REG);
1236        val &= BIT(16);
1237        writel(val, reg + SUN6I_A31_PLL_MIPI_REG);
1238
1239        /* Force AHB1 to PLL6 / 3 */
1240        val = readl(reg + SUN6I_A31_AHB1_REG);
1241        /* set PLL6 pre-div = 3 */
1242        val &= ~GENMASK(7, 6);
1243        val |= 0x2 << 6;
1244        /* select PLL6 / pre-div */
1245        val &= ~GENMASK(13, 12);
1246        val |= 0x3 << 12;
1247        writel(val, reg + SUN6I_A31_AHB1_REG);
1248
1249        sunxi_ccu_probe(node, reg, &sun6i_a31_ccu_desc);
1250
1251        ccu_mux_notifier_register(pll_cpu_clk.common.hw.clk,
1252                                  &sun6i_a31_cpu_nb);
1253}
1254CLK_OF_DECLARE(sun6i_a31_ccu, "allwinner,sun6i-a31-ccu",
1255               sun6i_a31_ccu_setup);
1256