linux/drivers/dma/stm32-dma.c
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   1// SPDX-License-Identifier: GPL-2.0-only
   2/*
   3 * Driver for STM32 DMA controller
   4 *
   5 * Inspired by dma-jz4740.c and tegra20-apb-dma.c
   6 *
   7 * Copyright (C) M'boumba Cedric Madianga 2015
   8 * Author: M'boumba Cedric Madianga <cedric.madianga@gmail.com>
   9 *         Pierre-Yves Mordret <pierre-yves.mordret@st.com>
  10 */
  11
  12#include <linux/clk.h>
  13#include <linux/delay.h>
  14#include <linux/dmaengine.h>
  15#include <linux/dma-mapping.h>
  16#include <linux/err.h>
  17#include <linux/init.h>
  18#include <linux/jiffies.h>
  19#include <linux/list.h>
  20#include <linux/module.h>
  21#include <linux/of.h>
  22#include <linux/of_device.h>
  23#include <linux/of_dma.h>
  24#include <linux/platform_device.h>
  25#include <linux/pm_runtime.h>
  26#include <linux/reset.h>
  27#include <linux/sched.h>
  28#include <linux/slab.h>
  29
  30#include "virt-dma.h"
  31
  32#define STM32_DMA_LISR                  0x0000 /* DMA Low Int Status Reg */
  33#define STM32_DMA_HISR                  0x0004 /* DMA High Int Status Reg */
  34#define STM32_DMA_LIFCR                 0x0008 /* DMA Low Int Flag Clear Reg */
  35#define STM32_DMA_HIFCR                 0x000c /* DMA High Int Flag Clear Reg */
  36#define STM32_DMA_TCI                   BIT(5) /* Transfer Complete Interrupt */
  37#define STM32_DMA_HTI                   BIT(4) /* Half Transfer Interrupt */
  38#define STM32_DMA_TEI                   BIT(3) /* Transfer Error Interrupt */
  39#define STM32_DMA_DMEI                  BIT(2) /* Direct Mode Error Interrupt */
  40#define STM32_DMA_FEI                   BIT(0) /* FIFO Error Interrupt */
  41#define STM32_DMA_MASKI                 (STM32_DMA_TCI \
  42                                         | STM32_DMA_TEI \
  43                                         | STM32_DMA_DMEI \
  44                                         | STM32_DMA_FEI)
  45
  46/* DMA Stream x Configuration Register */
  47#define STM32_DMA_SCR(x)                (0x0010 + 0x18 * (x)) /* x = 0..7 */
  48#define STM32_DMA_SCR_REQ(n)            ((n & 0x7) << 25)
  49#define STM32_DMA_SCR_MBURST_MASK       GENMASK(24, 23)
  50#define STM32_DMA_SCR_MBURST(n)         ((n & 0x3) << 23)
  51#define STM32_DMA_SCR_PBURST_MASK       GENMASK(22, 21)
  52#define STM32_DMA_SCR_PBURST(n)         ((n & 0x3) << 21)
  53#define STM32_DMA_SCR_PL_MASK           GENMASK(17, 16)
  54#define STM32_DMA_SCR_PL(n)             ((n & 0x3) << 16)
  55#define STM32_DMA_SCR_MSIZE_MASK        GENMASK(14, 13)
  56#define STM32_DMA_SCR_MSIZE(n)          ((n & 0x3) << 13)
  57#define STM32_DMA_SCR_PSIZE_MASK        GENMASK(12, 11)
  58#define STM32_DMA_SCR_PSIZE(n)          ((n & 0x3) << 11)
  59#define STM32_DMA_SCR_PSIZE_GET(n)      ((n & STM32_DMA_SCR_PSIZE_MASK) >> 11)
  60#define STM32_DMA_SCR_DIR_MASK          GENMASK(7, 6)
  61#define STM32_DMA_SCR_DIR(n)            ((n & 0x3) << 6)
  62#define STM32_DMA_SCR_CT                BIT(19) /* Target in double buffer */
  63#define STM32_DMA_SCR_DBM               BIT(18) /* Double Buffer Mode */
  64#define STM32_DMA_SCR_PINCOS            BIT(15) /* Peripheral inc offset size */
  65#define STM32_DMA_SCR_MINC              BIT(10) /* Memory increment mode */
  66#define STM32_DMA_SCR_PINC              BIT(9) /* Peripheral increment mode */
  67#define STM32_DMA_SCR_CIRC              BIT(8) /* Circular mode */
  68#define STM32_DMA_SCR_PFCTRL            BIT(5) /* Peripheral Flow Controller */
  69#define STM32_DMA_SCR_TCIE              BIT(4) /* Transfer Complete Int Enable
  70                                                */
  71#define STM32_DMA_SCR_TEIE              BIT(2) /* Transfer Error Int Enable */
  72#define STM32_DMA_SCR_DMEIE             BIT(1) /* Direct Mode Err Int Enable */
  73#define STM32_DMA_SCR_EN                BIT(0) /* Stream Enable */
  74#define STM32_DMA_SCR_CFG_MASK          (STM32_DMA_SCR_PINC \
  75                                        | STM32_DMA_SCR_MINC \
  76                                        | STM32_DMA_SCR_PINCOS \
  77                                        | STM32_DMA_SCR_PL_MASK)
  78#define STM32_DMA_SCR_IRQ_MASK          (STM32_DMA_SCR_TCIE \
  79                                        | STM32_DMA_SCR_TEIE \
  80                                        | STM32_DMA_SCR_DMEIE)
  81
  82/* DMA Stream x number of data register */
  83#define STM32_DMA_SNDTR(x)              (0x0014 + 0x18 * (x))
  84
  85/* DMA stream peripheral address register */
  86#define STM32_DMA_SPAR(x)               (0x0018 + 0x18 * (x))
  87
  88/* DMA stream x memory 0 address register */
  89#define STM32_DMA_SM0AR(x)              (0x001c + 0x18 * (x))
  90
  91/* DMA stream x memory 1 address register */
  92#define STM32_DMA_SM1AR(x)              (0x0020 + 0x18 * (x))
  93
  94/* DMA stream x FIFO control register */
  95#define STM32_DMA_SFCR(x)               (0x0024 + 0x18 * (x))
  96#define STM32_DMA_SFCR_FTH_MASK         GENMASK(1, 0)
  97#define STM32_DMA_SFCR_FTH(n)           (n & STM32_DMA_SFCR_FTH_MASK)
  98#define STM32_DMA_SFCR_FEIE             BIT(7) /* FIFO error interrupt enable */
  99#define STM32_DMA_SFCR_DMDIS            BIT(2) /* Direct mode disable */
 100#define STM32_DMA_SFCR_MASK             (STM32_DMA_SFCR_FEIE \
 101                                        | STM32_DMA_SFCR_DMDIS)
 102
 103/* DMA direction */
 104#define STM32_DMA_DEV_TO_MEM            0x00
 105#define STM32_DMA_MEM_TO_DEV            0x01
 106#define STM32_DMA_MEM_TO_MEM            0x02
 107
 108/* DMA priority level */
 109#define STM32_DMA_PRIORITY_LOW          0x00
 110#define STM32_DMA_PRIORITY_MEDIUM       0x01
 111#define STM32_DMA_PRIORITY_HIGH         0x02
 112#define STM32_DMA_PRIORITY_VERY_HIGH    0x03
 113
 114/* DMA FIFO threshold selection */
 115#define STM32_DMA_FIFO_THRESHOLD_1QUARTERFULL           0x00
 116#define STM32_DMA_FIFO_THRESHOLD_HALFFULL               0x01
 117#define STM32_DMA_FIFO_THRESHOLD_3QUARTERSFULL          0x02
 118#define STM32_DMA_FIFO_THRESHOLD_FULL                   0x03
 119
 120#define STM32_DMA_MAX_DATA_ITEMS        0xffff
 121/*
 122 * Valid transfer starts from @0 to @0xFFFE leading to unaligned scatter
 123 * gather at boundary. Thus it's safer to round down this value on FIFO
 124 * size (16 Bytes)
 125 */
 126#define STM32_DMA_ALIGNED_MAX_DATA_ITEMS        \
 127        ALIGN_DOWN(STM32_DMA_MAX_DATA_ITEMS, 16)
 128#define STM32_DMA_MAX_CHANNELS          0x08
 129#define STM32_DMA_MAX_REQUEST_ID        0x08
 130#define STM32_DMA_MAX_DATA_PARAM        0x03
 131#define STM32_DMA_FIFO_SIZE             16      /* FIFO is 16 bytes */
 132#define STM32_DMA_MIN_BURST             4
 133#define STM32_DMA_MAX_BURST             16
 134
 135/* DMA Features */
 136#define STM32_DMA_THRESHOLD_FTR_MASK    GENMASK(1, 0)
 137#define STM32_DMA_THRESHOLD_FTR_GET(n)  ((n) & STM32_DMA_THRESHOLD_FTR_MASK)
 138
 139enum stm32_dma_width {
 140        STM32_DMA_BYTE,
 141        STM32_DMA_HALF_WORD,
 142        STM32_DMA_WORD,
 143};
 144
 145enum stm32_dma_burst_size {
 146        STM32_DMA_BURST_SINGLE,
 147        STM32_DMA_BURST_INCR4,
 148        STM32_DMA_BURST_INCR8,
 149        STM32_DMA_BURST_INCR16,
 150};
 151
 152/**
 153 * struct stm32_dma_cfg - STM32 DMA custom configuration
 154 * @channel_id: channel ID
 155 * @request_line: DMA request
 156 * @stream_config: 32bit mask specifying the DMA channel configuration
 157 * @features: 32bit mask specifying the DMA Feature list
 158 */
 159struct stm32_dma_cfg {
 160        u32 channel_id;
 161        u32 request_line;
 162        u32 stream_config;
 163        u32 features;
 164};
 165
 166struct stm32_dma_chan_reg {
 167        u32 dma_lisr;
 168        u32 dma_hisr;
 169        u32 dma_lifcr;
 170        u32 dma_hifcr;
 171        u32 dma_scr;
 172        u32 dma_sndtr;
 173        u32 dma_spar;
 174        u32 dma_sm0ar;
 175        u32 dma_sm1ar;
 176        u32 dma_sfcr;
 177};
 178
 179struct stm32_dma_sg_req {
 180        u32 len;
 181        struct stm32_dma_chan_reg chan_reg;
 182};
 183
 184struct stm32_dma_desc {
 185        struct virt_dma_desc vdesc;
 186        bool cyclic;
 187        u32 num_sgs;
 188        struct stm32_dma_sg_req sg_req[];
 189};
 190
 191struct stm32_dma_chan {
 192        struct virt_dma_chan vchan;
 193        bool config_init;
 194        bool busy;
 195        u32 id;
 196        u32 irq;
 197        struct stm32_dma_desc *desc;
 198        u32 next_sg;
 199        struct dma_slave_config dma_sconfig;
 200        struct stm32_dma_chan_reg chan_reg;
 201        u32 threshold;
 202        u32 mem_burst;
 203        u32 mem_width;
 204};
 205
 206struct stm32_dma_device {
 207        struct dma_device ddev;
 208        void __iomem *base;
 209        struct clk *clk;
 210        struct reset_control *rst;
 211        bool mem2mem;
 212        struct stm32_dma_chan chan[STM32_DMA_MAX_CHANNELS];
 213};
 214
 215static struct stm32_dma_device *stm32_dma_get_dev(struct stm32_dma_chan *chan)
 216{
 217        return container_of(chan->vchan.chan.device, struct stm32_dma_device,
 218                            ddev);
 219}
 220
 221static struct stm32_dma_chan *to_stm32_dma_chan(struct dma_chan *c)
 222{
 223        return container_of(c, struct stm32_dma_chan, vchan.chan);
 224}
 225
 226static struct stm32_dma_desc *to_stm32_dma_desc(struct virt_dma_desc *vdesc)
 227{
 228        return container_of(vdesc, struct stm32_dma_desc, vdesc);
 229}
 230
 231static struct device *chan2dev(struct stm32_dma_chan *chan)
 232{
 233        return &chan->vchan.chan.dev->device;
 234}
 235
 236static u32 stm32_dma_read(struct stm32_dma_device *dmadev, u32 reg)
 237{
 238        return readl_relaxed(dmadev->base + reg);
 239}
 240
 241static void stm32_dma_write(struct stm32_dma_device *dmadev, u32 reg, u32 val)
 242{
 243        writel_relaxed(val, dmadev->base + reg);
 244}
 245
 246static struct stm32_dma_desc *stm32_dma_alloc_desc(u32 num_sgs)
 247{
 248        return kzalloc(sizeof(struct stm32_dma_desc) +
 249                       sizeof(struct stm32_dma_sg_req) * num_sgs, GFP_NOWAIT);
 250}
 251
 252static int stm32_dma_get_width(struct stm32_dma_chan *chan,
 253                               enum dma_slave_buswidth width)
 254{
 255        switch (width) {
 256        case DMA_SLAVE_BUSWIDTH_1_BYTE:
 257                return STM32_DMA_BYTE;
 258        case DMA_SLAVE_BUSWIDTH_2_BYTES:
 259                return STM32_DMA_HALF_WORD;
 260        case DMA_SLAVE_BUSWIDTH_4_BYTES:
 261                return STM32_DMA_WORD;
 262        default:
 263                dev_err(chan2dev(chan), "Dma bus width not supported\n");
 264                return -EINVAL;
 265        }
 266}
 267
 268static enum dma_slave_buswidth stm32_dma_get_max_width(u32 buf_len,
 269                                                       u32 threshold)
 270{
 271        enum dma_slave_buswidth max_width;
 272
 273        if (threshold == STM32_DMA_FIFO_THRESHOLD_FULL)
 274                max_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 275        else
 276                max_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
 277
 278        while ((buf_len < max_width  || buf_len % max_width) &&
 279               max_width > DMA_SLAVE_BUSWIDTH_1_BYTE)
 280                max_width = max_width >> 1;
 281
 282        return max_width;
 283}
 284
 285static bool stm32_dma_fifo_threshold_is_allowed(u32 burst, u32 threshold,
 286                                                enum dma_slave_buswidth width)
 287{
 288        u32 remaining;
 289
 290        if (width != DMA_SLAVE_BUSWIDTH_UNDEFINED) {
 291                if (burst != 0) {
 292                        /*
 293                         * If number of beats fit in several whole bursts
 294                         * this configuration is allowed.
 295                         */
 296                        remaining = ((STM32_DMA_FIFO_SIZE / width) *
 297                                     (threshold + 1) / 4) % burst;
 298
 299                        if (remaining == 0)
 300                                return true;
 301                } else {
 302                        return true;
 303                }
 304        }
 305
 306        return false;
 307}
 308
 309static bool stm32_dma_is_burst_possible(u32 buf_len, u32 threshold)
 310{
 311        /*
 312         * Buffer or period length has to be aligned on FIFO depth.
 313         * Otherwise bytes may be stuck within FIFO at buffer or period
 314         * length.
 315         */
 316        return ((buf_len % ((threshold + 1) * 4)) == 0);
 317}
 318
 319static u32 stm32_dma_get_best_burst(u32 buf_len, u32 max_burst, u32 threshold,
 320                                    enum dma_slave_buswidth width)
 321{
 322        u32 best_burst = max_burst;
 323
 324        if (best_burst == 1 || !stm32_dma_is_burst_possible(buf_len, threshold))
 325                return 0;
 326
 327        while ((buf_len < best_burst * width && best_burst > 1) ||
 328               !stm32_dma_fifo_threshold_is_allowed(best_burst, threshold,
 329                                                    width)) {
 330                if (best_burst > STM32_DMA_MIN_BURST)
 331                        best_burst = best_burst >> 1;
 332                else
 333                        best_burst = 0;
 334        }
 335
 336        return best_burst;
 337}
 338
 339static int stm32_dma_get_burst(struct stm32_dma_chan *chan, u32 maxburst)
 340{
 341        switch (maxburst) {
 342        case 0:
 343        case 1:
 344                return STM32_DMA_BURST_SINGLE;
 345        case 4:
 346                return STM32_DMA_BURST_INCR4;
 347        case 8:
 348                return STM32_DMA_BURST_INCR8;
 349        case 16:
 350                return STM32_DMA_BURST_INCR16;
 351        default:
 352                dev_err(chan2dev(chan), "Dma burst size not supported\n");
 353                return -EINVAL;
 354        }
 355}
 356
 357static void stm32_dma_set_fifo_config(struct stm32_dma_chan *chan,
 358                                      u32 src_burst, u32 dst_burst)
 359{
 360        chan->chan_reg.dma_sfcr &= ~STM32_DMA_SFCR_MASK;
 361        chan->chan_reg.dma_scr &= ~STM32_DMA_SCR_DMEIE;
 362
 363        if (!src_burst && !dst_burst) {
 364                /* Using direct mode */
 365                chan->chan_reg.dma_scr |= STM32_DMA_SCR_DMEIE;
 366        } else {
 367                /* Using FIFO mode */
 368                chan->chan_reg.dma_sfcr |= STM32_DMA_SFCR_MASK;
 369        }
 370}
 371
 372static int stm32_dma_slave_config(struct dma_chan *c,
 373                                  struct dma_slave_config *config)
 374{
 375        struct stm32_dma_chan *chan = to_stm32_dma_chan(c);
 376
 377        memcpy(&chan->dma_sconfig, config, sizeof(*config));
 378
 379        chan->config_init = true;
 380
 381        return 0;
 382}
 383
 384static u32 stm32_dma_irq_status(struct stm32_dma_chan *chan)
 385{
 386        struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan);
 387        u32 flags, dma_isr;
 388
 389        /*
 390         * Read "flags" from DMA_xISR register corresponding to the selected
 391         * DMA channel at the correct bit offset inside that register.
 392         *
 393         * If (ch % 4) is 2 or 3, left shift the mask by 16 bits.
 394         * If (ch % 4) is 1 or 3, additionally left shift the mask by 6 bits.
 395         */
 396
 397        if (chan->id & 4)
 398                dma_isr = stm32_dma_read(dmadev, STM32_DMA_HISR);
 399        else
 400                dma_isr = stm32_dma_read(dmadev, STM32_DMA_LISR);
 401
 402        flags = dma_isr >> (((chan->id & 2) << 3) | ((chan->id & 1) * 6));
 403
 404        return flags & STM32_DMA_MASKI;
 405}
 406
 407static void stm32_dma_irq_clear(struct stm32_dma_chan *chan, u32 flags)
 408{
 409        struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan);
 410        u32 dma_ifcr;
 411
 412        /*
 413         * Write "flags" to the DMA_xIFCR register corresponding to the selected
 414         * DMA channel at the correct bit offset inside that register.
 415         *
 416         * If (ch % 4) is 2 or 3, left shift the mask by 16 bits.
 417         * If (ch % 4) is 1 or 3, additionally left shift the mask by 6 bits.
 418         */
 419        flags &= STM32_DMA_MASKI;
 420        dma_ifcr = flags << (((chan->id & 2) << 3) | ((chan->id & 1) * 6));
 421
 422        if (chan->id & 4)
 423                stm32_dma_write(dmadev, STM32_DMA_HIFCR, dma_ifcr);
 424        else
 425                stm32_dma_write(dmadev, STM32_DMA_LIFCR, dma_ifcr);
 426}
 427
 428static int stm32_dma_disable_chan(struct stm32_dma_chan *chan)
 429{
 430        struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan);
 431        unsigned long timeout = jiffies + msecs_to_jiffies(5000);
 432        u32 dma_scr, id;
 433
 434        id = chan->id;
 435        dma_scr = stm32_dma_read(dmadev, STM32_DMA_SCR(id));
 436
 437        if (dma_scr & STM32_DMA_SCR_EN) {
 438                dma_scr &= ~STM32_DMA_SCR_EN;
 439                stm32_dma_write(dmadev, STM32_DMA_SCR(id), dma_scr);
 440
 441                do {
 442                        dma_scr = stm32_dma_read(dmadev, STM32_DMA_SCR(id));
 443                        dma_scr &= STM32_DMA_SCR_EN;
 444                        if (!dma_scr)
 445                                break;
 446
 447                        if (time_after_eq(jiffies, timeout)) {
 448                                dev_err(chan2dev(chan), "%s: timeout!\n",
 449                                        __func__);
 450                                return -EBUSY;
 451                        }
 452                        cond_resched();
 453                } while (1);
 454        }
 455
 456        return 0;
 457}
 458
 459static void stm32_dma_stop(struct stm32_dma_chan *chan)
 460{
 461        struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan);
 462        u32 dma_scr, dma_sfcr, status;
 463        int ret;
 464
 465        /* Disable interrupts */
 466        dma_scr = stm32_dma_read(dmadev, STM32_DMA_SCR(chan->id));
 467        dma_scr &= ~STM32_DMA_SCR_IRQ_MASK;
 468        stm32_dma_write(dmadev, STM32_DMA_SCR(chan->id), dma_scr);
 469        dma_sfcr = stm32_dma_read(dmadev, STM32_DMA_SFCR(chan->id));
 470        dma_sfcr &= ~STM32_DMA_SFCR_FEIE;
 471        stm32_dma_write(dmadev, STM32_DMA_SFCR(chan->id), dma_sfcr);
 472
 473        /* Disable DMA */
 474        ret = stm32_dma_disable_chan(chan);
 475        if (ret < 0)
 476                return;
 477
 478        /* Clear interrupt status if it is there */
 479        status = stm32_dma_irq_status(chan);
 480        if (status) {
 481                dev_dbg(chan2dev(chan), "%s(): clearing interrupt: 0x%08x\n",
 482                        __func__, status);
 483                stm32_dma_irq_clear(chan, status);
 484        }
 485
 486        chan->busy = false;
 487}
 488
 489static int stm32_dma_terminate_all(struct dma_chan *c)
 490{
 491        struct stm32_dma_chan *chan = to_stm32_dma_chan(c);
 492        unsigned long flags;
 493        LIST_HEAD(head);
 494
 495        spin_lock_irqsave(&chan->vchan.lock, flags);
 496
 497        if (chan->busy) {
 498                stm32_dma_stop(chan);
 499                chan->desc = NULL;
 500        }
 501
 502        vchan_get_all_descriptors(&chan->vchan, &head);
 503        spin_unlock_irqrestore(&chan->vchan.lock, flags);
 504        vchan_dma_desc_free_list(&chan->vchan, &head);
 505
 506        return 0;
 507}
 508
 509static void stm32_dma_synchronize(struct dma_chan *c)
 510{
 511        struct stm32_dma_chan *chan = to_stm32_dma_chan(c);
 512
 513        vchan_synchronize(&chan->vchan);
 514}
 515
 516static void stm32_dma_dump_reg(struct stm32_dma_chan *chan)
 517{
 518        struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan);
 519        u32 scr = stm32_dma_read(dmadev, STM32_DMA_SCR(chan->id));
 520        u32 ndtr = stm32_dma_read(dmadev, STM32_DMA_SNDTR(chan->id));
 521        u32 spar = stm32_dma_read(dmadev, STM32_DMA_SPAR(chan->id));
 522        u32 sm0ar = stm32_dma_read(dmadev, STM32_DMA_SM0AR(chan->id));
 523        u32 sm1ar = stm32_dma_read(dmadev, STM32_DMA_SM1AR(chan->id));
 524        u32 sfcr = stm32_dma_read(dmadev, STM32_DMA_SFCR(chan->id));
 525
 526        dev_dbg(chan2dev(chan), "SCR:   0x%08x\n", scr);
 527        dev_dbg(chan2dev(chan), "NDTR:  0x%08x\n", ndtr);
 528        dev_dbg(chan2dev(chan), "SPAR:  0x%08x\n", spar);
 529        dev_dbg(chan2dev(chan), "SM0AR: 0x%08x\n", sm0ar);
 530        dev_dbg(chan2dev(chan), "SM1AR: 0x%08x\n", sm1ar);
 531        dev_dbg(chan2dev(chan), "SFCR:  0x%08x\n", sfcr);
 532}
 533
 534static void stm32_dma_configure_next_sg(struct stm32_dma_chan *chan);
 535
 536static void stm32_dma_start_transfer(struct stm32_dma_chan *chan)
 537{
 538        struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan);
 539        struct virt_dma_desc *vdesc;
 540        struct stm32_dma_sg_req *sg_req;
 541        struct stm32_dma_chan_reg *reg;
 542        u32 status;
 543        int ret;
 544
 545        ret = stm32_dma_disable_chan(chan);
 546        if (ret < 0)
 547                return;
 548
 549        if (!chan->desc) {
 550                vdesc = vchan_next_desc(&chan->vchan);
 551                if (!vdesc)
 552                        return;
 553
 554                chan->desc = to_stm32_dma_desc(vdesc);
 555                chan->next_sg = 0;
 556        }
 557
 558        if (chan->next_sg == chan->desc->num_sgs)
 559                chan->next_sg = 0;
 560
 561        sg_req = &chan->desc->sg_req[chan->next_sg];
 562        reg = &sg_req->chan_reg;
 563
 564        stm32_dma_write(dmadev, STM32_DMA_SCR(chan->id), reg->dma_scr);
 565        stm32_dma_write(dmadev, STM32_DMA_SPAR(chan->id), reg->dma_spar);
 566        stm32_dma_write(dmadev, STM32_DMA_SM0AR(chan->id), reg->dma_sm0ar);
 567        stm32_dma_write(dmadev, STM32_DMA_SFCR(chan->id), reg->dma_sfcr);
 568        stm32_dma_write(dmadev, STM32_DMA_SM1AR(chan->id), reg->dma_sm1ar);
 569        stm32_dma_write(dmadev, STM32_DMA_SNDTR(chan->id), reg->dma_sndtr);
 570
 571        chan->next_sg++;
 572
 573        /* Clear interrupt status if it is there */
 574        status = stm32_dma_irq_status(chan);
 575        if (status)
 576                stm32_dma_irq_clear(chan, status);
 577
 578        if (chan->desc->cyclic)
 579                stm32_dma_configure_next_sg(chan);
 580
 581        stm32_dma_dump_reg(chan);
 582
 583        /* Start DMA */
 584        reg->dma_scr |= STM32_DMA_SCR_EN;
 585        stm32_dma_write(dmadev, STM32_DMA_SCR(chan->id), reg->dma_scr);
 586
 587        chan->busy = true;
 588
 589        dev_dbg(chan2dev(chan), "vchan %pK: started\n", &chan->vchan);
 590}
 591
 592static void stm32_dma_configure_next_sg(struct stm32_dma_chan *chan)
 593{
 594        struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan);
 595        struct stm32_dma_sg_req *sg_req;
 596        u32 dma_scr, dma_sm0ar, dma_sm1ar, id;
 597
 598        id = chan->id;
 599        dma_scr = stm32_dma_read(dmadev, STM32_DMA_SCR(id));
 600
 601        if (dma_scr & STM32_DMA_SCR_DBM) {
 602                if (chan->next_sg == chan->desc->num_sgs)
 603                        chan->next_sg = 0;
 604
 605                sg_req = &chan->desc->sg_req[chan->next_sg];
 606
 607                if (dma_scr & STM32_DMA_SCR_CT) {
 608                        dma_sm0ar = sg_req->chan_reg.dma_sm0ar;
 609                        stm32_dma_write(dmadev, STM32_DMA_SM0AR(id), dma_sm0ar);
 610                        dev_dbg(chan2dev(chan), "CT=1 <=> SM0AR: 0x%08x\n",
 611                                stm32_dma_read(dmadev, STM32_DMA_SM0AR(id)));
 612                } else {
 613                        dma_sm1ar = sg_req->chan_reg.dma_sm1ar;
 614                        stm32_dma_write(dmadev, STM32_DMA_SM1AR(id), dma_sm1ar);
 615                        dev_dbg(chan2dev(chan), "CT=0 <=> SM1AR: 0x%08x\n",
 616                                stm32_dma_read(dmadev, STM32_DMA_SM1AR(id)));
 617                }
 618        }
 619}
 620
 621static void stm32_dma_handle_chan_done(struct stm32_dma_chan *chan)
 622{
 623        if (chan->desc) {
 624                if (chan->desc->cyclic) {
 625                        vchan_cyclic_callback(&chan->desc->vdesc);
 626                        chan->next_sg++;
 627                        stm32_dma_configure_next_sg(chan);
 628                } else {
 629                        chan->busy = false;
 630                        if (chan->next_sg == chan->desc->num_sgs) {
 631                                list_del(&chan->desc->vdesc.node);
 632                                vchan_cookie_complete(&chan->desc->vdesc);
 633                                chan->desc = NULL;
 634                        }
 635                        stm32_dma_start_transfer(chan);
 636                }
 637        }
 638}
 639
 640static irqreturn_t stm32_dma_chan_irq(int irq, void *devid)
 641{
 642        struct stm32_dma_chan *chan = devid;
 643        struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan);
 644        u32 status, scr, sfcr;
 645
 646        spin_lock(&chan->vchan.lock);
 647
 648        status = stm32_dma_irq_status(chan);
 649        scr = stm32_dma_read(dmadev, STM32_DMA_SCR(chan->id));
 650        sfcr = stm32_dma_read(dmadev, STM32_DMA_SFCR(chan->id));
 651
 652        if (status & STM32_DMA_TCI) {
 653                stm32_dma_irq_clear(chan, STM32_DMA_TCI);
 654                if (scr & STM32_DMA_SCR_TCIE)
 655                        stm32_dma_handle_chan_done(chan);
 656                status &= ~STM32_DMA_TCI;
 657        }
 658        if (status & STM32_DMA_HTI) {
 659                stm32_dma_irq_clear(chan, STM32_DMA_HTI);
 660                status &= ~STM32_DMA_HTI;
 661        }
 662        if (status & STM32_DMA_FEI) {
 663                stm32_dma_irq_clear(chan, STM32_DMA_FEI);
 664                status &= ~STM32_DMA_FEI;
 665                if (sfcr & STM32_DMA_SFCR_FEIE) {
 666                        if (!(scr & STM32_DMA_SCR_EN))
 667                                dev_err(chan2dev(chan), "FIFO Error\n");
 668                        else
 669                                dev_dbg(chan2dev(chan), "FIFO over/underrun\n");
 670                }
 671        }
 672        if (status) {
 673                stm32_dma_irq_clear(chan, status);
 674                dev_err(chan2dev(chan), "DMA error: status=0x%08x\n", status);
 675                if (!(scr & STM32_DMA_SCR_EN))
 676                        dev_err(chan2dev(chan), "chan disabled by HW\n");
 677        }
 678
 679        spin_unlock(&chan->vchan.lock);
 680
 681        return IRQ_HANDLED;
 682}
 683
 684static void stm32_dma_issue_pending(struct dma_chan *c)
 685{
 686        struct stm32_dma_chan *chan = to_stm32_dma_chan(c);
 687        unsigned long flags;
 688
 689        spin_lock_irqsave(&chan->vchan.lock, flags);
 690        if (vchan_issue_pending(&chan->vchan) && !chan->desc && !chan->busy) {
 691                dev_dbg(chan2dev(chan), "vchan %pK: issued\n", &chan->vchan);
 692                stm32_dma_start_transfer(chan);
 693
 694        }
 695        spin_unlock_irqrestore(&chan->vchan.lock, flags);
 696}
 697
 698static int stm32_dma_set_xfer_param(struct stm32_dma_chan *chan,
 699                                    enum dma_transfer_direction direction,
 700                                    enum dma_slave_buswidth *buswidth,
 701                                    u32 buf_len)
 702{
 703        enum dma_slave_buswidth src_addr_width, dst_addr_width;
 704        int src_bus_width, dst_bus_width;
 705        int src_burst_size, dst_burst_size;
 706        u32 src_maxburst, dst_maxburst, src_best_burst, dst_best_burst;
 707        u32 dma_scr, threshold;
 708
 709        src_addr_width = chan->dma_sconfig.src_addr_width;
 710        dst_addr_width = chan->dma_sconfig.dst_addr_width;
 711        src_maxburst = chan->dma_sconfig.src_maxburst;
 712        dst_maxburst = chan->dma_sconfig.dst_maxburst;
 713        threshold = chan->threshold;
 714
 715        switch (direction) {
 716        case DMA_MEM_TO_DEV:
 717                /* Set device data size */
 718                dst_bus_width = stm32_dma_get_width(chan, dst_addr_width);
 719                if (dst_bus_width < 0)
 720                        return dst_bus_width;
 721
 722                /* Set device burst size */
 723                dst_best_burst = stm32_dma_get_best_burst(buf_len,
 724                                                          dst_maxburst,
 725                                                          threshold,
 726                                                          dst_addr_width);
 727
 728                dst_burst_size = stm32_dma_get_burst(chan, dst_best_burst);
 729                if (dst_burst_size < 0)
 730                        return dst_burst_size;
 731
 732                /* Set memory data size */
 733                src_addr_width = stm32_dma_get_max_width(buf_len, threshold);
 734                chan->mem_width = src_addr_width;
 735                src_bus_width = stm32_dma_get_width(chan, src_addr_width);
 736                if (src_bus_width < 0)
 737                        return src_bus_width;
 738
 739                /* Set memory burst size */
 740                src_maxburst = STM32_DMA_MAX_BURST;
 741                src_best_burst = stm32_dma_get_best_burst(buf_len,
 742                                                          src_maxburst,
 743                                                          threshold,
 744                                                          src_addr_width);
 745                src_burst_size = stm32_dma_get_burst(chan, src_best_burst);
 746                if (src_burst_size < 0)
 747                        return src_burst_size;
 748
 749                dma_scr = STM32_DMA_SCR_DIR(STM32_DMA_MEM_TO_DEV) |
 750                        STM32_DMA_SCR_PSIZE(dst_bus_width) |
 751                        STM32_DMA_SCR_MSIZE(src_bus_width) |
 752                        STM32_DMA_SCR_PBURST(dst_burst_size) |
 753                        STM32_DMA_SCR_MBURST(src_burst_size);
 754
 755                /* Set FIFO threshold */
 756                chan->chan_reg.dma_sfcr &= ~STM32_DMA_SFCR_FTH_MASK;
 757                chan->chan_reg.dma_sfcr |= STM32_DMA_SFCR_FTH(threshold);
 758
 759                /* Set peripheral address */
 760                chan->chan_reg.dma_spar = chan->dma_sconfig.dst_addr;
 761                *buswidth = dst_addr_width;
 762                break;
 763
 764        case DMA_DEV_TO_MEM:
 765                /* Set device data size */
 766                src_bus_width = stm32_dma_get_width(chan, src_addr_width);
 767                if (src_bus_width < 0)
 768                        return src_bus_width;
 769
 770                /* Set device burst size */
 771                src_best_burst = stm32_dma_get_best_burst(buf_len,
 772                                                          src_maxburst,
 773                                                          threshold,
 774                                                          src_addr_width);
 775                chan->mem_burst = src_best_burst;
 776                src_burst_size = stm32_dma_get_burst(chan, src_best_burst);
 777                if (src_burst_size < 0)
 778                        return src_burst_size;
 779
 780                /* Set memory data size */
 781                dst_addr_width = stm32_dma_get_max_width(buf_len, threshold);
 782                chan->mem_width = dst_addr_width;
 783                dst_bus_width = stm32_dma_get_width(chan, dst_addr_width);
 784                if (dst_bus_width < 0)
 785                        return dst_bus_width;
 786
 787                /* Set memory burst size */
 788                dst_maxburst = STM32_DMA_MAX_BURST;
 789                dst_best_burst = stm32_dma_get_best_burst(buf_len,
 790                                                          dst_maxburst,
 791                                                          threshold,
 792                                                          dst_addr_width);
 793                chan->mem_burst = dst_best_burst;
 794                dst_burst_size = stm32_dma_get_burst(chan, dst_best_burst);
 795                if (dst_burst_size < 0)
 796                        return dst_burst_size;
 797
 798                dma_scr = STM32_DMA_SCR_DIR(STM32_DMA_DEV_TO_MEM) |
 799                        STM32_DMA_SCR_PSIZE(src_bus_width) |
 800                        STM32_DMA_SCR_MSIZE(dst_bus_width) |
 801                        STM32_DMA_SCR_PBURST(src_burst_size) |
 802                        STM32_DMA_SCR_MBURST(dst_burst_size);
 803
 804                /* Set FIFO threshold */
 805                chan->chan_reg.dma_sfcr &= ~STM32_DMA_SFCR_FTH_MASK;
 806                chan->chan_reg.dma_sfcr |= STM32_DMA_SFCR_FTH(threshold);
 807
 808                /* Set peripheral address */
 809                chan->chan_reg.dma_spar = chan->dma_sconfig.src_addr;
 810                *buswidth = chan->dma_sconfig.src_addr_width;
 811                break;
 812
 813        default:
 814                dev_err(chan2dev(chan), "Dma direction is not supported\n");
 815                return -EINVAL;
 816        }
 817
 818        stm32_dma_set_fifo_config(chan, src_best_burst, dst_best_burst);
 819
 820        /* Set DMA control register */
 821        chan->chan_reg.dma_scr &= ~(STM32_DMA_SCR_DIR_MASK |
 822                        STM32_DMA_SCR_PSIZE_MASK | STM32_DMA_SCR_MSIZE_MASK |
 823                        STM32_DMA_SCR_PBURST_MASK | STM32_DMA_SCR_MBURST_MASK);
 824        chan->chan_reg.dma_scr |= dma_scr;
 825
 826        return 0;
 827}
 828
 829static void stm32_dma_clear_reg(struct stm32_dma_chan_reg *regs)
 830{
 831        memset(regs, 0, sizeof(struct stm32_dma_chan_reg));
 832}
 833
 834static struct dma_async_tx_descriptor *stm32_dma_prep_slave_sg(
 835        struct dma_chan *c, struct scatterlist *sgl,
 836        u32 sg_len, enum dma_transfer_direction direction,
 837        unsigned long flags, void *context)
 838{
 839        struct stm32_dma_chan *chan = to_stm32_dma_chan(c);
 840        struct stm32_dma_desc *desc;
 841        struct scatterlist *sg;
 842        enum dma_slave_buswidth buswidth;
 843        u32 nb_data_items;
 844        int i, ret;
 845
 846        if (!chan->config_init) {
 847                dev_err(chan2dev(chan), "dma channel is not configured\n");
 848                return NULL;
 849        }
 850
 851        if (sg_len < 1) {
 852                dev_err(chan2dev(chan), "Invalid segment length %d\n", sg_len);
 853                return NULL;
 854        }
 855
 856        desc = stm32_dma_alloc_desc(sg_len);
 857        if (!desc)
 858                return NULL;
 859
 860        /* Set peripheral flow controller */
 861        if (chan->dma_sconfig.device_fc)
 862                chan->chan_reg.dma_scr |= STM32_DMA_SCR_PFCTRL;
 863        else
 864                chan->chan_reg.dma_scr &= ~STM32_DMA_SCR_PFCTRL;
 865
 866        for_each_sg(sgl, sg, sg_len, i) {
 867                ret = stm32_dma_set_xfer_param(chan, direction, &buswidth,
 868                                               sg_dma_len(sg));
 869                if (ret < 0)
 870                        goto err;
 871
 872                desc->sg_req[i].len = sg_dma_len(sg);
 873
 874                nb_data_items = desc->sg_req[i].len / buswidth;
 875                if (nb_data_items > STM32_DMA_ALIGNED_MAX_DATA_ITEMS) {
 876                        dev_err(chan2dev(chan), "nb items not supported\n");
 877                        goto err;
 878                }
 879
 880                stm32_dma_clear_reg(&desc->sg_req[i].chan_reg);
 881                desc->sg_req[i].chan_reg.dma_scr = chan->chan_reg.dma_scr;
 882                desc->sg_req[i].chan_reg.dma_sfcr = chan->chan_reg.dma_sfcr;
 883                desc->sg_req[i].chan_reg.dma_spar = chan->chan_reg.dma_spar;
 884                desc->sg_req[i].chan_reg.dma_sm0ar = sg_dma_address(sg);
 885                desc->sg_req[i].chan_reg.dma_sm1ar = sg_dma_address(sg);
 886                desc->sg_req[i].chan_reg.dma_sndtr = nb_data_items;
 887        }
 888
 889        desc->num_sgs = sg_len;
 890        desc->cyclic = false;
 891
 892        return vchan_tx_prep(&chan->vchan, &desc->vdesc, flags);
 893
 894err:
 895        kfree(desc);
 896        return NULL;
 897}
 898
 899static struct dma_async_tx_descriptor *stm32_dma_prep_dma_cyclic(
 900        struct dma_chan *c, dma_addr_t buf_addr, size_t buf_len,
 901        size_t period_len, enum dma_transfer_direction direction,
 902        unsigned long flags)
 903{
 904        struct stm32_dma_chan *chan = to_stm32_dma_chan(c);
 905        struct stm32_dma_desc *desc;
 906        enum dma_slave_buswidth buswidth;
 907        u32 num_periods, nb_data_items;
 908        int i, ret;
 909
 910        if (!buf_len || !period_len) {
 911                dev_err(chan2dev(chan), "Invalid buffer/period len\n");
 912                return NULL;
 913        }
 914
 915        if (!chan->config_init) {
 916                dev_err(chan2dev(chan), "dma channel is not configured\n");
 917                return NULL;
 918        }
 919
 920        if (buf_len % period_len) {
 921                dev_err(chan2dev(chan), "buf_len not multiple of period_len\n");
 922                return NULL;
 923        }
 924
 925        /*
 926         * We allow to take more number of requests till DMA is
 927         * not started. The driver will loop over all requests.
 928         * Once DMA is started then new requests can be queued only after
 929         * terminating the DMA.
 930         */
 931        if (chan->busy) {
 932                dev_err(chan2dev(chan), "Request not allowed when dma busy\n");
 933                return NULL;
 934        }
 935
 936        ret = stm32_dma_set_xfer_param(chan, direction, &buswidth, period_len);
 937        if (ret < 0)
 938                return NULL;
 939
 940        nb_data_items = period_len / buswidth;
 941        if (nb_data_items > STM32_DMA_ALIGNED_MAX_DATA_ITEMS) {
 942                dev_err(chan2dev(chan), "number of items not supported\n");
 943                return NULL;
 944        }
 945
 946        /*  Enable Circular mode or double buffer mode */
 947        if (buf_len == period_len)
 948                chan->chan_reg.dma_scr |= STM32_DMA_SCR_CIRC;
 949        else
 950                chan->chan_reg.dma_scr |= STM32_DMA_SCR_DBM;
 951
 952        /* Clear periph ctrl if client set it */
 953        chan->chan_reg.dma_scr &= ~STM32_DMA_SCR_PFCTRL;
 954
 955        num_periods = buf_len / period_len;
 956
 957        desc = stm32_dma_alloc_desc(num_periods);
 958        if (!desc)
 959                return NULL;
 960
 961        for (i = 0; i < num_periods; i++) {
 962                desc->sg_req[i].len = period_len;
 963
 964                stm32_dma_clear_reg(&desc->sg_req[i].chan_reg);
 965                desc->sg_req[i].chan_reg.dma_scr = chan->chan_reg.dma_scr;
 966                desc->sg_req[i].chan_reg.dma_sfcr = chan->chan_reg.dma_sfcr;
 967                desc->sg_req[i].chan_reg.dma_spar = chan->chan_reg.dma_spar;
 968                desc->sg_req[i].chan_reg.dma_sm0ar = buf_addr;
 969                desc->sg_req[i].chan_reg.dma_sm1ar = buf_addr;
 970                desc->sg_req[i].chan_reg.dma_sndtr = nb_data_items;
 971                buf_addr += period_len;
 972        }
 973
 974        desc->num_sgs = num_periods;
 975        desc->cyclic = true;
 976
 977        return vchan_tx_prep(&chan->vchan, &desc->vdesc, flags);
 978}
 979
 980static struct dma_async_tx_descriptor *stm32_dma_prep_dma_memcpy(
 981        struct dma_chan *c, dma_addr_t dest,
 982        dma_addr_t src, size_t len, unsigned long flags)
 983{
 984        struct stm32_dma_chan *chan = to_stm32_dma_chan(c);
 985        enum dma_slave_buswidth max_width;
 986        struct stm32_dma_desc *desc;
 987        size_t xfer_count, offset;
 988        u32 num_sgs, best_burst, dma_burst, threshold;
 989        int i;
 990
 991        num_sgs = DIV_ROUND_UP(len, STM32_DMA_ALIGNED_MAX_DATA_ITEMS);
 992        desc = stm32_dma_alloc_desc(num_sgs);
 993        if (!desc)
 994                return NULL;
 995
 996        threshold = chan->threshold;
 997
 998        for (offset = 0, i = 0; offset < len; offset += xfer_count, i++) {
 999                xfer_count = min_t(size_t, len - offset,
1000                                   STM32_DMA_ALIGNED_MAX_DATA_ITEMS);
1001
1002                /* Compute best burst size */
1003                max_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1004                best_burst = stm32_dma_get_best_burst(len, STM32_DMA_MAX_BURST,
1005                                                      threshold, max_width);
1006                dma_burst = stm32_dma_get_burst(chan, best_burst);
1007
1008                stm32_dma_clear_reg(&desc->sg_req[i].chan_reg);
1009                desc->sg_req[i].chan_reg.dma_scr =
1010                        STM32_DMA_SCR_DIR(STM32_DMA_MEM_TO_MEM) |
1011                        STM32_DMA_SCR_PBURST(dma_burst) |
1012                        STM32_DMA_SCR_MBURST(dma_burst) |
1013                        STM32_DMA_SCR_MINC |
1014                        STM32_DMA_SCR_PINC |
1015                        STM32_DMA_SCR_TCIE |
1016                        STM32_DMA_SCR_TEIE;
1017                desc->sg_req[i].chan_reg.dma_sfcr |= STM32_DMA_SFCR_MASK;
1018                desc->sg_req[i].chan_reg.dma_sfcr |=
1019                        STM32_DMA_SFCR_FTH(threshold);
1020                desc->sg_req[i].chan_reg.dma_spar = src + offset;
1021                desc->sg_req[i].chan_reg.dma_sm0ar = dest + offset;
1022                desc->sg_req[i].chan_reg.dma_sndtr = xfer_count;
1023                desc->sg_req[i].len = xfer_count;
1024        }
1025
1026        desc->num_sgs = num_sgs;
1027        desc->cyclic = false;
1028
1029        return vchan_tx_prep(&chan->vchan, &desc->vdesc, flags);
1030}
1031
1032static u32 stm32_dma_get_remaining_bytes(struct stm32_dma_chan *chan)
1033{
1034        u32 dma_scr, width, ndtr;
1035        struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan);
1036
1037        dma_scr = stm32_dma_read(dmadev, STM32_DMA_SCR(chan->id));
1038        width = STM32_DMA_SCR_PSIZE_GET(dma_scr);
1039        ndtr = stm32_dma_read(dmadev, STM32_DMA_SNDTR(chan->id));
1040
1041        return ndtr << width;
1042}
1043
1044/**
1045 * stm32_dma_is_current_sg - check that expected sg_req is currently transferred
1046 * @chan: dma channel
1047 *
1048 * This function called when IRQ are disable, checks that the hardware has not
1049 * switched on the next transfer in double buffer mode. The test is done by
1050 * comparing the next_sg memory address with the hardware related register
1051 * (based on CT bit value).
1052 *
1053 * Returns true if expected current transfer is still running or double
1054 * buffer mode is not activated.
1055 */
1056static bool stm32_dma_is_current_sg(struct stm32_dma_chan *chan)
1057{
1058        struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan);
1059        struct stm32_dma_sg_req *sg_req;
1060        u32 dma_scr, dma_smar, id;
1061
1062        id = chan->id;
1063        dma_scr = stm32_dma_read(dmadev, STM32_DMA_SCR(id));
1064
1065        if (!(dma_scr & STM32_DMA_SCR_DBM))
1066                return true;
1067
1068        sg_req = &chan->desc->sg_req[chan->next_sg];
1069
1070        if (dma_scr & STM32_DMA_SCR_CT) {
1071                dma_smar = stm32_dma_read(dmadev, STM32_DMA_SM0AR(id));
1072                return (dma_smar == sg_req->chan_reg.dma_sm0ar);
1073        }
1074
1075        dma_smar = stm32_dma_read(dmadev, STM32_DMA_SM1AR(id));
1076
1077        return (dma_smar == sg_req->chan_reg.dma_sm1ar);
1078}
1079
1080static size_t stm32_dma_desc_residue(struct stm32_dma_chan *chan,
1081                                     struct stm32_dma_desc *desc,
1082                                     u32 next_sg)
1083{
1084        u32 modulo, burst_size;
1085        u32 residue;
1086        u32 n_sg = next_sg;
1087        struct stm32_dma_sg_req *sg_req = &chan->desc->sg_req[chan->next_sg];
1088        int i;
1089
1090        /*
1091         * Calculate the residue means compute the descriptors
1092         * information:
1093         * - the sg_req currently transferred
1094         * - the Hardware remaining position in this sg (NDTR bits field).
1095         *
1096         * A race condition may occur if DMA is running in cyclic or double
1097         * buffer mode, since the DMA register are automatically reloaded at end
1098         * of period transfer. The hardware may have switched to the next
1099         * transfer (CT bit updated) just before the position (SxNDTR reg) is
1100         * read.
1101         * In this case the SxNDTR reg could (or not) correspond to the new
1102         * transfer position, and not the expected one.
1103         * The strategy implemented in the stm32 driver is to:
1104         *  - read the SxNDTR register
1105         *  - crosscheck that hardware is still in current transfer.
1106         * In case of switch, we can assume that the DMA is at the beginning of
1107         * the next transfer. So we approximate the residue in consequence, by
1108         * pointing on the beginning of next transfer.
1109         *
1110         * This race condition doesn't apply for none cyclic mode, as double
1111         * buffer is not used. In such situation registers are updated by the
1112         * software.
1113         */
1114
1115        residue = stm32_dma_get_remaining_bytes(chan);
1116
1117        if (!stm32_dma_is_current_sg(chan)) {
1118                n_sg++;
1119                if (n_sg == chan->desc->num_sgs)
1120                        n_sg = 0;
1121                residue = sg_req->len;
1122        }
1123
1124        /*
1125         * In cyclic mode, for the last period, residue = remaining bytes
1126         * from NDTR,
1127         * else for all other periods in cyclic mode, and in sg mode,
1128         * residue = remaining bytes from NDTR + remaining
1129         * periods/sg to be transferred
1130         */
1131        if (!chan->desc->cyclic || n_sg != 0)
1132                for (i = n_sg; i < desc->num_sgs; i++)
1133                        residue += desc->sg_req[i].len;
1134
1135        if (!chan->mem_burst)
1136                return residue;
1137
1138        burst_size = chan->mem_burst * chan->mem_width;
1139        modulo = residue % burst_size;
1140        if (modulo)
1141                residue = residue - modulo + burst_size;
1142
1143        return residue;
1144}
1145
1146static enum dma_status stm32_dma_tx_status(struct dma_chan *c,
1147                                           dma_cookie_t cookie,
1148                                           struct dma_tx_state *state)
1149{
1150        struct stm32_dma_chan *chan = to_stm32_dma_chan(c);
1151        struct virt_dma_desc *vdesc;
1152        enum dma_status status;
1153        unsigned long flags;
1154        u32 residue = 0;
1155
1156        status = dma_cookie_status(c, cookie, state);
1157        if (status == DMA_COMPLETE || !state)
1158                return status;
1159
1160        spin_lock_irqsave(&chan->vchan.lock, flags);
1161        vdesc = vchan_find_desc(&chan->vchan, cookie);
1162        if (chan->desc && cookie == chan->desc->vdesc.tx.cookie)
1163                residue = stm32_dma_desc_residue(chan, chan->desc,
1164                                                 chan->next_sg);
1165        else if (vdesc)
1166                residue = stm32_dma_desc_residue(chan,
1167                                                 to_stm32_dma_desc(vdesc), 0);
1168        dma_set_residue(state, residue);
1169
1170        spin_unlock_irqrestore(&chan->vchan.lock, flags);
1171
1172        return status;
1173}
1174
1175static int stm32_dma_alloc_chan_resources(struct dma_chan *c)
1176{
1177        struct stm32_dma_chan *chan = to_stm32_dma_chan(c);
1178        struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan);
1179        int ret;
1180
1181        chan->config_init = false;
1182
1183        ret = pm_runtime_get_sync(dmadev->ddev.dev);
1184        if (ret < 0)
1185                return ret;
1186
1187        ret = stm32_dma_disable_chan(chan);
1188        if (ret < 0)
1189                pm_runtime_put(dmadev->ddev.dev);
1190
1191        return ret;
1192}
1193
1194static void stm32_dma_free_chan_resources(struct dma_chan *c)
1195{
1196        struct stm32_dma_chan *chan = to_stm32_dma_chan(c);
1197        struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan);
1198        unsigned long flags;
1199
1200        dev_dbg(chan2dev(chan), "Freeing channel %d\n", chan->id);
1201
1202        if (chan->busy) {
1203                spin_lock_irqsave(&chan->vchan.lock, flags);
1204                stm32_dma_stop(chan);
1205                chan->desc = NULL;
1206                spin_unlock_irqrestore(&chan->vchan.lock, flags);
1207        }
1208
1209        pm_runtime_put(dmadev->ddev.dev);
1210
1211        vchan_free_chan_resources(to_virt_chan(c));
1212}
1213
1214static void stm32_dma_desc_free(struct virt_dma_desc *vdesc)
1215{
1216        kfree(container_of(vdesc, struct stm32_dma_desc, vdesc));
1217}
1218
1219static void stm32_dma_set_config(struct stm32_dma_chan *chan,
1220                                 struct stm32_dma_cfg *cfg)
1221{
1222        stm32_dma_clear_reg(&chan->chan_reg);
1223
1224        chan->chan_reg.dma_scr = cfg->stream_config & STM32_DMA_SCR_CFG_MASK;
1225        chan->chan_reg.dma_scr |= STM32_DMA_SCR_REQ(cfg->request_line);
1226
1227        /* Enable Interrupts  */
1228        chan->chan_reg.dma_scr |= STM32_DMA_SCR_TEIE | STM32_DMA_SCR_TCIE;
1229
1230        chan->threshold = STM32_DMA_THRESHOLD_FTR_GET(cfg->features);
1231}
1232
1233static struct dma_chan *stm32_dma_of_xlate(struct of_phandle_args *dma_spec,
1234                                           struct of_dma *ofdma)
1235{
1236        struct stm32_dma_device *dmadev = ofdma->of_dma_data;
1237        struct device *dev = dmadev->ddev.dev;
1238        struct stm32_dma_cfg cfg;
1239        struct stm32_dma_chan *chan;
1240        struct dma_chan *c;
1241
1242        if (dma_spec->args_count < 4) {
1243                dev_err(dev, "Bad number of cells\n");
1244                return NULL;
1245        }
1246
1247        cfg.channel_id = dma_spec->args[0];
1248        cfg.request_line = dma_spec->args[1];
1249        cfg.stream_config = dma_spec->args[2];
1250        cfg.features = dma_spec->args[3];
1251
1252        if (cfg.channel_id >= STM32_DMA_MAX_CHANNELS ||
1253            cfg.request_line >= STM32_DMA_MAX_REQUEST_ID) {
1254                dev_err(dev, "Bad channel and/or request id\n");
1255                return NULL;
1256        }
1257
1258        chan = &dmadev->chan[cfg.channel_id];
1259
1260        c = dma_get_slave_channel(&chan->vchan.chan);
1261        if (!c) {
1262                dev_err(dev, "No more channels available\n");
1263                return NULL;
1264        }
1265
1266        stm32_dma_set_config(chan, &cfg);
1267
1268        return c;
1269}
1270
1271static const struct of_device_id stm32_dma_of_match[] = {
1272        { .compatible = "st,stm32-dma", },
1273        { /* sentinel */ },
1274};
1275MODULE_DEVICE_TABLE(of, stm32_dma_of_match);
1276
1277static int stm32_dma_probe(struct platform_device *pdev)
1278{
1279        struct stm32_dma_chan *chan;
1280        struct stm32_dma_device *dmadev;
1281        struct dma_device *dd;
1282        const struct of_device_id *match;
1283        struct resource *res;
1284        int i, ret;
1285
1286        match = of_match_device(stm32_dma_of_match, &pdev->dev);
1287        if (!match) {
1288                dev_err(&pdev->dev, "Error: No device match found\n");
1289                return -ENODEV;
1290        }
1291
1292        dmadev = devm_kzalloc(&pdev->dev, sizeof(*dmadev), GFP_KERNEL);
1293        if (!dmadev)
1294                return -ENOMEM;
1295
1296        dd = &dmadev->ddev;
1297
1298        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1299        dmadev->base = devm_ioremap_resource(&pdev->dev, res);
1300        if (IS_ERR(dmadev->base))
1301                return PTR_ERR(dmadev->base);
1302
1303        dmadev->clk = devm_clk_get(&pdev->dev, NULL);
1304        if (IS_ERR(dmadev->clk)) {
1305                dev_err(&pdev->dev, "Error: Missing controller clock\n");
1306                return PTR_ERR(dmadev->clk);
1307        }
1308
1309        ret = clk_prepare_enable(dmadev->clk);
1310        if (ret < 0) {
1311                dev_err(&pdev->dev, "clk_prep_enable error: %d\n", ret);
1312                return ret;
1313        }
1314
1315        dmadev->mem2mem = of_property_read_bool(pdev->dev.of_node,
1316                                                "st,mem2mem");
1317
1318        dmadev->rst = devm_reset_control_get(&pdev->dev, NULL);
1319        if (!IS_ERR(dmadev->rst)) {
1320                reset_control_assert(dmadev->rst);
1321                udelay(2);
1322                reset_control_deassert(dmadev->rst);
1323        }
1324
1325        dma_cap_set(DMA_SLAVE, dd->cap_mask);
1326        dma_cap_set(DMA_PRIVATE, dd->cap_mask);
1327        dma_cap_set(DMA_CYCLIC, dd->cap_mask);
1328        dd->device_alloc_chan_resources = stm32_dma_alloc_chan_resources;
1329        dd->device_free_chan_resources = stm32_dma_free_chan_resources;
1330        dd->device_tx_status = stm32_dma_tx_status;
1331        dd->device_issue_pending = stm32_dma_issue_pending;
1332        dd->device_prep_slave_sg = stm32_dma_prep_slave_sg;
1333        dd->device_prep_dma_cyclic = stm32_dma_prep_dma_cyclic;
1334        dd->device_config = stm32_dma_slave_config;
1335        dd->device_terminate_all = stm32_dma_terminate_all;
1336        dd->device_synchronize = stm32_dma_synchronize;
1337        dd->src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |
1338                BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) |
1339                BIT(DMA_SLAVE_BUSWIDTH_4_BYTES);
1340        dd->dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |
1341                BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) |
1342                BIT(DMA_SLAVE_BUSWIDTH_4_BYTES);
1343        dd->directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
1344        dd->residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
1345        dd->max_burst = STM32_DMA_MAX_BURST;
1346        dd->dev = &pdev->dev;
1347        INIT_LIST_HEAD(&dd->channels);
1348
1349        if (dmadev->mem2mem) {
1350                dma_cap_set(DMA_MEMCPY, dd->cap_mask);
1351                dd->device_prep_dma_memcpy = stm32_dma_prep_dma_memcpy;
1352                dd->directions |= BIT(DMA_MEM_TO_MEM);
1353        }
1354
1355        for (i = 0; i < STM32_DMA_MAX_CHANNELS; i++) {
1356                chan = &dmadev->chan[i];
1357                chan->id = i;
1358                chan->vchan.desc_free = stm32_dma_desc_free;
1359                vchan_init(&chan->vchan, dd);
1360        }
1361
1362        ret = dma_async_device_register(dd);
1363        if (ret)
1364                goto clk_free;
1365
1366        for (i = 0; i < STM32_DMA_MAX_CHANNELS; i++) {
1367                chan = &dmadev->chan[i];
1368                chan->irq = platform_get_irq(pdev, i);
1369                ret = platform_get_irq(pdev, i);
1370                if (ret < 0)  {
1371                        if (ret != -EPROBE_DEFER)
1372                                dev_err(&pdev->dev,
1373                                        "No irq resource for chan %d\n", i);
1374                        goto err_unregister;
1375                }
1376                chan->irq = ret;
1377
1378                ret = devm_request_irq(&pdev->dev, chan->irq,
1379                                       stm32_dma_chan_irq, 0,
1380                                       dev_name(chan2dev(chan)), chan);
1381                if (ret) {
1382                        dev_err(&pdev->dev,
1383                                "request_irq failed with err %d channel %d\n",
1384                                ret, i);
1385                        goto err_unregister;
1386                }
1387        }
1388
1389        ret = of_dma_controller_register(pdev->dev.of_node,
1390                                         stm32_dma_of_xlate, dmadev);
1391        if (ret < 0) {
1392                dev_err(&pdev->dev,
1393                        "STM32 DMA DMA OF registration failed %d\n", ret);
1394                goto err_unregister;
1395        }
1396
1397        platform_set_drvdata(pdev, dmadev);
1398
1399        pm_runtime_set_active(&pdev->dev);
1400        pm_runtime_enable(&pdev->dev);
1401        pm_runtime_get_noresume(&pdev->dev);
1402        pm_runtime_put(&pdev->dev);
1403
1404        dev_info(&pdev->dev, "STM32 DMA driver registered\n");
1405
1406        return 0;
1407
1408err_unregister:
1409        dma_async_device_unregister(dd);
1410clk_free:
1411        clk_disable_unprepare(dmadev->clk);
1412
1413        return ret;
1414}
1415
1416#ifdef CONFIG_PM
1417static int stm32_dma_runtime_suspend(struct device *dev)
1418{
1419        struct stm32_dma_device *dmadev = dev_get_drvdata(dev);
1420
1421        clk_disable_unprepare(dmadev->clk);
1422
1423        return 0;
1424}
1425
1426static int stm32_dma_runtime_resume(struct device *dev)
1427{
1428        struct stm32_dma_device *dmadev = dev_get_drvdata(dev);
1429        int ret;
1430
1431        ret = clk_prepare_enable(dmadev->clk);
1432        if (ret) {
1433                dev_err(dev, "failed to prepare_enable clock\n");
1434                return ret;
1435        }
1436
1437        return 0;
1438}
1439#endif
1440
1441static const struct dev_pm_ops stm32_dma_pm_ops = {
1442        SET_RUNTIME_PM_OPS(stm32_dma_runtime_suspend,
1443                           stm32_dma_runtime_resume, NULL)
1444};
1445
1446static struct platform_driver stm32_dma_driver = {
1447        .driver = {
1448                .name = "stm32-dma",
1449                .of_match_table = stm32_dma_of_match,
1450                .pm = &stm32_dma_pm_ops,
1451        },
1452};
1453
1454static int __init stm32_dma_init(void)
1455{
1456        return platform_driver_probe(&stm32_dma_driver, stm32_dma_probe);
1457}
1458subsys_initcall(stm32_dma_init);
1459