1
2
3
4
5
6
7
8#include <linux/bitops.h>
9#include <linux/clk.h>
10#include <linux/gpio/driver.h>
11#include <linux/init.h>
12#include <linux/interrupt.h>
13#include <linux/io.h>
14#include <linux/module.h>
15#include <linux/platform_device.h>
16#include <linux/pm_runtime.h>
17#include <linux/of.h>
18
19#define DRIVER_NAME "zynq-gpio"
20
21
22#define ZYNQ_GPIO_MAX_BANK 4
23#define ZYNQMP_GPIO_MAX_BANK 6
24
25#define ZYNQ_GPIO_BANK0_NGPIO 32
26#define ZYNQ_GPIO_BANK1_NGPIO 22
27#define ZYNQ_GPIO_BANK2_NGPIO 32
28#define ZYNQ_GPIO_BANK3_NGPIO 32
29
30#define ZYNQMP_GPIO_BANK0_NGPIO 26
31#define ZYNQMP_GPIO_BANK1_NGPIO 26
32#define ZYNQMP_GPIO_BANK2_NGPIO 26
33#define ZYNQMP_GPIO_BANK3_NGPIO 32
34#define ZYNQMP_GPIO_BANK4_NGPIO 32
35#define ZYNQMP_GPIO_BANK5_NGPIO 32
36
37#define ZYNQ_GPIO_NR_GPIOS 118
38#define ZYNQMP_GPIO_NR_GPIOS 174
39
40#define ZYNQ_GPIO_BANK0_PIN_MIN(str) 0
41#define ZYNQ_GPIO_BANK0_PIN_MAX(str) (ZYNQ_GPIO_BANK0_PIN_MIN(str) + \
42 ZYNQ##str##_GPIO_BANK0_NGPIO - 1)
43#define ZYNQ_GPIO_BANK1_PIN_MIN(str) (ZYNQ_GPIO_BANK0_PIN_MAX(str) + 1)
44#define ZYNQ_GPIO_BANK1_PIN_MAX(str) (ZYNQ_GPIO_BANK1_PIN_MIN(str) + \
45 ZYNQ##str##_GPIO_BANK1_NGPIO - 1)
46#define ZYNQ_GPIO_BANK2_PIN_MIN(str) (ZYNQ_GPIO_BANK1_PIN_MAX(str) + 1)
47#define ZYNQ_GPIO_BANK2_PIN_MAX(str) (ZYNQ_GPIO_BANK2_PIN_MIN(str) + \
48 ZYNQ##str##_GPIO_BANK2_NGPIO - 1)
49#define ZYNQ_GPIO_BANK3_PIN_MIN(str) (ZYNQ_GPIO_BANK2_PIN_MAX(str) + 1)
50#define ZYNQ_GPIO_BANK3_PIN_MAX(str) (ZYNQ_GPIO_BANK3_PIN_MIN(str) + \
51 ZYNQ##str##_GPIO_BANK3_NGPIO - 1)
52#define ZYNQ_GPIO_BANK4_PIN_MIN(str) (ZYNQ_GPIO_BANK3_PIN_MAX(str) + 1)
53#define ZYNQ_GPIO_BANK4_PIN_MAX(str) (ZYNQ_GPIO_BANK4_PIN_MIN(str) + \
54 ZYNQ##str##_GPIO_BANK4_NGPIO - 1)
55#define ZYNQ_GPIO_BANK5_PIN_MIN(str) (ZYNQ_GPIO_BANK4_PIN_MAX(str) + 1)
56#define ZYNQ_GPIO_BANK5_PIN_MAX(str) (ZYNQ_GPIO_BANK5_PIN_MIN(str) + \
57 ZYNQ##str##_GPIO_BANK5_NGPIO - 1)
58
59
60
61#define ZYNQ_GPIO_DATA_LSW_OFFSET(BANK) (0x000 + (8 * BANK))
62
63#define ZYNQ_GPIO_DATA_MSW_OFFSET(BANK) (0x004 + (8 * BANK))
64
65#define ZYNQ_GPIO_DATA_OFFSET(BANK) (0x040 + (4 * BANK))
66#define ZYNQ_GPIO_DATA_RO_OFFSET(BANK) (0x060 + (4 * BANK))
67
68#define ZYNQ_GPIO_DIRM_OFFSET(BANK) (0x204 + (0x40 * BANK))
69
70#define ZYNQ_GPIO_OUTEN_OFFSET(BANK) (0x208 + (0x40 * BANK))
71
72#define ZYNQ_GPIO_INTMASK_OFFSET(BANK) (0x20C + (0x40 * BANK))
73
74#define ZYNQ_GPIO_INTEN_OFFSET(BANK) (0x210 + (0x40 * BANK))
75
76#define ZYNQ_GPIO_INTDIS_OFFSET(BANK) (0x214 + (0x40 * BANK))
77
78#define ZYNQ_GPIO_INTSTS_OFFSET(BANK) (0x218 + (0x40 * BANK))
79
80#define ZYNQ_GPIO_INTTYPE_OFFSET(BANK) (0x21C + (0x40 * BANK))
81
82#define ZYNQ_GPIO_INTPOL_OFFSET(BANK) (0x220 + (0x40 * BANK))
83
84#define ZYNQ_GPIO_INTANY_OFFSET(BANK) (0x224 + (0x40 * BANK))
85
86
87#define ZYNQ_GPIO_IXR_DISABLE_ALL 0xFFFFFFFF
88
89
90#define ZYNQ_GPIO_MID_PIN_NUM 16
91
92
93#define ZYNQ_GPIO_UPPER_MASK 0xFFFF0000
94
95
96#define ZYNQ_GPIO_QUIRK_IS_ZYNQ BIT(0)
97#define GPIO_QUIRK_DATA_RO_BUG BIT(1)
98
99struct gpio_regs {
100 u32 datamsw[ZYNQMP_GPIO_MAX_BANK];
101 u32 datalsw[ZYNQMP_GPIO_MAX_BANK];
102 u32 dirm[ZYNQMP_GPIO_MAX_BANK];
103 u32 outen[ZYNQMP_GPIO_MAX_BANK];
104 u32 int_en[ZYNQMP_GPIO_MAX_BANK];
105 u32 int_dis[ZYNQMP_GPIO_MAX_BANK];
106 u32 int_type[ZYNQMP_GPIO_MAX_BANK];
107 u32 int_polarity[ZYNQMP_GPIO_MAX_BANK];
108 u32 int_any[ZYNQMP_GPIO_MAX_BANK];
109};
110
111
112
113
114
115
116
117
118
119
120struct zynq_gpio {
121 struct gpio_chip chip;
122 void __iomem *base_addr;
123 struct clk *clk;
124 int irq;
125 const struct zynq_platform_data *p_data;
126 struct gpio_regs context;
127};
128
129
130
131
132
133
134
135
136
137
138struct zynq_platform_data {
139 const char *label;
140 u32 quirks;
141 u16 ngpio;
142 int max_bank;
143 int bank_min[ZYNQMP_GPIO_MAX_BANK];
144 int bank_max[ZYNQMP_GPIO_MAX_BANK];
145};
146
147static struct irq_chip zynq_gpio_level_irqchip;
148static struct irq_chip zynq_gpio_edge_irqchip;
149
150
151
152
153
154
155
156static int zynq_gpio_is_zynq(struct zynq_gpio *gpio)
157{
158 return !!(gpio->p_data->quirks & ZYNQ_GPIO_QUIRK_IS_ZYNQ);
159}
160
161
162
163
164
165
166
167static int gpio_data_ro_bug(struct zynq_gpio *gpio)
168{
169 return !!(gpio->p_data->quirks & GPIO_QUIRK_DATA_RO_BUG);
170}
171
172
173
174
175
176
177
178
179
180
181
182
183
184static inline void zynq_gpio_get_bank_pin(unsigned int pin_num,
185 unsigned int *bank_num,
186 unsigned int *bank_pin_num,
187 struct zynq_gpio *gpio)
188{
189 int bank;
190
191 for (bank = 0; bank < gpio->p_data->max_bank; bank++) {
192 if ((pin_num >= gpio->p_data->bank_min[bank]) &&
193 (pin_num <= gpio->p_data->bank_max[bank])) {
194 *bank_num = bank;
195 *bank_pin_num = pin_num -
196 gpio->p_data->bank_min[bank];
197 return;
198 }
199 }
200
201
202 WARN(true, "invalid GPIO pin number: %u", pin_num);
203 *bank_num = 0;
204 *bank_pin_num = 0;
205}
206
207
208
209
210
211
212
213
214
215
216static int zynq_gpio_get_value(struct gpio_chip *chip, unsigned int pin)
217{
218 u32 data;
219 unsigned int bank_num, bank_pin_num;
220 struct zynq_gpio *gpio = gpiochip_get_data(chip);
221
222 zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio);
223
224 if (gpio_data_ro_bug(gpio)) {
225 if (zynq_gpio_is_zynq(gpio)) {
226 if (bank_num <= 1) {
227 data = readl_relaxed(gpio->base_addr +
228 ZYNQ_GPIO_DATA_RO_OFFSET(bank_num));
229 } else {
230 data = readl_relaxed(gpio->base_addr +
231 ZYNQ_GPIO_DATA_OFFSET(bank_num));
232 }
233 } else {
234 if (bank_num <= 2) {
235 data = readl_relaxed(gpio->base_addr +
236 ZYNQ_GPIO_DATA_RO_OFFSET(bank_num));
237 } else {
238 data = readl_relaxed(gpio->base_addr +
239 ZYNQ_GPIO_DATA_OFFSET(bank_num));
240 }
241 }
242 } else {
243 data = readl_relaxed(gpio->base_addr +
244 ZYNQ_GPIO_DATA_RO_OFFSET(bank_num));
245 }
246 return (data >> bank_pin_num) & 1;
247}
248
249
250
251
252
253
254
255
256
257
258
259static void zynq_gpio_set_value(struct gpio_chip *chip, unsigned int pin,
260 int state)
261{
262 unsigned int reg_offset, bank_num, bank_pin_num;
263 struct zynq_gpio *gpio = gpiochip_get_data(chip);
264
265 zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio);
266
267 if (bank_pin_num >= ZYNQ_GPIO_MID_PIN_NUM) {
268
269 bank_pin_num -= ZYNQ_GPIO_MID_PIN_NUM;
270 reg_offset = ZYNQ_GPIO_DATA_MSW_OFFSET(bank_num);
271 } else {
272 reg_offset = ZYNQ_GPIO_DATA_LSW_OFFSET(bank_num);
273 }
274
275
276
277
278
279 state = !!state;
280 state = ~(1 << (bank_pin_num + ZYNQ_GPIO_MID_PIN_NUM)) &
281 ((state << bank_pin_num) | ZYNQ_GPIO_UPPER_MASK);
282
283 writel_relaxed(state, gpio->base_addr + reg_offset);
284}
285
286
287
288
289
290
291
292
293
294
295
296static int zynq_gpio_dir_in(struct gpio_chip *chip, unsigned int pin)
297{
298 u32 reg;
299 unsigned int bank_num, bank_pin_num;
300 struct zynq_gpio *gpio = gpiochip_get_data(chip);
301
302 zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio);
303
304
305
306
307
308 if (zynq_gpio_is_zynq(gpio) && bank_num == 0 &&
309 (bank_pin_num == 7 || bank_pin_num == 8))
310 return -EINVAL;
311
312
313 reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
314 reg &= ~BIT(bank_pin_num);
315 writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
316
317 return 0;
318}
319
320
321
322
323
324
325
326
327
328
329
330
331
332static int zynq_gpio_dir_out(struct gpio_chip *chip, unsigned int pin,
333 int state)
334{
335 u32 reg;
336 unsigned int bank_num, bank_pin_num;
337 struct zynq_gpio *gpio = gpiochip_get_data(chip);
338
339 zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio);
340
341
342 reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
343 reg |= BIT(bank_pin_num);
344 writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
345
346
347 reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_OUTEN_OFFSET(bank_num));
348 reg |= BIT(bank_pin_num);
349 writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_OUTEN_OFFSET(bank_num));
350
351
352 zynq_gpio_set_value(chip, pin, state);
353 return 0;
354}
355
356
357
358
359
360
361
362
363
364
365static int zynq_gpio_get_direction(struct gpio_chip *chip, unsigned int pin)
366{
367 u32 reg;
368 unsigned int bank_num, bank_pin_num;
369 struct zynq_gpio *gpio = gpiochip_get_data(chip);
370
371 zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio);
372
373 reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
374
375 return !(reg & BIT(bank_pin_num));
376}
377
378
379
380
381
382
383
384
385
386static void zynq_gpio_irq_mask(struct irq_data *irq_data)
387{
388 unsigned int device_pin_num, bank_num, bank_pin_num;
389 struct zynq_gpio *gpio =
390 gpiochip_get_data(irq_data_get_irq_chip_data(irq_data));
391
392 device_pin_num = irq_data->hwirq;
393 zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num, gpio);
394 writel_relaxed(BIT(bank_pin_num),
395 gpio->base_addr + ZYNQ_GPIO_INTDIS_OFFSET(bank_num));
396}
397
398
399
400
401
402
403
404
405
406
407static void zynq_gpio_irq_unmask(struct irq_data *irq_data)
408{
409 unsigned int device_pin_num, bank_num, bank_pin_num;
410 struct zynq_gpio *gpio =
411 gpiochip_get_data(irq_data_get_irq_chip_data(irq_data));
412
413 device_pin_num = irq_data->hwirq;
414 zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num, gpio);
415 writel_relaxed(BIT(bank_pin_num),
416 gpio->base_addr + ZYNQ_GPIO_INTEN_OFFSET(bank_num));
417}
418
419
420
421
422
423
424
425
426
427static void zynq_gpio_irq_ack(struct irq_data *irq_data)
428{
429 unsigned int device_pin_num, bank_num, bank_pin_num;
430 struct zynq_gpio *gpio =
431 gpiochip_get_data(irq_data_get_irq_chip_data(irq_data));
432
433 device_pin_num = irq_data->hwirq;
434 zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num, gpio);
435 writel_relaxed(BIT(bank_pin_num),
436 gpio->base_addr + ZYNQ_GPIO_INTSTS_OFFSET(bank_num));
437}
438
439
440
441
442
443
444
445
446static void zynq_gpio_irq_enable(struct irq_data *irq_data)
447{
448
449
450
451
452
453
454
455
456
457
458 zynq_gpio_irq_ack(irq_data);
459 zynq_gpio_irq_unmask(irq_data);
460}
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477static int zynq_gpio_set_irq_type(struct irq_data *irq_data, unsigned int type)
478{
479 u32 int_type, int_pol, int_any;
480 unsigned int device_pin_num, bank_num, bank_pin_num;
481 struct zynq_gpio *gpio =
482 gpiochip_get_data(irq_data_get_irq_chip_data(irq_data));
483
484 device_pin_num = irq_data->hwirq;
485 zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num, gpio);
486
487 int_type = readl_relaxed(gpio->base_addr +
488 ZYNQ_GPIO_INTTYPE_OFFSET(bank_num));
489 int_pol = readl_relaxed(gpio->base_addr +
490 ZYNQ_GPIO_INTPOL_OFFSET(bank_num));
491 int_any = readl_relaxed(gpio->base_addr +
492 ZYNQ_GPIO_INTANY_OFFSET(bank_num));
493
494
495
496
497
498 switch (type) {
499 case IRQ_TYPE_EDGE_RISING:
500 int_type |= BIT(bank_pin_num);
501 int_pol |= BIT(bank_pin_num);
502 int_any &= ~BIT(bank_pin_num);
503 break;
504 case IRQ_TYPE_EDGE_FALLING:
505 int_type |= BIT(bank_pin_num);
506 int_pol &= ~BIT(bank_pin_num);
507 int_any &= ~BIT(bank_pin_num);
508 break;
509 case IRQ_TYPE_EDGE_BOTH:
510 int_type |= BIT(bank_pin_num);
511 int_any |= BIT(bank_pin_num);
512 break;
513 case IRQ_TYPE_LEVEL_HIGH:
514 int_type &= ~BIT(bank_pin_num);
515 int_pol |= BIT(bank_pin_num);
516 break;
517 case IRQ_TYPE_LEVEL_LOW:
518 int_type &= ~BIT(bank_pin_num);
519 int_pol &= ~BIT(bank_pin_num);
520 break;
521 default:
522 return -EINVAL;
523 }
524
525 writel_relaxed(int_type,
526 gpio->base_addr + ZYNQ_GPIO_INTTYPE_OFFSET(bank_num));
527 writel_relaxed(int_pol,
528 gpio->base_addr + ZYNQ_GPIO_INTPOL_OFFSET(bank_num));
529 writel_relaxed(int_any,
530 gpio->base_addr + ZYNQ_GPIO_INTANY_OFFSET(bank_num));
531
532 if (type & IRQ_TYPE_LEVEL_MASK)
533 irq_set_chip_handler_name_locked(irq_data,
534 &zynq_gpio_level_irqchip,
535 handle_fasteoi_irq, NULL);
536 else
537 irq_set_chip_handler_name_locked(irq_data,
538 &zynq_gpio_edge_irqchip,
539 handle_level_irq, NULL);
540
541 return 0;
542}
543
544static int zynq_gpio_set_wake(struct irq_data *data, unsigned int on)
545{
546 struct zynq_gpio *gpio =
547 gpiochip_get_data(irq_data_get_irq_chip_data(data));
548
549 irq_set_irq_wake(gpio->irq, on);
550
551 return 0;
552}
553
554static int zynq_gpio_irq_reqres(struct irq_data *d)
555{
556 struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
557 int ret;
558
559 ret = pm_runtime_get_sync(chip->parent);
560 if (ret < 0)
561 return ret;
562
563 return gpiochip_reqres_irq(chip, d->hwirq);
564}
565
566static void zynq_gpio_irq_relres(struct irq_data *d)
567{
568 struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
569
570 gpiochip_relres_irq(chip, d->hwirq);
571 pm_runtime_put(chip->parent);
572}
573
574
575static struct irq_chip zynq_gpio_level_irqchip = {
576 .name = DRIVER_NAME,
577 .irq_enable = zynq_gpio_irq_enable,
578 .irq_eoi = zynq_gpio_irq_ack,
579 .irq_mask = zynq_gpio_irq_mask,
580 .irq_unmask = zynq_gpio_irq_unmask,
581 .irq_set_type = zynq_gpio_set_irq_type,
582 .irq_set_wake = zynq_gpio_set_wake,
583 .irq_request_resources = zynq_gpio_irq_reqres,
584 .irq_release_resources = zynq_gpio_irq_relres,
585 .flags = IRQCHIP_EOI_THREADED | IRQCHIP_EOI_IF_HANDLED |
586 IRQCHIP_MASK_ON_SUSPEND,
587};
588
589static struct irq_chip zynq_gpio_edge_irqchip = {
590 .name = DRIVER_NAME,
591 .irq_enable = zynq_gpio_irq_enable,
592 .irq_ack = zynq_gpio_irq_ack,
593 .irq_mask = zynq_gpio_irq_mask,
594 .irq_unmask = zynq_gpio_irq_unmask,
595 .irq_set_type = zynq_gpio_set_irq_type,
596 .irq_set_wake = zynq_gpio_set_wake,
597 .irq_request_resources = zynq_gpio_irq_reqres,
598 .irq_release_resources = zynq_gpio_irq_relres,
599 .flags = IRQCHIP_MASK_ON_SUSPEND,
600};
601
602static void zynq_gpio_handle_bank_irq(struct zynq_gpio *gpio,
603 unsigned int bank_num,
604 unsigned long pending)
605{
606 unsigned int bank_offset = gpio->p_data->bank_min[bank_num];
607 struct irq_domain *irqdomain = gpio->chip.irq.domain;
608 int offset;
609
610 if (!pending)
611 return;
612
613 for_each_set_bit(offset, &pending, 32) {
614 unsigned int gpio_irq;
615
616 gpio_irq = irq_find_mapping(irqdomain, offset + bank_offset);
617 generic_handle_irq(gpio_irq);
618 }
619}
620
621
622
623
624
625
626
627
628
629
630
631static void zynq_gpio_irqhandler(struct irq_desc *desc)
632{
633 u32 int_sts, int_enb;
634 unsigned int bank_num;
635 struct zynq_gpio *gpio =
636 gpiochip_get_data(irq_desc_get_handler_data(desc));
637 struct irq_chip *irqchip = irq_desc_get_chip(desc);
638
639 chained_irq_enter(irqchip, desc);
640
641 for (bank_num = 0; bank_num < gpio->p_data->max_bank; bank_num++) {
642 int_sts = readl_relaxed(gpio->base_addr +
643 ZYNQ_GPIO_INTSTS_OFFSET(bank_num));
644 int_enb = readl_relaxed(gpio->base_addr +
645 ZYNQ_GPIO_INTMASK_OFFSET(bank_num));
646 zynq_gpio_handle_bank_irq(gpio, bank_num, int_sts & ~int_enb);
647 }
648
649 chained_irq_exit(irqchip, desc);
650}
651
652static void zynq_gpio_save_context(struct zynq_gpio *gpio)
653{
654 unsigned int bank_num;
655
656 for (bank_num = 0; bank_num < gpio->p_data->max_bank; bank_num++) {
657 gpio->context.datalsw[bank_num] =
658 readl_relaxed(gpio->base_addr +
659 ZYNQ_GPIO_DATA_LSW_OFFSET(bank_num));
660 gpio->context.datamsw[bank_num] =
661 readl_relaxed(gpio->base_addr +
662 ZYNQ_GPIO_DATA_MSW_OFFSET(bank_num));
663 gpio->context.dirm[bank_num] = readl_relaxed(gpio->base_addr +
664 ZYNQ_GPIO_DIRM_OFFSET(bank_num));
665 gpio->context.int_en[bank_num] = readl_relaxed(gpio->base_addr +
666 ZYNQ_GPIO_INTMASK_OFFSET(bank_num));
667 gpio->context.int_type[bank_num] =
668 readl_relaxed(gpio->base_addr +
669 ZYNQ_GPIO_INTTYPE_OFFSET(bank_num));
670 gpio->context.int_polarity[bank_num] =
671 readl_relaxed(gpio->base_addr +
672 ZYNQ_GPIO_INTPOL_OFFSET(bank_num));
673 gpio->context.int_any[bank_num] =
674 readl_relaxed(gpio->base_addr +
675 ZYNQ_GPIO_INTANY_OFFSET(bank_num));
676 }
677}
678
679static void zynq_gpio_restore_context(struct zynq_gpio *gpio)
680{
681 unsigned int bank_num;
682
683 for (bank_num = 0; bank_num < gpio->p_data->max_bank; bank_num++) {
684 writel_relaxed(gpio->context.datalsw[bank_num],
685 gpio->base_addr +
686 ZYNQ_GPIO_DATA_LSW_OFFSET(bank_num));
687 writel_relaxed(gpio->context.datamsw[bank_num],
688 gpio->base_addr +
689 ZYNQ_GPIO_DATA_MSW_OFFSET(bank_num));
690 writel_relaxed(gpio->context.dirm[bank_num],
691 gpio->base_addr +
692 ZYNQ_GPIO_DIRM_OFFSET(bank_num));
693 writel_relaxed(gpio->context.int_en[bank_num],
694 gpio->base_addr +
695 ZYNQ_GPIO_INTEN_OFFSET(bank_num));
696 writel_relaxed(gpio->context.int_type[bank_num],
697 gpio->base_addr +
698 ZYNQ_GPIO_INTTYPE_OFFSET(bank_num));
699 writel_relaxed(gpio->context.int_polarity[bank_num],
700 gpio->base_addr +
701 ZYNQ_GPIO_INTPOL_OFFSET(bank_num));
702 writel_relaxed(gpio->context.int_any[bank_num],
703 gpio->base_addr +
704 ZYNQ_GPIO_INTANY_OFFSET(bank_num));
705 }
706}
707
708static int __maybe_unused zynq_gpio_suspend(struct device *dev)
709{
710 struct zynq_gpio *gpio = dev_get_drvdata(dev);
711 struct irq_data *data = irq_get_irq_data(gpio->irq);
712
713 if (!irqd_is_wakeup_set(data)) {
714 zynq_gpio_save_context(gpio);
715 return pm_runtime_force_suspend(dev);
716 }
717
718 return 0;
719}
720
721static int __maybe_unused zynq_gpio_resume(struct device *dev)
722{
723 struct zynq_gpio *gpio = dev_get_drvdata(dev);
724 struct irq_data *data = irq_get_irq_data(gpio->irq);
725 int ret;
726
727 if (!irqd_is_wakeup_set(data)) {
728 ret = pm_runtime_force_resume(dev);
729 zynq_gpio_restore_context(gpio);
730 return ret;
731 }
732
733 return 0;
734}
735
736static int __maybe_unused zynq_gpio_runtime_suspend(struct device *dev)
737{
738 struct zynq_gpio *gpio = dev_get_drvdata(dev);
739
740 clk_disable_unprepare(gpio->clk);
741
742 return 0;
743}
744
745static int __maybe_unused zynq_gpio_runtime_resume(struct device *dev)
746{
747 struct zynq_gpio *gpio = dev_get_drvdata(dev);
748
749 return clk_prepare_enable(gpio->clk);
750}
751
752static int zynq_gpio_request(struct gpio_chip *chip, unsigned int offset)
753{
754 int ret;
755
756 ret = pm_runtime_get_sync(chip->parent);
757
758
759
760
761
762 return ret < 0 ? ret : 0;
763}
764
765static void zynq_gpio_free(struct gpio_chip *chip, unsigned int offset)
766{
767 pm_runtime_put(chip->parent);
768}
769
770static const struct dev_pm_ops zynq_gpio_dev_pm_ops = {
771 SET_SYSTEM_SLEEP_PM_OPS(zynq_gpio_suspend, zynq_gpio_resume)
772 SET_RUNTIME_PM_OPS(zynq_gpio_runtime_suspend,
773 zynq_gpio_runtime_resume, NULL)
774};
775
776static const struct zynq_platform_data zynqmp_gpio_def = {
777 .label = "zynqmp_gpio",
778 .quirks = GPIO_QUIRK_DATA_RO_BUG,
779 .ngpio = ZYNQMP_GPIO_NR_GPIOS,
780 .max_bank = ZYNQMP_GPIO_MAX_BANK,
781 .bank_min[0] = ZYNQ_GPIO_BANK0_PIN_MIN(MP),
782 .bank_max[0] = ZYNQ_GPIO_BANK0_PIN_MAX(MP),
783 .bank_min[1] = ZYNQ_GPIO_BANK1_PIN_MIN(MP),
784 .bank_max[1] = ZYNQ_GPIO_BANK1_PIN_MAX(MP),
785 .bank_min[2] = ZYNQ_GPIO_BANK2_PIN_MIN(MP),
786 .bank_max[2] = ZYNQ_GPIO_BANK2_PIN_MAX(MP),
787 .bank_min[3] = ZYNQ_GPIO_BANK3_PIN_MIN(MP),
788 .bank_max[3] = ZYNQ_GPIO_BANK3_PIN_MAX(MP),
789 .bank_min[4] = ZYNQ_GPIO_BANK4_PIN_MIN(MP),
790 .bank_max[4] = ZYNQ_GPIO_BANK4_PIN_MAX(MP),
791 .bank_min[5] = ZYNQ_GPIO_BANK5_PIN_MIN(MP),
792 .bank_max[5] = ZYNQ_GPIO_BANK5_PIN_MAX(MP),
793};
794
795static const struct zynq_platform_data zynq_gpio_def = {
796 .label = "zynq_gpio",
797 .quirks = ZYNQ_GPIO_QUIRK_IS_ZYNQ | GPIO_QUIRK_DATA_RO_BUG,
798 .ngpio = ZYNQ_GPIO_NR_GPIOS,
799 .max_bank = ZYNQ_GPIO_MAX_BANK,
800 .bank_min[0] = ZYNQ_GPIO_BANK0_PIN_MIN(),
801 .bank_max[0] = ZYNQ_GPIO_BANK0_PIN_MAX(),
802 .bank_min[1] = ZYNQ_GPIO_BANK1_PIN_MIN(),
803 .bank_max[1] = ZYNQ_GPIO_BANK1_PIN_MAX(),
804 .bank_min[2] = ZYNQ_GPIO_BANK2_PIN_MIN(),
805 .bank_max[2] = ZYNQ_GPIO_BANK2_PIN_MAX(),
806 .bank_min[3] = ZYNQ_GPIO_BANK3_PIN_MIN(),
807 .bank_max[3] = ZYNQ_GPIO_BANK3_PIN_MAX(),
808};
809
810static const struct of_device_id zynq_gpio_of_match[] = {
811 { .compatible = "xlnx,zynq-gpio-1.0", .data = &zynq_gpio_def },
812 { .compatible = "xlnx,zynqmp-gpio-1.0", .data = &zynqmp_gpio_def },
813 { }
814};
815MODULE_DEVICE_TABLE(of, zynq_gpio_of_match);
816
817
818
819
820
821
822
823
824
825
826
827
828static int zynq_gpio_probe(struct platform_device *pdev)
829{
830 int ret, bank_num;
831 struct zynq_gpio *gpio;
832 struct gpio_chip *chip;
833 const struct of_device_id *match;
834
835 gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
836 if (!gpio)
837 return -ENOMEM;
838
839 match = of_match_node(zynq_gpio_of_match, pdev->dev.of_node);
840 if (!match) {
841 dev_err(&pdev->dev, "of_match_node() failed\n");
842 return -EINVAL;
843 }
844 gpio->p_data = match->data;
845 platform_set_drvdata(pdev, gpio);
846
847 gpio->base_addr = devm_platform_ioremap_resource(pdev, 0);
848 if (IS_ERR(gpio->base_addr))
849 return PTR_ERR(gpio->base_addr);
850
851 gpio->irq = platform_get_irq(pdev, 0);
852 if (gpio->irq < 0) {
853 dev_err(&pdev->dev, "invalid IRQ\n");
854 return gpio->irq;
855 }
856
857
858 chip = &gpio->chip;
859 chip->label = gpio->p_data->label;
860 chip->owner = THIS_MODULE;
861 chip->parent = &pdev->dev;
862 chip->get = zynq_gpio_get_value;
863 chip->set = zynq_gpio_set_value;
864 chip->request = zynq_gpio_request;
865 chip->free = zynq_gpio_free;
866 chip->direction_input = zynq_gpio_dir_in;
867 chip->direction_output = zynq_gpio_dir_out;
868 chip->get_direction = zynq_gpio_get_direction;
869 chip->base = of_alias_get_id(pdev->dev.of_node, "gpio");
870 chip->ngpio = gpio->p_data->ngpio;
871
872
873 gpio->clk = devm_clk_get(&pdev->dev, NULL);
874 if (IS_ERR(gpio->clk)) {
875 dev_err(&pdev->dev, "input clock not found.\n");
876 return PTR_ERR(gpio->clk);
877 }
878 ret = clk_prepare_enable(gpio->clk);
879 if (ret) {
880 dev_err(&pdev->dev, "Unable to enable clock.\n");
881 return ret;
882 }
883
884 pm_runtime_set_active(&pdev->dev);
885 pm_runtime_enable(&pdev->dev);
886 ret = pm_runtime_get_sync(&pdev->dev);
887 if (ret < 0)
888 goto err_pm_dis;
889
890
891 ret = gpiochip_add_data(chip, gpio);
892 if (ret) {
893 dev_err(&pdev->dev, "Failed to add gpio chip\n");
894 goto err_pm_put;
895 }
896
897
898 for (bank_num = 0; bank_num < gpio->p_data->max_bank; bank_num++)
899 writel_relaxed(ZYNQ_GPIO_IXR_DISABLE_ALL, gpio->base_addr +
900 ZYNQ_GPIO_INTDIS_OFFSET(bank_num));
901
902 ret = gpiochip_irqchip_add(chip, &zynq_gpio_edge_irqchip, 0,
903 handle_level_irq, IRQ_TYPE_NONE);
904 if (ret) {
905 dev_err(&pdev->dev, "Failed to add irq chip\n");
906 goto err_rm_gpiochip;
907 }
908
909 gpiochip_set_chained_irqchip(chip, &zynq_gpio_edge_irqchip, gpio->irq,
910 zynq_gpio_irqhandler);
911
912 pm_runtime_put(&pdev->dev);
913
914 return 0;
915
916err_rm_gpiochip:
917 gpiochip_remove(chip);
918err_pm_put:
919 pm_runtime_put(&pdev->dev);
920err_pm_dis:
921 pm_runtime_disable(&pdev->dev);
922 clk_disable_unprepare(gpio->clk);
923
924 return ret;
925}
926
927
928
929
930
931
932
933static int zynq_gpio_remove(struct platform_device *pdev)
934{
935 struct zynq_gpio *gpio = platform_get_drvdata(pdev);
936
937 pm_runtime_get_sync(&pdev->dev);
938 gpiochip_remove(&gpio->chip);
939 clk_disable_unprepare(gpio->clk);
940 device_set_wakeup_capable(&pdev->dev, 0);
941 pm_runtime_disable(&pdev->dev);
942 return 0;
943}
944
945static struct platform_driver zynq_gpio_driver = {
946 .driver = {
947 .name = DRIVER_NAME,
948 .pm = &zynq_gpio_dev_pm_ops,
949 .of_match_table = zynq_gpio_of_match,
950 },
951 .probe = zynq_gpio_probe,
952 .remove = zynq_gpio_remove,
953};
954
955
956
957
958
959
960static int __init zynq_gpio_init(void)
961{
962 return platform_driver_register(&zynq_gpio_driver);
963}
964postcore_initcall(zynq_gpio_init);
965
966static void __exit zynq_gpio_exit(void)
967{
968 platform_driver_unregister(&zynq_gpio_driver);
969}
970module_exit(zynq_gpio_exit);
971
972MODULE_AUTHOR("Xilinx Inc.");
973MODULE_DESCRIPTION("Zynq GPIO driver");
974MODULE_LICENSE("GPL");
975