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25#include <drm/drmP.h>
26#include <drm/amdgpu_drm.h>
27#include <drm/drm_gem.h>
28#include "amdgpu_drv.h"
29
30#include <drm/drm_pciids.h>
31#include <linux/console.h>
32#include <linux/module.h>
33#include <linux/pm_runtime.h>
34#include <linux/vga_switcheroo.h>
35#include <drm/drm_probe_helper.h>
36
37#include "amdgpu.h"
38#include "amdgpu_irq.h"
39#include "amdgpu_gem.h"
40
41#include "amdgpu_amdkfd.h"
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80#define KMS_DRIVER_MAJOR 3
81#define KMS_DRIVER_MINOR 32
82#define KMS_DRIVER_PATCHLEVEL 0
83
84int amdgpu_vram_limit = 0;
85int amdgpu_vis_vram_limit = 0;
86int amdgpu_gart_size = -1;
87int amdgpu_gtt_size = -1;
88int amdgpu_moverate = -1;
89int amdgpu_benchmarking = 0;
90int amdgpu_testing = 0;
91int amdgpu_audio = -1;
92int amdgpu_disp_priority = 0;
93int amdgpu_hw_i2c = 0;
94int amdgpu_pcie_gen2 = -1;
95int amdgpu_msi = -1;
96int amdgpu_lockup_timeout = 10000;
97int amdgpu_dpm = -1;
98int amdgpu_fw_load_type = -1;
99int amdgpu_aspm = -1;
100int amdgpu_runtime_pm = -1;
101uint amdgpu_ip_block_mask = 0xffffffff;
102int amdgpu_bapm = -1;
103int amdgpu_deep_color = 0;
104int amdgpu_vm_size = -1;
105int amdgpu_vm_fragment_size = -1;
106int amdgpu_vm_block_size = -1;
107int amdgpu_vm_fault_stop = 0;
108int amdgpu_vm_debug = 0;
109int amdgpu_vram_page_split = 512;
110int amdgpu_vm_update_mode = -1;
111int amdgpu_exp_hw_support = 0;
112int amdgpu_dc = -1;
113int amdgpu_sched_jobs = 32;
114int amdgpu_sched_hw_submission = 2;
115uint amdgpu_pcie_gen_cap = 0;
116uint amdgpu_pcie_lane_cap = 0;
117uint amdgpu_cg_mask = 0xffffffff;
118uint amdgpu_pg_mask = 0xffffffff;
119uint amdgpu_sdma_phase_quantum = 32;
120char *amdgpu_disable_cu = NULL;
121char *amdgpu_virtual_display = NULL;
122
123uint amdgpu_pp_feature_mask = 0xffffbfff;
124int amdgpu_ngg = 0;
125int amdgpu_prim_buf_per_se = 0;
126int amdgpu_pos_buf_per_se = 0;
127int amdgpu_cntl_sb_buf_per_se = 0;
128int amdgpu_param_buf_per_se = 0;
129int amdgpu_job_hang_limit = 0;
130int amdgpu_lbpw = -1;
131int amdgpu_compute_multipipe = -1;
132int amdgpu_gpu_recovery = -1;
133int amdgpu_emu_mode = 0;
134uint amdgpu_smu_memory_pool_size = 0;
135
136uint amdgpu_dc_feature_mask = 0;
137
138struct amdgpu_mgpu_info mgpu_info = {
139 .mutex = __MUTEX_INITIALIZER(mgpu_info.mutex),
140};
141int amdgpu_ras_enable = -1;
142uint amdgpu_ras_mask = 0xffffffff;
143
144
145
146
147
148MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes");
149module_param_named(vramlimit, amdgpu_vram_limit, int, 0600);
150
151
152
153
154
155MODULE_PARM_DESC(vis_vramlimit, "Restrict visible VRAM for testing, in megabytes");
156module_param_named(vis_vramlimit, amdgpu_vis_vram_limit, int, 0444);
157
158
159
160
161
162MODULE_PARM_DESC(gartsize, "Size of GART to setup in megabytes (32, 64, etc., -1=auto)");
163module_param_named(gartsize, amdgpu_gart_size, uint, 0600);
164
165
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167
168
169
170MODULE_PARM_DESC(gttsize, "Size of the GTT domain in megabytes (-1 = auto)");
171module_param_named(gttsize, amdgpu_gtt_size, int, 0600);
172
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174
175
176
177MODULE_PARM_DESC(moverate, "Maximum buffer migration rate in MB/s. (32, 64, etc., -1=auto, 0=1=disabled)");
178module_param_named(moverate, amdgpu_moverate, int, 0600);
179
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183
184MODULE_PARM_DESC(benchmark, "Run benchmark");
185module_param_named(benchmark, amdgpu_benchmarking, int, 0444);
186
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190
191MODULE_PARM_DESC(test, "Run tests");
192module_param_named(test, amdgpu_testing, int, 0444);
193
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196
197
198MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)");
199module_param_named(audio, amdgpu_audio, int, 0444);
200
201
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203
204
205MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)");
206module_param_named(disp_priority, amdgpu_disp_priority, int, 0444);
207
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210
211
212MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)");
213module_param_named(hw_i2c, amdgpu_hw_i2c, int, 0444);
214
215
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217
218
219MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)");
220module_param_named(pcie_gen2, amdgpu_pcie_gen2, int, 0444);
221
222
223
224
225
226MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)");
227module_param_named(msi, amdgpu_msi, int, 0444);
228
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230
231
232
233
234MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms > 0 (default 10000)");
235module_param_named(lockup_timeout, amdgpu_lockup_timeout, int, 0444);
236
237
238
239
240
241MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)");
242module_param_named(dpm, amdgpu_dpm, int, 0444);
243
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245
246
247
248MODULE_PARM_DESC(fw_load_type, "firmware loading type (0 = direct, 1 = SMU, 2 = PSP, -1 = auto)");
249module_param_named(fw_load_type, amdgpu_fw_load_type, int, 0444);
250
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254
255MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)");
256module_param_named(aspm, amdgpu_aspm, int, 0444);
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261
262
263MODULE_PARM_DESC(runpm, "PX runtime pm (1 = force enable, 0 = disable, -1 = PX only default)");
264module_param_named(runpm, amdgpu_runtime_pm, int, 0444);
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272
273MODULE_PARM_DESC(ip_block_mask, "IP Block Mask (all blocks enabled (default))");
274module_param_named(ip_block_mask, amdgpu_ip_block_mask, uint, 0444);
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280
281MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)");
282module_param_named(bapm, amdgpu_bapm, int, 0444);
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288MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))");
289module_param_named(deep_color, amdgpu_deep_color, int, 0444);
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295MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 64GB)");
296module_param_named(vm_size, amdgpu_vm_size, int, 0444);
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301
302MODULE_PARM_DESC(vm_fragment_size, "VM fragment size in bits (4, 5, etc. 4 = 64K (default), Max 9 = 2M)");
303module_param_named(vm_fragment_size, amdgpu_vm_fragment_size, int, 0444);
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309MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)");
310module_param_named(vm_block_size, amdgpu_vm_block_size, int, 0444);
311
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314
315
316MODULE_PARM_DESC(vm_fault_stop, "Stop on VM fault (0 = never (default), 1 = print first, 2 = always)");
317module_param_named(vm_fault_stop, amdgpu_vm_fault_stop, int, 0444);
318
319
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321
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323MODULE_PARM_DESC(vm_debug, "Debug VM handling (0 = disabled (default), 1 = enabled)");
324module_param_named(vm_debug, amdgpu_vm_debug, int, 0644);
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330
331MODULE_PARM_DESC(vm_update_mode, "VM update using CPU (0 = never (default except for large BAR(LB)), 1 = Graphics only, 2 = Compute only (default for LB), 3 = Both");
332module_param_named(vm_update_mode, amdgpu_vm_update_mode, int, 0444);
333
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336
337
338MODULE_PARM_DESC(vram_page_split, "Number of pages after we split VRAM allocations (default 512, -1 = disable)");
339module_param_named(vram_page_split, amdgpu_vram_page_split, int, 0444);
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344
345MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = disable (default))");
346module_param_named(exp_hw_support, amdgpu_exp_hw_support, int, 0444);
347
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352MODULE_PARM_DESC(dc, "Display Core driver (1 = enable, 0 = disable, -1 = auto (default))");
353module_param_named(dc, amdgpu_dc, int, 0444);
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357
358
359MODULE_PARM_DESC(sched_jobs, "the max number of jobs supported in the sw queue (default 32)");
360module_param_named(sched_jobs, amdgpu_sched_jobs, int, 0444);
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365
366MODULE_PARM_DESC(sched_hw_submission, "the max number of HW submissions (default 2)");
367module_param_named(sched_hw_submission, amdgpu_sched_hw_submission, int, 0444);
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373
374MODULE_PARM_DESC(ppfeaturemask, "all power features enabled (default))");
375module_param_named(ppfeaturemask, amdgpu_pp_feature_mask, uint, 0444);
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381
382MODULE_PARM_DESC(pcie_gen_cap, "PCIE Gen Caps (0: autodetect (default))");
383module_param_named(pcie_gen_cap, amdgpu_pcie_gen_cap, uint, 0444);
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390MODULE_PARM_DESC(pcie_lane_cap, "PCIE Lane Caps (0: autodetect (default))");
391module_param_named(pcie_lane_cap, amdgpu_pcie_lane_cap, uint, 0444);
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397
398MODULE_PARM_DESC(cg_mask, "Clockgating flags mask (0 = disable clock gating)");
399module_param_named(cg_mask, amdgpu_cg_mask, uint, 0444);
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406MODULE_PARM_DESC(pg_mask, "Powergating flags mask (0 = disable power gating)");
407module_param_named(pg_mask, amdgpu_pg_mask, uint, 0444);
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412
413MODULE_PARM_DESC(sdma_phase_quantum, "SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change (default 32))");
414module_param_named(sdma_phase_quantum, amdgpu_sdma_phase_quantum, uint, 0444);
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420MODULE_PARM_DESC(disable_cu, "Disable CUs (se.sh.cu,...)");
421module_param_named(disable_cu, amdgpu_disable_cu, charp, 0444);
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429
430MODULE_PARM_DESC(virtual_display,
431 "Enable virtual display feature (the virtual_display will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x)");
432module_param_named(virtual_display, amdgpu_virtual_display, charp, 0444);
433
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438MODULE_PARM_DESC(ngg, "Next Generation Graphics (1 = enable, 0 = disable(default depending on gfx))");
439module_param_named(ngg, amdgpu_ngg, int, 0444);
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442
443
444
445MODULE_PARM_DESC(prim_buf_per_se, "the size of Primitive Buffer per Shader Engine (default depending on gfx)");
446module_param_named(prim_buf_per_se, amdgpu_prim_buf_per_se, int, 0444);
447
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450
451
452MODULE_PARM_DESC(pos_buf_per_se, "the size of Position Buffer per Shader Engine (default depending on gfx)");
453module_param_named(pos_buf_per_se, amdgpu_pos_buf_per_se, int, 0444);
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458
459MODULE_PARM_DESC(cntl_sb_buf_per_se, "the size of Control Sideband per Shader Engine (default depending on gfx)");
460module_param_named(cntl_sb_buf_per_se, amdgpu_cntl_sb_buf_per_se, int, 0444);
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467MODULE_PARM_DESC(param_buf_per_se, "the size of Off-Chip Parameter Cache per Shader Engine (default depending on gfx)");
468module_param_named(param_buf_per_se, amdgpu_param_buf_per_se, int, 0444);
469
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471
472
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474MODULE_PARM_DESC(job_hang_limit, "how much time allow a job hang and not drop it (default 0)");
475module_param_named(job_hang_limit, amdgpu_job_hang_limit, int ,0444);
476
477
478
479
480
481MODULE_PARM_DESC(lbpw, "Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable, -1 = auto)");
482module_param_named(lbpw, amdgpu_lbpw, int, 0444);
483
484MODULE_PARM_DESC(compute_multipipe, "Force compute queues to be spread across pipes (1 = enable, 0 = disable, -1 = auto)");
485module_param_named(compute_multipipe, amdgpu_compute_multipipe, int, 0444);
486
487
488
489
490
491MODULE_PARM_DESC(gpu_recovery, "Enable GPU recovery mechanism, (1 = enable, 0 = disable, -1 = auto)");
492module_param_named(gpu_recovery, amdgpu_gpu_recovery, int, 0444);
493
494
495
496
497
498MODULE_PARM_DESC(emu_mode, "Emulation mode, (1 = enable, 0 = disable)");
499module_param_named(emu_mode, amdgpu_emu_mode, int, 0444);
500
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502
503
504
505MODULE_PARM_DESC(ras_enable, "Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default))");
506module_param_named(ras_enable, amdgpu_ras_enable, int, 0444);
507
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513MODULE_PARM_DESC(ras_mask, "Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1");
514module_param_named(ras_mask, amdgpu_ras_mask, uint, 0444);
515
516
517
518
519
520
521
522#ifdef CONFIG_DRM_AMDGPU_SI
523
524#if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE)
525int amdgpu_si_support = 0;
526MODULE_PARM_DESC(si_support, "SI support (1 = enabled, 0 = disabled (default))");
527#else
528int amdgpu_si_support = 1;
529MODULE_PARM_DESC(si_support, "SI support (1 = enabled (default), 0 = disabled)");
530#endif
531
532module_param_named(si_support, amdgpu_si_support, int, 0444);
533#endif
534
535
536
537
538
539
540
541#ifdef CONFIG_DRM_AMDGPU_CIK
542
543#if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE)
544int amdgpu_cik_support = 0;
545MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled, 0 = disabled (default))");
546#else
547int amdgpu_cik_support = 1;
548MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled (default), 0 = disabled)");
549#endif
550
551module_param_named(cik_support, amdgpu_cik_support, int, 0444);
552#endif
553
554
555
556
557
558
559MODULE_PARM_DESC(smu_memory_pool_size,
560 "reserve gtt for smu debug usage, 0 = disable,"
561 "0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte");
562module_param_named(smu_memory_pool_size, amdgpu_smu_memory_pool_size, uint, 0444);
563
564#ifdef CONFIG_HSA_AMD
565
566
567
568
569
570
571int sched_policy = KFD_SCHED_POLICY_HWS;
572module_param(sched_policy, int, 0444);
573MODULE_PARM_DESC(sched_policy,
574 "Scheduling policy (0 = HWS (Default), 1 = HWS without over-subscription, 2 = Non-HWS (Used for debugging only)");
575
576
577
578
579
580
581int hws_max_conc_proc = 8;
582module_param(hws_max_conc_proc, int, 0444);
583MODULE_PARM_DESC(hws_max_conc_proc,
584 "Max # processes HWS can execute concurrently when sched_policy=0 (0 = no concurrency, #VMIDs for KFD = Maximum(default))");
585
586
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588
589
590
591
592int cwsr_enable = 1;
593module_param(cwsr_enable, int, 0444);
594MODULE_PARM_DESC(cwsr_enable, "CWSR enable (0 = Off, 1 = On (Default))");
595
596
597
598
599
600
601int max_num_of_queues_per_device = KFD_MAX_NUM_OF_QUEUES_PER_DEVICE_DEFAULT;
602module_param(max_num_of_queues_per_device, int, 0444);
603MODULE_PARM_DESC(max_num_of_queues_per_device,
604 "Maximum number of supported queues per device (1 = Minimum, 4096 = default)");
605
606
607
608
609
610
611int send_sigterm;
612module_param(send_sigterm, int, 0444);
613MODULE_PARM_DESC(send_sigterm,
614 "Send sigterm to HSA process on unhandled exception (0 = disable, 1 = enable)");
615
616
617
618
619
620
621
622
623int debug_largebar;
624module_param(debug_largebar, int, 0444);
625MODULE_PARM_DESC(debug_largebar,
626 "Debug large-bar flag used to simulate large-bar capability on non-large bar machine (0 = disable, 1 = enable)");
627
628
629
630
631
632
633
634int ignore_crat;
635module_param(ignore_crat, int, 0444);
636MODULE_PARM_DESC(ignore_crat,
637 "Ignore CRAT table during KFD initialization (0 = use CRAT (default), 1 = ignore CRAT)");
638
639
640
641
642
643
644
645int noretry;
646module_param(noretry, int, 0644);
647MODULE_PARM_DESC(noretry,
648 "Set sh_mem_config.retry_disable on Vega10 (0 = retry enabled (default), 1 = retry disabled)");
649
650
651
652
653
654
655int halt_if_hws_hang;
656module_param(halt_if_hws_hang, int, 0644);
657MODULE_PARM_DESC(halt_if_hws_hang, "Halt if HWS hang is detected (0 = off (default), 1 = on)");
658#endif
659
660
661
662
663
664
665MODULE_PARM_DESC(dcfeaturemask, "all stable DC features enabled (default))");
666module_param_named(dcfeaturemask, amdgpu_dc_feature_mask, uint, 0444);
667
668static const struct pci_device_id pciidlist[] = {
669#ifdef CONFIG_DRM_AMDGPU_SI
670 {0x1002, 0x6780, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
671 {0x1002, 0x6784, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
672 {0x1002, 0x6788, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
673 {0x1002, 0x678A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
674 {0x1002, 0x6790, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
675 {0x1002, 0x6791, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
676 {0x1002, 0x6792, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
677 {0x1002, 0x6798, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
678 {0x1002, 0x6799, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
679 {0x1002, 0x679A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
680 {0x1002, 0x679B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
681 {0x1002, 0x679E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
682 {0x1002, 0x679F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
683 {0x1002, 0x6800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY},
684 {0x1002, 0x6801, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY},
685 {0x1002, 0x6802, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY},
686 {0x1002, 0x6806, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
687 {0x1002, 0x6808, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
688 {0x1002, 0x6809, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
689 {0x1002, 0x6810, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
690 {0x1002, 0x6811, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
691 {0x1002, 0x6816, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
692 {0x1002, 0x6817, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
693 {0x1002, 0x6818, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
694 {0x1002, 0x6819, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
695 {0x1002, 0x6600, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
696 {0x1002, 0x6601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
697 {0x1002, 0x6602, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
698 {0x1002, 0x6603, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
699 {0x1002, 0x6604, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
700 {0x1002, 0x6605, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
701 {0x1002, 0x6606, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
702 {0x1002, 0x6607, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
703 {0x1002, 0x6608, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
704 {0x1002, 0x6610, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
705 {0x1002, 0x6611, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
706 {0x1002, 0x6613, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
707 {0x1002, 0x6617, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
708 {0x1002, 0x6620, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
709 {0x1002, 0x6621, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
710 {0x1002, 0x6623, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
711 {0x1002, 0x6631, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
712 {0x1002, 0x6820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
713 {0x1002, 0x6821, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
714 {0x1002, 0x6822, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
715 {0x1002, 0x6823, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
716 {0x1002, 0x6824, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
717 {0x1002, 0x6825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
718 {0x1002, 0x6826, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
719 {0x1002, 0x6827, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
720 {0x1002, 0x6828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
721 {0x1002, 0x6829, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
722 {0x1002, 0x682A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
723 {0x1002, 0x682B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
724 {0x1002, 0x682C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
725 {0x1002, 0x682D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
726 {0x1002, 0x682F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
727 {0x1002, 0x6830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
728 {0x1002, 0x6831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
729 {0x1002, 0x6835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
730 {0x1002, 0x6837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
731 {0x1002, 0x6838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
732 {0x1002, 0x6839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
733 {0x1002, 0x683B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
734 {0x1002, 0x683D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
735 {0x1002, 0x683F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
736 {0x1002, 0x6660, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
737 {0x1002, 0x6663, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
738 {0x1002, 0x6664, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
739 {0x1002, 0x6665, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
740 {0x1002, 0x6667, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
741 {0x1002, 0x666F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
742#endif
743#ifdef CONFIG_DRM_AMDGPU_CIK
744
745 {0x1002, 0x1304, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
746 {0x1002, 0x1305, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
747 {0x1002, 0x1306, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
748 {0x1002, 0x1307, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
749 {0x1002, 0x1309, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
750 {0x1002, 0x130A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
751 {0x1002, 0x130B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
752 {0x1002, 0x130C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
753 {0x1002, 0x130D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
754 {0x1002, 0x130E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
755 {0x1002, 0x130F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
756 {0x1002, 0x1310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
757 {0x1002, 0x1311, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
758 {0x1002, 0x1312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
759 {0x1002, 0x1313, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
760 {0x1002, 0x1315, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
761 {0x1002, 0x1316, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
762 {0x1002, 0x1317, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
763 {0x1002, 0x1318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
764 {0x1002, 0x131B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
765 {0x1002, 0x131C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
766 {0x1002, 0x131D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
767
768 {0x1002, 0x6640, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
769 {0x1002, 0x6641, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
770 {0x1002, 0x6646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
771 {0x1002, 0x6647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
772 {0x1002, 0x6649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
773 {0x1002, 0x6650, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
774 {0x1002, 0x6651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
775 {0x1002, 0x6658, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
776 {0x1002, 0x665c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
777 {0x1002, 0x665d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
778 {0x1002, 0x665f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
779
780 {0x1002, 0x67A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
781 {0x1002, 0x67A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
782 {0x1002, 0x67A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
783 {0x1002, 0x67A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
784 {0x1002, 0x67A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
785 {0x1002, 0x67AA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
786 {0x1002, 0x67B0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
787 {0x1002, 0x67B1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
788 {0x1002, 0x67B8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
789 {0x1002, 0x67B9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
790 {0x1002, 0x67BA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
791 {0x1002, 0x67BE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
792
793 {0x1002, 0x9830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
794 {0x1002, 0x9831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
795 {0x1002, 0x9832, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
796 {0x1002, 0x9833, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
797 {0x1002, 0x9834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
798 {0x1002, 0x9835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
799 {0x1002, 0x9836, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
800 {0x1002, 0x9837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
801 {0x1002, 0x9838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
802 {0x1002, 0x9839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
803 {0x1002, 0x983a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
804 {0x1002, 0x983b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
805 {0x1002, 0x983c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
806 {0x1002, 0x983d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
807 {0x1002, 0x983e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
808 {0x1002, 0x983f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
809
810 {0x1002, 0x9850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
811 {0x1002, 0x9851, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
812 {0x1002, 0x9852, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
813 {0x1002, 0x9853, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
814 {0x1002, 0x9854, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
815 {0x1002, 0x9855, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
816 {0x1002, 0x9856, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
817 {0x1002, 0x9857, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
818 {0x1002, 0x9858, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
819 {0x1002, 0x9859, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
820 {0x1002, 0x985A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
821 {0x1002, 0x985B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
822 {0x1002, 0x985C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
823 {0x1002, 0x985D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
824 {0x1002, 0x985E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
825 {0x1002, 0x985F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
826#endif
827
828 {0x1002, 0x6900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
829 {0x1002, 0x6901, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
830 {0x1002, 0x6902, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
831 {0x1002, 0x6903, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
832 {0x1002, 0x6907, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
833
834 {0x1002, 0x6920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
835 {0x1002, 0x6921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
836 {0x1002, 0x6928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
837 {0x1002, 0x6929, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
838 {0x1002, 0x692B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
839 {0x1002, 0x692F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
840 {0x1002, 0x6930, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
841 {0x1002, 0x6938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
842 {0x1002, 0x6939, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
843
844 {0x1002, 0x7300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI},
845 {0x1002, 0x730F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI},
846
847 {0x1002, 0x9870, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
848 {0x1002, 0x9874, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
849 {0x1002, 0x9875, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
850 {0x1002, 0x9876, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
851 {0x1002, 0x9877, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
852
853 {0x1002, 0x98E4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_STONEY|AMD_IS_APU},
854
855 {0x1002, 0x67E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
856 {0x1002, 0x67E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
857 {0x1002, 0x67E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
858 {0x1002, 0x67EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
859 {0x1002, 0x67EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
860 {0x1002, 0x67FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
861 {0x1002, 0x67E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
862 {0x1002, 0x67E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
863 {0x1002, 0x67E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
864
865 {0x1002, 0x67C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
866 {0x1002, 0x67C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
867 {0x1002, 0x67C2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
868 {0x1002, 0x67C4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
869 {0x1002, 0x67C7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
870 {0x1002, 0x67D0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
871 {0x1002, 0x67DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
872 {0x1002, 0x67C8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
873 {0x1002, 0x67C9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
874 {0x1002, 0x67CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
875 {0x1002, 0x67CC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
876 {0x1002, 0x67CF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
877 {0x1002, 0x6FDF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
878
879 {0x1002, 0x6980, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
880 {0x1002, 0x6981, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
881 {0x1002, 0x6985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
882 {0x1002, 0x6986, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
883 {0x1002, 0x6987, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
884 {0x1002, 0x6995, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
885 {0x1002, 0x6997, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
886 {0x1002, 0x699F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
887
888 {0x1002, 0x694C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM},
889 {0x1002, 0x694E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM},
890 {0x1002, 0x694F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM},
891
892 {0x1002, 0x6860, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
893 {0x1002, 0x6861, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
894 {0x1002, 0x6862, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
895 {0x1002, 0x6863, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
896 {0x1002, 0x6864, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
897 {0x1002, 0x6867, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
898 {0x1002, 0x6868, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
899 {0x1002, 0x6869, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
900 {0x1002, 0x686a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
901 {0x1002, 0x686b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
902 {0x1002, 0x686c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
903 {0x1002, 0x686d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
904 {0x1002, 0x686e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
905 {0x1002, 0x686f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
906 {0x1002, 0x687f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
907
908 {0x1002, 0x69A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
909 {0x1002, 0x69A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
910 {0x1002, 0x69A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
911 {0x1002, 0x69A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
912 {0x1002, 0x69AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
913
914 {0x1002, 0x66A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
915 {0x1002, 0x66A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
916 {0x1002, 0x66A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
917 {0x1002, 0x66A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
918 {0x1002, 0x66A4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
919 {0x1002, 0x66A7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
920 {0x1002, 0x66AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
921
922 {0x1002, 0x15dd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU},
923 {0x1002, 0x15d8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU},
924
925 {0, 0, 0}
926};
927
928MODULE_DEVICE_TABLE(pci, pciidlist);
929
930static struct drm_driver kms_driver;
931
932static int amdgpu_pci_probe(struct pci_dev *pdev,
933 const struct pci_device_id *ent)
934{
935 struct drm_device *dev;
936 unsigned long flags = ent->driver_data;
937 int ret, retry = 0;
938 bool supports_atomic = false;
939
940 if (!amdgpu_virtual_display &&
941 amdgpu_device_asic_has_dc_support(flags & AMD_ASIC_MASK))
942 supports_atomic = true;
943
944 if ((flags & AMD_EXP_HW_SUPPORT) && !amdgpu_exp_hw_support) {
945 DRM_INFO("This hardware requires experimental hardware support.\n"
946 "See modparam exp_hw_support\n");
947 return -ENODEV;
948 }
949
950
951 ret = drm_fb_helper_remove_conflicting_pci_framebuffers(pdev, 0, "amdgpudrmfb");
952 if (ret)
953 return ret;
954
955 dev = drm_dev_alloc(&kms_driver, &pdev->dev);
956 if (IS_ERR(dev))
957 return PTR_ERR(dev);
958
959 if (!supports_atomic)
960 dev->driver_features &= ~DRIVER_ATOMIC;
961
962 ret = pci_enable_device(pdev);
963 if (ret)
964 goto err_free;
965
966 dev->pdev = pdev;
967
968 pci_set_drvdata(pdev, dev);
969
970retry_init:
971 ret = drm_dev_register(dev, ent->driver_data);
972 if (ret == -EAGAIN && ++retry <= 3) {
973 DRM_INFO("retry init %d\n", retry);
974
975 msleep(5000);
976 goto retry_init;
977 } else if (ret)
978 goto err_pci;
979
980 return 0;
981
982err_pci:
983 pci_disable_device(pdev);
984err_free:
985 drm_dev_put(dev);
986 return ret;
987}
988
989static void
990amdgpu_pci_remove(struct pci_dev *pdev)
991{
992 struct drm_device *dev = pci_get_drvdata(pdev);
993
994 DRM_ERROR("Device removal is currently not supported outside of fbcon\n");
995 drm_dev_unplug(dev);
996 drm_dev_put(dev);
997 pci_disable_device(pdev);
998 pci_set_drvdata(pdev, NULL);
999}
1000
1001static void
1002amdgpu_pci_shutdown(struct pci_dev *pdev)
1003{
1004 struct drm_device *dev = pci_get_drvdata(pdev);
1005 struct amdgpu_device *adev = dev->dev_private;
1006
1007
1008
1009
1010
1011
1012 amdgpu_device_ip_suspend(adev);
1013}
1014
1015static int amdgpu_pmops_suspend(struct device *dev)
1016{
1017 struct pci_dev *pdev = to_pci_dev(dev);
1018
1019 struct drm_device *drm_dev = pci_get_drvdata(pdev);
1020 return amdgpu_device_suspend(drm_dev, true, true);
1021}
1022
1023static int amdgpu_pmops_resume(struct device *dev)
1024{
1025 struct pci_dev *pdev = to_pci_dev(dev);
1026 struct drm_device *drm_dev = pci_get_drvdata(pdev);
1027
1028
1029 if (amdgpu_device_is_px(drm_dev)) {
1030 pm_runtime_disable(dev);
1031 pm_runtime_set_active(dev);
1032 pm_runtime_enable(dev);
1033 }
1034
1035 return amdgpu_device_resume(drm_dev, true, true);
1036}
1037
1038static int amdgpu_pmops_freeze(struct device *dev)
1039{
1040 struct pci_dev *pdev = to_pci_dev(dev);
1041
1042 struct drm_device *drm_dev = pci_get_drvdata(pdev);
1043 return amdgpu_device_suspend(drm_dev, false, true);
1044}
1045
1046static int amdgpu_pmops_thaw(struct device *dev)
1047{
1048 struct pci_dev *pdev = to_pci_dev(dev);
1049
1050 struct drm_device *drm_dev = pci_get_drvdata(pdev);
1051 return amdgpu_device_resume(drm_dev, false, true);
1052}
1053
1054static int amdgpu_pmops_poweroff(struct device *dev)
1055{
1056 struct pci_dev *pdev = to_pci_dev(dev);
1057
1058 struct drm_device *drm_dev = pci_get_drvdata(pdev);
1059 return amdgpu_device_suspend(drm_dev, true, true);
1060}
1061
1062static int amdgpu_pmops_restore(struct device *dev)
1063{
1064 struct pci_dev *pdev = to_pci_dev(dev);
1065
1066 struct drm_device *drm_dev = pci_get_drvdata(pdev);
1067 return amdgpu_device_resume(drm_dev, false, true);
1068}
1069
1070static int amdgpu_pmops_runtime_suspend(struct device *dev)
1071{
1072 struct pci_dev *pdev = to_pci_dev(dev);
1073 struct drm_device *drm_dev = pci_get_drvdata(pdev);
1074 int ret;
1075
1076 if (!amdgpu_device_is_px(drm_dev)) {
1077 pm_runtime_forbid(dev);
1078 return -EBUSY;
1079 }
1080
1081 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1082 drm_kms_helper_poll_disable(drm_dev);
1083
1084 ret = amdgpu_device_suspend(drm_dev, false, false);
1085 pci_save_state(pdev);
1086 pci_disable_device(pdev);
1087 pci_ignore_hotplug(pdev);
1088 if (amdgpu_is_atpx_hybrid())
1089 pci_set_power_state(pdev, PCI_D3cold);
1090 else if (!amdgpu_has_atpx_dgpu_power_cntl())
1091 pci_set_power_state(pdev, PCI_D3hot);
1092 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF;
1093
1094 return 0;
1095}
1096
1097static int amdgpu_pmops_runtime_resume(struct device *dev)
1098{
1099 struct pci_dev *pdev = to_pci_dev(dev);
1100 struct drm_device *drm_dev = pci_get_drvdata(pdev);
1101 int ret;
1102
1103 if (!amdgpu_device_is_px(drm_dev))
1104 return -EINVAL;
1105
1106 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1107
1108 if (amdgpu_is_atpx_hybrid() ||
1109 !amdgpu_has_atpx_dgpu_power_cntl())
1110 pci_set_power_state(pdev, PCI_D0);
1111 pci_restore_state(pdev);
1112 ret = pci_enable_device(pdev);
1113 if (ret)
1114 return ret;
1115 pci_set_master(pdev);
1116
1117 ret = amdgpu_device_resume(drm_dev, false, false);
1118 drm_kms_helper_poll_enable(drm_dev);
1119 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON;
1120 return 0;
1121}
1122
1123static int amdgpu_pmops_runtime_idle(struct device *dev)
1124{
1125 struct pci_dev *pdev = to_pci_dev(dev);
1126 struct drm_device *drm_dev = pci_get_drvdata(pdev);
1127 struct drm_crtc *crtc;
1128
1129 if (!amdgpu_device_is_px(drm_dev)) {
1130 pm_runtime_forbid(dev);
1131 return -EBUSY;
1132 }
1133
1134 list_for_each_entry(crtc, &drm_dev->mode_config.crtc_list, head) {
1135 if (crtc->enabled) {
1136 DRM_DEBUG_DRIVER("failing to power off - crtc active\n");
1137 return -EBUSY;
1138 }
1139 }
1140
1141 pm_runtime_mark_last_busy(dev);
1142 pm_runtime_autosuspend(dev);
1143
1144 return 1;
1145}
1146
1147long amdgpu_drm_ioctl(struct file *filp,
1148 unsigned int cmd, unsigned long arg)
1149{
1150 struct drm_file *file_priv = filp->private_data;
1151 struct drm_device *dev;
1152 long ret;
1153 dev = file_priv->minor->dev;
1154 ret = pm_runtime_get_sync(dev->dev);
1155 if (ret < 0)
1156 return ret;
1157
1158 ret = drm_ioctl(filp, cmd, arg);
1159
1160 pm_runtime_mark_last_busy(dev->dev);
1161 pm_runtime_put_autosuspend(dev->dev);
1162 return ret;
1163}
1164
1165static const struct dev_pm_ops amdgpu_pm_ops = {
1166 .suspend = amdgpu_pmops_suspend,
1167 .resume = amdgpu_pmops_resume,
1168 .freeze = amdgpu_pmops_freeze,
1169 .thaw = amdgpu_pmops_thaw,
1170 .poweroff = amdgpu_pmops_poweroff,
1171 .restore = amdgpu_pmops_restore,
1172 .runtime_suspend = amdgpu_pmops_runtime_suspend,
1173 .runtime_resume = amdgpu_pmops_runtime_resume,
1174 .runtime_idle = amdgpu_pmops_runtime_idle,
1175};
1176
1177static int amdgpu_flush(struct file *f, fl_owner_t id)
1178{
1179 struct drm_file *file_priv = f->private_data;
1180 struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
1181 long timeout = MAX_WAIT_SCHED_ENTITY_Q_EMPTY;
1182
1183 timeout = amdgpu_ctx_mgr_entity_flush(&fpriv->ctx_mgr, timeout);
1184 timeout = amdgpu_vm_wait_idle(&fpriv->vm, timeout);
1185
1186 return timeout >= 0 ? 0 : timeout;
1187}
1188
1189static const struct file_operations amdgpu_driver_kms_fops = {
1190 .owner = THIS_MODULE,
1191 .open = drm_open,
1192 .flush = amdgpu_flush,
1193 .release = drm_release,
1194 .unlocked_ioctl = amdgpu_drm_ioctl,
1195 .mmap = amdgpu_mmap,
1196 .poll = drm_poll,
1197 .read = drm_read,
1198#ifdef CONFIG_COMPAT
1199 .compat_ioctl = amdgpu_kms_compat_ioctl,
1200#endif
1201};
1202
1203int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv)
1204{
1205 struct drm_file *file;
1206
1207 if (!filp)
1208 return -EINVAL;
1209
1210 if (filp->f_op != &amdgpu_driver_kms_fops) {
1211 return -EINVAL;
1212 }
1213
1214 file = filp->private_data;
1215 *fpriv = file->driver_priv;
1216 return 0;
1217}
1218
1219static bool
1220amdgpu_get_crtc_scanout_position(struct drm_device *dev, unsigned int pipe,
1221 bool in_vblank_irq, int *vpos, int *hpos,
1222 ktime_t *stime, ktime_t *etime,
1223 const struct drm_display_mode *mode)
1224{
1225 return amdgpu_display_get_crtc_scanoutpos(dev, pipe, 0, vpos, hpos,
1226 stime, etime, mode);
1227}
1228
1229static struct drm_driver kms_driver = {
1230 .driver_features =
1231 DRIVER_USE_AGP | DRIVER_ATOMIC |
1232 DRIVER_GEM |
1233 DRIVER_PRIME | DRIVER_RENDER | DRIVER_MODESET | DRIVER_SYNCOBJ,
1234 .load = amdgpu_driver_load_kms,
1235 .open = amdgpu_driver_open_kms,
1236 .postclose = amdgpu_driver_postclose_kms,
1237 .lastclose = amdgpu_driver_lastclose_kms,
1238 .unload = amdgpu_driver_unload_kms,
1239 .get_vblank_counter = amdgpu_get_vblank_counter_kms,
1240 .enable_vblank = amdgpu_enable_vblank_kms,
1241 .disable_vblank = amdgpu_disable_vblank_kms,
1242 .get_vblank_timestamp = drm_calc_vbltimestamp_from_scanoutpos,
1243 .get_scanout_position = amdgpu_get_crtc_scanout_position,
1244 .irq_handler = amdgpu_irq_handler,
1245 .ioctls = amdgpu_ioctls_kms,
1246 .gem_free_object_unlocked = amdgpu_gem_object_free,
1247 .gem_open_object = amdgpu_gem_object_open,
1248 .gem_close_object = amdgpu_gem_object_close,
1249 .dumb_create = amdgpu_mode_dumb_create,
1250 .dumb_map_offset = amdgpu_mode_dumb_mmap,
1251 .fops = &amdgpu_driver_kms_fops,
1252
1253 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
1254 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
1255 .gem_prime_export = amdgpu_gem_prime_export,
1256 .gem_prime_import = amdgpu_gem_prime_import,
1257 .gem_prime_res_obj = amdgpu_gem_prime_res_obj,
1258 .gem_prime_get_sg_table = amdgpu_gem_prime_get_sg_table,
1259 .gem_prime_import_sg_table = amdgpu_gem_prime_import_sg_table,
1260 .gem_prime_vmap = amdgpu_gem_prime_vmap,
1261 .gem_prime_vunmap = amdgpu_gem_prime_vunmap,
1262 .gem_prime_mmap = amdgpu_gem_prime_mmap,
1263
1264 .name = DRIVER_NAME,
1265 .desc = DRIVER_DESC,
1266 .date = DRIVER_DATE,
1267 .major = KMS_DRIVER_MAJOR,
1268 .minor = KMS_DRIVER_MINOR,
1269 .patchlevel = KMS_DRIVER_PATCHLEVEL,
1270};
1271
1272static struct pci_driver amdgpu_kms_pci_driver = {
1273 .name = DRIVER_NAME,
1274 .id_table = pciidlist,
1275 .probe = amdgpu_pci_probe,
1276 .remove = amdgpu_pci_remove,
1277 .shutdown = amdgpu_pci_shutdown,
1278 .driver.pm = &amdgpu_pm_ops,
1279};
1280
1281
1282
1283static int __init amdgpu_init(void)
1284{
1285 int r;
1286
1287 if (vgacon_text_force()) {
1288 DRM_ERROR("VGACON disables amdgpu kernel modesetting.\n");
1289 return -EINVAL;
1290 }
1291
1292 r = amdgpu_sync_init();
1293 if (r)
1294 goto error_sync;
1295
1296 r = amdgpu_fence_slab_init();
1297 if (r)
1298 goto error_fence;
1299
1300 DRM_INFO("amdgpu kernel modesetting enabled.\n");
1301 kms_driver.num_ioctls = amdgpu_max_kms_ioctl;
1302 amdgpu_register_atpx_handler();
1303
1304
1305 amdgpu_amdkfd_init();
1306
1307
1308 return pci_register_driver(&amdgpu_kms_pci_driver);
1309
1310error_fence:
1311 amdgpu_sync_fini();
1312
1313error_sync:
1314 return r;
1315}
1316
1317static void __exit amdgpu_exit(void)
1318{
1319 amdgpu_amdkfd_fini();
1320 pci_unregister_driver(&amdgpu_kms_pci_driver);
1321 amdgpu_unregister_atpx_handler();
1322 amdgpu_sync_fini();
1323 amdgpu_fence_slab_fini();
1324}
1325
1326module_init(amdgpu_init);
1327module_exit(amdgpu_exit);
1328
1329MODULE_AUTHOR(DRIVER_AUTHOR);
1330MODULE_DESCRIPTION(DRIVER_DESC);
1331MODULE_LICENSE("GPL and additional rights");
1332