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26#ifndef __AMDGPU_DM_H__
27#define __AMDGPU_DM_H__
28
29#include <drm/drmP.h>
30#include <drm/drm_atomic.h>
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41
42#define AMDGPU_DM_MAX_DISPLAY_INDEX 31
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47
48#include "irq_types.h"
49#include "signal_types.h"
50
51
52struct amdgpu_device;
53struct drm_device;
54struct amdgpu_dm_irq_handler_data;
55struct dc;
56
57struct common_irq_params {
58 struct amdgpu_device *adev;
59 enum dc_irq_source irq_src;
60};
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66
67
68struct irq_list_head {
69 struct list_head head;
70
71 struct work_struct work;
72};
73
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79
80struct dm_comressor_info {
81 void *cpu_addr;
82 struct amdgpu_bo *bo_ptr;
83 uint64_t gpu_addr;
84};
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90
91
92struct amdgpu_dm_backlight_caps {
93 int min_input_signal;
94 int max_input_signal;
95 bool caps_valid;
96};
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109
110struct amdgpu_display_manager {
111
112 struct dc *dc;
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120 struct cgs_device *cgs_device;
121
122 struct amdgpu_device *adev;
123 struct drm_device *ddev;
124 u16 display_indexes_num;
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132
133 struct drm_private_obj atomic_obj;
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141 struct mutex dc_lock;
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155 struct irq_list_head irq_handler_list_low_tab[DAL_IRQ_SOURCES_NUMBER];
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164
165 struct list_head irq_handler_list_high_tab[DAL_IRQ_SOURCES_NUMBER];
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172
173 struct common_irq_params
174 pflip_params[DC_IRQ_SOURCE_PFLIP_LAST - DC_IRQ_SOURCE_PFLIP_FIRST + 1];
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181
182 struct common_irq_params
183 vblank_params[DC_IRQ_SOURCE_VBLANK6 - DC_IRQ_SOURCE_VBLANK1 + 1];
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190
191 struct common_irq_params
192 vupdate_params[DC_IRQ_SOURCE_VUPDATE6 - DC_IRQ_SOURCE_VUPDATE1 + 1];
193
194 spinlock_t irq_handler_list_table_lock;
195
196 struct backlight_device *backlight_dev;
197
198 const struct dc_link *backlight_link;
199 struct amdgpu_dm_backlight_caps backlight_caps;
200
201 struct mod_freesync *freesync_module;
202
203 struct drm_atomic_state *cached_state;
204
205 struct dm_comressor_info compressor;
206
207 const struct firmware *fw_dmcu;
208 uint32_t dmcu_fw_version;
209};
210
211struct amdgpu_dm_connector {
212
213 struct drm_connector base;
214 uint32_t connector_id;
215
216
217
218 struct edid *edid;
219
220
221 struct amdgpu_hpd hpd;
222
223
224 int num_modes;
225
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227
228 struct dc_sink *dc_sink;
229 struct dc_link *dc_link;
230 struct dc_sink *dc_em_sink;
231
232
233 struct drm_dp_mst_topology_mgr mst_mgr;
234 struct amdgpu_dm_dp_aux dm_dp_aux;
235 struct drm_dp_mst_port *port;
236 struct amdgpu_dm_connector *mst_port;
237 struct amdgpu_encoder *mst_encoder;
238
239
240 struct amdgpu_i2c_adapter *i2c;
241
242
243 int min_vfreq ;
244 int max_vfreq ;
245 int pixel_clock_mhz;
246
247 struct mutex hpd_lock;
248
249 bool fake_enable;
250#ifdef CONFIG_DEBUG_FS
251 uint32_t debugfs_dpcd_address;
252 uint32_t debugfs_dpcd_size;
253#endif
254};
255
256#define to_amdgpu_dm_connector(x) container_of(x, struct amdgpu_dm_connector, base)
257
258extern const struct amdgpu_ip_block_version dm_ip_block;
259
260struct amdgpu_framebuffer;
261struct amdgpu_display_manager;
262struct dc_validation_set;
263struct dc_plane_state;
264
265struct dm_plane_state {
266 struct drm_plane_state base;
267 struct dc_plane_state *dc_state;
268};
269
270struct dm_crtc_state {
271 struct drm_crtc_state base;
272 struct dc_stream_state *stream;
273
274 int active_planes;
275 bool interrupts_enabled;
276
277 int crc_skip_count;
278 bool crc_enabled;
279
280 bool freesync_timing_changed;
281 bool freesync_vrr_info_changed;
282
283 bool vrr_supported;
284 struct mod_freesync_config freesync_config;
285 struct mod_vrr_params vrr_params;
286 struct dc_info_packet vrr_infopacket;
287
288 int abm_level;
289};
290
291#define to_dm_crtc_state(x) container_of(x, struct dm_crtc_state, base)
292
293struct dm_atomic_state {
294 struct drm_private_state base;
295
296 struct dc_state *context;
297};
298
299#define to_dm_atomic_state(x) container_of(x, struct dm_atomic_state, base)
300
301struct dm_connector_state {
302 struct drm_connector_state base;
303
304 enum amdgpu_rmx_type scaling;
305 uint8_t underscan_vborder;
306 uint8_t underscan_hborder;
307 uint8_t max_bpc;
308 bool underscan_enable;
309 bool freesync_capable;
310 uint8_t abm_level;
311};
312
313#define to_dm_connector_state(x)\
314 container_of((x), struct dm_connector_state, base)
315
316void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector);
317struct drm_connector_state *
318amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector);
319int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector,
320 struct drm_connector_state *state,
321 struct drm_property *property,
322 uint64_t val);
323
324int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector,
325 const struct drm_connector_state *state,
326 struct drm_property *property,
327 uint64_t *val);
328
329int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev);
330
331void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm,
332 struct amdgpu_dm_connector *aconnector,
333 int connector_type,
334 struct dc_link *link,
335 int link_index);
336
337enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector,
338 struct drm_display_mode *mode);
339
340void dm_restore_drm_connector_state(struct drm_device *dev,
341 struct drm_connector *connector);
342
343void amdgpu_dm_update_freesync_caps(struct drm_connector *connector,
344 struct edid *edid);
345
346
347#ifdef CONFIG_DEBUG_FS
348int amdgpu_dm_crtc_set_crc_source(struct drm_crtc *crtc, const char *src_name);
349int amdgpu_dm_crtc_verify_crc_source(struct drm_crtc *crtc,
350 const char *src_name,
351 size_t *values_cnt);
352void amdgpu_dm_crtc_handle_crc_irq(struct drm_crtc *crtc);
353#else
354#define amdgpu_dm_crtc_set_crc_source NULL
355#define amdgpu_dm_crtc_verify_crc_source NULL
356#define amdgpu_dm_crtc_handle_crc_irq(x)
357#endif
358
359#define MAX_COLOR_LUT_ENTRIES 4096
360
361#define MAX_COLOR_LEGACY_LUT_ENTRIES 256
362
363void amdgpu_dm_init_color_mod(void);
364int amdgpu_dm_set_degamma_lut(struct drm_crtc_state *crtc_state,
365 struct dc_plane_state *dc_plane_state);
366void amdgpu_dm_set_ctm(struct dm_crtc_state *crtc);
367int amdgpu_dm_set_regamma_lut(struct dm_crtc_state *crtc);
368
369extern const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs;
370
371#endif
372