LXR linux/drivers/gpu/drm/amd/display/dc/dm_services

   1/*
   2 * Copyright 2012-15 Advanced Micro Devices, Inc.
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the "Software"),
   6 * to deal in the Software without restriction, including without limitation
   7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8 * and/or sell copies of the Software, and to permit persons to whom the
   9 * Software is furnished to do so, subject to the following conditions:
  10 *
  11 * The above copyright notice and this permission notice shall be included in
  12 * all copies or substantial portions of the Software.
  13 *
  14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20 * OTHER DEALINGS IN THE SOFTWARE.
  21 *
  22 * Authors: AMD
  23 *
  24 */
  25
  26#ifndef __DM_SERVICES_TYPES_H__
  27#define __DM_SERVICES_TYPES_H__
  28
  29#include "os_types.h"
  30#include "dc_types.h"
  31
  32struct pp_smu_funcs;
  33
  34struct dm_pp_clock_range {
  35        int min_khz;
  36        int max_khz;
  37};
  38
  39enum dm_pp_clocks_state {
  40        DM_PP_CLOCKS_STATE_INVALID,
  41        DM_PP_CLOCKS_STATE_ULTRA_LOW,
  42        DM_PP_CLOCKS_STATE_LOW,
  43        DM_PP_CLOCKS_STATE_NOMINAL,
  44        DM_PP_CLOCKS_STATE_PERFORMANCE,
  45
  46        /* Starting from DCE11, Max 8 levels of DPM state supported. */
  47        DM_PP_CLOCKS_DPM_STATE_LEVEL_INVALID = DM_PP_CLOCKS_STATE_INVALID,
  48        DM_PP_CLOCKS_DPM_STATE_LEVEL_0,
  49        DM_PP_CLOCKS_DPM_STATE_LEVEL_1,
  50        DM_PP_CLOCKS_DPM_STATE_LEVEL_2,
  51        /* to be backward compatible */
  52        DM_PP_CLOCKS_DPM_STATE_LEVEL_3,
  53        DM_PP_CLOCKS_DPM_STATE_LEVEL_4,
  54        DM_PP_CLOCKS_DPM_STATE_LEVEL_5,
  55        DM_PP_CLOCKS_DPM_STATE_LEVEL_6,
  56        DM_PP_CLOCKS_DPM_STATE_LEVEL_7,
  57
  58        DM_PP_CLOCKS_MAX_STATES
  59};
  60
  61struct dm_pp_gpu_clock_range {
  62        enum dm_pp_clocks_state clock_state;
  63        struct dm_pp_clock_range sclk;
  64        struct dm_pp_clock_range mclk;
  65        struct dm_pp_clock_range eclk;
  66        struct dm_pp_clock_range dclk;
  67};
  68
  69enum dm_pp_clock_type {
  70        DM_PP_CLOCK_TYPE_DISPLAY_CLK = 1,
  71        DM_PP_CLOCK_TYPE_ENGINE_CLK, /* System clock */
  72        DM_PP_CLOCK_TYPE_MEMORY_CLK,
  73        DM_PP_CLOCK_TYPE_DCFCLK,
  74        DM_PP_CLOCK_TYPE_DCEFCLK,
  75        DM_PP_CLOCK_TYPE_SOCCLK,
  76        DM_PP_CLOCK_TYPE_PIXELCLK,
  77        DM_PP_CLOCK_TYPE_DISPLAYPHYCLK,
  78        DM_PP_CLOCK_TYPE_DPPCLK,
  79        DM_PP_CLOCK_TYPE_FCLK,
  80};
  81
  82#define DC_DECODE_PP_CLOCK_TYPE(clk_type) \
  83        (clk_type) == DM_PP_CLOCK_TYPE_DISPLAY_CLK ? "Display" : \
  84        (clk_type) == DM_PP_CLOCK_TYPE_ENGINE_CLK ? "Engine" : \
  85        (clk_type) == DM_PP_CLOCK_TYPE_MEMORY_CLK ? "Memory" : \
  86        (clk_type) == DM_PP_CLOCK_TYPE_DCFCLK ? "DCF" : \
  87        (clk_type) == DM_PP_CLOCK_TYPE_DCEFCLK ? "DCEF" : \
  88        (clk_type) == DM_PP_CLOCK_TYPE_SOCCLK ? "SoC" : \
  89        (clk_type) == DM_PP_CLOCK_TYPE_PIXELCLK ? "Pixel" : \
  90        (clk_type) == DM_PP_CLOCK_TYPE_DISPLAYPHYCLK ? "Display PHY" : \
  91        (clk_type) == DM_PP_CLOCK_TYPE_DPPCLK ? "DPP" : \
  92        (clk_type) == DM_PP_CLOCK_TYPE_FCLK ? "F" : \
  93        "Invalid"
  94
  95#define DM_PP_MAX_CLOCK_LEVELS 16
  96
  97struct dm_pp_clock_levels {
  98        uint32_t num_levels;
  99        uint32_t clocks_in_khz[DM_PP_MAX_CLOCK_LEVELS];
 100};
 101
 102struct dm_pp_clock_with_latency {
 103        uint32_t clocks_in_khz;
 104        uint32_t latency_in_us;
 105};
 106
 107struct dm_pp_clock_levels_with_latency {
 108        uint32_t num_levels;
 109        struct dm_pp_clock_with_latency data[DM_PP_MAX_CLOCK_LEVELS];
 110};
 111
 112struct dm_pp_clock_with_voltage {
 113        uint32_t clocks_in_khz;
 114        uint32_t voltage_in_mv;
 115};
 116
 117struct dm_pp_clock_levels_with_voltage {
 118        uint32_t num_levels;
 119        struct dm_pp_clock_with_voltage data[DM_PP_MAX_CLOCK_LEVELS];
 120};
 121
 122struct dm_pp_single_disp_config {
 123        enum signal_type signal;
 124        uint8_t transmitter;
 125        uint8_t ddi_channel_mapping;
 126        uint8_t pipe_idx;
 127        uint32_t src_height;
 128        uint32_t src_width;
 129        uint32_t v_refresh;
 130        uint32_t sym_clock; /* HDMI only */
 131        struct dc_link_settings link_settings; /* DP only */
 132};
 133
 134#define MAX_WM_SETS 4
 135
 136enum dm_pp_wm_set_id {
 137        WM_SET_A = 0,
 138        WM_SET_B,
 139        WM_SET_C,
 140        WM_SET_D,
 141        WM_SET_INVALID = 0xffff,
 142};
 143
 144struct dm_pp_clock_range_for_wm_set {
 145        enum dm_pp_wm_set_id wm_set_id;
 146        uint32_t wm_min_eng_clk_in_khz;
 147        uint32_t wm_max_eng_clk_in_khz;
 148        uint32_t wm_min_mem_clk_in_khz;
 149        uint32_t wm_max_mem_clk_in_khz;
 150};
 151
 152struct dm_pp_wm_sets_with_clock_ranges {
 153        uint32_t num_wm_sets;
 154        struct dm_pp_clock_range_for_wm_set wm_clk_ranges[MAX_WM_SETS];
 155};
 156
 157struct dm_pp_clock_range_for_dmif_wm_set_soc15 {
 158        enum dm_pp_wm_set_id wm_set_id;
 159        uint32_t wm_min_dcfclk_clk_in_khz;
 160        uint32_t wm_max_dcfclk_clk_in_khz;
 161        uint32_t wm_min_mem_clk_in_khz;
 162        uint32_t wm_max_mem_clk_in_khz;
 163};
 164
 165struct dm_pp_clock_range_for_mcif_wm_set_soc15 {
 166        enum dm_pp_wm_set_id wm_set_id;
 167        uint32_t wm_min_socclk_clk_in_khz;
 168        uint32_t wm_max_socclk_clk_in_khz;
 169        uint32_t wm_min_mem_clk_in_khz;
 170        uint32_t wm_max_mem_clk_in_khz;
 171};
 172
 173struct dm_pp_wm_sets_with_clock_ranges_soc15 {
 174        uint32_t num_wm_dmif_sets;
 175        uint32_t num_wm_mcif_sets;
 176        struct dm_pp_clock_range_for_dmif_wm_set_soc15
 177                wm_dmif_clocks_ranges[MAX_WM_SETS];
 178        struct dm_pp_clock_range_for_mcif_wm_set_soc15
 179                wm_mcif_clocks_ranges[MAX_WM_SETS];
 180};
 181
 182#define MAX_DISPLAY_CONFIGS 6
 183
 184struct dm_pp_display_configuration {
 185        bool nb_pstate_switch_disable;/* controls NB PState switch */
 186        bool cpu_cc6_disable; /* controls CPU CState switch ( on or off) */
 187        bool cpu_pstate_disable;
 188        uint32_t cpu_pstate_separation_time;
 189
 190        uint32_t min_memory_clock_khz;
 191        uint32_t min_engine_clock_khz;
 192        uint32_t min_engine_clock_deep_sleep_khz;
 193
 194        uint32_t avail_mclk_switch_time_us;
 195        uint32_t avail_mclk_switch_time_in_disp_active_us;
 196        uint32_t min_dcfclock_khz;
 197        uint32_t min_dcfc_deep_sleep_clock_khz;
 198
 199        uint32_t disp_clk_khz;
 200
 201        bool all_displays_in_sync;
 202
 203        uint8_t display_count;
 204        struct dm_pp_single_disp_config disp_configs[MAX_DISPLAY_CONFIGS];
 205
 206        /*Controller Index of primary display - used in MCLK SMC switching hang
 207         * SW Workaround*/
 208        uint8_t crtc_index;
 209        /*htotal*1000/pixelclk - used in MCLK SMC switching hang SW Workaround*/
 210        uint32_t line_time_in_us;
 211};
 212
 213struct dm_bl_data_point {
 214                /* Brightness level in percentage */
 215                uint8_t luminance;
 216                /* Brightness level as effective value in range 0-255,
 217                 * corresponding to above percentage
 218                 */
 219                uint8_t signal_level;
 220};
 221
 222/* Total size of the structure should not exceed 256 bytes */
 223struct dm_acpi_atif_backlight_caps {
 224        uint16_t size; /* Bytes 0-1 (2 bytes) */
 225        uint16_t flags; /* Byted 2-3 (2 bytes) */
 226        uint8_t  error_code; /* Byte 4 */
 227        uint8_t  ac_level_percentage; /* Byte 5 */
 228        uint8_t  dc_level_percentage; /* Byte 6 */
 229        uint8_t  min_input_signal; /* Byte 7 */
 230        uint8_t  max_input_signal; /* Byte 8 */
 231        uint8_t  num_data_points; /* Byte 9 */
 232        struct dm_bl_data_point data_points[99]; /* Bytes 10-207 (198 bytes)*/
 233};
 234
 235enum dm_acpi_display_type {
 236        AcpiDisplayType_LCD1 = 0,
 237        AcpiDisplayType_CRT1 = 1,
 238        AcpiDisplayType_DFP1 = 3,
 239        AcpiDisplayType_CRT2 = 4,
 240        AcpiDisplayType_LCD2 = 5,
 241        AcpiDisplayType_DFP2 = 7,
 242        AcpiDisplayType_DFP3 = 9,
 243        AcpiDisplayType_DFP4 = 10,
 244        AcpiDisplayType_DFP5 = 11,
 245        AcpiDisplayType_DFP6 = 12
 246};
 247
 248struct dm_pp_power_level_change_request {
 249        enum dm_pp_clocks_state power_level;
 250};
 251
 252struct dm_pp_clock_for_voltage_req {
 253        enum dm_pp_clock_type clk_type;
 254        uint32_t clocks_in_khz;
 255};
 256
 257struct dm_pp_static_clock_info {
 258        uint32_t max_sclk_khz;
 259        uint32_t max_mclk_khz;
 260
 261        /* max possible display block clocks state */
 262        enum dm_pp_clocks_state max_clocks_state;
 263};
 264
 265struct dtn_min_clk_info {
 266        uint32_t disp_clk_khz;
 267        uint32_t min_engine_clock_khz;
 268        uint32_t min_memory_clock_khz;
 269};
 270
 271#endif
 272