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8#include <linux/delay.h>
9#include <linux/err.h>
10#include <linux/interrupt.h>
11#include <linux/i2c.h>
12#include <linux/kernel.h>
13#include <linux/module.h>
14#include <linux/of_gpio.h>
15#include <linux/of_irq.h>
16#include <linux/of_platform.h>
17#include <linux/regmap.h>
18#include <linux/types.h>
19#include <linux/gpio/consumer.h>
20#include <linux/regulator/consumer.h>
21
22#include <drm/drmP.h>
23#include <drm/drm_atomic_helper.h>
24#include <drm/drm_crtc.h>
25#include <drm/drm_dp_helper.h>
26#include <drm/drm_edid.h>
27#include <drm/drm_probe_helper.h>
28
29#include "analogix-anx78xx.h"
30
31#define I2C_NUM_ADDRESSES 5
32#define I2C_IDX_TX_P0 0
33#define I2C_IDX_TX_P1 1
34#define I2C_IDX_TX_P2 2
35#define I2C_IDX_RX_P0 3
36#define I2C_IDX_RX_P1 4
37
38#define XTAL_CLK 270
39#define AUX_CH_BUFFER_SIZE 16
40#define AUX_WAIT_TIMEOUT_MS 15
41
42static const u8 anx78xx_i2c_addresses[] = {
43 [I2C_IDX_TX_P0] = TX_P0,
44 [I2C_IDX_TX_P1] = TX_P1,
45 [I2C_IDX_TX_P2] = TX_P2,
46 [I2C_IDX_RX_P0] = RX_P0,
47 [I2C_IDX_RX_P1] = RX_P1,
48};
49
50struct anx78xx_platform_data {
51 struct regulator *dvdd10;
52 struct gpio_desc *gpiod_hpd;
53 struct gpio_desc *gpiod_pd;
54 struct gpio_desc *gpiod_reset;
55
56 int hpd_irq;
57 int intp_irq;
58};
59
60struct anx78xx {
61 struct drm_dp_aux aux;
62 struct drm_bridge bridge;
63 struct i2c_client *client;
64 struct edid *edid;
65 struct drm_connector connector;
66 struct drm_dp_link link;
67 struct anx78xx_platform_data pdata;
68 struct mutex lock;
69
70
71
72
73
74 struct i2c_client *i2c_dummy[I2C_NUM_ADDRESSES];
75 struct regmap *map[I2C_NUM_ADDRESSES];
76
77 u16 chipid;
78 u8 dpcd[DP_RECEIVER_CAP_SIZE];
79
80 bool powered;
81};
82
83static inline struct anx78xx *connector_to_anx78xx(struct drm_connector *c)
84{
85 return container_of(c, struct anx78xx, connector);
86}
87
88static inline struct anx78xx *bridge_to_anx78xx(struct drm_bridge *bridge)
89{
90 return container_of(bridge, struct anx78xx, bridge);
91}
92
93static int anx78xx_set_bits(struct regmap *map, u8 reg, u8 mask)
94{
95 return regmap_update_bits(map, reg, mask, mask);
96}
97
98static int anx78xx_clear_bits(struct regmap *map, u8 reg, u8 mask)
99{
100 return regmap_update_bits(map, reg, mask, 0);
101}
102
103static bool anx78xx_aux_op_finished(struct anx78xx *anx78xx)
104{
105 unsigned int value;
106 int err;
107
108 err = regmap_read(anx78xx->map[I2C_IDX_TX_P0], SP_DP_AUX_CH_CTRL2_REG,
109 &value);
110 if (err < 0)
111 return false;
112
113 return (value & SP_AUX_EN) == 0;
114}
115
116static int anx78xx_aux_wait(struct anx78xx *anx78xx)
117{
118 unsigned long timeout;
119 unsigned int status;
120 int err;
121
122 timeout = jiffies + msecs_to_jiffies(AUX_WAIT_TIMEOUT_MS) + 1;
123
124 while (!anx78xx_aux_op_finished(anx78xx)) {
125 if (time_after(jiffies, timeout)) {
126 if (!anx78xx_aux_op_finished(anx78xx)) {
127 DRM_ERROR("Timed out waiting AUX to finish\n");
128 return -ETIMEDOUT;
129 }
130
131 break;
132 }
133
134 usleep_range(1000, 2000);
135 }
136
137
138 err = regmap_read(anx78xx->map[I2C_IDX_TX_P0], SP_AUX_CH_STATUS_REG,
139 &status);
140 if (err < 0) {
141 DRM_ERROR("Failed to read from AUX channel: %d\n", err);
142 return err;
143 }
144
145 if (status & SP_AUX_STATUS) {
146 DRM_ERROR("Failed to wait for AUX channel (status: %02x)\n",
147 status);
148 return -ETIMEDOUT;
149 }
150
151 return 0;
152}
153
154static int anx78xx_aux_address(struct anx78xx *anx78xx, unsigned int addr)
155{
156 int err;
157
158 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0], SP_AUX_ADDR_7_0_REG,
159 addr & 0xff);
160 if (err)
161 return err;
162
163 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0], SP_AUX_ADDR_15_8_REG,
164 (addr & 0xff00) >> 8);
165 if (err)
166 return err;
167
168
169
170
171
172
173 err = regmap_update_bits(anx78xx->map[I2C_IDX_TX_P0],
174 SP_AUX_ADDR_19_16_REG,
175 SP_AUX_ADDR_19_16_MASK,
176 (addr & 0xf0000) >> 16);
177
178 if (err)
179 return err;
180
181 return 0;
182}
183
184static ssize_t anx78xx_aux_transfer(struct drm_dp_aux *aux,
185 struct drm_dp_aux_msg *msg)
186{
187 struct anx78xx *anx78xx = container_of(aux, struct anx78xx, aux);
188 u8 ctrl1 = msg->request;
189 u8 ctrl2 = SP_AUX_EN;
190 u8 *buffer = msg->buffer;
191 int err;
192
193
194 if (WARN_ON(msg->size > AUX_CH_BUFFER_SIZE))
195 return -E2BIG;
196
197
198 if (msg->size < 1)
199 ctrl2 |= SP_ADDR_ONLY;
200 else
201 ctrl1 |= (msg->size - 1) << SP_AUX_LENGTH_SHIFT;
202
203 if ((msg->request & DP_AUX_I2C_READ) == 0) {
204
205 err = regmap_bulk_write(anx78xx->map[I2C_IDX_TX_P0],
206 SP_DP_BUF_DATA0_REG, buffer,
207 msg->size);
208 if (err)
209 return err;
210 }
211
212
213 err = anx78xx_aux_address(anx78xx, msg->address);
214 if (err)
215 return err;
216
217 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0], SP_DP_AUX_CH_CTRL1_REG,
218 ctrl1);
219 if (err)
220 return err;
221
222
223 err = regmap_update_bits(anx78xx->map[I2C_IDX_TX_P0],
224 SP_DP_AUX_CH_CTRL2_REG, SP_ADDR_ONLY |
225 SP_AUX_EN, ctrl2);
226 if (err)
227 return err;
228
229 err = anx78xx_aux_wait(anx78xx);
230 if (err)
231 return err;
232
233 msg->reply = DP_AUX_I2C_REPLY_ACK;
234
235 if ((msg->size > 0) && (msg->request & DP_AUX_I2C_READ)) {
236
237 err = regmap_bulk_read(anx78xx->map[I2C_IDX_TX_P0],
238 SP_DP_BUF_DATA0_REG, buffer,
239 msg->size);
240 if (err)
241 return err;
242 }
243
244 err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_TX_P0],
245 SP_DP_AUX_CH_CTRL2_REG, SP_ADDR_ONLY);
246 if (err)
247 return err;
248
249 return msg->size;
250}
251
252static int anx78xx_set_hpd(struct anx78xx *anx78xx)
253{
254 int err;
255
256 err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_RX_P0],
257 SP_TMDS_CTRL_BASE + 7, SP_PD_RT);
258 if (err)
259 return err;
260
261 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P2], SP_VID_CTRL3_REG,
262 SP_HPD_OUT);
263 if (err)
264 return err;
265
266 return 0;
267}
268
269static int anx78xx_clear_hpd(struct anx78xx *anx78xx)
270{
271 int err;
272
273 err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_TX_P2], SP_VID_CTRL3_REG,
274 SP_HPD_OUT);
275 if (err)
276 return err;
277
278 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_RX_P0],
279 SP_TMDS_CTRL_BASE + 7, SP_PD_RT);
280 if (err)
281 return err;
282
283 return 0;
284}
285
286static const struct reg_sequence tmds_phy_initialization[] = {
287 { SP_TMDS_CTRL_BASE + 1, 0x90 },
288 { SP_TMDS_CTRL_BASE + 2, 0xa9 },
289 { SP_TMDS_CTRL_BASE + 6, 0x92 },
290 { SP_TMDS_CTRL_BASE + 7, 0x80 },
291 { SP_TMDS_CTRL_BASE + 20, 0xf2 },
292 { SP_TMDS_CTRL_BASE + 22, 0xc4 },
293 { SP_TMDS_CTRL_BASE + 23, 0x18 },
294};
295
296static int anx78xx_rx_initialization(struct anx78xx *anx78xx)
297{
298 int err;
299
300 err = regmap_write(anx78xx->map[I2C_IDX_RX_P0], SP_HDMI_MUTE_CTRL_REG,
301 SP_AUD_MUTE | SP_VID_MUTE);
302 if (err)
303 return err;
304
305 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_RX_P0], SP_CHIP_CTRL_REG,
306 SP_MAN_HDMI5V_DET | SP_PLLLOCK_CKDT_EN |
307 SP_DIGITAL_CKDT_EN);
308 if (err)
309 return err;
310
311 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_RX_P0],
312 SP_SOFTWARE_RESET1_REG, SP_HDCP_MAN_RST |
313 SP_SW_MAN_RST | SP_TMDS_RST | SP_VIDEO_RST);
314 if (err)
315 return err;
316
317 err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_RX_P0],
318 SP_SOFTWARE_RESET1_REG, SP_HDCP_MAN_RST |
319 SP_SW_MAN_RST | SP_TMDS_RST | SP_VIDEO_RST);
320 if (err)
321 return err;
322
323
324 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_RX_P0],
325 SP_AUD_EXCEPTION_ENABLE_BASE + 1, BIT(5) |
326 BIT(6));
327 if (err)
328 return err;
329
330 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_RX_P0],
331 SP_AUD_EXCEPTION_ENABLE_BASE + 3,
332 SP_AEC_EN21);
333 if (err)
334 return err;
335
336 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_RX_P0], SP_AUDVID_CTRL_REG,
337 SP_AVC_EN | SP_AAC_OE | SP_AAC_EN);
338 if (err)
339 return err;
340
341 err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_RX_P0],
342 SP_SYSTEM_POWER_DOWN1_REG, SP_PWDN_CTRL);
343 if (err)
344 return err;
345
346 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_RX_P0],
347 SP_VID_DATA_RANGE_CTRL_REG, SP_R2Y_INPUT_LIMIT);
348 if (err)
349 return err;
350
351
352 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0],
353 SP_DP_EXTRA_I2C_DEV_ADDR_REG, SP_I2C_EXTRA_ADDR);
354 if (err)
355 return err;
356
357
358 err = regmap_multi_reg_write(anx78xx->map[I2C_IDX_RX_P0],
359 tmds_phy_initialization,
360 ARRAY_SIZE(tmds_phy_initialization));
361 if (err)
362 return err;
363
364 err = anx78xx_clear_hpd(anx78xx);
365 if (err)
366 return err;
367
368 return 0;
369}
370
371static const u8 dp_tx_output_precise_tune_bits[20] = {
372 0x01, 0x03, 0x07, 0x7f, 0x71, 0x6b, 0x7f,
373 0x73, 0x7f, 0x7f, 0x00, 0x00, 0x00, 0x00,
374 0x0c, 0x42, 0x1e, 0x3e, 0x72, 0x7e,
375};
376
377static int anx78xx_link_phy_initialization(struct anx78xx *anx78xx)
378{
379 int err;
380
381
382
383
384
385 err = regmap_write(anx78xx->map[I2C_IDX_TX_P2], SP_ANALOG_CTRL0_REG,
386 0x02);
387 if (err)
388 return err;
389
390
391
392
393 err = regmap_bulk_write(anx78xx->map[I2C_IDX_TX_P1],
394 SP_DP_TX_LT_CTRL0_REG,
395 dp_tx_output_precise_tune_bits,
396 ARRAY_SIZE(dp_tx_output_precise_tune_bits));
397
398 if (err)
399 return err;
400
401 return 0;
402}
403
404static int anx78xx_xtal_clk_sel(struct anx78xx *anx78xx)
405{
406 unsigned int value;
407 int err;
408
409 err = regmap_update_bits(anx78xx->map[I2C_IDX_TX_P2],
410 SP_ANALOG_DEBUG2_REG,
411 SP_XTAL_FRQ | SP_FORCE_SW_OFF_BYPASS,
412 SP_XTAL_FRQ_27M);
413 if (err)
414 return err;
415
416 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0], SP_DP_AUX_CH_CTRL3_REG,
417 XTAL_CLK & SP_WAIT_COUNTER_7_0_MASK);
418 if (err)
419 return err;
420
421 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0], SP_DP_AUX_CH_CTRL4_REG,
422 ((XTAL_CLK & 0xff00) >> 2) | (XTAL_CLK / 10));
423 if (err)
424 return err;
425
426 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0],
427 SP_I2C_GEN_10US_TIMER0_REG, XTAL_CLK & 0xff);
428 if (err)
429 return err;
430
431 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0],
432 SP_I2C_GEN_10US_TIMER1_REG,
433 (XTAL_CLK & 0xff00) >> 8);
434 if (err)
435 return err;
436
437 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0], SP_AUX_MISC_CTRL_REG,
438 XTAL_CLK / 10 - 1);
439 if (err)
440 return err;
441
442 err = regmap_read(anx78xx->map[I2C_IDX_RX_P0],
443 SP_HDMI_US_TIMER_CTRL_REG,
444 &value);
445 if (err)
446 return err;
447
448 err = regmap_write(anx78xx->map[I2C_IDX_RX_P0],
449 SP_HDMI_US_TIMER_CTRL_REG,
450 (value & SP_MS_TIMER_MARGIN_10_8_MASK) |
451 ((((XTAL_CLK / 10) >> 1) - 2) << 3));
452 if (err)
453 return err;
454
455 return 0;
456}
457
458static const struct reg_sequence otp_key_protect[] = {
459 { SP_OTP_KEY_PROTECT1_REG, SP_OTP_PSW1 },
460 { SP_OTP_KEY_PROTECT2_REG, SP_OTP_PSW2 },
461 { SP_OTP_KEY_PROTECT3_REG, SP_OTP_PSW3 },
462};
463
464static int anx78xx_tx_initialization(struct anx78xx *anx78xx)
465{
466 int err;
467
468
469 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0], SP_DP_AUX_CH_CTRL2_REG,
470 0x30);
471 if (err)
472 return err;
473
474
475 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P0],
476 SP_DP_AUX_CH_CTRL2_REG, 0x08);
477 if (err)
478 return err;
479
480 err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_TX_P0],
481 SP_DP_HDCP_CTRL_REG, SP_AUTO_EN |
482 SP_AUTO_START);
483 if (err)
484 return err;
485
486 err = regmap_multi_reg_write(anx78xx->map[I2C_IDX_TX_P0],
487 otp_key_protect,
488 ARRAY_SIZE(otp_key_protect));
489 if (err)
490 return err;
491
492 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P0],
493 SP_HDCP_KEY_COMMAND_REG, SP_DISABLE_SYNC_HDCP);
494 if (err)
495 return err;
496
497 err = regmap_write(anx78xx->map[I2C_IDX_TX_P2], SP_VID_CTRL8_REG,
498 SP_VID_VRES_TH);
499 if (err)
500 return err;
501
502
503
504
505
506 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0], SP_HDCP_AUTO_TIMER_REG,
507 0x00);
508 if (err)
509 return err;
510
511 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P0],
512 SP_DP_HDCP_CTRL_REG, SP_LINK_POLLING);
513 if (err)
514 return err;
515
516 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P0],
517 SP_DP_LINK_DEBUG_CTRL_REG, SP_M_VID_DEBUG);
518 if (err)
519 return err;
520
521 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P2],
522 SP_ANALOG_DEBUG2_REG, SP_POWERON_TIME_1P5MS);
523 if (err)
524 return err;
525
526 err = anx78xx_xtal_clk_sel(anx78xx);
527 if (err)
528 return err;
529
530 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0], SP_AUX_DEFER_CTRL_REG,
531 SP_DEFER_CTRL_EN | 0x0c);
532 if (err)
533 return err;
534
535 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P0],
536 SP_DP_POLLING_CTRL_REG,
537 SP_AUTO_POLLING_DISABLE);
538 if (err)
539 return err;
540
541
542
543
544
545 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0],
546 SP_HDCP_LINK_CHECK_TIMER_REG, 0x1d);
547 if (err)
548 return err;
549
550 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P0],
551 SP_DP_MISC_CTRL_REG, SP_EQ_TRAINING_LOOP);
552 if (err)
553 return err;
554
555
556 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P0],
557 SP_DP_ANALOG_POWER_DOWN_REG, SP_CH0_PD);
558 if (err)
559 return err;
560
561 err = anx78xx_link_phy_initialization(anx78xx);
562 if (err)
563 return err;
564
565
566 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P0],
567 SP_DP_M_CALCULATION_CTRL_REG, SP_M_GEN_CLK_SEL);
568 if (err)
569 return err;
570
571 return 0;
572}
573
574static int anx78xx_enable_interrupts(struct anx78xx *anx78xx)
575{
576 int err;
577
578
579
580
581
582 err = regmap_write(anx78xx->map[I2C_IDX_TX_P2], SP_INT_CTRL_REG, 0x01);
583 if (err)
584 return err;
585
586 err = regmap_write(anx78xx->map[I2C_IDX_TX_P2],
587 SP_COMMON_INT_MASK4_REG, SP_HPD_LOST | SP_HPD_PLUG);
588 if (err)
589 return err;
590
591 err = regmap_write(anx78xx->map[I2C_IDX_TX_P2], SP_DP_INT_MASK1_REG,
592 SP_TRAINING_FINISH);
593 if (err)
594 return err;
595
596 err = regmap_write(anx78xx->map[I2C_IDX_RX_P0], SP_INT_MASK1_REG,
597 SP_CKDT_CHG | SP_SCDT_CHG);
598 if (err)
599 return err;
600
601 return 0;
602}
603
604static void anx78xx_poweron(struct anx78xx *anx78xx)
605{
606 struct anx78xx_platform_data *pdata = &anx78xx->pdata;
607 int err;
608
609 if (WARN_ON(anx78xx->powered))
610 return;
611
612 if (pdata->dvdd10) {
613 err = regulator_enable(pdata->dvdd10);
614 if (err) {
615 DRM_ERROR("Failed to enable DVDD10 regulator: %d\n",
616 err);
617 return;
618 }
619
620 usleep_range(1000, 2000);
621 }
622
623 gpiod_set_value_cansleep(pdata->gpiod_reset, 1);
624 usleep_range(1000, 2000);
625
626 gpiod_set_value_cansleep(pdata->gpiod_pd, 0);
627 usleep_range(1000, 2000);
628
629 gpiod_set_value_cansleep(pdata->gpiod_reset, 0);
630
631
632 anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P2], SP_POWERDOWN_CTRL_REG,
633 SP_HDCP_PD | SP_AUDIO_PD | SP_VIDEO_PD | SP_LINK_PD);
634 anx78xx_clear_bits(anx78xx->map[I2C_IDX_TX_P2], SP_POWERDOWN_CTRL_REG,
635 SP_REGISTER_PD | SP_TOTAL_PD);
636
637 anx78xx->powered = true;
638}
639
640static void anx78xx_poweroff(struct anx78xx *anx78xx)
641{
642 struct anx78xx_platform_data *pdata = &anx78xx->pdata;
643 int err;
644
645 if (WARN_ON(!anx78xx->powered))
646 return;
647
648 gpiod_set_value_cansleep(pdata->gpiod_reset, 1);
649 usleep_range(1000, 2000);
650
651 gpiod_set_value_cansleep(pdata->gpiod_pd, 1);
652 usleep_range(1000, 2000);
653
654 if (pdata->dvdd10) {
655 err = regulator_disable(pdata->dvdd10);
656 if (err) {
657 DRM_ERROR("Failed to disable DVDD10 regulator: %d\n",
658 err);
659 return;
660 }
661
662 usleep_range(1000, 2000);
663 }
664
665 anx78xx->powered = false;
666}
667
668static int anx78xx_start(struct anx78xx *anx78xx)
669{
670 int err;
671
672
673 err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_TX_P2],
674 SP_POWERDOWN_CTRL_REG,
675 SP_HDCP_PD | SP_AUDIO_PD | SP_VIDEO_PD |
676 SP_LINK_PD);
677
678 err = anx78xx_enable_interrupts(anx78xx);
679 if (err) {
680 DRM_ERROR("Failed to enable interrupts: %d\n", err);
681 goto err_poweroff;
682 }
683
684 err = anx78xx_rx_initialization(anx78xx);
685 if (err) {
686 DRM_ERROR("Failed receiver initialization: %d\n", err);
687 goto err_poweroff;
688 }
689
690 err = anx78xx_tx_initialization(anx78xx);
691 if (err) {
692 DRM_ERROR("Failed transmitter initialization: %d\n", err);
693 goto err_poweroff;
694 }
695
696
697
698
699
700 usleep_range(10000, 15000);
701
702 return 0;
703
704err_poweroff:
705 DRM_ERROR("Failed SlimPort transmitter initialization: %d\n", err);
706 anx78xx_poweroff(anx78xx);
707
708 return err;
709}
710
711static int anx78xx_init_pdata(struct anx78xx *anx78xx)
712{
713 struct anx78xx_platform_data *pdata = &anx78xx->pdata;
714 struct device *dev = &anx78xx->client->dev;
715
716
717 pdata->dvdd10 = devm_regulator_get(dev, "dvdd10");
718 if (IS_ERR(pdata->dvdd10)) {
719 DRM_ERROR("DVDD10 regulator not found\n");
720 return PTR_ERR(pdata->dvdd10);
721 }
722
723
724 pdata->gpiod_hpd = devm_gpiod_get(dev, "hpd", GPIOD_IN);
725 if (IS_ERR(pdata->gpiod_hpd))
726 return PTR_ERR(pdata->gpiod_hpd);
727
728
729 pdata->gpiod_pd = devm_gpiod_get(dev, "pd", GPIOD_OUT_HIGH);
730 if (IS_ERR(pdata->gpiod_pd))
731 return PTR_ERR(pdata->gpiod_pd);
732
733
734 pdata->gpiod_reset = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
735
736 return PTR_ERR_OR_ZERO(pdata->gpiod_reset);
737}
738
739static int anx78xx_dp_link_training(struct anx78xx *anx78xx)
740{
741 u8 dp_bw, value;
742 int err;
743
744 err = regmap_write(anx78xx->map[I2C_IDX_RX_P0], SP_HDMI_MUTE_CTRL_REG,
745 0x0);
746 if (err)
747 return err;
748
749 err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_TX_P2],
750 SP_POWERDOWN_CTRL_REG,
751 SP_TOTAL_PD);
752 if (err)
753 return err;
754
755 err = drm_dp_dpcd_readb(&anx78xx->aux, DP_MAX_LINK_RATE, &dp_bw);
756 if (err < 0)
757 return err;
758
759 switch (dp_bw) {
760 case DP_LINK_BW_1_62:
761 case DP_LINK_BW_2_7:
762 case DP_LINK_BW_5_4:
763 break;
764
765 default:
766 DRM_DEBUG_KMS("DP bandwidth (%#02x) not supported\n", dp_bw);
767 return -EINVAL;
768 }
769
770 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P2], SP_VID_CTRL1_REG,
771 SP_VIDEO_MUTE);
772 if (err)
773 return err;
774
775 err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_TX_P2],
776 SP_VID_CTRL1_REG, SP_VIDEO_EN);
777 if (err)
778 return err;
779
780
781 err = drm_dp_dpcd_read(&anx78xx->aux, DP_DPCD_REV,
782 &anx78xx->dpcd, DP_RECEIVER_CAP_SIZE);
783 if (err < 0) {
784 DRM_ERROR("Failed to read DPCD: %d\n", err);
785 return err;
786 }
787
788
789 err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_TX_P0],
790 SP_DP_ANALOG_POWER_DOWN_REG, SP_CH0_PD);
791 if (err)
792 return err;
793
794
795 err = drm_dp_link_probe(&anx78xx->aux, &anx78xx->link);
796 if (err < 0) {
797 DRM_ERROR("Failed to probe link capabilities: %d\n", err);
798 return err;
799 }
800
801
802 err = drm_dp_link_power_up(&anx78xx->aux, &anx78xx->link);
803 if (err < 0) {
804 DRM_ERROR("Failed to power up DisplayPort link: %d\n", err);
805 return err;
806 }
807
808
809 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0],
810 SP_DP_DOWNSPREAD_CTRL1_REG, 0);
811 if (err)
812 return err;
813
814 if (anx78xx->dpcd[DP_MAX_DOWNSPREAD] & DP_MAX_DOWNSPREAD_0_5) {
815 DRM_DEBUG("Enable downspread on the sink\n");
816
817 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0],
818 SP_DP_DOWNSPREAD_CTRL1_REG, 8);
819 if (err)
820 return err;
821
822 err = drm_dp_dpcd_writeb(&anx78xx->aux, DP_DOWNSPREAD_CTRL,
823 DP_SPREAD_AMP_0_5);
824 if (err < 0)
825 return err;
826 } else {
827 err = drm_dp_dpcd_writeb(&anx78xx->aux, DP_DOWNSPREAD_CTRL, 0);
828 if (err < 0)
829 return err;
830 }
831
832
833 if (drm_dp_enhanced_frame_cap(anx78xx->dpcd))
834 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P0],
835 SP_DP_SYSTEM_CTRL_BASE + 4,
836 SP_ENHANCED_MODE);
837 else
838 err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_TX_P0],
839 SP_DP_SYSTEM_CTRL_BASE + 4,
840 SP_ENHANCED_MODE);
841 if (err)
842 return err;
843
844 value = drm_dp_link_rate_to_bw_code(anx78xx->link.rate);
845 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0],
846 SP_DP_MAIN_LINK_BW_SET_REG, value);
847 if (err)
848 return err;
849
850 err = drm_dp_link_configure(&anx78xx->aux, &anx78xx->link);
851 if (err < 0) {
852 DRM_ERROR("Failed to configure DisplayPort link: %d\n", err);
853 return err;
854 }
855
856
857 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0], SP_DP_LT_CTRL_REG,
858 SP_LT_EN);
859 if (err)
860 return err;
861
862 return 0;
863}
864
865static int anx78xx_config_dp_output(struct anx78xx *anx78xx)
866{
867 int err;
868
869 err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_TX_P2], SP_VID_CTRL1_REG,
870 SP_VIDEO_MUTE);
871 if (err)
872 return err;
873
874
875 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P2], SP_VID_CTRL1_REG,
876 SP_VIDEO_EN);
877 if (err)
878 return err;
879
880 return 0;
881}
882
883static int anx78xx_send_video_infoframe(struct anx78xx *anx78xx,
884 struct hdmi_avi_infoframe *frame)
885{
886 u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];
887 int err;
888
889 err = hdmi_avi_infoframe_pack(frame, buffer, sizeof(buffer));
890 if (err < 0) {
891 DRM_ERROR("Failed to pack AVI infoframe: %d\n", err);
892 return err;
893 }
894
895 err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_TX_P0],
896 SP_PACKET_SEND_CTRL_REG, SP_AVI_IF_EN);
897 if (err)
898 return err;
899
900 err = regmap_bulk_write(anx78xx->map[I2C_IDX_TX_P2],
901 SP_INFOFRAME_AVI_DB1_REG, buffer,
902 frame->length);
903 if (err)
904 return err;
905
906 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P0],
907 SP_PACKET_SEND_CTRL_REG, SP_AVI_IF_UD);
908 if (err)
909 return err;
910
911 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P0],
912 SP_PACKET_SEND_CTRL_REG, SP_AVI_IF_EN);
913 if (err)
914 return err;
915
916 return 0;
917}
918
919static int anx78xx_get_downstream_info(struct anx78xx *anx78xx)
920{
921 u8 value;
922 int err;
923
924 err = drm_dp_dpcd_readb(&anx78xx->aux, DP_SINK_COUNT, &value);
925 if (err < 0) {
926 DRM_ERROR("Get sink count failed %d\n", err);
927 return err;
928 }
929
930 if (!DP_GET_SINK_COUNT(value)) {
931 DRM_ERROR("Downstream disconnected\n");
932 return -EIO;
933 }
934
935 return 0;
936}
937
938static int anx78xx_get_modes(struct drm_connector *connector)
939{
940 struct anx78xx *anx78xx = connector_to_anx78xx(connector);
941 int err, num_modes = 0;
942
943 if (WARN_ON(!anx78xx->powered))
944 return 0;
945
946 if (anx78xx->edid)
947 return drm_add_edid_modes(connector, anx78xx->edid);
948
949 mutex_lock(&anx78xx->lock);
950
951 err = anx78xx_get_downstream_info(anx78xx);
952 if (err) {
953 DRM_ERROR("Failed to get downstream info: %d\n", err);
954 goto unlock;
955 }
956
957 anx78xx->edid = drm_get_edid(connector, &anx78xx->aux.ddc);
958 if (!anx78xx->edid) {
959 DRM_ERROR("Failed to read EDID\n");
960 goto unlock;
961 }
962
963 err = drm_connector_update_edid_property(connector,
964 anx78xx->edid);
965 if (err) {
966 DRM_ERROR("Failed to update EDID property: %d\n", err);
967 goto unlock;
968 }
969
970 num_modes = drm_add_edid_modes(connector, anx78xx->edid);
971
972unlock:
973 mutex_unlock(&anx78xx->lock);
974
975 return num_modes;
976}
977
978static const struct drm_connector_helper_funcs anx78xx_connector_helper_funcs = {
979 .get_modes = anx78xx_get_modes,
980};
981
982static enum drm_connector_status anx78xx_detect(struct drm_connector *connector,
983 bool force)
984{
985 struct anx78xx *anx78xx = connector_to_anx78xx(connector);
986
987 if (!gpiod_get_value(anx78xx->pdata.gpiod_hpd))
988 return connector_status_disconnected;
989
990 return connector_status_connected;
991}
992
993static const struct drm_connector_funcs anx78xx_connector_funcs = {
994 .fill_modes = drm_helper_probe_single_connector_modes,
995 .detect = anx78xx_detect,
996 .destroy = drm_connector_cleanup,
997 .reset = drm_atomic_helper_connector_reset,
998 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
999 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1000};
1001
1002static int anx78xx_bridge_attach(struct drm_bridge *bridge)
1003{
1004 struct anx78xx *anx78xx = bridge_to_anx78xx(bridge);
1005 int err;
1006
1007 if (!bridge->encoder) {
1008 DRM_ERROR("Parent encoder object not found");
1009 return -ENODEV;
1010 }
1011
1012
1013 anx78xx->aux.name = "DP-AUX";
1014 anx78xx->aux.dev = &anx78xx->client->dev;
1015 anx78xx->aux.transfer = anx78xx_aux_transfer;
1016
1017 err = drm_dp_aux_register(&anx78xx->aux);
1018 if (err < 0) {
1019 DRM_ERROR("Failed to register aux channel: %d\n", err);
1020 return err;
1021 }
1022
1023 err = drm_connector_init(bridge->dev, &anx78xx->connector,
1024 &anx78xx_connector_funcs,
1025 DRM_MODE_CONNECTOR_DisplayPort);
1026 if (err) {
1027 DRM_ERROR("Failed to initialize connector: %d\n", err);
1028 return err;
1029 }
1030
1031 drm_connector_helper_add(&anx78xx->connector,
1032 &anx78xx_connector_helper_funcs);
1033
1034 err = drm_connector_register(&anx78xx->connector);
1035 if (err) {
1036 DRM_ERROR("Failed to register connector: %d\n", err);
1037 return err;
1038 }
1039
1040 anx78xx->connector.polled = DRM_CONNECTOR_POLL_HPD;
1041
1042 err = drm_connector_attach_encoder(&anx78xx->connector,
1043 bridge->encoder);
1044 if (err) {
1045 DRM_ERROR("Failed to link up connector to encoder: %d\n", err);
1046 return err;
1047 }
1048
1049 return 0;
1050}
1051
1052static enum drm_mode_status
1053anx78xx_bridge_mode_valid(struct drm_bridge *bridge,
1054 const struct drm_display_mode *mode)
1055{
1056 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1057 return MODE_NO_INTERLACE;
1058
1059
1060 if (mode->clock > 154000)
1061 return MODE_CLOCK_HIGH;
1062
1063 return MODE_OK;
1064}
1065
1066static void anx78xx_bridge_disable(struct drm_bridge *bridge)
1067{
1068 struct anx78xx *anx78xx = bridge_to_anx78xx(bridge);
1069
1070
1071 anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P2], SP_POWERDOWN_CTRL_REG,
1072 SP_HDCP_PD | SP_AUDIO_PD | SP_VIDEO_PD | SP_LINK_PD);
1073}
1074
1075static void anx78xx_bridge_mode_set(struct drm_bridge *bridge,
1076 const struct drm_display_mode *mode,
1077 const struct drm_display_mode *adjusted_mode)
1078{
1079 struct anx78xx *anx78xx = bridge_to_anx78xx(bridge);
1080 struct hdmi_avi_infoframe frame;
1081 int err;
1082
1083 if (WARN_ON(!anx78xx->powered))
1084 return;
1085
1086 mutex_lock(&anx78xx->lock);
1087
1088 err = drm_hdmi_avi_infoframe_from_display_mode(&frame,
1089 &anx78xx->connector,
1090 adjusted_mode);
1091 if (err) {
1092 DRM_ERROR("Failed to setup AVI infoframe: %d\n", err);
1093 goto unlock;
1094 }
1095
1096 err = anx78xx_send_video_infoframe(anx78xx, &frame);
1097 if (err)
1098 DRM_ERROR("Failed to send AVI infoframe: %d\n", err);
1099
1100unlock:
1101 mutex_unlock(&anx78xx->lock);
1102}
1103
1104static void anx78xx_bridge_enable(struct drm_bridge *bridge)
1105{
1106 struct anx78xx *anx78xx = bridge_to_anx78xx(bridge);
1107 int err;
1108
1109 err = anx78xx_start(anx78xx);
1110 if (err) {
1111 DRM_ERROR("Failed to initialize: %d\n", err);
1112 return;
1113 }
1114
1115 err = anx78xx_set_hpd(anx78xx);
1116 if (err)
1117 DRM_ERROR("Failed to set HPD: %d\n", err);
1118}
1119
1120static const struct drm_bridge_funcs anx78xx_bridge_funcs = {
1121 .attach = anx78xx_bridge_attach,
1122 .mode_valid = anx78xx_bridge_mode_valid,
1123 .disable = anx78xx_bridge_disable,
1124 .mode_set = anx78xx_bridge_mode_set,
1125 .enable = anx78xx_bridge_enable,
1126};
1127
1128static irqreturn_t anx78xx_hpd_threaded_handler(int irq, void *data)
1129{
1130 struct anx78xx *anx78xx = data;
1131 int err;
1132
1133 if (anx78xx->powered)
1134 return IRQ_HANDLED;
1135
1136 mutex_lock(&anx78xx->lock);
1137
1138
1139 anx78xx_poweron(anx78xx);
1140
1141 err = anx78xx_enable_interrupts(anx78xx);
1142 if (err)
1143 DRM_ERROR("Failed to enable interrupts: %d\n", err);
1144
1145 mutex_unlock(&anx78xx->lock);
1146
1147 return IRQ_HANDLED;
1148}
1149
1150static int anx78xx_handle_dp_int_1(struct anx78xx *anx78xx, u8 irq)
1151{
1152 int err;
1153
1154 DRM_DEBUG_KMS("Handle DP interrupt 1: %02x\n", irq);
1155
1156 err = regmap_write(anx78xx->map[I2C_IDX_TX_P2], SP_DP_INT_STATUS1_REG,
1157 irq);
1158 if (err)
1159 return err;
1160
1161 if (irq & SP_TRAINING_FINISH) {
1162 DRM_DEBUG_KMS("IRQ: hardware link training finished\n");
1163 err = anx78xx_config_dp_output(anx78xx);
1164 }
1165
1166 return err;
1167}
1168
1169static bool anx78xx_handle_common_int_4(struct anx78xx *anx78xx, u8 irq)
1170{
1171 bool event = false;
1172 int err;
1173
1174 DRM_DEBUG_KMS("Handle common interrupt 4: %02x\n", irq);
1175
1176 err = regmap_write(anx78xx->map[I2C_IDX_TX_P2],
1177 SP_COMMON_INT_STATUS4_REG, irq);
1178 if (err) {
1179 DRM_ERROR("Failed to write SP_COMMON_INT_STATUS4 %d\n", err);
1180 return event;
1181 }
1182
1183 if (irq & SP_HPD_LOST) {
1184 DRM_DEBUG_KMS("IRQ: Hot plug detect - cable is pulled out\n");
1185 event = true;
1186 anx78xx_poweroff(anx78xx);
1187
1188 kfree(anx78xx->edid);
1189 anx78xx->edid = NULL;
1190 } else if (irq & SP_HPD_PLUG) {
1191 DRM_DEBUG_KMS("IRQ: Hot plug detect - cable plug\n");
1192 event = true;
1193 }
1194
1195 return event;
1196}
1197
1198static void anx78xx_handle_hdmi_int_1(struct anx78xx *anx78xx, u8 irq)
1199{
1200 unsigned int value;
1201 int err;
1202
1203 DRM_DEBUG_KMS("Handle HDMI interrupt 1: %02x\n", irq);
1204
1205 err = regmap_write(anx78xx->map[I2C_IDX_RX_P0], SP_INT_STATUS1_REG,
1206 irq);
1207 if (err) {
1208 DRM_ERROR("Write HDMI int 1 failed: %d\n", err);
1209 return;
1210 }
1211
1212 if ((irq & SP_CKDT_CHG) || (irq & SP_SCDT_CHG)) {
1213 DRM_DEBUG_KMS("IRQ: HDMI input detected\n");
1214
1215 err = regmap_read(anx78xx->map[I2C_IDX_RX_P0],
1216 SP_SYSTEM_STATUS_REG, &value);
1217 if (err) {
1218 DRM_ERROR("Read system status reg failed: %d\n", err);
1219 return;
1220 }
1221
1222 if (!(value & SP_TMDS_CLOCK_DET)) {
1223 DRM_DEBUG_KMS("IRQ: *** Waiting for HDMI clock ***\n");
1224 return;
1225 }
1226
1227 if (!(value & SP_TMDS_DE_DET)) {
1228 DRM_DEBUG_KMS("IRQ: *** Waiting for HDMI signal ***\n");
1229 return;
1230 }
1231
1232 err = anx78xx_dp_link_training(anx78xx);
1233 if (err)
1234 DRM_ERROR("Failed to start link training: %d\n", err);
1235 }
1236}
1237
1238static irqreturn_t anx78xx_intp_threaded_handler(int unused, void *data)
1239{
1240 struct anx78xx *anx78xx = data;
1241 bool event = false;
1242 unsigned int irq;
1243 int err;
1244
1245 mutex_lock(&anx78xx->lock);
1246
1247 err = regmap_read(anx78xx->map[I2C_IDX_TX_P2], SP_DP_INT_STATUS1_REG,
1248 &irq);
1249 if (err) {
1250 DRM_ERROR("Failed to read DP interrupt 1 status: %d\n", err);
1251 goto unlock;
1252 }
1253
1254 if (irq)
1255 anx78xx_handle_dp_int_1(anx78xx, irq);
1256
1257 err = regmap_read(anx78xx->map[I2C_IDX_TX_P2],
1258 SP_COMMON_INT_STATUS4_REG, &irq);
1259 if (err) {
1260 DRM_ERROR("Failed to read common interrupt 4 status: %d\n",
1261 err);
1262 goto unlock;
1263 }
1264
1265 if (irq)
1266 event = anx78xx_handle_common_int_4(anx78xx, irq);
1267
1268
1269 if (!anx78xx->powered)
1270 goto unlock;
1271
1272 err = regmap_read(anx78xx->map[I2C_IDX_RX_P0], SP_INT_STATUS1_REG,
1273 &irq);
1274 if (err) {
1275 DRM_ERROR("Failed to read HDMI int 1 status: %d\n", err);
1276 goto unlock;
1277 }
1278
1279 if (irq)
1280 anx78xx_handle_hdmi_int_1(anx78xx, irq);
1281
1282unlock:
1283 mutex_unlock(&anx78xx->lock);
1284
1285 if (event)
1286 drm_helper_hpd_irq_event(anx78xx->connector.dev);
1287
1288 return IRQ_HANDLED;
1289}
1290
1291static void unregister_i2c_dummy_clients(struct anx78xx *anx78xx)
1292{
1293 unsigned int i;
1294
1295 for (i = 0; i < ARRAY_SIZE(anx78xx->i2c_dummy); i++)
1296 i2c_unregister_device(anx78xx->i2c_dummy[i]);
1297}
1298
1299static const struct regmap_config anx78xx_regmap_config = {
1300 .reg_bits = 8,
1301 .val_bits = 8,
1302};
1303
1304static const u16 anx78xx_chipid_list[] = {
1305 0x7812,
1306 0x7814,
1307 0x7818,
1308};
1309
1310static int anx78xx_i2c_probe(struct i2c_client *client,
1311 const struct i2c_device_id *id)
1312{
1313 struct anx78xx *anx78xx;
1314 struct anx78xx_platform_data *pdata;
1315 unsigned int i, idl, idh, version;
1316 bool found = false;
1317 int err;
1318
1319 anx78xx = devm_kzalloc(&client->dev, sizeof(*anx78xx), GFP_KERNEL);
1320 if (!anx78xx)
1321 return -ENOMEM;
1322
1323 pdata = &anx78xx->pdata;
1324
1325 mutex_init(&anx78xx->lock);
1326
1327#if IS_ENABLED(CONFIG_OF)
1328 anx78xx->bridge.of_node = client->dev.of_node;
1329#endif
1330
1331 anx78xx->client = client;
1332 i2c_set_clientdata(client, anx78xx);
1333
1334 err = anx78xx_init_pdata(anx78xx);
1335 if (err) {
1336 DRM_ERROR("Failed to initialize pdata: %d\n", err);
1337 return err;
1338 }
1339
1340 pdata->hpd_irq = gpiod_to_irq(pdata->gpiod_hpd);
1341 if (pdata->hpd_irq < 0) {
1342 DRM_ERROR("Failed to get HPD IRQ: %d\n", pdata->hpd_irq);
1343 return -ENODEV;
1344 }
1345
1346 pdata->intp_irq = client->irq;
1347 if (!pdata->intp_irq) {
1348 DRM_ERROR("Failed to get CABLE_DET and INTP IRQ\n");
1349 return -ENODEV;
1350 }
1351
1352
1353 for (i = 0; i < I2C_NUM_ADDRESSES; i++) {
1354 anx78xx->i2c_dummy[i] = i2c_new_dummy(client->adapter,
1355 anx78xx_i2c_addresses[i] >> 1);
1356 if (!anx78xx->i2c_dummy[i]) {
1357 err = -ENOMEM;
1358 DRM_ERROR("Failed to reserve I2C bus %02x\n",
1359 anx78xx_i2c_addresses[i]);
1360 goto err_unregister_i2c;
1361 }
1362
1363 anx78xx->map[i] = devm_regmap_init_i2c(anx78xx->i2c_dummy[i],
1364 &anx78xx_regmap_config);
1365 if (IS_ERR(anx78xx->map[i])) {
1366 err = PTR_ERR(anx78xx->map[i]);
1367 DRM_ERROR("Failed regmap initialization %02x\n",
1368 anx78xx_i2c_addresses[i]);
1369 goto err_unregister_i2c;
1370 }
1371 }
1372
1373
1374 anx78xx_poweron(anx78xx);
1375
1376 err = regmap_read(anx78xx->map[I2C_IDX_TX_P2], SP_DEVICE_IDL_REG,
1377 &idl);
1378 if (err)
1379 goto err_poweroff;
1380
1381 err = regmap_read(anx78xx->map[I2C_IDX_TX_P2], SP_DEVICE_IDH_REG,
1382 &idh);
1383 if (err)
1384 goto err_poweroff;
1385
1386 anx78xx->chipid = (u8)idl | ((u8)idh << 8);
1387
1388 err = regmap_read(anx78xx->map[I2C_IDX_TX_P2], SP_DEVICE_VERSION_REG,
1389 &version);
1390 if (err)
1391 goto err_poweroff;
1392
1393 for (i = 0; i < ARRAY_SIZE(anx78xx_chipid_list); i++) {
1394 if (anx78xx->chipid == anx78xx_chipid_list[i]) {
1395 DRM_INFO("Found ANX%x (ver. %d) SlimPort Transmitter\n",
1396 anx78xx->chipid, version);
1397 found = true;
1398 break;
1399 }
1400 }
1401
1402 if (!found) {
1403 DRM_ERROR("ANX%x (ver. %d) not supported by this driver\n",
1404 anx78xx->chipid, version);
1405 err = -ENODEV;
1406 goto err_poweroff;
1407 }
1408
1409 err = devm_request_threaded_irq(&client->dev, pdata->hpd_irq, NULL,
1410 anx78xx_hpd_threaded_handler,
1411 IRQF_TRIGGER_RISING | IRQF_ONESHOT,
1412 "anx78xx-hpd", anx78xx);
1413 if (err) {
1414 DRM_ERROR("Failed to request CABLE_DET threaded IRQ: %d\n",
1415 err);
1416 goto err_poweroff;
1417 }
1418
1419 err = devm_request_threaded_irq(&client->dev, pdata->intp_irq, NULL,
1420 anx78xx_intp_threaded_handler,
1421 IRQF_TRIGGER_RISING | IRQF_ONESHOT,
1422 "anx78xx-intp", anx78xx);
1423 if (err) {
1424 DRM_ERROR("Failed to request INTP threaded IRQ: %d\n", err);
1425 goto err_poweroff;
1426 }
1427
1428 anx78xx->bridge.funcs = &anx78xx_bridge_funcs;
1429
1430 drm_bridge_add(&anx78xx->bridge);
1431
1432
1433 if (!gpiod_get_value(anx78xx->pdata.gpiod_hpd))
1434 anx78xx_poweroff(anx78xx);
1435
1436 return 0;
1437
1438err_poweroff:
1439 anx78xx_poweroff(anx78xx);
1440
1441err_unregister_i2c:
1442 unregister_i2c_dummy_clients(anx78xx);
1443 return err;
1444}
1445
1446static int anx78xx_i2c_remove(struct i2c_client *client)
1447{
1448 struct anx78xx *anx78xx = i2c_get_clientdata(client);
1449
1450 drm_bridge_remove(&anx78xx->bridge);
1451
1452 unregister_i2c_dummy_clients(anx78xx);
1453
1454 kfree(anx78xx->edid);
1455
1456 return 0;
1457}
1458
1459static const struct i2c_device_id anx78xx_id[] = {
1460 { "anx7814", 0 },
1461 { }
1462};
1463MODULE_DEVICE_TABLE(i2c, anx78xx_id);
1464
1465#if IS_ENABLED(CONFIG_OF)
1466static const struct of_device_id anx78xx_match_table[] = {
1467 { .compatible = "analogix,anx7814", },
1468 { },
1469};
1470MODULE_DEVICE_TABLE(of, anx78xx_match_table);
1471#endif
1472
1473static struct i2c_driver anx78xx_driver = {
1474 .driver = {
1475 .name = "anx7814",
1476 .of_match_table = of_match_ptr(anx78xx_match_table),
1477 },
1478 .probe = anx78xx_i2c_probe,
1479 .remove = anx78xx_i2c_remove,
1480 .id_table = anx78xx_id,
1481};
1482module_i2c_driver(anx78xx_driver);
1483
1484MODULE_DESCRIPTION("ANX78xx SlimPort Transmitter driver");
1485MODULE_AUTHOR("Enric Balletbo i Serra <enric.balletbo@collabora.com>");
1486MODULE_LICENSE("GPL v2");
1487
