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9#include <linux/module.h>
10#include <linux/platform_device.h>
11#include <linux/err.h>
12#include <linux/clk.h>
13#include <linux/io.h>
14#include <linux/iopoll.h>
15#include <linux/interrupt.h>
16#include <linux/of.h>
17#include <linux/of_gpio.h>
18#include <linux/gpio.h>
19#include <linux/component.h>
20#include <linux/phy/phy.h>
21
22#include <drm/drmP.h>
23#include <drm/drm_atomic_helper.h>
24#include <drm/drm_crtc.h>
25#include <drm/drm_panel.h>
26#include <drm/drm_probe_helper.h>
27
28#include <drm/bridge/analogix_dp.h>
29
30#include "analogix_dp_core.h"
31#include "analogix_dp_reg.h"
32
33#define to_dp(nm) container_of(nm, struct analogix_dp_device, nm)
34
35static const bool verify_fast_training;
36
37struct bridge_init {
38 struct i2c_client *client;
39 struct device_node *node;
40};
41
42static int analogix_dp_init_dp(struct analogix_dp_device *dp)
43{
44 int ret;
45
46 analogix_dp_reset(dp);
47
48 analogix_dp_swreset(dp);
49
50 analogix_dp_init_analog_param(dp);
51 analogix_dp_init_interrupt(dp);
52
53
54 analogix_dp_enable_sw_function(dp);
55
56 analogix_dp_config_interrupt(dp);
57 ret = analogix_dp_init_analog_func(dp);
58 if (ret)
59 return ret;
60
61 analogix_dp_init_hpd(dp);
62 analogix_dp_init_aux(dp);
63 return 0;
64}
65
66static int analogix_dp_detect_hpd(struct analogix_dp_device *dp)
67{
68 int timeout_loop = 0;
69
70 while (timeout_loop < DP_TIMEOUT_LOOP_COUNT) {
71 if (analogix_dp_get_plug_in_status(dp) == 0)
72 return 0;
73
74 timeout_loop++;
75 usleep_range(1000, 1100);
76 }
77
78
79
80
81
82
83 if (!dp->force_hpd)
84 return -ETIMEDOUT;
85
86
87
88
89
90
91 dev_dbg(dp->dev, "failed to get hpd plug status, try to force hpd\n");
92
93 analogix_dp_force_hpd(dp);
94
95 if (analogix_dp_get_plug_in_status(dp) != 0) {
96 dev_err(dp->dev, "failed to get hpd plug in status\n");
97 return -EINVAL;
98 }
99
100 dev_dbg(dp->dev, "success to get plug in status after force hpd\n");
101
102 return 0;
103}
104
105int analogix_dp_psr_enabled(struct analogix_dp_device *dp)
106{
107
108 return dp->psr_enable;
109}
110EXPORT_SYMBOL_GPL(analogix_dp_psr_enabled);
111
112int analogix_dp_enable_psr(struct analogix_dp_device *dp)
113{
114 struct edp_vsc_psr psr_vsc;
115
116 if (!dp->psr_enable)
117 return 0;
118
119
120 memset(&psr_vsc, 0, sizeof(psr_vsc));
121 psr_vsc.sdp_header.HB0 = 0;
122 psr_vsc.sdp_header.HB1 = 0x7;
123 psr_vsc.sdp_header.HB2 = 0x2;
124 psr_vsc.sdp_header.HB3 = 0x8;
125
126 psr_vsc.DB0 = 0;
127 psr_vsc.DB1 = EDP_VSC_PSR_STATE_ACTIVE | EDP_VSC_PSR_CRC_VALUES_VALID;
128
129 return analogix_dp_send_psr_spd(dp, &psr_vsc, true);
130}
131EXPORT_SYMBOL_GPL(analogix_dp_enable_psr);
132
133int analogix_dp_disable_psr(struct analogix_dp_device *dp)
134{
135 struct edp_vsc_psr psr_vsc;
136 int ret;
137
138 if (!dp->psr_enable)
139 return 0;
140
141
142 memset(&psr_vsc, 0, sizeof(psr_vsc));
143 psr_vsc.sdp_header.HB0 = 0;
144 psr_vsc.sdp_header.HB1 = 0x7;
145 psr_vsc.sdp_header.HB2 = 0x2;
146 psr_vsc.sdp_header.HB3 = 0x8;
147
148 psr_vsc.DB0 = 0;
149 psr_vsc.DB1 = 0;
150
151 ret = drm_dp_dpcd_writeb(&dp->aux, DP_SET_POWER, DP_SET_POWER_D0);
152 if (ret != 1) {
153 dev_err(dp->dev, "Failed to set DP Power0 %d\n", ret);
154 return ret;
155 }
156
157 return analogix_dp_send_psr_spd(dp, &psr_vsc, false);
158}
159EXPORT_SYMBOL_GPL(analogix_dp_disable_psr);
160
161static int analogix_dp_detect_sink_psr(struct analogix_dp_device *dp)
162{
163 unsigned char psr_version;
164 int ret;
165
166 ret = drm_dp_dpcd_readb(&dp->aux, DP_PSR_SUPPORT, &psr_version);
167 if (ret != 1) {
168 dev_err(dp->dev, "failed to get PSR version, disable it\n");
169 return ret;
170 }
171
172 dev_dbg(dp->dev, "Panel PSR version : %x\n", psr_version);
173
174 dp->psr_enable = (psr_version & DP_PSR_IS_SUPPORTED) ? true : false;
175
176 return 0;
177}
178
179static int analogix_dp_enable_sink_psr(struct analogix_dp_device *dp)
180{
181 unsigned char psr_en;
182 int ret;
183
184
185 ret = drm_dp_dpcd_readb(&dp->aux, DP_PSR_EN_CFG, &psr_en);
186 if (ret != 1) {
187 dev_err(dp->dev, "failed to get psr config\n");
188 goto end;
189 }
190
191 psr_en &= ~DP_PSR_ENABLE;
192 ret = drm_dp_dpcd_writeb(&dp->aux, DP_PSR_EN_CFG, psr_en);
193 if (ret != 1) {
194 dev_err(dp->dev, "failed to disable panel psr\n");
195 goto end;
196 }
197
198
199 psr_en = DP_PSR_MAIN_LINK_ACTIVE | DP_PSR_CRC_VERIFICATION;
200 ret = drm_dp_dpcd_writeb(&dp->aux, DP_PSR_EN_CFG, psr_en);
201 if (ret != 1) {
202 dev_err(dp->dev, "failed to set panel psr\n");
203 goto end;
204 }
205
206
207 psr_en = DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE |
208 DP_PSR_CRC_VERIFICATION;
209 ret = drm_dp_dpcd_writeb(&dp->aux, DP_PSR_EN_CFG, psr_en);
210 if (ret != 1) {
211 dev_err(dp->dev, "failed to set panel psr\n");
212 goto end;
213 }
214
215 analogix_dp_enable_psr_crc(dp);
216
217 return 0;
218end:
219 dev_err(dp->dev, "enable psr fail, force to disable psr\n");
220 dp->psr_enable = false;
221
222 return ret;
223}
224
225static int
226analogix_dp_enable_rx_to_enhanced_mode(struct analogix_dp_device *dp,
227 bool enable)
228{
229 u8 data;
230 int ret;
231
232 ret = drm_dp_dpcd_readb(&dp->aux, DP_LANE_COUNT_SET, &data);
233 if (ret != 1)
234 return ret;
235
236 if (enable)
237 ret = drm_dp_dpcd_writeb(&dp->aux, DP_LANE_COUNT_SET,
238 DP_LANE_COUNT_ENHANCED_FRAME_EN |
239 DPCD_LANE_COUNT_SET(data));
240 else
241 ret = drm_dp_dpcd_writeb(&dp->aux, DP_LANE_COUNT_SET,
242 DPCD_LANE_COUNT_SET(data));
243
244 return ret < 0 ? ret : 0;
245}
246
247static int analogix_dp_is_enhanced_mode_available(struct analogix_dp_device *dp,
248 u8 *enhanced_mode_support)
249{
250 u8 data;
251 int ret;
252
253 ret = drm_dp_dpcd_readb(&dp->aux, DP_MAX_LANE_COUNT, &data);
254 if (ret != 1) {
255 *enhanced_mode_support = 0;
256 return ret;
257 }
258
259 *enhanced_mode_support = DPCD_ENHANCED_FRAME_CAP(data);
260
261 return 0;
262}
263
264static int analogix_dp_set_enhanced_mode(struct analogix_dp_device *dp)
265{
266 u8 data;
267 int ret;
268
269 ret = analogix_dp_is_enhanced_mode_available(dp, &data);
270 if (ret < 0)
271 return ret;
272
273 ret = analogix_dp_enable_rx_to_enhanced_mode(dp, data);
274 if (ret < 0)
275 return ret;
276
277 analogix_dp_enable_enhanced_mode(dp, data);
278
279 return 0;
280}
281
282static int analogix_dp_training_pattern_dis(struct analogix_dp_device *dp)
283{
284 int ret;
285
286 analogix_dp_set_training_pattern(dp, DP_NONE);
287
288 ret = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET,
289 DP_TRAINING_PATTERN_DISABLE);
290
291 return ret < 0 ? ret : 0;
292}
293
294static void
295analogix_dp_set_lane_lane_pre_emphasis(struct analogix_dp_device *dp,
296 int pre_emphasis, int lane)
297{
298 switch (lane) {
299 case 0:
300 analogix_dp_set_lane0_pre_emphasis(dp, pre_emphasis);
301 break;
302 case 1:
303 analogix_dp_set_lane1_pre_emphasis(dp, pre_emphasis);
304 break;
305
306 case 2:
307 analogix_dp_set_lane2_pre_emphasis(dp, pre_emphasis);
308 break;
309
310 case 3:
311 analogix_dp_set_lane3_pre_emphasis(dp, pre_emphasis);
312 break;
313 }
314}
315
316static int analogix_dp_link_start(struct analogix_dp_device *dp)
317{
318 u8 buf[4];
319 int lane, lane_count, pll_tries, retval;
320
321 lane_count = dp->link_train.lane_count;
322
323 dp->link_train.lt_state = CLOCK_RECOVERY;
324 dp->link_train.eq_loop = 0;
325
326 for (lane = 0; lane < lane_count; lane++)
327 dp->link_train.cr_loop[lane] = 0;
328
329
330 analogix_dp_set_link_bandwidth(dp, dp->link_train.link_rate);
331 analogix_dp_set_lane_count(dp, dp->link_train.lane_count);
332
333
334 buf[0] = dp->link_train.link_rate;
335 buf[1] = dp->link_train.lane_count;
336 retval = drm_dp_dpcd_write(&dp->aux, DP_LINK_BW_SET, buf, 2);
337 if (retval < 0)
338 return retval;
339
340 retval = analogix_dp_set_enhanced_mode(dp);
341 if (retval < 0) {
342 dev_err(dp->dev, "failed to set enhance mode\n");
343 return retval;
344 }
345
346
347 for (lane = 0; lane < lane_count; lane++)
348 analogix_dp_set_lane_lane_pre_emphasis(dp,
349 PRE_EMPHASIS_LEVEL_0, lane);
350
351
352 pll_tries = 0;
353 while (analogix_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
354 if (pll_tries == DP_TIMEOUT_LOOP_COUNT) {
355 dev_err(dp->dev, "Wait for PLL lock timed out\n");
356 return -ETIMEDOUT;
357 }
358
359 pll_tries++;
360 usleep_range(90, 120);
361 }
362
363
364 analogix_dp_set_training_pattern(dp, TRAINING_PTN1);
365
366
367 retval = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET,
368 DP_LINK_SCRAMBLING_DISABLE |
369 DP_TRAINING_PATTERN_1);
370 if (retval < 0)
371 return retval;
372
373 for (lane = 0; lane < lane_count; lane++)
374 buf[lane] = DP_TRAIN_PRE_EMPH_LEVEL_0 |
375 DP_TRAIN_VOLTAGE_SWING_LEVEL_0;
376
377 retval = drm_dp_dpcd_write(&dp->aux, DP_TRAINING_LANE0_SET, buf,
378 lane_count);
379 if (retval < 0)
380 return retval;
381
382 return 0;
383}
384
385static unsigned char analogix_dp_get_lane_status(u8 link_status[2], int lane)
386{
387 int shift = (lane & 1) * 4;
388 u8 link_value = link_status[lane >> 1];
389
390 return (link_value >> shift) & 0xf;
391}
392
393static int analogix_dp_clock_recovery_ok(u8 link_status[2], int lane_count)
394{
395 int lane;
396 u8 lane_status;
397
398 for (lane = 0; lane < lane_count; lane++) {
399 lane_status = analogix_dp_get_lane_status(link_status, lane);
400 if ((lane_status & DP_LANE_CR_DONE) == 0)
401 return -EINVAL;
402 }
403 return 0;
404}
405
406static int analogix_dp_channel_eq_ok(u8 link_status[2], u8 link_align,
407 int lane_count)
408{
409 int lane;
410 u8 lane_status;
411
412 if ((link_align & DP_INTERLANE_ALIGN_DONE) == 0)
413 return -EINVAL;
414
415 for (lane = 0; lane < lane_count; lane++) {
416 lane_status = analogix_dp_get_lane_status(link_status, lane);
417 lane_status &= DP_CHANNEL_EQ_BITS;
418 if (lane_status != DP_CHANNEL_EQ_BITS)
419 return -EINVAL;
420 }
421
422 return 0;
423}
424
425static unsigned char
426analogix_dp_get_adjust_request_voltage(u8 adjust_request[2], int lane)
427{
428 int shift = (lane & 1) * 4;
429 u8 link_value = adjust_request[lane >> 1];
430
431 return (link_value >> shift) & 0x3;
432}
433
434static unsigned char analogix_dp_get_adjust_request_pre_emphasis(
435 u8 adjust_request[2],
436 int lane)
437{
438 int shift = (lane & 1) * 4;
439 u8 link_value = adjust_request[lane >> 1];
440
441 return ((link_value >> shift) & 0xc) >> 2;
442}
443
444static void analogix_dp_set_lane_link_training(struct analogix_dp_device *dp,
445 u8 training_lane_set, int lane)
446{
447 switch (lane) {
448 case 0:
449 analogix_dp_set_lane0_link_training(dp, training_lane_set);
450 break;
451 case 1:
452 analogix_dp_set_lane1_link_training(dp, training_lane_set);
453 break;
454
455 case 2:
456 analogix_dp_set_lane2_link_training(dp, training_lane_set);
457 break;
458
459 case 3:
460 analogix_dp_set_lane3_link_training(dp, training_lane_set);
461 break;
462 }
463}
464
465static unsigned int
466analogix_dp_get_lane_link_training(struct analogix_dp_device *dp,
467 int lane)
468{
469 u32 reg;
470
471 switch (lane) {
472 case 0:
473 reg = analogix_dp_get_lane0_link_training(dp);
474 break;
475 case 1:
476 reg = analogix_dp_get_lane1_link_training(dp);
477 break;
478 case 2:
479 reg = analogix_dp_get_lane2_link_training(dp);
480 break;
481 case 3:
482 reg = analogix_dp_get_lane3_link_training(dp);
483 break;
484 default:
485 WARN_ON(1);
486 return 0;
487 }
488
489 return reg;
490}
491
492static void analogix_dp_reduce_link_rate(struct analogix_dp_device *dp)
493{
494 analogix_dp_training_pattern_dis(dp);
495 analogix_dp_set_enhanced_mode(dp);
496
497 dp->link_train.lt_state = FAILED;
498}
499
500static void analogix_dp_get_adjust_training_lane(struct analogix_dp_device *dp,
501 u8 adjust_request[2])
502{
503 int lane, lane_count;
504 u8 voltage_swing, pre_emphasis, training_lane;
505
506 lane_count = dp->link_train.lane_count;
507 for (lane = 0; lane < lane_count; lane++) {
508 voltage_swing = analogix_dp_get_adjust_request_voltage(
509 adjust_request, lane);
510 pre_emphasis = analogix_dp_get_adjust_request_pre_emphasis(
511 adjust_request, lane);
512 training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) |
513 DPCD_PRE_EMPHASIS_SET(pre_emphasis);
514
515 if (voltage_swing == VOLTAGE_LEVEL_3)
516 training_lane |= DP_TRAIN_MAX_SWING_REACHED;
517 if (pre_emphasis == PRE_EMPHASIS_LEVEL_3)
518 training_lane |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
519
520 dp->link_train.training_lane[lane] = training_lane;
521 }
522}
523
524static int analogix_dp_process_clock_recovery(struct analogix_dp_device *dp)
525{
526 int lane, lane_count, retval;
527 u8 voltage_swing, pre_emphasis, training_lane;
528 u8 link_status[2], adjust_request[2];
529
530 usleep_range(100, 101);
531
532 lane_count = dp->link_train.lane_count;
533
534 retval = drm_dp_dpcd_read(&dp->aux, DP_LANE0_1_STATUS, link_status, 2);
535 if (retval < 0)
536 return retval;
537
538 retval = drm_dp_dpcd_read(&dp->aux, DP_ADJUST_REQUEST_LANE0_1,
539 adjust_request, 2);
540 if (retval < 0)
541 return retval;
542
543 if (analogix_dp_clock_recovery_ok(link_status, lane_count) == 0) {
544
545 analogix_dp_set_training_pattern(dp, TRAINING_PTN2);
546
547 retval = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET,
548 DP_LINK_SCRAMBLING_DISABLE |
549 DP_TRAINING_PATTERN_2);
550 if (retval < 0)
551 return retval;
552
553 dev_dbg(dp->dev, "Link Training Clock Recovery success\n");
554 dp->link_train.lt_state = EQUALIZER_TRAINING;
555 } else {
556 for (lane = 0; lane < lane_count; lane++) {
557 training_lane = analogix_dp_get_lane_link_training(
558 dp, lane);
559 voltage_swing = analogix_dp_get_adjust_request_voltage(
560 adjust_request, lane);
561 pre_emphasis = analogix_dp_get_adjust_request_pre_emphasis(
562 adjust_request, lane);
563
564 if (DPCD_VOLTAGE_SWING_GET(training_lane) ==
565 voltage_swing &&
566 DPCD_PRE_EMPHASIS_GET(training_lane) ==
567 pre_emphasis)
568 dp->link_train.cr_loop[lane]++;
569
570 if (dp->link_train.cr_loop[lane] == MAX_CR_LOOP ||
571 voltage_swing == VOLTAGE_LEVEL_3 ||
572 pre_emphasis == PRE_EMPHASIS_LEVEL_3) {
573 dev_err(dp->dev, "CR Max reached (%d,%d,%d)\n",
574 dp->link_train.cr_loop[lane],
575 voltage_swing, pre_emphasis);
576 analogix_dp_reduce_link_rate(dp);
577 return -EIO;
578 }
579 }
580 }
581
582 analogix_dp_get_adjust_training_lane(dp, adjust_request);
583
584 for (lane = 0; lane < lane_count; lane++)
585 analogix_dp_set_lane_link_training(dp,
586 dp->link_train.training_lane[lane], lane);
587
588 retval = drm_dp_dpcd_write(&dp->aux, DP_TRAINING_LANE0_SET,
589 dp->link_train.training_lane, lane_count);
590 if (retval < 0)
591 return retval;
592
593 return 0;
594}
595
596static int analogix_dp_process_equalizer_training(struct analogix_dp_device *dp)
597{
598 int lane, lane_count, retval;
599 u32 reg;
600 u8 link_align, link_status[2], adjust_request[2];
601
602 usleep_range(400, 401);
603
604 lane_count = dp->link_train.lane_count;
605
606 retval = drm_dp_dpcd_read(&dp->aux, DP_LANE0_1_STATUS, link_status, 2);
607 if (retval < 0)
608 return retval;
609
610 if (analogix_dp_clock_recovery_ok(link_status, lane_count)) {
611 analogix_dp_reduce_link_rate(dp);
612 return -EIO;
613 }
614
615 retval = drm_dp_dpcd_read(&dp->aux, DP_ADJUST_REQUEST_LANE0_1,
616 adjust_request, 2);
617 if (retval < 0)
618 return retval;
619
620 retval = drm_dp_dpcd_readb(&dp->aux, DP_LANE_ALIGN_STATUS_UPDATED,
621 &link_align);
622 if (retval < 0)
623 return retval;
624
625 analogix_dp_get_adjust_training_lane(dp, adjust_request);
626
627 if (!analogix_dp_channel_eq_ok(link_status, link_align, lane_count)) {
628
629 retval = analogix_dp_training_pattern_dis(dp);
630 if (retval < 0)
631 return retval;
632
633 dev_dbg(dp->dev, "Link Training success!\n");
634 analogix_dp_get_link_bandwidth(dp, ®);
635 dp->link_train.link_rate = reg;
636 dev_dbg(dp->dev, "final bandwidth = %.2x\n",
637 dp->link_train.link_rate);
638
639 analogix_dp_get_lane_count(dp, ®);
640 dp->link_train.lane_count = reg;
641 dev_dbg(dp->dev, "final lane count = %.2x\n",
642 dp->link_train.lane_count);
643
644 dp->link_train.lt_state = FINISHED;
645
646 return 0;
647 }
648
649
650 dp->link_train.eq_loop++;
651
652 if (dp->link_train.eq_loop > MAX_EQ_LOOP) {
653 dev_err(dp->dev, "EQ Max loop\n");
654 analogix_dp_reduce_link_rate(dp);
655 return -EIO;
656 }
657
658 for (lane = 0; lane < lane_count; lane++)
659 analogix_dp_set_lane_link_training(dp,
660 dp->link_train.training_lane[lane], lane);
661
662 retval = drm_dp_dpcd_write(&dp->aux, DP_TRAINING_LANE0_SET,
663 dp->link_train.training_lane, lane_count);
664 if (retval < 0)
665 return retval;
666
667 return 0;
668}
669
670static void analogix_dp_get_max_rx_bandwidth(struct analogix_dp_device *dp,
671 u8 *bandwidth)
672{
673 u8 data;
674
675
676
677
678
679
680
681 drm_dp_dpcd_readb(&dp->aux, DP_MAX_LINK_RATE, &data);
682 *bandwidth = data;
683}
684
685static void analogix_dp_get_max_rx_lane_count(struct analogix_dp_device *dp,
686 u8 *lane_count)
687{
688 u8 data;
689
690
691
692
693
694 drm_dp_dpcd_readb(&dp->aux, DP_MAX_LANE_COUNT, &data);
695 *lane_count = DPCD_MAX_LANE_COUNT(data);
696}
697
698static int analogix_dp_full_link_train(struct analogix_dp_device *dp,
699 u32 max_lanes, u32 max_rate)
700{
701 int retval = 0;
702 bool training_finished = false;
703
704
705
706
707
708 analogix_dp_reset_macro(dp);
709
710
711 analogix_dp_get_max_rx_bandwidth(dp, &dp->link_train.link_rate);
712 analogix_dp_get_max_rx_lane_count(dp, &dp->link_train.lane_count);
713
714 if ((dp->link_train.link_rate != DP_LINK_BW_1_62) &&
715 (dp->link_train.link_rate != DP_LINK_BW_2_7) &&
716 (dp->link_train.link_rate != DP_LINK_BW_5_4)) {
717 dev_err(dp->dev, "Rx Max Link Rate is abnormal :%x !\n",
718 dp->link_train.link_rate);
719 dp->link_train.link_rate = DP_LINK_BW_1_62;
720 }
721
722 if (dp->link_train.lane_count == 0) {
723 dev_err(dp->dev, "Rx Max Lane count is abnormal :%x !\n",
724 dp->link_train.lane_count);
725 dp->link_train.lane_count = (u8)LANE_COUNT1;
726 }
727
728
729 if (dp->link_train.lane_count > max_lanes)
730 dp->link_train.lane_count = max_lanes;
731 if (dp->link_train.link_rate > max_rate)
732 dp->link_train.link_rate = max_rate;
733
734
735 analogix_dp_set_analog_power_down(dp, POWER_ALL, 0);
736
737 dp->link_train.lt_state = START;
738
739
740 while (!retval && !training_finished) {
741 switch (dp->link_train.lt_state) {
742 case START:
743 retval = analogix_dp_link_start(dp);
744 if (retval)
745 dev_err(dp->dev, "LT link start failed!\n");
746 break;
747 case CLOCK_RECOVERY:
748 retval = analogix_dp_process_clock_recovery(dp);
749 if (retval)
750 dev_err(dp->dev, "LT CR failed!\n");
751 break;
752 case EQUALIZER_TRAINING:
753 retval = analogix_dp_process_equalizer_training(dp);
754 if (retval)
755 dev_err(dp->dev, "LT EQ failed!\n");
756 break;
757 case FINISHED:
758 training_finished = 1;
759 break;
760 case FAILED:
761 return -EREMOTEIO;
762 }
763 }
764 if (retval)
765 dev_err(dp->dev, "eDP link training failed (%d)\n", retval);
766
767 return retval;
768}
769
770static int analogix_dp_fast_link_train(struct analogix_dp_device *dp)
771{
772 int i, ret;
773 u8 link_align, link_status[2];
774 enum pll_status status;
775
776 analogix_dp_reset_macro(dp);
777
778 analogix_dp_set_link_bandwidth(dp, dp->link_train.link_rate);
779 analogix_dp_set_lane_count(dp, dp->link_train.lane_count);
780
781 for (i = 0; i < dp->link_train.lane_count; i++) {
782 analogix_dp_set_lane_link_training(dp,
783 dp->link_train.training_lane[i], i);
784 }
785
786 ret = readx_poll_timeout(analogix_dp_get_pll_lock_status, dp, status,
787 status != PLL_UNLOCKED, 120,
788 120 * DP_TIMEOUT_LOOP_COUNT);
789 if (ret) {
790 DRM_DEV_ERROR(dp->dev, "Wait for pll lock failed %d\n", ret);
791 return ret;
792 }
793
794
795 analogix_dp_set_training_pattern(dp, TRAINING_PTN1);
796
797 usleep_range(500, 600);
798
799 analogix_dp_set_training_pattern(dp, TRAINING_PTN2);
800
801 usleep_range(500, 600);
802
803
804 analogix_dp_set_training_pattern(dp, DP_NONE);
805
806
807
808
809
810 if (verify_fast_training) {
811 ret = drm_dp_dpcd_readb(&dp->aux, DP_LANE_ALIGN_STATUS_UPDATED,
812 &link_align);
813 if (ret < 0) {
814 DRM_DEV_ERROR(dp->dev, "Read align status failed %d\n",
815 ret);
816 return ret;
817 }
818
819 ret = drm_dp_dpcd_read(&dp->aux, DP_LANE0_1_STATUS, link_status,
820 2);
821 if (ret < 0) {
822 DRM_DEV_ERROR(dp->dev, "Read link status failed %d\n",
823 ret);
824 return ret;
825 }
826
827 if (analogix_dp_clock_recovery_ok(link_status,
828 dp->link_train.lane_count)) {
829 DRM_DEV_ERROR(dp->dev, "Clock recovery failed\n");
830 analogix_dp_reduce_link_rate(dp);
831 return -EIO;
832 }
833
834 if (analogix_dp_channel_eq_ok(link_status, link_align,
835 dp->link_train.lane_count)) {
836 DRM_DEV_ERROR(dp->dev, "Channel EQ failed\n");
837 analogix_dp_reduce_link_rate(dp);
838 return -EIO;
839 }
840 }
841
842 return 0;
843}
844
845static int analogix_dp_train_link(struct analogix_dp_device *dp)
846{
847 if (dp->fast_train_enable)
848 return analogix_dp_fast_link_train(dp);
849
850 return analogix_dp_full_link_train(dp, dp->video_info.max_lane_count,
851 dp->video_info.max_link_rate);
852}
853
854static int analogix_dp_config_video(struct analogix_dp_device *dp)
855{
856 int timeout_loop = 0;
857 int done_count = 0;
858
859 analogix_dp_config_video_slave_mode(dp);
860
861 analogix_dp_set_video_color_format(dp);
862
863 if (analogix_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
864 dev_err(dp->dev, "PLL is not locked yet.\n");
865 return -EINVAL;
866 }
867
868 for (;;) {
869 timeout_loop++;
870 if (analogix_dp_is_slave_video_stream_clock_on(dp) == 0)
871 break;
872 if (timeout_loop > DP_TIMEOUT_LOOP_COUNT) {
873 dev_err(dp->dev, "Timeout of slave video streamclk ok\n");
874 return -ETIMEDOUT;
875 }
876 usleep_range(1000, 1001);
877 }
878
879
880 analogix_dp_set_video_cr_mn(dp, CALCULATED_M, 0, 0);
881
882
883 analogix_dp_set_video_timing_mode(dp, VIDEO_TIMING_FROM_CAPTURE);
884
885
886 analogix_dp_enable_video_mute(dp, 0);
887
888
889 analogix_dp_enable_video_master(dp, 0);
890
891
892 analogix_dp_start_video(dp);
893
894 timeout_loop = 0;
895
896 for (;;) {
897 timeout_loop++;
898 if (analogix_dp_is_video_stream_on(dp) == 0) {
899 done_count++;
900 if (done_count > 10)
901 break;
902 } else if (done_count) {
903 done_count = 0;
904 }
905 if (timeout_loop > DP_TIMEOUT_LOOP_COUNT) {
906 dev_warn(dp->dev,
907 "Ignoring timeout of video streamclk ok\n");
908 break;
909 }
910
911 usleep_range(1000, 1001);
912 }
913
914 return 0;
915}
916
917static int analogix_dp_enable_scramble(struct analogix_dp_device *dp,
918 bool enable)
919{
920 u8 data;
921 int ret;
922
923 if (enable) {
924 analogix_dp_enable_scrambling(dp);
925
926 ret = drm_dp_dpcd_readb(&dp->aux, DP_TRAINING_PATTERN_SET,
927 &data);
928 if (ret != 1)
929 return ret;
930 ret = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET,
931 (u8)(data & ~DP_LINK_SCRAMBLING_DISABLE));
932 } else {
933 analogix_dp_disable_scrambling(dp);
934
935 ret = drm_dp_dpcd_readb(&dp->aux, DP_TRAINING_PATTERN_SET,
936 &data);
937 if (ret != 1)
938 return ret;
939 ret = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET,
940 (u8)(data | DP_LINK_SCRAMBLING_DISABLE));
941 }
942 return ret < 0 ? ret : 0;
943}
944
945static irqreturn_t analogix_dp_hardirq(int irq, void *arg)
946{
947 struct analogix_dp_device *dp = arg;
948 irqreturn_t ret = IRQ_NONE;
949 enum dp_irq_type irq_type;
950
951 irq_type = analogix_dp_get_irq_type(dp);
952 if (irq_type != DP_IRQ_TYPE_UNKNOWN) {
953 analogix_dp_mute_hpd_interrupt(dp);
954 ret = IRQ_WAKE_THREAD;
955 }
956
957 return ret;
958}
959
960static irqreturn_t analogix_dp_irq_thread(int irq, void *arg)
961{
962 struct analogix_dp_device *dp = arg;
963 enum dp_irq_type irq_type;
964
965 irq_type = analogix_dp_get_irq_type(dp);
966 if (irq_type & DP_IRQ_TYPE_HP_CABLE_IN ||
967 irq_type & DP_IRQ_TYPE_HP_CABLE_OUT) {
968 dev_dbg(dp->dev, "Detected cable status changed!\n");
969 if (dp->drm_dev)
970 drm_helper_hpd_irq_event(dp->drm_dev);
971 }
972
973 if (irq_type != DP_IRQ_TYPE_UNKNOWN) {
974 analogix_dp_clear_hotplug_interrupts(dp);
975 analogix_dp_unmute_hpd_interrupt(dp);
976 }
977
978 return IRQ_HANDLED;
979}
980
981static int analogix_dp_fast_link_train_detection(struct analogix_dp_device *dp)
982{
983 int ret;
984 u8 spread;
985
986 ret = drm_dp_dpcd_readb(&dp->aux, DP_MAX_DOWNSPREAD, &spread);
987 if (ret != 1) {
988 dev_err(dp->dev, "failed to read downspread %d\n", ret);
989 return ret;
990 }
991 dp->fast_train_enable = !!(spread & DP_NO_AUX_HANDSHAKE_LINK_TRAINING);
992 dev_dbg(dp->dev, "fast link training %s\n",
993 dp->fast_train_enable ? "supported" : "unsupported");
994 return 0;
995}
996
997static int analogix_dp_commit(struct analogix_dp_device *dp)
998{
999 int ret;
1000
1001
1002 if (dp->plat_data->panel) {
1003 if (drm_panel_disable(dp->plat_data->panel))
1004 DRM_ERROR("failed to disable the panel\n");
1005 }
1006
1007 ret = analogix_dp_train_link(dp);
1008 if (ret) {
1009 dev_err(dp->dev, "unable to do link train, ret=%d\n", ret);
1010 return ret;
1011 }
1012
1013 ret = analogix_dp_enable_scramble(dp, 1);
1014 if (ret < 0) {
1015 dev_err(dp->dev, "can not enable scramble\n");
1016 return ret;
1017 }
1018
1019 analogix_dp_init_video(dp);
1020 ret = analogix_dp_config_video(dp);
1021 if (ret) {
1022 dev_err(dp->dev, "unable to config video\n");
1023 return ret;
1024 }
1025
1026
1027 if (dp->plat_data->panel) {
1028 ret = drm_panel_enable(dp->plat_data->panel);
1029 if (ret) {
1030 DRM_ERROR("failed to enable the panel\n");
1031 return ret;
1032 }
1033 }
1034
1035 ret = analogix_dp_detect_sink_psr(dp);
1036 if (ret)
1037 return ret;
1038
1039 if (dp->psr_enable) {
1040 ret = analogix_dp_enable_sink_psr(dp);
1041 if (ret)
1042 return ret;
1043 }
1044
1045
1046 ret = analogix_dp_fast_link_train_detection(dp);
1047 if (ret)
1048 dp->psr_enable = false;
1049
1050 return ret;
1051}
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064
1065
1066static int analogix_dp_prepare_panel(struct analogix_dp_device *dp,
1067 bool prepare, bool is_modeset_prepare)
1068{
1069 int ret = 0;
1070
1071 if (!dp->plat_data->panel)
1072 return 0;
1073
1074 mutex_lock(&dp->panel_lock);
1075
1076
1077
1078
1079
1080 if (dp->panel_is_modeset && !is_modeset_prepare)
1081 goto out;
1082
1083 if (prepare)
1084 ret = drm_panel_prepare(dp->plat_data->panel);
1085 else
1086 ret = drm_panel_unprepare(dp->plat_data->panel);
1087
1088 if (ret)
1089 goto out;
1090
1091 if (is_modeset_prepare)
1092 dp->panel_is_modeset = prepare;
1093
1094out:
1095 mutex_unlock(&dp->panel_lock);
1096 return ret;
1097}
1098
1099static int analogix_dp_get_modes(struct drm_connector *connector)
1100{
1101 struct analogix_dp_device *dp = to_dp(connector);
1102 struct edid *edid;
1103 int ret, num_modes = 0;
1104
1105 if (dp->plat_data->panel) {
1106 num_modes += drm_panel_get_modes(dp->plat_data->panel);
1107 } else {
1108 ret = analogix_dp_prepare_panel(dp, true, false);
1109 if (ret) {
1110 DRM_ERROR("Failed to prepare panel (%d)\n", ret);
1111 return 0;
1112 }
1113
1114 pm_runtime_get_sync(dp->dev);
1115 edid = drm_get_edid(connector, &dp->aux.ddc);
1116 pm_runtime_put(dp->dev);
1117 if (edid) {
1118 drm_connector_update_edid_property(&dp->connector,
1119 edid);
1120 num_modes += drm_add_edid_modes(&dp->connector, edid);
1121 kfree(edid);
1122 }
1123
1124 ret = analogix_dp_prepare_panel(dp, false, false);
1125 if (ret)
1126 DRM_ERROR("Failed to unprepare panel (%d)\n", ret);
1127 }
1128
1129 if (dp->plat_data->get_modes)
1130 num_modes += dp->plat_data->get_modes(dp->plat_data, connector);
1131
1132 return num_modes;
1133}
1134
1135static struct drm_encoder *
1136analogix_dp_best_encoder(struct drm_connector *connector)
1137{
1138 struct analogix_dp_device *dp = to_dp(connector);
1139
1140 return dp->encoder;
1141}
1142
1143static const struct drm_connector_helper_funcs analogix_dp_connector_helper_funcs = {
1144 .get_modes = analogix_dp_get_modes,
1145 .best_encoder = analogix_dp_best_encoder,
1146};
1147
1148static enum drm_connector_status
1149analogix_dp_detect(struct drm_connector *connector, bool force)
1150{
1151 struct analogix_dp_device *dp = to_dp(connector);
1152 enum drm_connector_status status = connector_status_disconnected;
1153 int ret;
1154
1155 if (dp->plat_data->panel)
1156 return connector_status_connected;
1157
1158 ret = analogix_dp_prepare_panel(dp, true, false);
1159 if (ret) {
1160 DRM_ERROR("Failed to prepare panel (%d)\n", ret);
1161 return connector_status_disconnected;
1162 }
1163
1164 if (!analogix_dp_detect_hpd(dp))
1165 status = connector_status_connected;
1166
1167 ret = analogix_dp_prepare_panel(dp, false, false);
1168 if (ret)
1169 DRM_ERROR("Failed to unprepare panel (%d)\n", ret);
1170
1171 return status;
1172}
1173
1174static const struct drm_connector_funcs analogix_dp_connector_funcs = {
1175 .fill_modes = drm_helper_probe_single_connector_modes,
1176 .detect = analogix_dp_detect,
1177 .destroy = drm_connector_cleanup,
1178 .reset = drm_atomic_helper_connector_reset,
1179 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1180 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1181};
1182
1183static int analogix_dp_bridge_attach(struct drm_bridge *bridge)
1184{
1185 struct analogix_dp_device *dp = bridge->driver_private;
1186 struct drm_encoder *encoder = dp->encoder;
1187 struct drm_connector *connector = NULL;
1188 int ret = 0;
1189
1190 if (!bridge->encoder) {
1191 DRM_ERROR("Parent encoder object not found");
1192 return -ENODEV;
1193 }
1194
1195 if (!dp->plat_data->skip_connector) {
1196 connector = &dp->connector;
1197 connector->polled = DRM_CONNECTOR_POLL_HPD;
1198
1199 ret = drm_connector_init(dp->drm_dev, connector,
1200 &analogix_dp_connector_funcs,
1201 DRM_MODE_CONNECTOR_eDP);
1202 if (ret) {
1203 DRM_ERROR("Failed to initialize connector with drm\n");
1204 return ret;
1205 }
1206
1207 drm_connector_helper_add(connector,
1208 &analogix_dp_connector_helper_funcs);
1209 drm_connector_attach_encoder(connector, encoder);
1210 }
1211
1212
1213
1214
1215
1216
1217
1218 if (dp->plat_data->attach) {
1219 ret = dp->plat_data->attach(dp->plat_data, bridge, connector);
1220 if (ret) {
1221 DRM_ERROR("Failed at platform attach func\n");
1222 return ret;
1223 }
1224 }
1225
1226 if (dp->plat_data->panel) {
1227 ret = drm_panel_attach(dp->plat_data->panel, &dp->connector);
1228 if (ret) {
1229 DRM_ERROR("Failed to attach panel\n");
1230 return ret;
1231 }
1232 }
1233
1234 return 0;
1235}
1236
1237static void analogix_dp_bridge_pre_enable(struct drm_bridge *bridge)
1238{
1239 struct analogix_dp_device *dp = bridge->driver_private;
1240 int ret;
1241
1242 ret = analogix_dp_prepare_panel(dp, true, true);
1243 if (ret)
1244 DRM_ERROR("failed to setup the panel ret = %d\n", ret);
1245}
1246
1247static int analogix_dp_set_bridge(struct analogix_dp_device *dp)
1248{
1249 int ret;
1250
1251 pm_runtime_get_sync(dp->dev);
1252
1253 ret = clk_prepare_enable(dp->clock);
1254 if (ret < 0) {
1255 DRM_ERROR("Failed to prepare_enable the clock clk [%d]\n", ret);
1256 goto out_dp_clk_pre;
1257 }
1258
1259 if (dp->plat_data->power_on_start)
1260 dp->plat_data->power_on_start(dp->plat_data);
1261
1262 phy_power_on(dp->phy);
1263
1264 ret = analogix_dp_init_dp(dp);
1265 if (ret)
1266 goto out_dp_init;
1267
1268
1269
1270
1271
1272
1273 ret = analogix_dp_detect_hpd(dp);
1274 if (ret) {
1275 DRM_ERROR("failed to get hpd single ret = %d\n", ret);
1276 goto out_dp_init;
1277 }
1278
1279 ret = analogix_dp_commit(dp);
1280 if (ret) {
1281 DRM_ERROR("dp commit error, ret = %d\n", ret);
1282 goto out_dp_init;
1283 }
1284
1285 if (dp->plat_data->power_on_end)
1286 dp->plat_data->power_on_end(dp->plat_data);
1287
1288 enable_irq(dp->irq);
1289 return 0;
1290
1291out_dp_init:
1292 phy_power_off(dp->phy);
1293 if (dp->plat_data->power_off)
1294 dp->plat_data->power_off(dp->plat_data);
1295 clk_disable_unprepare(dp->clock);
1296out_dp_clk_pre:
1297 pm_runtime_put_sync(dp->dev);
1298
1299 return ret;
1300}
1301
1302static void analogix_dp_bridge_enable(struct drm_bridge *bridge)
1303{
1304 struct analogix_dp_device *dp = bridge->driver_private;
1305 int timeout_loop = 0;
1306
1307 if (dp->dpms_mode == DRM_MODE_DPMS_ON)
1308 return;
1309
1310 while (timeout_loop < MAX_PLL_LOCK_LOOP) {
1311 if (analogix_dp_set_bridge(dp) == 0) {
1312 dp->dpms_mode = DRM_MODE_DPMS_ON;
1313 return;
1314 }
1315 dev_err(dp->dev, "failed to set bridge, retry: %d\n",
1316 timeout_loop);
1317 timeout_loop++;
1318 usleep_range(10, 11);
1319 }
1320 dev_err(dp->dev, "too many times retry set bridge, give it up\n");
1321}
1322
1323static void analogix_dp_bridge_disable(struct drm_bridge *bridge)
1324{
1325 struct analogix_dp_device *dp = bridge->driver_private;
1326 int ret;
1327
1328 if (dp->dpms_mode != DRM_MODE_DPMS_ON)
1329 return;
1330
1331 if (dp->plat_data->panel) {
1332 if (drm_panel_disable(dp->plat_data->panel)) {
1333 DRM_ERROR("failed to disable the panel\n");
1334 return;
1335 }
1336 }
1337
1338 disable_irq(dp->irq);
1339
1340 if (dp->plat_data->power_off)
1341 dp->plat_data->power_off(dp->plat_data);
1342
1343 analogix_dp_set_analog_power_down(dp, POWER_ALL, 1);
1344 phy_power_off(dp->phy);
1345
1346 clk_disable_unprepare(dp->clock);
1347
1348 pm_runtime_put_sync(dp->dev);
1349
1350 ret = analogix_dp_prepare_panel(dp, false, true);
1351 if (ret)
1352 DRM_ERROR("failed to setup the panel ret = %d\n", ret);
1353
1354 dp->psr_enable = false;
1355 dp->fast_train_enable = false;
1356 dp->dpms_mode = DRM_MODE_DPMS_OFF;
1357}
1358
1359static void analogix_dp_bridge_mode_set(struct drm_bridge *bridge,
1360 const struct drm_display_mode *orig_mode,
1361 const struct drm_display_mode *mode)
1362{
1363 struct analogix_dp_device *dp = bridge->driver_private;
1364 struct drm_display_info *display_info = &dp->connector.display_info;
1365 struct video_info *video = &dp->video_info;
1366 struct device_node *dp_node = dp->dev->of_node;
1367 int vic;
1368
1369
1370 video->interlaced = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
1371 video->v_sync_polarity = !!(mode->flags & DRM_MODE_FLAG_NVSYNC);
1372 video->h_sync_polarity = !!(mode->flags & DRM_MODE_FLAG_NHSYNC);
1373
1374
1375 vic = drm_match_cea_mode(mode);
1376 if ((vic == 6) || (vic == 7) || (vic == 21) || (vic == 22) ||
1377 (vic == 2) || (vic == 3) || (vic == 17) || (vic == 18)) {
1378 video->dynamic_range = CEA;
1379 video->ycbcr_coeff = COLOR_YCBCR601;
1380 } else if (vic) {
1381 video->dynamic_range = CEA;
1382 video->ycbcr_coeff = COLOR_YCBCR709;
1383 } else {
1384 video->dynamic_range = VESA;
1385 video->ycbcr_coeff = COLOR_YCBCR709;
1386 }
1387
1388
1389 switch (display_info->bpc) {
1390 case 12:
1391 video->color_depth = COLOR_12;
1392 break;
1393 case 10:
1394 video->color_depth = COLOR_10;
1395 break;
1396 case 8:
1397 video->color_depth = COLOR_8;
1398 break;
1399 case 6:
1400 video->color_depth = COLOR_6;
1401 break;
1402 default:
1403 video->color_depth = COLOR_8;
1404 break;
1405 }
1406 if (display_info->color_formats & DRM_COLOR_FORMAT_YCRCB444)
1407 video->color_space = COLOR_YCBCR444;
1408 else if (display_info->color_formats & DRM_COLOR_FORMAT_YCRCB422)
1409 video->color_space = COLOR_YCBCR422;
1410 else if (display_info->color_formats & DRM_COLOR_FORMAT_RGB444)
1411 video->color_space = COLOR_RGB;
1412 else
1413 video->color_space = COLOR_RGB;
1414
1415
1416
1417
1418
1419
1420
1421
1422 of_property_read_u32(dp_node, "samsung,color-space",
1423 &video->color_space);
1424 of_property_read_u32(dp_node, "samsung,dynamic-range",
1425 &video->dynamic_range);
1426 of_property_read_u32(dp_node, "samsung,ycbcr-coeff",
1427 &video->ycbcr_coeff);
1428 of_property_read_u32(dp_node, "samsung,color-depth",
1429 &video->color_depth);
1430 if (of_property_read_bool(dp_node, "hsync-active-high"))
1431 video->h_sync_polarity = true;
1432 if (of_property_read_bool(dp_node, "vsync-active-high"))
1433 video->v_sync_polarity = true;
1434 if (of_property_read_bool(dp_node, "interlaced"))
1435 video->interlaced = true;
1436}
1437
1438static void analogix_dp_bridge_nop(struct drm_bridge *bridge)
1439{
1440
1441}
1442
1443static const struct drm_bridge_funcs analogix_dp_bridge_funcs = {
1444 .pre_enable = analogix_dp_bridge_pre_enable,
1445 .enable = analogix_dp_bridge_enable,
1446 .disable = analogix_dp_bridge_disable,
1447 .post_disable = analogix_dp_bridge_nop,
1448 .mode_set = analogix_dp_bridge_mode_set,
1449 .attach = analogix_dp_bridge_attach,
1450};
1451
1452static int analogix_dp_create_bridge(struct drm_device *drm_dev,
1453 struct analogix_dp_device *dp)
1454{
1455 struct drm_bridge *bridge;
1456 int ret;
1457
1458 bridge = devm_kzalloc(drm_dev->dev, sizeof(*bridge), GFP_KERNEL);
1459 if (!bridge) {
1460 DRM_ERROR("failed to allocate for drm bridge\n");
1461 return -ENOMEM;
1462 }
1463
1464 dp->bridge = bridge;
1465
1466 bridge->driver_private = dp;
1467 bridge->funcs = &analogix_dp_bridge_funcs;
1468
1469 ret = drm_bridge_attach(dp->encoder, bridge, NULL);
1470 if (ret) {
1471 DRM_ERROR("failed to attach drm bridge\n");
1472 return -EINVAL;
1473 }
1474
1475 return 0;
1476}
1477
1478static int analogix_dp_dt_parse_pdata(struct analogix_dp_device *dp)
1479{
1480 struct device_node *dp_node = dp->dev->of_node;
1481 struct video_info *video_info = &dp->video_info;
1482
1483 switch (dp->plat_data->dev_type) {
1484 case RK3288_DP:
1485 case RK3399_EDP:
1486
1487
1488
1489
1490 video_info->max_link_rate = 0x0A;
1491 video_info->max_lane_count = 0x04;
1492 break;
1493 case EXYNOS_DP:
1494
1495
1496
1497
1498 of_property_read_u32(dp_node, "samsung,link-rate",
1499 &video_info->max_link_rate);
1500 of_property_read_u32(dp_node, "samsung,lane-count",
1501 &video_info->max_lane_count);
1502 break;
1503 }
1504
1505 return 0;
1506}
1507
1508static ssize_t analogix_dpaux_transfer(struct drm_dp_aux *aux,
1509 struct drm_dp_aux_msg *msg)
1510{
1511 struct analogix_dp_device *dp = to_dp(aux);
1512
1513 return analogix_dp_transfer(dp, msg);
1514}
1515
1516struct analogix_dp_device *
1517analogix_dp_bind(struct device *dev, struct drm_device *drm_dev,
1518 struct analogix_dp_plat_data *plat_data)
1519{
1520 struct platform_device *pdev = to_platform_device(dev);
1521 struct analogix_dp_device *dp;
1522 struct resource *res;
1523 unsigned int irq_flags;
1524 int ret;
1525
1526 if (!plat_data) {
1527 dev_err(dev, "Invalided input plat_data\n");
1528 return ERR_PTR(-EINVAL);
1529 }
1530
1531 dp = devm_kzalloc(dev, sizeof(struct analogix_dp_device), GFP_KERNEL);
1532 if (!dp)
1533 return ERR_PTR(-ENOMEM);
1534
1535 dp->dev = &pdev->dev;
1536 dp->dpms_mode = DRM_MODE_DPMS_OFF;
1537
1538 mutex_init(&dp->panel_lock);
1539 dp->panel_is_modeset = false;
1540
1541
1542
1543
1544
1545
1546 dp->plat_data = plat_data;
1547
1548 ret = analogix_dp_dt_parse_pdata(dp);
1549 if (ret)
1550 return ERR_PTR(ret);
1551
1552 dp->phy = devm_phy_get(dp->dev, "dp");
1553 if (IS_ERR(dp->phy)) {
1554 dev_err(dp->dev, "no DP phy configured\n");
1555 ret = PTR_ERR(dp->phy);
1556 if (ret) {
1557
1558
1559
1560
1561 if (ret == -ENOSYS || ret == -ENODEV)
1562 dp->phy = NULL;
1563 else
1564 return ERR_PTR(ret);
1565 }
1566 }
1567
1568 dp->clock = devm_clk_get(&pdev->dev, "dp");
1569 if (IS_ERR(dp->clock)) {
1570 dev_err(&pdev->dev, "failed to get clock\n");
1571 return ERR_CAST(dp->clock);
1572 }
1573
1574 clk_prepare_enable(dp->clock);
1575
1576 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1577
1578 dp->reg_base = devm_ioremap_resource(&pdev->dev, res);
1579 if (IS_ERR(dp->reg_base))
1580 return ERR_CAST(dp->reg_base);
1581
1582 dp->force_hpd = of_property_read_bool(dev->of_node, "force-hpd");
1583
1584 dp->hpd_gpio = of_get_named_gpio(dev->of_node, "hpd-gpios", 0);
1585 if (!gpio_is_valid(dp->hpd_gpio))
1586 dp->hpd_gpio = of_get_named_gpio(dev->of_node,
1587 "samsung,hpd-gpio", 0);
1588
1589 if (gpio_is_valid(dp->hpd_gpio)) {
1590
1591
1592
1593
1594
1595
1596
1597 ret = devm_gpio_request_one(&pdev->dev, dp->hpd_gpio, GPIOF_IN,
1598 "hpd_gpio");
1599 if (ret) {
1600 dev_err(&pdev->dev, "failed to get hpd gpio\n");
1601 return ERR_PTR(ret);
1602 }
1603 dp->irq = gpio_to_irq(dp->hpd_gpio);
1604 irq_flags = IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING;
1605 } else {
1606 dp->hpd_gpio = -ENODEV;
1607 dp->irq = platform_get_irq(pdev, 0);
1608 irq_flags = 0;
1609 }
1610
1611 if (dp->irq == -ENXIO) {
1612 dev_err(&pdev->dev, "failed to get irq\n");
1613 return ERR_PTR(-ENODEV);
1614 }
1615
1616 ret = devm_request_threaded_irq(&pdev->dev, dp->irq,
1617 analogix_dp_hardirq,
1618 analogix_dp_irq_thread,
1619 irq_flags, "analogix-dp", dp);
1620 if (ret) {
1621 dev_err(&pdev->dev, "failed to request irq\n");
1622 goto err_disable_pm_runtime;
1623 }
1624 disable_irq(dp->irq);
1625
1626 dp->drm_dev = drm_dev;
1627 dp->encoder = dp->plat_data->encoder;
1628
1629 dp->aux.name = "DP-AUX";
1630 dp->aux.transfer = analogix_dpaux_transfer;
1631 dp->aux.dev = &pdev->dev;
1632
1633 ret = drm_dp_aux_register(&dp->aux);
1634 if (ret)
1635 return ERR_PTR(ret);
1636
1637 pm_runtime_enable(dev);
1638
1639 ret = analogix_dp_create_bridge(drm_dev, dp);
1640 if (ret) {
1641 DRM_ERROR("failed to create bridge (%d)\n", ret);
1642 goto err_disable_pm_runtime;
1643 }
1644
1645 return dp;
1646
1647err_disable_pm_runtime:
1648
1649 pm_runtime_disable(dev);
1650
1651 return ERR_PTR(ret);
1652}
1653EXPORT_SYMBOL_GPL(analogix_dp_bind);
1654
1655void analogix_dp_unbind(struct analogix_dp_device *dp)
1656{
1657 analogix_dp_bridge_disable(dp->bridge);
1658 dp->connector.funcs->destroy(&dp->connector);
1659
1660 if (dp->plat_data->panel) {
1661 if (drm_panel_unprepare(dp->plat_data->panel))
1662 DRM_ERROR("failed to turnoff the panel\n");
1663 if (drm_panel_detach(dp->plat_data->panel))
1664 DRM_ERROR("failed to detach the panel\n");
1665 }
1666
1667 drm_dp_aux_unregister(&dp->aux);
1668 pm_runtime_disable(dp->dev);
1669 clk_disable_unprepare(dp->clock);
1670}
1671EXPORT_SYMBOL_GPL(analogix_dp_unbind);
1672
1673#ifdef CONFIG_PM
1674int analogix_dp_suspend(struct analogix_dp_device *dp)
1675{
1676 clk_disable_unprepare(dp->clock);
1677
1678 if (dp->plat_data->panel) {
1679 if (drm_panel_unprepare(dp->plat_data->panel))
1680 DRM_ERROR("failed to turnoff the panel\n");
1681 }
1682
1683 return 0;
1684}
1685EXPORT_SYMBOL_GPL(analogix_dp_suspend);
1686
1687int analogix_dp_resume(struct analogix_dp_device *dp)
1688{
1689 int ret;
1690
1691 ret = clk_prepare_enable(dp->clock);
1692 if (ret < 0) {
1693 DRM_ERROR("Failed to prepare_enable the clock clk [%d]\n", ret);
1694 return ret;
1695 }
1696
1697 if (dp->plat_data->panel) {
1698 if (drm_panel_prepare(dp->plat_data->panel)) {
1699 DRM_ERROR("failed to setup the panel\n");
1700 return -EBUSY;
1701 }
1702 }
1703
1704 return 0;
1705}
1706EXPORT_SYMBOL_GPL(analogix_dp_resume);
1707#endif
1708
1709int analogix_dp_start_crc(struct drm_connector *connector)
1710{
1711 struct analogix_dp_device *dp = to_dp(connector);
1712
1713 if (!connector->state->crtc) {
1714 DRM_ERROR("Connector %s doesn't currently have a CRTC.\n",
1715 connector->name);
1716 return -EINVAL;
1717 }
1718
1719 return drm_dp_start_crc(&dp->aux, connector->state->crtc);
1720}
1721EXPORT_SYMBOL_GPL(analogix_dp_start_crc);
1722
1723int analogix_dp_stop_crc(struct drm_connector *connector)
1724{
1725 struct analogix_dp_device *dp = to_dp(connector);
1726
1727 return drm_dp_stop_crc(&dp->aux);
1728}
1729EXPORT_SYMBOL_GPL(analogix_dp_stop_crc);
1730
1731MODULE_AUTHOR("Jingoo Han <jg1.han@samsung.com>");
1732MODULE_DESCRIPTION("Analogix DP Core Driver");
1733MODULE_LICENSE("GPL v2");
1734
